* [Intel-gfx] [CI] drm/i915: Disable atomics in L3 for gen9
@ 2021-05-28 17:25 J. Bruce Fields
2021-05-29 5:29 ` Greg KH
0 siblings, 1 reply; 5+ messages in thread
From: J. Bruce Fields @ 2021-05-28 17:25 UTC (permalink / raw)
To: stable; +Cc: intel-gfx, Chris Wilson
Would it be possible to apply
58586680ffad "drm/i915: Disable atomics in L3 for gen9"
to stable kernels?
I'm finding it quite easy to crash my Thinkpad X1 Carbon 6th gen with
Blender on Fedora 34 (which is using the 5.11.y kernels). It applies
cleanly, and I've been running 5.11.16 with the patch applied and seeing
no obvious ill effects.
--b.
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [CI] drm/i915: Disable atomics in L3 for gen9
2021-05-28 17:25 [Intel-gfx] [CI] drm/i915: Disable atomics in L3 for gen9 J. Bruce Fields
@ 2021-05-29 5:29 ` Greg KH
2021-05-29 21:19 ` J. Bruce Fields
0 siblings, 1 reply; 5+ messages in thread
From: Greg KH @ 2021-05-29 5:29 UTC (permalink / raw)
To: J. Bruce Fields; +Cc: intel-gfx, stable, Chris Wilson
On Fri, May 28, 2021 at 01:25:43PM -0400, J. Bruce Fields wrote:
> Would it be possible to apply
>
> 58586680ffad "drm/i915: Disable atomics in L3 for gen9"
>
> to stable kernels?
>
> I'm finding it quite easy to crash my Thinkpad X1 Carbon 6th gen with
> Blender on Fedora 34 (which is using the 5.11.y kernels). It applies
> cleanly, and I've been running 5.11.16 with the patch applied and seeing
> no obvious ill effects.
As 5.11.y is now end-of-life, and has been for a week or so, what
kernel(s) would you want this applied to given that 5.12.y is the latest
stable kernel tree?
What prevents you from moving to 5.12.y now?
thanks,
greg k-h
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [CI] drm/i915: Disable atomics in L3 for gen9
2021-05-29 5:29 ` Greg KH
@ 2021-05-29 21:19 ` J. Bruce Fields
0 siblings, 0 replies; 5+ messages in thread
From: J. Bruce Fields @ 2021-05-29 21:19 UTC (permalink / raw)
To: Greg KH; +Cc: intel-gfx, stable, Chris Wilson
On Sat, May 29, 2021 at 07:29:12AM +0200, Greg KH wrote:
> On Fri, May 28, 2021 at 01:25:43PM -0400, J. Bruce Fields wrote:
> > Would it be possible to apply
> >
> > 58586680ffad "drm/i915: Disable atomics in L3 for gen9"
> >
> > to stable kernels?
> >
> > I'm finding it quite easy to crash my Thinkpad X1 Carbon 6th gen with
> > Blender on Fedora 34 (which is using the 5.11.y kernels). It applies
> > cleanly, and I've been running 5.11.16 with the patch applied and seeing
> > no obvious ill effects.
>
> As 5.11.y is now end-of-life, and has been for a week or so, what
> kernel(s) would you want this applied to given that 5.12.y is the latest
> stable kernel tree?
Oh, apologies, I hadn't realized. That's fine, then.
--b.
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] [CI] drm/i915: Disable atomics in L3 for gen9
@ 2021-01-25 21:52 Chris Wilson
0 siblings, 0 replies; 5+ messages in thread
From: Chris Wilson @ 2021-01-25 21:52 UTC (permalink / raw)
To: intel-gfx
Enabling atomic operations in L3 leads to unrecoverable GPU hangs, as
the machine stops responding milliseconds after receipt of the reset
request [GDRT]. By disabling the cached atomics, the hang do not occur
and we presume the GPU would reset normally for similar hangs.
Reported-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110998
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Reviewed-by: Jason Ekstrand <jason@jlesktrand.net>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++++
drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 82e15c8c7a97..7a1d8c68aefb 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1840,6 +1840,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
wa_write_or(wal,
GEN8_L3SQCREG4,
GEN8_LQSC_FLUSH_COHERENT_LINES);
+
+ /* Disable atomics in L3 to prevent unrecoverable hangs */
+ wa_write_masked_or(wal, GEN9_SCRATCH_LNCF1,
+ GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0);
+ wa_write_masked_or(wal, GEN8_L3SQCREG4,
+ GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0);
+ wa_write_masked_or(wal, GEN9_SCRATCH1,
+ EVICTION_PERF_FIX_ENABLE, 0);
}
if (IS_HASWELL(i915)) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8b9bbc6bacb1..fa3866f9ccfc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8222,6 +8222,7 @@ enum {
#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
#define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21)
+#define GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(22)
/* GEN8 chicken */
#define HDC_CHICKEN0 _MMIO(0x7300)
@@ -12104,6 +12105,12 @@ enum skl_power_gate {
#define __GEN11_VCS2_MOCS0 0x10000
#define GEN11_MFX2_MOCS(i) _MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)
+#define GEN9_SCRATCH_LNCF1 _MMIO(0xb008)
+#define GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(0)
+
+#define GEN9_SCRATCH1 _MMIO(0xb11c)
+#define EVICTION_PERF_FIX_ENABLE REG_BIT(8)
+
#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
#define PMFLUSHDONE_LNICRSDROP (1 << 20)
#define PMFLUSH_GAPL3UNBLOCK (1 << 21)
--
2.20.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Intel-gfx] [CI] drm/i915: Disable atomics in L3 for gen9
@ 2020-11-09 20:16 Chris Wilson
0 siblings, 0 replies; 5+ messages in thread
From: Chris Wilson @ 2020-11-09 20:16 UTC (permalink / raw)
To: intel-gfx
Enabling atomic operations in L3 leads to unrecoverable GPU hangs, as
the machine stops responding milliseconds after receipt of the reset
request [GDRT]. By disabling the cached atomics, the hang do not occur
and we presume the GPU would reset normally for similar hangs.
Reported-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110998
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Reviewed-by: Jason Ekstrand <jason@jlesktrand.net>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++++
drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index fed9503a7c4e..dc20b0344f17 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1959,6 +1959,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
wa_write_or(wal,
GEN8_L3SQCREG4,
GEN8_LQSC_FLUSH_COHERENT_LINES);
+
+ /* Disable atomics in L3 to prevent unrecoverable hangs */
+ wa_write_masked_or(wal, GEN9_SCRATCH_LNCF1,
+ GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0);
+ wa_write_masked_or(wal, GEN8_L3SQCREG4,
+ GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0);
+ wa_write_masked_or(wal, GEN9_SCRATCH1,
+ EVICTION_PERF_FIX_ENABLE, 0);
}
if (IS_GEN(i915, 7))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bb0656875697..c9646dca6ed0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8209,6 +8209,7 @@ enum {
#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
#define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21)
+#define GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(22)
/* GEN8 chicken */
#define HDC_CHICKEN0 _MMIO(0x7300)
@@ -12029,6 +12030,12 @@ enum skl_power_gate {
#define __GEN11_VCS2_MOCS0 0x10000
#define GEN11_MFX2_MOCS(i) _MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)
+#define GEN9_SCRATCH_LNCF1 _MMIO(0xb008)
+#define GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(0)
+
+#define GEN9_SCRATCH1 _MMIO(0xb11c)
+#define EVICTION_PERF_FIX_ENABLE REG_BIT(8)
+
#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
#define PMFLUSHDONE_LNICRSDROP (1 << 20)
#define PMFLUSH_GAPL3UNBLOCK (1 << 21)
--
2.20.1
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2021-05-28 17:25 [Intel-gfx] [CI] drm/i915: Disable atomics in L3 for gen9 J. Bruce Fields
2021-05-29 5:29 ` Greg KH
2021-05-29 21:19 ` J. Bruce Fields
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2020-11-09 20:16 Chris Wilson
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