From: Lee Shawn C <shawn.c.lee@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: cooper.chiou@intel.com, william.tseng@intel.com, jani.nikula@intel.com
Subject: [Intel-gfx] [V3 2/7] drm/i915/jsl: program DSI panel GPIOs
Date: Fri, 23 Jul 2021 15:05:43 +0800 [thread overview]
Message-ID: <20210723070548.29315-3-shawn.c.lee@intel.com> (raw)
In-Reply-To: <20210723070548.29315-1-shawn.c.lee@intel.com>
DSI driver should have its own implementation to toggle
gpio pins based on GPIO info coming from VBT sequences.
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: William Tseng <william.tseng@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
---
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 44 +++++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 10 +++++
2 files changed, 53 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index cc93e045a425..dd03e5629ba6 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -43,6 +43,7 @@
#include "intel_display_types.h"
#include "intel_dsi.h"
#include "intel_sideband.h"
+#include "intel_de.h"
#define MIPI_TRANSFER_MODE_SHIFT 0
#define MIPI_VIRTUAL_CHANNEL_SHIFT 1
@@ -354,7 +355,48 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
static void icl_exec_gpio(struct drm_i915_private *dev_priv,
u8 gpio_source, u8 gpio_index, bool value)
{
- drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
+ u32 val;
+
+ switch (gpio_index) {
+ case ICL_GPIO_L_VDDEN_1:
+ val = intel_de_read(dev_priv, ICP_PP_CONTROL(1));
+ if (value)
+ val |= PWR_STATE_TARGET;
+ else
+ val &= ~PWR_STATE_TARGET;
+ intel_de_write(dev_priv, ICP_PP_CONTROL(1), val);
+ break;
+ case ICL_GPIO_L_BKLTEN_1:
+ val = intel_de_read(dev_priv, ICP_PP_CONTROL(1));
+ if (value)
+ val |= BACKLIGHT_ENABLE;
+ else
+ val &= ~BACKLIGHT_ENABLE;
+ intel_de_write(dev_priv, ICP_PP_CONTROL(1), val);
+ break;
+ case ICL_GPIO_DDPA_CTRLCLK_1:
+ val = intel_de_read(dev_priv, GPIO(1));
+ if (value)
+ val |= GPIO_CLOCK_VAL_OUT;
+ else
+ val &= ~GPIO_CLOCK_VAL_OUT;
+ val |= GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_VAL_MASK;
+ intel_de_write(dev_priv, GPIO(1), val);
+ break;
+ case ICL_GPIO_DDPA_CTRLDATA_1:
+ val = intel_de_read(dev_priv, GPIO(1));
+ if (value)
+ val |= GPIO_DATA_VAL_OUT;
+ else
+ val &= ~GPIO_DATA_VAL_OUT;
+ val |= GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT | GPIO_DATA_VAL_MASK;
+ intel_de_write(dev_priv, GPIO(1), val);
+ break;
+ default:
+ /* TODO: Add support for remaining GPIOs */
+ DRM_ERROR("Invalid GPIO number (%d) from VBT\n", gpio_index);
+ break;
+ }
}
static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 943fe485c662..b725234e0e9c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5143,6 +5143,16 @@ enum {
#define _PP_STATUS 0x61200
#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
#define PP_ON REG_BIT(31)
+
+#define _PP_CONTROL_1 0xc7204
+#define _PP_CONTROL_2 0xc7304
+#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
+ _PP_CONTROL_2)
+#define POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
+#define VDD_OVERRIDE_FORCE REG_BIT(3)
+#define BACKLIGHT_ENABLE REG_BIT(2)
+#define PWR_DOWN_ON_RESET REG_BIT(1)
+#define PWR_STATE_TARGET REG_BIT(0)
/*
* Indicates that all dependencies of the panel are on:
*
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-07-23 6:58 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-23 7:05 [Intel-gfx] [V3 0/7] MIPI DSI driver enhancements Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 1/7] drm/i915/dsi: send correct gpio_number on gen11 platform Lee Shawn C
2021-07-23 7:05 ` Lee Shawn C [this message]
2021-08-10 9:31 ` [Intel-gfx] [V3 2/7] drm/i915/jsl: program DSI panel GPIOs Jani Nikula
2021-08-10 10:04 ` Lee, Shawn C
2021-08-10 11:53 ` Jani Nikula
2021-08-11 1:50 ` Lee, Shawn C
2021-08-11 14:10 ` Lee, Shawn C
2021-08-12 14:52 ` Lee, Shawn C
2021-08-12 12:22 ` Jani Nikula
2021-07-23 7:05 ` [Intel-gfx] [V3 3/7] drm/i915/dsi: wait for header and payload credit available Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 4/7] drm/i915/dsi: refine send MIPI DCS command sequence Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 5/7] drm/i915: Get proper min cdclk if vDSC enabled Lee Shawn C
2021-07-23 7:06 ` Kulkarni, Vandita
2021-07-23 7:05 ` [Intel-gfx] [V3 6/7] drm/i915/dsi: Retrieve max brightness level from VBT Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 7/7] drm/i915/dsi: Send proper brightness value via MIPI DCS command Lee Shawn C
2021-07-23 11:14 ` kernel test robot
2021-07-26 6:54 ` [Intel-gfx] [v2] " Lee Shawn C
2021-07-23 7:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for MIPI DSI driver enhancements (rev3) Patchwork
2021-07-23 7:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-23 8:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-23 12:57 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-07-26 6:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for MIPI DSI driver enhancements (rev4) Patchwork
2021-07-26 6:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-26 7:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-26 9:24 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210723070548.29315-3-shawn.c.lee@intel.com \
--to=shawn.c.lee@intel.com \
--cc=cooper.chiou@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jani.nikula@intel.com \
--cc=william.tseng@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).