From: Animesh Manna <animesh.manna@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>,
Imre Deak <imre.deak@intel.com>,
Animesh Manna <animesh.manna@intel.com>
Subject: [Intel-gfx] [PATCH 4/5] drm/i915/dp: fix DG1 and RKL max source rates
Date: Thu, 12 Aug 2021 11:18:05 +0530 [thread overview]
Message-ID: <20210812054806.22745-5-animesh.manna@intel.com> (raw)
In-Reply-To: <20210812054806.22745-1-animesh.manna@intel.com>
From: Jani Nikula <jani.nikula@intel.com>
Combo phy is limited to 5.4 GHz on low-voltage SKUs, but both eDP and DP
can do 8.1 GHz on combo phy.
Bspec: 49182, 49205, 49202
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d27f29477713..e8d2d381c587 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -258,6 +258,18 @@ static int ehl_max_source_rate(struct intel_dp *intel_dp)
return 810000;
}
+static int dg1_max_source_rate(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
+
+ if (intel_phy_is_combo(i915, phy) && is_low_voltage_sku(i915, phy))
+ return 540000;
+
+ return 810000;
+}
+
static void
intel_dp_set_source_rates(struct intel_dp *intel_dp)
{
@@ -290,7 +302,9 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
if (DISPLAY_VER(dev_priv) >= 11) {
source_rates = icl_rates;
size = ARRAY_SIZE(icl_rates);
- if (IS_JSL_EHL(dev_priv))
+ if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+ max_rate = dg1_max_source_rate(intel_dp);
+ else if (IS_JSL_EHL(dev_priv))
max_rate = ehl_max_source_rate(intel_dp);
else
max_rate = icl_max_source_rate(intel_dp);
--
2.29.0
next prev parent reply other threads:[~2021-08-12 6:10 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-12 5:48 [Intel-gfx] [PATCH 0/5] Fix in max source calculation for dp/edp Animesh Manna
2021-08-12 5:48 ` [Intel-gfx] [PATCH 1/5] drm/i915/dp: Fix eDP max rate for display 11+ Animesh Manna
2021-08-12 15:04 ` Imre Deak
2021-08-13 10:34 ` Manna, Animesh
2021-08-12 5:48 ` [Intel-gfx] [PATCH 2/5] drm/i915/dp: fix TGL and ICL max source rates Animesh Manna
2021-08-12 15:12 ` Imre Deak
2021-08-12 5:48 ` [Intel-gfx] [PATCH 3/5] drm/i915/dp: fix EHL/JSL max source rates calculation Animesh Manna
2021-08-12 15:24 ` Imre Deak
2021-08-12 5:48 ` Animesh Manna [this message]
2021-08-12 15:40 ` [Intel-gfx] [PATCH 4/5] drm/i915/dp: fix DG1 and RKL max source rates Imre Deak
2021-08-12 5:48 ` [Intel-gfx] [PATCH 5/5] drm/i915/dp: fix for ADL_P/S and DG2 dp/edp " Animesh Manna
2021-08-12 15:44 ` Imre Deak
2021-08-12 7:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix in max source calculation for dp/edp Patchwork
2021-08-12 7:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-08-12 9:32 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-08-23 6:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix in max source calculation for dp/edp (rev2) Patchwork
2021-08-23 6:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-08-23 8:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-09-01 11:20 ` [Intel-gfx] [PATCH 0/5] Fix in max source calculation for dp/edp Jani Nikula
2021-09-01 16:03 Animesh Manna
2021-09-01 16:04 ` [Intel-gfx] [PATCH 4/5] drm/i915/dp: fix DG1 and RKL max source rates Animesh Manna
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