From: Imre Deak <imre.deak@intel.com>
To: Animesh Manna <animesh.manna@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
"Matt Atwood" <matthew.s.atwood@intel.com>,
"Uma Shankar" <uma.shankar@intel.com>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"José Roberto de Souza" <jose.souza@intel.com>,
"Jani Nikula" <jani.nikula@intel.com>
Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915/dp: Fix eDP max rate for display 11+
Date: Thu, 12 Aug 2021 18:04:00 +0300 [thread overview]
Message-ID: <20210812150400.GC2600583@ideak-desk.fi.intel.com> (raw)
In-Reply-To: <20210812054806.22745-2-animesh.manna@intel.com>
On Thu, Aug 12, 2021 at 11:18:02AM +0530, Animesh Manna wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
>
> intel_dp_set_source_rates() calls intel_dp_is_edp(), which is unsafe to
> use before intel_encoder->type is set. This causes incorrect max source
> rate to be used for display 11+. On EHL and JSL, HBR3 is used instead of
> HBR2, and on the other affected platforms, HBR2 is used instead of HBR3.
>
> Move intel_dp_set_source_rates() to after intel_encoder->type is
> set. Add comment to intel_dp_is_edp() describing unsafe usages. Cleanup
> intel_dp_init_connector() while at it.
>
> Note: The same change was originally added as commit 680c45c767f6
> ("drm/i915/dp: Correctly advertise HBR3 for GEN11+"), but later reverted
> due to issues in CI in commit d3913019602e ("Revert "drm/i915/dp:
> Correctly advertise HBR3 for GEN11+"").
AFAIR, this issue was that TGL started to use TPS4, which somehow broke
link training on the panel connected to that box. But I think TPS4 is
supported on TGL, regardless of the link rate used, so this change looks
ok wrt. that.
As a side-note allowing TPS4 only on ports supporting HBR3 looks
incorrect, I think TPS4 is either supported or not by a platform
regardless of what is the max link rate. Due to that we may stop using
TPS4 on EHL/JSL after this patchset, but I think that can be fixed
separately.
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 28 ++++++++++---------------
> 1 file changed, 11 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 75d4ebc66941..4df56af36b3f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -100,6 +100,8 @@ static const u8 valid_dsc_slicecount[] = {1, 2, 4};
> *
> * If a CPU or PCH DP output is attached to an eDP panel, this function
> * will return true, and false otherwise.
> + *
> + * This function is not safe to use prior to encoder type being set.
> */
> bool intel_dp_is_edp(struct intel_dp *intel_dp)
> {
> @@ -5294,8 +5296,6 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
> intel_encoder->base.name))
> return false;
>
> - intel_dp_set_source_rates(intel_dp);
> -
> intel_dp->reset_link_params = true;
> intel_dp->pps.pps_pipe = INVALID_PIPE;
> intel_dp->pps.active_pipe = INVALID_PIPE;
> @@ -5311,28 +5311,22 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
> */
> drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
> type = DRM_MODE_CONNECTOR_eDP;
> + intel_encoder->type = INTEL_OUTPUT_EDP;
> +
> + /* eDP only on port B and/or C on vlv/chv */
> + if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
> + IS_CHERRYVIEW(dev_priv)) &&
> + port != PORT_B && port != PORT_C))
> + return false;
> } else {
> type = DRM_MODE_CONNECTOR_DisplayPort;
> }
>
> + intel_dp_set_source_rates(intel_dp);
> +
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
>
> - /*
> - * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
> - * for DP the encoder type can be set by the caller to
> - * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
> - */
> - if (type == DRM_MODE_CONNECTOR_eDP)
> - intel_encoder->type = INTEL_OUTPUT_EDP;
> -
> - /* eDP only on port B and/or C on vlv/chv */
> - if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
> - IS_CHERRYVIEW(dev_priv)) &&
> - intel_dp_is_edp(intel_dp) &&
> - port != PORT_B && port != PORT_C))
> - return false;
> -
> drm_dbg_kms(&dev_priv->drm,
> "Adding %s connector on [ENCODER:%d:%s]\n",
> type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
> --
> 2.29.0
>
next prev parent reply other threads:[~2021-08-12 15:04 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-12 5:48 [Intel-gfx] [PATCH 0/5] Fix in max source calculation for dp/edp Animesh Manna
2021-08-12 5:48 ` [Intel-gfx] [PATCH 1/5] drm/i915/dp: Fix eDP max rate for display 11+ Animesh Manna
2021-08-12 15:04 ` Imre Deak [this message]
2021-08-13 10:34 ` Manna, Animesh
2021-08-12 5:48 ` [Intel-gfx] [PATCH 2/5] drm/i915/dp: fix TGL and ICL max source rates Animesh Manna
2021-08-12 15:12 ` Imre Deak
2021-08-12 5:48 ` [Intel-gfx] [PATCH 3/5] drm/i915/dp: fix EHL/JSL max source rates calculation Animesh Manna
2021-08-12 15:24 ` Imre Deak
2021-08-12 5:48 ` [Intel-gfx] [PATCH 4/5] drm/i915/dp: fix DG1 and RKL max source rates Animesh Manna
2021-08-12 15:40 ` Imre Deak
2021-08-12 5:48 ` [Intel-gfx] [PATCH 5/5] drm/i915/dp: fix for ADL_P/S and DG2 dp/edp " Animesh Manna
2021-08-12 15:44 ` Imre Deak
2021-08-12 7:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix in max source calculation for dp/edp Patchwork
2021-08-12 7:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-08-12 9:32 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-08-23 6:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix in max source calculation for dp/edp (rev2) Patchwork
2021-08-23 6:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-08-23 8:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-09-01 11:20 ` [Intel-gfx] [PATCH 0/5] Fix in max source calculation for dp/edp Jani Nikula
2021-09-01 16:03 Animesh Manna
2021-09-01 16:03 ` [Intel-gfx] [PATCH 1/5] drm/i915/dp: Fix eDP max rate for display 11+ Animesh Manna
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