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From: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>, CQ Tang <cq.tang@intel.com>
Subject: [Intel-gfx] [PATCH 1/5] drm/i915/gt: Add support of mocs propagation
Date: Thu, 12 Aug 2021 12:17:54 +0530	[thread overview]
Message-ID: <20210812064758.4102925-2-ayaz.siddiqui@intel.com> (raw)
In-Reply-To: <20210812064758.4102925-1-ayaz.siddiqui@intel.com>

Now there are lots of Command and registers that require mocs index
programming.
So propagating mocs_index from mocs to gt so that it can be
used directly without having platform-specific checks.

Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
Cc: CQ Tang<cq.tang@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_types.h |  4 ++++
 drivers/gpu/drm/i915/gt/intel_mocs.c     | 10 ++++++++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index a81e21bf1bd1a..88601a2d2c229 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -192,6 +192,10 @@ struct intel_gt {
 
 		unsigned long mslice_mask;
 	} info;
+
+	struct i915_mocs_index_gt {
+		u8 uc_index;
+	} mocs;
 };
 
 enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 582c4423b95d6..c66e226e71499 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -22,6 +22,7 @@ struct drm_i915_mocs_table {
 	unsigned int size;
 	unsigned int n_entries;
 	const struct drm_i915_mocs_entry *table;
+	u8 uc_index;
 };
 
 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
@@ -340,6 +341,8 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
 {
 	unsigned int flags;
 
+	memset(table, 0, sizeof(struct drm_i915_mocs_table));
+
 	if (IS_DG1(i915)) {
 		table->size = ARRAY_SIZE(dg1_mocs_table);
 		table->table = dg1_mocs_table;
@@ -504,6 +507,12 @@ static u32 global_mocs_offset(void)
 	return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));
 }
 
+static void set_mocs_index(struct intel_gt *gt,
+			    struct drm_i915_mocs_table *table)
+{
+	gt->mocs.uc_index = table->uc_index;
+}
+
 void intel_mocs_init(struct intel_gt *gt)
 {
 	struct drm_i915_mocs_table table;
@@ -515,6 +524,7 @@ void intel_mocs_init(struct intel_gt *gt)
 	flags = get_mocs_settings(gt->i915, &table);
 	if (flags & HAS_GLOBAL_MOCS)
 		__init_mocs_table(gt->uncore, &table, global_mocs_offset());
+	set_mocs_index(gt, &table);
 }
 
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
-- 
2.26.2


  reply	other threads:[~2021-08-12  6:51 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-12  6:47 [Intel-gfx] [PATCH 0/5] drm/i915/gt: Initialize unused MOCS entries to L3_WB Ayaz A Siddiqui
2021-08-12  6:47 ` Ayaz A Siddiqui [this message]
2021-08-12  6:47 ` [Intel-gfx] [PATCH 2/5] drm/i915/gt: Use cmd_cctl override for platforms >= gen12 Ayaz A Siddiqui
2021-08-13  7:53   ` Jani Nikula
2021-08-12  6:47 ` [Intel-gfx] [PATCH 3/5] drm/i915/gt: Set BLIT_CCTL reg to un-cached Ayaz A Siddiqui
2021-08-12  6:47 ` [Intel-gfx] [PATCH 4/5] drm/i915/gt: Initialize unused MOCS entries with device specific values Ayaz A Siddiqui
2021-08-12  6:47 ` [Intel-gfx] [PATCH 5/5] drm/i95/adl: Define MOCS table for Alderlake Ayaz A Siddiqui
2021-08-12  9:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Initialize unused MOCS entries to L3_WB Patchwork
2021-08-13  7:54   ` Jani Nikula
2021-08-18  9:50     ` Siddiqui, Ayaz A
2021-08-12  9:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-12 10:28 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

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