From: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH 5/5] drm/i95/adl: Define MOCS table for Alderlake
Date: Thu, 12 Aug 2021 12:17:58 +0530 [thread overview]
Message-ID: <20210812064758.4102925-6-ayaz.siddiqui@intel.com> (raw)
In-Reply-To: <20210812064758.4102925-1-ayaz.siddiqui@intel.com>
In order to program unused and reserved mocs entries to L3_WB,
we need to create a separate mocs table for alderlake.
This patch will also covers wa_1608975824.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 40 +++++++++++++++++++++++++++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 02610dc1cf2c3..a3123fecb887f 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -322,6 +322,38 @@ static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
MOCS_ENTRY(62, 0, L3_1_UC),
MOCS_ENTRY(63, 0, L3_1_UC),
};
+static const struct drm_i915_mocs_entry adl_mocs_table[] = {
+ /* wa_1608975824 */
+ MOCS_ENTRY(0,
+ LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+
+ GEN11_MOCS_ENTRIES,
+ /* Implicitly enable L1 - HDC:L1 + L3 + LLC */
+ MOCS_ENTRY(48,
+ LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_3_WB),
+ /* Implicitly enable L1 - HDC:L1 + L3 */
+ MOCS_ENTRY(49,
+ LE_1_UC | LE_TC_1_LLC,
+ L3_3_WB),
+ /* Implicitly enable L1 - HDC:L1 + LLC */
+ MOCS_ENTRY(50,
+ LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_1_UC),
+ /* Implicitly enable L1 - HDC:L1 */
+ MOCS_ENTRY(51,
+ LE_1_UC | LE_TC_1_LLC,
+ L3_1_UC),
+ /* HW Special Case (CCS) */
+ MOCS_ENTRY(60,
+ LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+ L3_1_UC),
+ /* HW Special Case (Displayable) */
+ MOCS_ENTRY(61,
+ LE_1_UC | LE_TC_1_LLC,
+ L3_3_WB),
+};
enum {
HAS_GLOBAL_MOCS = BIT(0),
@@ -444,7 +476,13 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
memset(table, 0, sizeof(struct drm_i915_mocs_table));
- if (IS_DG1(i915)) {
+ if (IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) {
+ table->size = ARRAY_SIZE(adl_mocs_table);
+ table->table = adl_mocs_table;
+ table->n_entries = GEN9_NUM_MOCS_ENTRIES;
+ table->uc_index = 3;
+ table->unused_entries_index = 2;
+ } else if (IS_DG1(i915)) {
table->size = ARRAY_SIZE(dg1_mocs_table);
table->table = dg1_mocs_table;
table->n_entries = GEN9_NUM_MOCS_ENTRIES;
--
2.26.2
next prev parent reply other threads:[~2021-08-12 6:52 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-12 6:47 [Intel-gfx] [PATCH 0/5] drm/i915/gt: Initialize unused MOCS entries to L3_WB Ayaz A Siddiqui
2021-08-12 6:47 ` [Intel-gfx] [PATCH 1/5] drm/i915/gt: Add support of mocs propagation Ayaz A Siddiqui
2021-08-12 6:47 ` [Intel-gfx] [PATCH 2/5] drm/i915/gt: Use cmd_cctl override for platforms >= gen12 Ayaz A Siddiqui
2021-08-13 7:53 ` Jani Nikula
2021-08-12 6:47 ` [Intel-gfx] [PATCH 3/5] drm/i915/gt: Set BLIT_CCTL reg to un-cached Ayaz A Siddiqui
2021-08-12 6:47 ` [Intel-gfx] [PATCH 4/5] drm/i915/gt: Initialize unused MOCS entries with device specific values Ayaz A Siddiqui
2021-08-12 6:47 ` Ayaz A Siddiqui [this message]
2021-08-12 9:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Initialize unused MOCS entries to L3_WB Patchwork
2021-08-13 7:54 ` Jani Nikula
2021-08-18 9:50 ` Siddiqui, Ayaz A
2021-08-12 9:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-12 10:28 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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