From: Lee Shawn C <shawn.c.lee@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com, ville.syrjala@linux.intel.com,
vandita.kulkarni@intel.com, cooper.chiou@intel.com,
william.tseng@intel.com, Lee Shawn C <shawn.c.lee@intel.com>,
Jani Nikula <jani.nikula@linux.intel.com>
Subject: [Intel-gfx] [v4 5/7] drm/i915: Get proper min cdclk if vDSC enabled
Date: Thu, 12 Aug 2021 23:42:35 +0800 [thread overview]
Message-ID: <20210812154237.13911-6-shawn.c.lee@intel.com> (raw)
In-Reply-To: <20210812154237.13911-1-shawn.c.lee@intel.com>
VDSC engine can process only 1 pixel per Cd clock. In case
VDSC is used and max slice count == 1, max supported pixel
clock should be 100% of CD clock. Then do min_cdclk and
pixel clock comparison to get proper min cdclk.
v2:
- Check for dsc enable and slice count ==1 then allow to
double confirm min cdclk value.
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: William Tseng <william.tseng@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 34fa4130d5c4..9aec17b33819 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2139,6 +2139,16 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
/* Account for additional needs from the planes */
min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
+ /*
+ * VDSC engine can process only 1 pixel per Cd clock.
+ * In case VDSC is used and max slice count == 1,
+ * max supported pixel clock should be 100% of CD clock.
+ * Then do min_cdclk and pixel clock comparison to get cdclk.
+ */
+ if (crtc_state->dsc.compression_enable &&
+ crtc_state->dsc.slice_count == 1)
+ min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
+
/*
* HACK. Currently for TGL platforms we calculate
* min_cdclk initially based on pixel_rate divided
--
2.17.1
next prev parent reply other threads:[~2021-08-12 15:41 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-12 15:42 [Intel-gfx] [v4 0/7] MIPI DSI driver enhancements Lee Shawn C
2021-08-12 15:42 ` [Intel-gfx] [v4 1/7] drm/i915/dsi: send correct gpio_number on gen11 platform Lee Shawn C
2021-08-12 15:42 ` [Intel-gfx] [v4 2/7] drm/i915/jsl: program DSI panel GPIOs Lee Shawn C
2021-08-23 12:06 ` Jani Nikula
2021-08-12 15:42 ` [Intel-gfx] [v4 3/7] drm/i915/dsi: wait for header and payload credit available Lee Shawn C
2021-08-26 5:54 ` Kulkarni, Vandita
2021-08-12 15:42 ` [Intel-gfx] [v4 4/7] drm/i915/dsi: refine send MIPI DCS command sequence Lee Shawn C
2021-08-23 9:45 ` Kulkarni, Vandita
2021-08-12 15:42 ` Lee Shawn C [this message]
2021-08-23 12:19 ` [Intel-gfx] [v4 5/7] drm/i915: Get proper min cdclk if vDSC enabled Kulkarni, Vandita
2021-08-12 15:42 ` [Intel-gfx] [v4 6/7] drm/i915/dsi: Retrieve max brightness level from VBT Lee Shawn C
2021-08-23 8:46 ` Kulkarni, Vandita
2021-08-23 9:03 ` Lee, Shawn C
2021-08-23 12:10 ` Kulkarni, Vandita
2021-08-24 14:00 ` [Intel-gfx] [PATCH] " Lee Shawn C
2021-08-24 14:33 ` Jani Nikula
2021-08-24 15:53 ` Lee, Shawn C
2021-08-12 15:42 ` [Intel-gfx] [v4 7/7] drm/i915/dsi: Send proper brightness value via MIPI DCS command Lee Shawn C
2021-08-12 23:22 ` kernel test robot
2021-08-13 2:46 ` [Intel-gfx] [v4] " Lee Shawn C
2021-08-18 11:10 ` Jani Nikula
2021-08-18 14:58 ` Lee, Shawn C
2021-08-19 11:16 ` [Intel-gfx] [v4] drm/i915/dsi: Read/write " Lee Shawn C
2021-08-12 20:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for MIPI DSI driver enhancements (rev5) Patchwork
2021-08-12 20:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-12 21:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-08-13 2:29 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-08-13 2:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for MIPI DSI driver enhancements (rev6) Patchwork
2021-08-13 2:58 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-13 3:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-08-13 7:56 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-08-19 11:45 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for MIPI DSI driver enhancements (rev7) Patchwork
2021-08-19 11:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-19 12:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-08-19 13:41 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-08-24 19:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for MIPI DSI driver enhancements (rev8) Patchwork
2021-08-24 19:12 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-24 19:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-08-25 1:22 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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