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From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, drmdevel@freedesktop.org
Cc: <daniel.vetter@ffwll.ch>
Subject: [Intel-gfx] [PATCH 08/21] drm/i915/selftests: Fix memory corruption in live_lrc_isolation
Date: Sun, 15 Aug 2021 13:15:46 -0700	[thread overview]
Message-ID: <20210815201559.1150-9-matthew.brost@intel.com> (raw)
In-Reply-To: <20210815201559.1150-1-matthew.brost@intel.com>

GuC submission has exposed an existing memory corruption in
live_lrc_isolation. We believe that some writes to the watchdog offsets
in the LRC (0x178 & 0x17c) can result in trashing of portions of the
address space. With GuC submission there are additional objects which
can move the context redzone into the space that is trashed. To
workaround this avoid poisoning the watchdog.

v2:
 (Daniel Vetter)
  - Add VLK ref in code to workaround

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/i915/gt/selftest_lrc.c | 29 +++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index b0977a3b699b..cdc6ae48a1e1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -1074,6 +1074,32 @@ record_registers(struct intel_context *ce,
 	goto err_after;
 }
 
+static u32 safe_offset(u32 offset, u32 reg)
+{
+	/* XXX skip testing of watchdog - VLK-22772 */
+	if (offset == 0x178 || offset == 0x17c)
+		reg = 0;
+
+	return reg;
+}
+
+static int get_offset_mask(struct intel_engine_cs *engine)
+{
+	if (GRAPHICS_VER(engine->i915) < 12)
+		return 0xfff;
+
+	switch (engine->class) {
+	default:
+	case RENDER_CLASS:
+		return 0x07ff;
+	case COPY_ENGINE_CLASS:
+		return 0x0fff;
+	case VIDEO_DECODE_CLASS:
+	case VIDEO_ENHANCEMENT_CLASS:
+		return 0x3fff;
+	}
+}
+
 static struct i915_vma *load_context(struct intel_context *ce, u32 poison)
 {
 	struct i915_vma *batch;
@@ -1117,7 +1143,8 @@ static struct i915_vma *load_context(struct intel_context *ce, u32 poison)
 		len = (len + 1) / 2;
 		*cs++ = MI_LOAD_REGISTER_IMM(len);
 		while (len--) {
-			*cs++ = hw[dw];
+			*cs++ = safe_offset(hw[dw] & get_offset_mask(ce->engine),
+					    hw[dw]);
 			*cs++ = poison;
 			dw += 2;
 		}
-- 
2.32.0


  parent reply	other threads:[~2021-08-15 20:21 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-15 20:15 [Intel-gfx] [PATCH 00/21] Clean up GuC CI failures, simplify locking, and kernel DOC Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 01/21] drm/i915/guc: Fix blocked context accounting Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 02/21] drm/i915/guc: outstanding G2H accounting Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 03/21] drm/i915/guc: Unwind context requests in reverse order Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 04/21] drm/i915/guc: Don't drop ce->guc_active.lock when unwinding context Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 05/21] drm/i915/guc: Workaround reset G2H is received after schedule done G2H Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 06/21] drm/i915/selftests: Add a cancel request selftest that triggers a reset Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 07/21] drm/i915/guc: Don't enable scheduling on a banned context, guc_id invalid, not registered Matthew Brost
2021-08-15 20:15 ` Matthew Brost [this message]
2021-08-15 20:15 ` [Intel-gfx] [PATCH 09/21] drm/i915/selftests: Add initial GuC selftest for scrubbing lost G2H Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 10/21] drm/i915/guc: Take context ref when cancelling request Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 11/21] drm/i915/guc: Don't touch guc_state.sched_state without a lock Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 12/21] drm/i915/guc: Reset LRC descriptor if register returns -ENODEV Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 13/21] drm/i915: Allocate error capture in atomic context Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 14/21] drm/i915/guc: Flush G2H work queue during reset Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 15/21] drm/i915/guc: Release submit fence from an IRQ Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 16/21] drm/i915/guc: Move guc_blocked fence to struct guc_state Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 17/21] drm/i915/guc: Rework and simplify locking Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 18/21] drm/i915/guc: Proper xarray usage for contexts_lookup Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 19/21] drm/i915/guc: Drop pin count check trick between sched_disable and re-pin Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 20/21] drm/i915/guc: Move GuC priority fields in context under guc_active Matthew Brost
2021-08-15 20:15 ` [Intel-gfx] [PATCH 21/21] drm/i915/guc: Add GuC kernel doc Matthew Brost
2021-08-15 20:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Clean up GuC CI failures, simplify locking, and kernel DOC Patchwork
2021-08-15 20:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-15 21:15 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-08-15 21:54   ` Matthew Brost

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