From: Ramalingam C <ramalingam.c@intel.com>
To: "Kattamanchi, JaswanthX" <jaswanthx.kattamanchi@intel.com>
Cc: "Siddiqui, Ayaz A" <ayaz.siddiqui@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"Vudum, Lakshminarayana" <lakshminarayana.vudum@intel.com>,
"Szwichtenberg, Radoslaw" <radoslaw.szwichtenberg@intel.com>,
"Meena, Mahesh" <mahesh.meena@intel.com>,
"De Marchi, Lucas" <lucas.demarchi@intel.com>,
"Roper, Matthew D" <matthew.d.roper@intel.com>,
"Illipilli, TejasreeX" <tejasreex.illipilli@intel.com>,
"Naramasetti,
LaxminarayanaX" <laxminarayanax.naramasetti@intel.com>
Subject: Re: [Intel-gfx] [PATCH V5 0/5] drm/i915/gt: Initialize unused MOCS entries to L3_WB
Date: Fri, 3 Sep 2021 20:50:13 +0530 [thread overview]
Message-ID: <20210903152011.GA32355@intel.com> (raw)
In-Reply-To: <DM6PR11MB3355DB44CD246075282CCBCAEECF9@DM6PR11MB3355.namprd11.prod.outlook.com>
Thanks Ayaz for the patches and all the review efforts. Merged the patches.
-Ram
On 2021-09-03 at 19:11:24 +0530, Kattamanchi, JaswanthX wrote:
> Hi Ayaz,
>
> Re-reported
>
> Patch : https://patchwork.freedesktop.org/series/94315/
>
> Regards,
> Jaswanth Kattamanchi
>
> -----Original Message-----
> From: Siddiqui, Ayaz A <ayaz.siddiqui@intel.com>
> Sent: Friday, September 3, 2021 6:29 PM
> To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>; Illipilli, TejasreeX <tejasreex.illipilli@intel.com>; Kattamanchi, JaswanthX <jaswanthx.kattamanchi@intel.com>
> Cc: Szwichtenberg, Radoslaw <radoslaw.szwichtenberg@intel.com>; Meena, Mahesh <mahesh.meena@intel.com>; C, Ramalingam <ramalingam.c@intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>
> Subject: RE: [PATCH V5 0/5] drm/i915/gt: Initialize unused MOCS entries to L3_WB
>
> Hi,
> I see a failure reported on IGT-CI for this series for SKL,
>
> igt@gem_ctx_isolation@preservation-s3@rcs0:
> shard-skl: PASS -> DMESG-WARN
>
> Changes set in this series are applicable for gen12 onward platforms except TGL/RKL.
>
> So above failure look like a false alarm to me.
>
> Regards
> -Ayaz
>
> > -----Original Message-----
> > From: Siddiqui, Ayaz A <ayaz.siddiqui@intel.com>
> > Sent: Friday, September 3, 2021 2:52 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Siddiqui, Ayaz A <ayaz.siddiqui@intel.com>
> > Subject: [PATCH V5 0/5] drm/i915/gt: Initialize unused MOCS entries to
> > L3_WB
> >
> > Gen >= 12 onwards MOCS table doesn't have a setting for PTE so
> > I915_MOCS_PTE is not a valid index and it will have different MOCS
> > values are based on the platform.
> >
> > To detect these kinds of misprogramming, all the unspecified and
> > reserved MOCS indexes are set to WB_L3. TGL/RKL unspecified MOCS
> > indexes are pointing to L3 UC are kept intact to avoid API break.
> >
> > This series also contains patches to program BLIT_CCTL and CMD_CCTL
> > registers to UC.
> > Since we are quite late to update MOCS table for TGL so added a new
> > MOCS table for ADL family.
> >
> > V2:
> > 1. Added CMD_CCTL to GUC regset list so that it can be restored
> > after engine reset.
> > 2. Checkpatch warning removal.
> >
> > V3:
> > 1. Changed implementation to have a framework only.
> > 2. Added register type for proper application.
> > 3. moved CMD_CCTL programming to a separate patch.
> > 4. Added L3CC initialization during gt reset so that MOCS indexes are
> > set before GuC initialization.
> > 5. Removed Renderer check for L3CC verification in selftest.
> >
> > V4:
> > 1. Moved register programming in Workaorund section as fake workaround.
> > 2. Removed seperate ADL mocs table, new logic is to set unused index as
> > L3_WB for gen12 platform except TGL/RKL.
> >
> > V5:
> > 1. Final version reviewed by Matt Roper 2. Removed "drm/i915/selftest:
> > Remove Renderer class check for l3cc table read" form series,
> > this patch will be taken care of in different series.
> >
> > Ayaz A Siddiqui (4):
> > drm/i915/gt: Add support of mocs propagation
> > drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward
> > drm/i915/gt: Set BLIT_CCTL reg to un-cached
> > drm/i915/gt: Initialize unused MOCS entries with device specific
> > values
> >
> > Sreedhar Telukuntla (1):
> > drm/i915/gt: Initialize L3CC table in mocs init
> >
> > drivers/gpu/drm/i915/gt/intel_gt.c | 2 +
> > drivers/gpu/drm/i915/gt/intel_gt_types.h | 4 ++
> > drivers/gpu/drm/i915/gt/intel_mocs.c | 72 ++++++++++++++-------
> > drivers/gpu/drm/i915/gt/intel_mocs.h | 1 +
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 70
> > +++++++++++++++++++-
> > drivers/gpu/drm/i915/i915_reg.h | 26 ++++++++
> > 6 files changed, 151 insertions(+), 24 deletions(-)
> >
> > --
> > 2.26.2
>
next prev parent reply other threads:[~2021-09-03 15:18 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-03 9:21 [Intel-gfx] [PATCH V5 0/5] drm/i915/gt: Initialize unused MOCS entries to L3_WB Ayaz A Siddiqui
2021-09-03 9:21 ` [Intel-gfx] [PATCH V5 1/5] drm/i915/gt: Add support of mocs propagation Ayaz A Siddiqui
2021-09-15 3:39 ` Matt Roper
2021-09-16 7:13 ` Siddiqui, Ayaz A
2021-09-03 9:21 ` [Intel-gfx] [PATCH V5 2/5] drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward Ayaz A Siddiqui
2021-09-03 9:21 ` [Intel-gfx] [PATCH V5 3/5] drm/i915/gt: Set BLIT_CCTL reg to un-cached Ayaz A Siddiqui
2021-09-03 9:21 ` [Intel-gfx] [PATCH V5 4/5] drm/i915/gt: Initialize unused MOCS entries with device specific values Ayaz A Siddiqui
2021-09-03 9:21 ` [Intel-gfx] [PATCH V5 5/5] drm/i915/gt: Initialize L3CC table in mocs init Ayaz A Siddiqui
2021-09-03 9:56 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/gt: Initialize unused MOCS entries to L3_WB Patchwork
2021-09-03 10:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-03 11:37 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-03 12:58 ` [Intel-gfx] [PATCH V5 0/5] " Siddiqui, Ayaz A
2021-09-03 13:41 ` Kattamanchi, JaswanthX
2021-09-03 15:20 ` Ramalingam C [this message]
2021-09-03 13:35 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
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