* [Intel-gfx] [PATCH 01/10] drm/i915: move display funcs into a display struct.
2021-09-06 3:43 [Intel-gfx] [RFC PATCH 00/10] refactor display structs a little bit Dave Airlie
@ 2021-09-06 3:43 ` Dave Airlie
2021-09-06 8:18 ` Jani Nikula
2021-09-06 3:43 ` [Intel-gfx] [PATCH 02/10] drm/i915/display: move cdclk info into display Dave Airlie
` (11 subsequent siblings)
12 siblings, 1 reply; 20+ messages in thread
From: Dave Airlie @ 2021-09-06 3:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
This is the first step in an idea to refactor the display code
into a bit more of a corner.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_audio.c | 24 +--
drivers/gpu/drm/i915/display/intel_cdclk.c | 148 +++++++++---------
drivers/gpu/drm/i915/display/intel_color.c | 64 ++++----
drivers/gpu/drm/i915/display/intel_display.c | 110 ++++++-------
.../drm/i915/display/intel_display_power.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 16 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 6 +-
drivers/gpu/drm/i915/display/intel_hotplug.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 10 +-
drivers/gpu/drm/i915/i915_irq.c | 14 +-
drivers/gpu/drm/i915/intel_pm.c | 104 ++++++------
11 files changed, 253 insertions(+), 249 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 532237588511..fd56191c8a68 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -848,8 +848,8 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
- if (dev_priv->display.audio_codec_enable)
- dev_priv->display.audio_codec_enable(encoder,
+ if (dev_priv->display.funcs.audio_codec_enable)
+ dev_priv->display.funcs.audio_codec_enable(encoder,
crtc_state,
conn_state);
@@ -893,8 +893,8 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
enum port port = encoder->port;
enum pipe pipe = crtc->pipe;
- if (dev_priv->display.audio_codec_disable)
- dev_priv->display.audio_codec_disable(encoder,
+ if (dev_priv->display.funcs.audio_codec_disable)
+ dev_priv->display.funcs.audio_codec_disable(encoder,
old_crtc_state,
old_conn_state);
@@ -922,17 +922,17 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
{
if (IS_G4X(dev_priv)) {
- dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
- dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
+ dev_priv->display.funcs.audio_codec_enable = g4x_audio_codec_enable;
+ dev_priv->display.funcs.audio_codec_disable = g4x_audio_codec_disable;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
- dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
+ dev_priv->display.funcs.audio_codec_enable = ilk_audio_codec_enable;
+ dev_priv->display.funcs.audio_codec_disable = ilk_audio_codec_disable;
} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
- dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
- dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
+ dev_priv->display.funcs.audio_codec_enable = hsw_audio_codec_enable;
+ dev_priv->display.funcs.audio_codec_disable = hsw_audio_codec_disable;
} else if (HAS_PCH_SPLIT(dev_priv)) {
- dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
- dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
+ dev_priv->display.funcs.audio_codec_enable = ilk_audio_codec_enable;
+ dev_priv->display.funcs.audio_codec_disable = ilk_audio_codec_disable;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 34fa4130d5c4..becbf0fc4c4d 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1466,7 +1466,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
* at least what the CDCLK frequency requires.
*/
cdclk_config->voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_config->cdclk);
+ dev_priv->display.funcs.calc_voltage_level(cdclk_config->cdclk);
}
static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
@@ -1777,7 +1777,7 @@ static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
cdclk_config.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
+ dev_priv->display.funcs.calc_voltage_level(cdclk_config.cdclk);
bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
}
@@ -1789,7 +1789,7 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
cdclk_config.cdclk = cdclk_config.bypass;
cdclk_config.vco = 0;
cdclk_config.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
+ dev_priv->display.funcs.calc_voltage_level(cdclk_config.cdclk);
bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
}
@@ -1932,7 +1932,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
return;
- if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.set_cdclk))
+ if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.set_cdclk))
return;
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
@@ -1956,7 +1956,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
&dev_priv->gmbus_mutex);
}
- dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+ dev_priv->display.funcs.set_cdclk(dev_priv, cdclk_config, pipe);
for_each_intel_dp(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2414,7 +2414,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
cdclk_state->logical.cdclk = cdclk;
cdclk_state->logical.voltage_level =
max_t(int, min_voltage_level,
- dev_priv->display.calc_voltage_level(cdclk));
+ dev_priv->display.funcs.calc_voltage_level(cdclk));
if (!cdclk_state->active_pipes) {
cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
@@ -2423,7 +2423,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
cdclk_state->actual.vco = vco;
cdclk_state->actual.cdclk = cdclk;
cdclk_state->actual.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk);
+ dev_priv->display.funcs.calc_voltage_level(cdclk);
} else {
cdclk_state->actual = cdclk_state->logical;
}
@@ -2515,7 +2515,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
new_cdclk_state->active_pipes =
intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
- ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
+ ret = dev_priv->display.funcs.modeset_calc_cdclk(new_cdclk_state);
if (ret)
return ret;
@@ -2695,7 +2695,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
*/
void intel_update_cdclk(struct drm_i915_private *dev_priv)
{
- dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
+ dev_priv->display.funcs.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
/*
* 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
@@ -2852,119 +2852,119 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
if (IS_DG2(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->display.funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->display.funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->display.funcs.calc_voltage_level = tgl_calc_voltage_level;
dev_priv->cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->display.funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->display.funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->display.funcs.calc_voltage_level = tgl_calc_voltage_level;
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->cdclk.table = adlp_a_step_cdclk_table;
else
dev_priv->cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->display.funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->display.funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->display.funcs.calc_voltage_level = tgl_calc_voltage_level;
dev_priv->cdclk.table = rkl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 12) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->display.funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->display.funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->display.funcs.calc_voltage_level = tgl_calc_voltage_level;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (IS_JSL_EHL(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
+ dev_priv->display.funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->display.funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->display.funcs.calc_voltage_level = ehl_calc_voltage_level;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 11) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
+ dev_priv->display.funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->display.funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->display.funcs.calc_voltage_level = icl_calc_voltage_level;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = bxt_calc_voltage_level;
+ dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->display.funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->display.funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->display.funcs.calc_voltage_level = bxt_calc_voltage_level;
if (IS_GEMINILAKE(dev_priv))
dev_priv->cdclk.table = glk_cdclk_table;
else
dev_priv->cdclk.table = bxt_cdclk_table;
} else if (DISPLAY_VER(dev_priv) == 9) {
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.set_cdclk = skl_set_cdclk;
- dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
+ dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->display.funcs.set_cdclk = skl_set_cdclk;
+ dev_priv->display.funcs.modeset_calc_cdclk = skl_modeset_calc_cdclk;
} else if (IS_BROADWELL(dev_priv)) {
- dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
- dev_priv->display.set_cdclk = bdw_set_cdclk;
- dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
+ dev_priv->display.funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
+ dev_priv->display.funcs.set_cdclk = bdw_set_cdclk;
+ dev_priv->display.funcs.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
} else if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
- dev_priv->display.set_cdclk = chv_set_cdclk;
- dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
+ dev_priv->display.funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
+ dev_priv->display.funcs.set_cdclk = chv_set_cdclk;
+ dev_priv->display.funcs.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
} else if (IS_VALLEYVIEW(dev_priv)) {
- dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
- dev_priv->display.set_cdclk = vlv_set_cdclk;
- dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
+ dev_priv->display.funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
+ dev_priv->display.funcs.set_cdclk = vlv_set_cdclk;
+ dev_priv->display.funcs.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
} else {
- dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
+ dev_priv->display.funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
+ dev_priv->display.funcs.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
}
if (DISPLAY_VER(dev_priv) >= 10 || IS_BROXTON(dev_priv))
- dev_priv->display.get_cdclk = bxt_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = bxt_get_cdclk;
else if (DISPLAY_VER(dev_priv) == 9)
- dev_priv->display.get_cdclk = skl_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = skl_get_cdclk;
else if (IS_BROADWELL(dev_priv))
- dev_priv->display.get_cdclk = bdw_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = bdw_get_cdclk;
else if (IS_HASWELL(dev_priv))
- dev_priv->display.get_cdclk = hsw_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = hsw_get_cdclk;
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- dev_priv->display.get_cdclk = vlv_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = vlv_get_cdclk;
else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
- dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = fixed_400mhz_get_cdclk;
else if (IS_IRONLAKE(dev_priv))
- dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = fixed_450mhz_get_cdclk;
else if (IS_GM45(dev_priv))
- dev_priv->display.get_cdclk = gm45_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = gm45_get_cdclk;
else if (IS_G45(dev_priv))
- dev_priv->display.get_cdclk = g33_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = g33_get_cdclk;
else if (IS_I965GM(dev_priv))
- dev_priv->display.get_cdclk = i965gm_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = i965gm_get_cdclk;
else if (IS_I965G(dev_priv))
- dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = fixed_400mhz_get_cdclk;
else if (IS_PINEVIEW(dev_priv))
- dev_priv->display.get_cdclk = pnv_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = pnv_get_cdclk;
else if (IS_G33(dev_priv))
- dev_priv->display.get_cdclk = g33_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = g33_get_cdclk;
else if (IS_I945GM(dev_priv))
- dev_priv->display.get_cdclk = i945gm_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = i945gm_get_cdclk;
else if (IS_I945G(dev_priv))
- dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = fixed_400mhz_get_cdclk;
else if (IS_I915GM(dev_priv))
- dev_priv->display.get_cdclk = i915gm_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = i915gm_get_cdclk;
else if (IS_I915G(dev_priv))
- dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = fixed_333mhz_get_cdclk;
else if (IS_I865G(dev_priv))
- dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = fixed_266mhz_get_cdclk;
else if (IS_I85X(dev_priv))
- dev_priv->display.get_cdclk = i85x_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = i85x_get_cdclk;
else if (IS_I845G(dev_priv))
- dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = fixed_200mhz_get_cdclk;
else if (IS_I830(dev_priv))
- dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = fixed_133mhz_get_cdclk;
- if (drm_WARN(&dev_priv->drm, !dev_priv->display.get_cdclk,
+ if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.get_cdclk,
"Unknown platform. Assuming 133 MHz CDCLK\n"))
- dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
+ dev_priv->display.funcs.get_cdclk = fixed_133mhz_get_cdclk;
}
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index afcb4bf3826c..8ac223156e31 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->display.load_luts(crtc_state);
+ dev_priv->display.funcs.load_luts(crtc_state);
}
void intel_color_commit(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->display.color_commit(crtc_state);
+ dev_priv->display.funcs.color_commit(crtc_state);
}
static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
@@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- return dev_priv->display.color_check(crtc_state);
+ return dev_priv->display.funcs.color_check(crtc_state);
}
void intel_color_get_config(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- if (dev_priv->display.read_luts)
- dev_priv->display.read_luts(crtc_state);
+ if (dev_priv->display.funcs.read_luts)
+ dev_priv->display.funcs.read_luts(crtc_state);
}
static bool need_plane_update(struct intel_plane *plane,
@@ -2101,51 +2101,51 @@ void intel_color_init(struct intel_crtc *crtc)
if (HAS_GMCH(dev_priv)) {
if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.color_check = chv_color_check;
- dev_priv->display.color_commit = i9xx_color_commit;
- dev_priv->display.load_luts = chv_load_luts;
- dev_priv->display.read_luts = chv_read_luts;
+ dev_priv->display.funcs.color_check = chv_color_check;
+ dev_priv->display.funcs.color_commit = i9xx_color_commit;
+ dev_priv->display.funcs.load_luts = chv_load_luts;
+ dev_priv->display.funcs.read_luts = chv_read_luts;
} else if (DISPLAY_VER(dev_priv) >= 4) {
- dev_priv->display.color_check = i9xx_color_check;
- dev_priv->display.color_commit = i9xx_color_commit;
- dev_priv->display.load_luts = i965_load_luts;
- dev_priv->display.read_luts = i965_read_luts;
+ dev_priv->display.funcs.color_check = i9xx_color_check;
+ dev_priv->display.funcs.color_commit = i9xx_color_commit;
+ dev_priv->display.funcs.load_luts = i965_load_luts;
+ dev_priv->display.funcs.read_luts = i965_read_luts;
} else {
- dev_priv->display.color_check = i9xx_color_check;
- dev_priv->display.color_commit = i9xx_color_commit;
- dev_priv->display.load_luts = i9xx_load_luts;
- dev_priv->display.read_luts = i9xx_read_luts;
+ dev_priv->display.funcs.color_check = i9xx_color_check;
+ dev_priv->display.funcs.color_commit = i9xx_color_commit;
+ dev_priv->display.funcs.load_luts = i9xx_load_luts;
+ dev_priv->display.funcs.read_luts = i9xx_read_luts;
}
} else {
if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->display.color_check = icl_color_check;
+ dev_priv->display.funcs.color_check = icl_color_check;
else if (DISPLAY_VER(dev_priv) >= 10)
- dev_priv->display.color_check = glk_color_check;
+ dev_priv->display.funcs.color_check = glk_color_check;
else if (DISPLAY_VER(dev_priv) >= 7)
- dev_priv->display.color_check = ivb_color_check;
+ dev_priv->display.funcs.color_check = ivb_color_check;
else
- dev_priv->display.color_check = ilk_color_check;
+ dev_priv->display.funcs.color_check = ilk_color_check;
if (DISPLAY_VER(dev_priv) >= 9)
- dev_priv->display.color_commit = skl_color_commit;
+ dev_priv->display.funcs.color_commit = skl_color_commit;
else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
- dev_priv->display.color_commit = hsw_color_commit;
+ dev_priv->display.funcs.color_commit = hsw_color_commit;
else
- dev_priv->display.color_commit = ilk_color_commit;
+ dev_priv->display.funcs.color_commit = ilk_color_commit;
if (DISPLAY_VER(dev_priv) >= 11) {
- dev_priv->display.load_luts = icl_load_luts;
- dev_priv->display.read_luts = icl_read_luts;
+ dev_priv->display.funcs.load_luts = icl_load_luts;
+ dev_priv->display.funcs.read_luts = icl_read_luts;
} else if (DISPLAY_VER(dev_priv) == 10) {
- dev_priv->display.load_luts = glk_load_luts;
- dev_priv->display.read_luts = glk_read_luts;
+ dev_priv->display.funcs.load_luts = glk_load_luts;
+ dev_priv->display.funcs.read_luts = glk_read_luts;
} else if (DISPLAY_VER(dev_priv) >= 8) {
- dev_priv->display.load_luts = bdw_load_luts;
+ dev_priv->display.funcs.load_luts = bdw_load_luts;
} else if (DISPLAY_VER(dev_priv) >= 7) {
- dev_priv->display.load_luts = ivb_load_luts;
+ dev_priv->display.funcs.load_luts = ivb_load_luts;
} else {
- dev_priv->display.load_luts = ilk_load_luts;
- dev_priv->display.read_luts = ilk_read_luts;
+ dev_priv->display.funcs.load_luts = ilk_load_luts;
+ dev_priv->display.funcs.read_luts = ilk_read_luts;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1f447ba776c7..f31585e56e84 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2060,7 +2060,7 @@ static void ilk_pch_enable(const struct intel_atomic_state *state,
assert_pch_transcoder_disabled(dev_priv, pipe);
/* For PCH output, training FDI link */
- dev_priv->display.fdi_link_train(crtc, crtc_state);
+ dev_priv->display.funcs.fdi_link_train(crtc, crtc_state);
/* We need to program the right clock selection before writing the pixel
* mutliplier into the DPLL. */
@@ -2526,8 +2526,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
* we'll continue to update watermarks the old way, if flags tell
* us to.
*/
- if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, crtc);
+ if (dev_priv->display.funcs.initial_watermarks)
+ dev_priv->display.funcs.initial_watermarks(state, crtc);
else if (new_crtc_state->update_wm_pre)
intel_update_watermarks(crtc);
}
@@ -2901,8 +2901,8 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(new_crtc_state);
- if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, crtc);
+ if (dev_priv->display.funcs.initial_watermarks)
+ dev_priv->display.funcs.initial_watermarks(state, crtc);
intel_enable_pipe(new_crtc_state);
if (new_crtc_state->has_pch_encoder)
@@ -3112,8 +3112,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
if (DISPLAY_VER(dev_priv) >= 11)
icl_set_pipe_chicken(new_crtc_state);
- if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, crtc);
+ if (dev_priv->display.funcs.initial_watermarks)
+ dev_priv->display.funcs.initial_watermarks(state, crtc);
if (DISPLAY_VER(dev_priv) >= 11) {
const struct intel_dbuf_state *dbuf_state =
@@ -3530,7 +3530,7 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(new_crtc_state);
- dev_priv->display.initial_watermarks(state, crtc);
+ dev_priv->display.funcs.initial_watermarks(state, crtc);
intel_enable_pipe(new_crtc_state);
intel_crtc_vblank_on(new_crtc_state);
@@ -3573,8 +3573,8 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(new_crtc_state);
- if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, crtc);
+ if (dev_priv->display.funcs.initial_watermarks)
+ dev_priv->display.funcs.initial_watermarks(state, crtc);
else
intel_update_watermarks(crtc);
intel_enable_pipe(new_crtc_state);
@@ -3642,7 +3642,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
if (DISPLAY_VER(dev_priv) != 2)
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
- if (!dev_priv->display.initial_watermarks)
+ if (!dev_priv->display.funcs.initial_watermarks)
intel_update_watermarks(crtc);
/* clock the pipe down to 640x480@60 to potentially save power */
@@ -3696,7 +3696,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
- dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
+ dev_priv->display.funcs.crtc_disable(to_intel_atomic_state(state), crtc);
drm_atomic_state_put(state);
@@ -5901,7 +5901,7 @@ static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- if (!i915->display.get_pipe_config(crtc, crtc_state))
+ if (!i915->display.funcs.get_pipe_config(crtc, crtc_state))
return false;
crtc_state->hw.active = true;
@@ -6728,10 +6728,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
crtc_state->update_wm_post = true;
if (mode_changed && crtc_state->hw.enable &&
- dev_priv->display.crtc_compute_clock &&
+ dev_priv->display.funcs.crtc_compute_clock &&
!crtc_state->bigjoiner_slave &&
!drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
- ret = dev_priv->display.crtc_compute_clock(crtc_state);
+ ret = dev_priv->display.funcs.crtc_compute_clock(crtc_state);
if (ret)
return ret;
}
@@ -6750,8 +6750,8 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
return ret;
}
- if (dev_priv->display.compute_pipe_wm) {
- ret = dev_priv->display.compute_pipe_wm(state, crtc);
+ if (dev_priv->display.funcs.compute_pipe_wm) {
+ ret = dev_priv->display.funcs.compute_pipe_wm(state, crtc);
if (ret) {
drm_dbg_kms(&dev_priv->drm,
"Target pipe watermarks are invalid\n");
@@ -6760,9 +6760,9 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
}
- if (dev_priv->display.compute_intermediate_wm) {
+ if (dev_priv->display.funcs.compute_intermediate_wm) {
if (drm_WARN_ON(&dev_priv->drm,
- !dev_priv->display.compute_pipe_wm))
+ !dev_priv->display.funcs.compute_pipe_wm))
return 0;
/*
@@ -6770,7 +6770,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
* old state and the new state. We can program these
* immediately.
*/
- ret = dev_priv->display.compute_intermediate_wm(state, crtc);
+ ret = dev_priv->display.funcs.compute_intermediate_wm(state, crtc);
if (ret) {
drm_dbg_kms(&dev_priv->drm,
"No valid intermediate pipe watermarks are possible\n");
@@ -8767,7 +8767,7 @@ static void intel_modeset_clear_plls(struct intel_atomic_state *state)
struct intel_crtc *crtc;
int i;
- if (!dev_priv->display.crtc_compute_clock)
+ if (!dev_priv->display.funcs.crtc_compute_clock)
return;
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
@@ -8879,8 +8879,8 @@ static int calc_watermark_data(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(dev);
/* Is there platform-specific watermark information to calculate? */
- if (dev_priv->display.compute_global_watermarks)
- return dev_priv->display.compute_global_watermarks(state);
+ if (dev_priv->display.funcs.compute_global_watermarks)
+ return dev_priv->display.funcs.compute_global_watermarks(state);
return 0;
}
@@ -9080,7 +9080,7 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
*need_cdclk_calc = true;
- ret = dev_priv->display.bw_calc_min_cdclk(state);
+ ret = dev_priv->display.funcs.bw_calc_min_cdclk(state);
if (ret)
return ret;
@@ -9705,8 +9705,8 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state,
intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
}
- if (dev_priv->display.atomic_update_watermarks)
- dev_priv->display.atomic_update_watermarks(state, crtc);
+ if (dev_priv->display.funcs.atomic_update_watermarks)
+ dev_priv->display.funcs.atomic_update_watermarks(state, crtc);
}
static void commit_pipe_post_planes(struct intel_atomic_state *state,
@@ -9738,7 +9738,7 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
intel_crtc_update_active_timings(new_crtc_state);
- dev_priv->display.crtc_enable(state, crtc);
+ dev_priv->display.funcs.crtc_enable(state, crtc);
if (new_crtc_state->bigjoiner_slave)
return;
@@ -9826,7 +9826,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
*/
intel_crtc_disable_pipe_crc(crtc);
- dev_priv->display.crtc_disable(state, crtc);
+ dev_priv->display.funcs.crtc_disable(state, crtc);
crtc->active = false;
intel_fbc_disable(crtc);
intel_disable_shared_dpll(old_crtc_state);
@@ -9834,8 +9834,8 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
/* FIXME unify this for all platforms */
if (!new_crtc_state->hw.active &&
!HAS_GMCH(dev_priv) &&
- dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, crtc);
+ dev_priv->display.funcs.initial_watermarks)
+ dev_priv->display.funcs.initial_watermarks(state, crtc);
}
static void intel_commit_modeset_disables(struct intel_atomic_state *state)
@@ -10206,7 +10206,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
}
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
- dev_priv->display.commit_modeset_enables(state);
+ dev_priv->display.funcs.commit_modeset_enables(state);
if (state->modeset) {
intel_encoders_update_complete(state);
@@ -10257,8 +10257,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
- if (dev_priv->display.optimize_watermarks)
- dev_priv->display.optimize_watermarks(state, crtc);
+ if (dev_priv->display.funcs.optimize_watermarks)
+ dev_priv->display.funcs.optimize_watermarks(state, crtc);
}
intel_dbuf_post_plane_update(state);
@@ -11225,36 +11225,36 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
intel_dpll_init_clock_hook(dev_priv);
if (DISPLAY_VER(dev_priv) >= 9) {
- dev_priv->display.get_pipe_config = hsw_get_pipe_config;
- dev_priv->display.crtc_enable = hsw_crtc_enable;
- dev_priv->display.crtc_disable = hsw_crtc_disable;
+ dev_priv->display.funcs.get_pipe_config = hsw_get_pipe_config;
+ dev_priv->display.funcs.crtc_enable = hsw_crtc_enable;
+ dev_priv->display.funcs.crtc_disable = hsw_crtc_disable;
} else if (HAS_DDI(dev_priv)) {
- dev_priv->display.get_pipe_config = hsw_get_pipe_config;
- dev_priv->display.crtc_enable = hsw_crtc_enable;
- dev_priv->display.crtc_disable = hsw_crtc_disable;
+ dev_priv->display.funcs.get_pipe_config = hsw_get_pipe_config;
+ dev_priv->display.funcs.crtc_enable = hsw_crtc_enable;
+ dev_priv->display.funcs.crtc_disable = hsw_crtc_disable;
} else if (HAS_PCH_SPLIT(dev_priv)) {
- dev_priv->display.get_pipe_config = ilk_get_pipe_config;
- dev_priv->display.crtc_enable = ilk_crtc_enable;
- dev_priv->display.crtc_disable = ilk_crtc_disable;
+ dev_priv->display.funcs.get_pipe_config = ilk_get_pipe_config;
+ dev_priv->display.funcs.crtc_enable = ilk_crtc_enable;
+ dev_priv->display.funcs.crtc_disable = ilk_crtc_disable;
} else if (IS_CHERRYVIEW(dev_priv) ||
IS_VALLEYVIEW(dev_priv)) {
- dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
- dev_priv->display.crtc_enable = valleyview_crtc_enable;
- dev_priv->display.crtc_disable = i9xx_crtc_disable;
+ dev_priv->display.funcs.get_pipe_config = i9xx_get_pipe_config;
+ dev_priv->display.funcs.crtc_enable = valleyview_crtc_enable;
+ dev_priv->display.funcs.crtc_disable = i9xx_crtc_disable;
} else {
- dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
- dev_priv->display.crtc_enable = i9xx_crtc_enable;
- dev_priv->display.crtc_disable = i9xx_crtc_disable;
+ dev_priv->display.funcs.get_pipe_config = i9xx_get_pipe_config;
+ dev_priv->display.funcs.crtc_enable = i9xx_crtc_enable;
+ dev_priv->display.funcs.crtc_disable = i9xx_crtc_disable;
}
intel_fdi_init_hook(dev_priv);
if (DISPLAY_VER(dev_priv) >= 9) {
- dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
- dev_priv->display.get_initial_plane_config = skl_get_initial_plane_config;
+ dev_priv->display.funcs.commit_modeset_enables = skl_commit_modeset_enables;
+ dev_priv->display.funcs.get_initial_plane_config = skl_get_initial_plane_config;
} else {
- dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
- dev_priv->display.get_initial_plane_config = i9xx_get_initial_plane_config;
+ dev_priv->display.funcs.commit_modeset_enables = intel_commit_modeset_enables;
+ dev_priv->display.funcs.get_initial_plane_config = i9xx_get_initial_plane_config;
}
}
@@ -11326,7 +11326,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
int i;
/* Only supported on platforms that use atomic watermark design */
- if (!dev_priv->display.optimize_watermarks)
+ if (!dev_priv->display.funcs.optimize_watermarks)
return;
state = drm_atomic_state_alloc(&dev_priv->drm);
@@ -11359,7 +11359,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
/* Write calculated watermark values back */
for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
crtc_state->wm.need_postvbl_update = true;
- dev_priv->display.optimize_watermarks(intel_state, crtc);
+ dev_priv->display.funcs.optimize_watermarks(intel_state, crtc);
to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
}
@@ -11683,7 +11683,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
* can even allow for smooth boot transitions if the BIOS
* fb is large enough for the active pipe configuration.
*/
- i915->display.get_initial_plane_config(crtc, &plane_config);
+ i915->display.funcs.get_initial_plane_config(crtc, &plane_config);
/*
* If the fb is shared between multiple heads, we'll
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index cce1a926fcc1..ebe4fee6d680 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1195,7 +1195,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- dev_priv->display.get_cdclk(dev_priv, &cdclk_config);
+ dev_priv->display.funcs.get_cdclk(dev_priv, &cdclk_config);
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
drm_WARN_ON(&dev_priv->drm,
intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 210f91f4a576..2dc7c0f95103 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1367,21 +1367,21 @@ void
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
{
if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
- dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
+ dev_priv->display.funcs.crtc_compute_clock = hsw_crtc_compute_clock;
else if (HAS_PCH_SPLIT(dev_priv))
- dev_priv->display.crtc_compute_clock = ilk_crtc_compute_clock;
+ dev_priv->display.funcs.crtc_compute_clock = ilk_crtc_compute_clock;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
+ dev_priv->display.funcs.crtc_compute_clock = chv_crtc_compute_clock;
else if (IS_VALLEYVIEW(dev_priv))
- dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
+ dev_priv->display.funcs.crtc_compute_clock = vlv_crtc_compute_clock;
else if (IS_G4X(dev_priv))
- dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
+ dev_priv->display.funcs.crtc_compute_clock = g4x_crtc_compute_clock;
else if (IS_PINEVIEW(dev_priv))
- dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
+ dev_priv->display.funcs.crtc_compute_clock = pnv_crtc_compute_clock;
else if (DISPLAY_VER(dev_priv) != 2)
- dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
+ dev_priv->display.funcs.crtc_compute_clock = i9xx_crtc_compute_clock;
else
- dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
+ dev_priv->display.funcs.crtc_compute_clock = i8xx_crtc_compute_clock;
}
static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index fc09b781f15f..aaa0207f483e 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -1009,11 +1009,11 @@ void
intel_fdi_init_hook(struct drm_i915_private *dev_priv)
{
if (IS_IRONLAKE(dev_priv)) {
- dev_priv->display.fdi_link_train = ilk_fdi_link_train;
+ dev_priv->display.funcs.fdi_link_train = ilk_fdi_link_train;
} else if (IS_SANDYBRIDGE(dev_priv)) {
- dev_priv->display.fdi_link_train = gen6_fdi_link_train;
+ dev_priv->display.funcs.fdi_link_train = gen6_fdi_link_train;
} else if (IS_IVYBRIDGE(dev_priv)) {
/* FIXME: detect B0+ stepping and use auto training */
- dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
+ dev_priv->display.funcs.fdi_link_train = ivb_manual_fdi_link_train;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 47c85ac97c87..6c65efcb8a9c 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -215,8 +215,8 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
static void intel_hpd_irq_setup(struct drm_i915_private *i915)
{
- if (i915->display_irqs_enabled && i915->display.hpd_irq_setup)
- i915->display.hpd_irq_setup(i915);
+ if (i915->display_irqs_enabled && i915->display.funcs.hpd_irq_setup)
+ i915->display.funcs.hpd_irq_setup(i915);
}
static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index be2392bbcecc..04335bace0e3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -825,6 +825,11 @@ struct i915_selftest_stash {
struct ida mock_region_instances;
};
+struct drm_i915_display {
+ /* Display functions */
+ struct drm_i915_display_funcs funcs;
+};
+
struct drm_i915_private {
struct drm_device drm;
@@ -838,6 +843,8 @@ struct drm_i915_private {
struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
struct intel_driver_caps caps;
+ struct drm_i915_display display;
+
/**
* Data Stolen Memory - aka "i915 stolen memory" gives us the start and
* end of stolen which we can optionally use to create GEM objects
@@ -971,9 +978,6 @@ struct drm_i915_private {
/* unbound hipri wq for page flips/plane updates */
struct workqueue_struct *flip_wq;
- /* Display functions */
- struct drm_i915_display_funcs display;
-
/* PCH chipset type */
enum intel_pch pch_type;
unsigned short pch_id;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0a1681384c84..b1e3f51dc593 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4395,20 +4395,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (HAS_GMCH(dev_priv)) {
if (I915_HAS_HOTPLUG(dev_priv))
- dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
+ dev_priv->display.funcs.hpd_irq_setup = i915_hpd_irq_setup;
} else {
if (HAS_PCH_DG1(dev_priv))
- dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
+ dev_priv->display.funcs.hpd_irq_setup = dg1_hpd_irq_setup;
else if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
+ dev_priv->display.funcs.hpd_irq_setup = gen11_hpd_irq_setup;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
+ dev_priv->display.funcs.hpd_irq_setup = bxt_hpd_irq_setup;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
+ dev_priv->display.funcs.hpd_irq_setup = icp_hpd_irq_setup;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
- dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
+ dev_priv->display.funcs.hpd_irq_setup = spt_hpd_irq_setup;
else
- dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
+ dev_priv->display.funcs.hpd_irq_setup = ilk_hpd_irq_setup;
}
}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cfc41f8fa74a..0c64b3a94cf1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2347,7 +2347,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
else
wm_info = &i830_a_wm_info;
- fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
+ fifo_size = dev_priv->display.funcs.get_fifo_size(dev_priv, PLANE_A);
crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *pipe_mode =
@@ -2374,7 +2374,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
if (DISPLAY_VER(dev_priv) == 2)
wm_info = &i830_bc_wm_info;
- fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
+ fifo_size = dev_priv->display.funcs.get_fifo_size(dev_priv, PLANE_B);
crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *pipe_mode =
@@ -2490,7 +2490,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
pipe_mode = &crtc->config->hw.pipe_mode;
planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
&i845_wm_info,
- dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
+ dev_priv->display.funcs.get_fifo_size(dev_priv, PLANE_A),
4, pessimal_latency_ns);
fwater_lo = intel_uncore_read(&dev_priv->uncore, FW_BLC) & ~0xfff;
fwater_lo |= (3<<8) | planea_wm;
@@ -7167,8 +7167,8 @@ void intel_update_watermarks(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- if (dev_priv->display.update_wm)
- dev_priv->display.update_wm(crtc);
+ if (dev_priv->display.funcs.update_wm)
+ dev_priv->display.funcs.update_wm(crtc);
}
void intel_enable_ipc(struct drm_i915_private *dev_priv)
@@ -7910,7 +7910,7 @@ static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
void intel_init_clock_gating(struct drm_i915_private *dev_priv)
{
- dev_priv->display.init_clock_gating(dev_priv);
+ dev_priv->display.funcs.init_clock_gating(dev_priv);
}
void intel_suspend_hw(struct drm_i915_private *dev_priv)
@@ -7937,52 +7937,52 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
if (IS_ALDERLAKE_P(dev_priv))
- dev_priv->display.init_clock_gating = adlp_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = adlp_init_clock_gating;
else if (IS_DG1(dev_priv))
- dev_priv->display.init_clock_gating = dg1_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = dg1_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 12)
- dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = gen12lp_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 11)
- dev_priv->display.init_clock_gating = icl_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = icl_init_clock_gating;
else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
- dev_priv->display.init_clock_gating = cfl_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = cfl_init_clock_gating;
else if (IS_SKYLAKE(dev_priv))
- dev_priv->display.init_clock_gating = skl_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = skl_init_clock_gating;
else if (IS_KABYLAKE(dev_priv))
- dev_priv->display.init_clock_gating = kbl_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = kbl_init_clock_gating;
else if (IS_BROXTON(dev_priv))
- dev_priv->display.init_clock_gating = bxt_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = bxt_init_clock_gating;
else if (IS_GEMINILAKE(dev_priv))
- dev_priv->display.init_clock_gating = glk_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = glk_init_clock_gating;
else if (IS_BROADWELL(dev_priv))
- dev_priv->display.init_clock_gating = bdw_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = bdw_init_clock_gating;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->display.init_clock_gating = chv_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = chv_init_clock_gating;
else if (IS_HASWELL(dev_priv))
- dev_priv->display.init_clock_gating = hsw_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = hsw_init_clock_gating;
else if (IS_IVYBRIDGE(dev_priv))
- dev_priv->display.init_clock_gating = ivb_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = ivb_init_clock_gating;
else if (IS_VALLEYVIEW(dev_priv))
- dev_priv->display.init_clock_gating = vlv_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = vlv_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 6)
- dev_priv->display.init_clock_gating = gen6_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = gen6_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 5)
- dev_priv->display.init_clock_gating = ilk_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = ilk_init_clock_gating;
else if (IS_G4X(dev_priv))
- dev_priv->display.init_clock_gating = g4x_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = g4x_init_clock_gating;
else if (IS_I965GM(dev_priv))
- dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = i965gm_init_clock_gating;
else if (IS_I965G(dev_priv))
- dev_priv->display.init_clock_gating = i965g_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = i965g_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 3)
- dev_priv->display.init_clock_gating = gen3_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = gen3_init_clock_gating;
else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
- dev_priv->display.init_clock_gating = i85x_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = i85x_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 2)
- dev_priv->display.init_clock_gating = i830_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = i830_init_clock_gating;
else {
MISSING_CASE(INTEL_DEVID(dev_priv));
- dev_priv->display.init_clock_gating = nop_init_clock_gating;
+ dev_priv->display.funcs.init_clock_gating = nop_init_clock_gating;
}
}
@@ -8001,7 +8001,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
/* For FIFO watermark updates */
if (DISPLAY_VER(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
- dev_priv->display.compute_global_watermarks = skl_compute_wm;
+ dev_priv->display.funcs.compute_global_watermarks = skl_compute_wm;
} else if (HAS_PCH_SPLIT(dev_priv)) {
ilk_setup_wm_latency(dev_priv);
@@ -8009,12 +8009,12 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
(DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] &&
dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
- dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
- dev_priv->display.compute_intermediate_wm =
+ dev_priv->display.funcs.compute_pipe_wm = ilk_compute_pipe_wm;
+ dev_priv->display.funcs.compute_intermediate_wm =
ilk_compute_intermediate_wm;
- dev_priv->display.initial_watermarks =
+ dev_priv->display.funcs.initial_watermarks =
ilk_initial_watermarks;
- dev_priv->display.optimize_watermarks =
+ dev_priv->display.funcs.optimize_watermarks =
ilk_optimize_watermarks;
} else {
drm_dbg_kms(&dev_priv->drm,
@@ -8023,17 +8023,17 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
}
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
vlv_setup_wm_latency(dev_priv);
- dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;
- dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;
- dev_priv->display.initial_watermarks = vlv_initial_watermarks;
- dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;
- dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;
+ dev_priv->display.funcs.compute_pipe_wm = vlv_compute_pipe_wm;
+ dev_priv->display.funcs.compute_intermediate_wm = vlv_compute_intermediate_wm;
+ dev_priv->display.funcs.initial_watermarks = vlv_initial_watermarks;
+ dev_priv->display.funcs.optimize_watermarks = vlv_optimize_watermarks;
+ dev_priv->display.funcs.atomic_update_watermarks = vlv_atomic_update_fifo;
} else if (IS_G4X(dev_priv)) {
g4x_setup_wm_latency(dev_priv);
- dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm;
- dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm;
- dev_priv->display.initial_watermarks = g4x_initial_watermarks;
- dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
+ dev_priv->display.funcs.compute_pipe_wm = g4x_compute_pipe_wm;
+ dev_priv->display.funcs.compute_intermediate_wm = g4x_compute_intermediate_wm;
+ dev_priv->display.funcs.initial_watermarks = g4x_initial_watermarks;
+ dev_priv->display.funcs.optimize_watermarks = g4x_optimize_watermarks;
} else if (IS_PINEVIEW(dev_priv)) {
if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
dev_priv->is_ddr3,
@@ -8047,21 +8047,21 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->fsb_freq, dev_priv->mem_freq);
/* Disable CxSR and never update its watermark again */
intel_set_memory_cxsr(dev_priv, false);
- dev_priv->display.update_wm = NULL;
+ dev_priv->display.funcs.update_wm = NULL;
} else
- dev_priv->display.update_wm = pnv_update_wm;
+ dev_priv->display.funcs.update_wm = pnv_update_wm;
} else if (DISPLAY_VER(dev_priv) == 4) {
- dev_priv->display.update_wm = i965_update_wm;
+ dev_priv->display.funcs.update_wm = i965_update_wm;
} else if (DISPLAY_VER(dev_priv) == 3) {
- dev_priv->display.update_wm = i9xx_update_wm;
- dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
+ dev_priv->display.funcs.update_wm = i9xx_update_wm;
+ dev_priv->display.funcs.get_fifo_size = i9xx_get_fifo_size;
} else if (DISPLAY_VER(dev_priv) == 2) {
if (INTEL_NUM_PIPES(dev_priv) == 1) {
- dev_priv->display.update_wm = i845_update_wm;
- dev_priv->display.get_fifo_size = i845_get_fifo_size;
+ dev_priv->display.funcs.update_wm = i845_update_wm;
+ dev_priv->display.funcs.get_fifo_size = i845_get_fifo_size;
} else {
- dev_priv->display.update_wm = i9xx_update_wm;
- dev_priv->display.get_fifo_size = i830_get_fifo_size;
+ dev_priv->display.funcs.update_wm = i9xx_update_wm;
+ dev_priv->display.funcs.get_fifo_size = i830_get_fifo_size;
}
} else {
drm_err(&dev_priv->drm,
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Intel-gfx] [PATCH 01/10] drm/i915: move display funcs into a display struct.
2021-09-06 3:43 ` [Intel-gfx] [PATCH 01/10] drm/i915: move display funcs into a display struct Dave Airlie
@ 2021-09-06 8:18 ` Jani Nikula
2021-09-06 19:44 ` Dave Airlie
0 siblings, 1 reply; 20+ messages in thread
From: Jani Nikula @ 2021-09-06 8:18 UTC (permalink / raw)
To: Dave Airlie, intel-gfx
Cc: Syrjala, Ville, Rodrigo Vivi, Joonas Lahtinen, Daniel Vetter
On Mon, 06 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> This is the first step in an idea to refactor the display code
> into a bit more of a corner.
So, do we want to make i915->display a pointer?
If we do, and we're about to touch every place accessing the display
struct, we might just as well have:
struct drm_i915_private {
struct drm_i915_display _display;
struct drm_i915_display *display;
};
and initialize i915->display = &i915->_display, and make all access
happen via the pointer. If we want to allocate it dynamically at some
point, it'll be a *much* easier task.
But the first question to figure out is whether we want to do that or
not.
BR,
Jani.
>
> Signed-off-by: Dave Airlie <airlied@redhat.com>
> ---
> drivers/gpu/drm/i915/display/intel_audio.c | 24 +--
> drivers/gpu/drm/i915/display/intel_cdclk.c | 148 +++++++++---------
> drivers/gpu/drm/i915/display/intel_color.c | 64 ++++----
> drivers/gpu/drm/i915/display/intel_display.c | 110 ++++++-------
> .../drm/i915/display/intel_display_power.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dpll.c | 16 +-
> drivers/gpu/drm/i915/display/intel_fdi.c | 6 +-
> drivers/gpu/drm/i915/display/intel_hotplug.c | 4 +-
> drivers/gpu/drm/i915/i915_drv.h | 10 +-
> drivers/gpu/drm/i915/i915_irq.c | 14 +-
> drivers/gpu/drm/i915/intel_pm.c | 104 ++++++------
> 11 files changed, 253 insertions(+), 249 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> index 532237588511..fd56191c8a68 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -848,8 +848,8 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
>
> connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
>
> - if (dev_priv->display.audio_codec_enable)
> - dev_priv->display.audio_codec_enable(encoder,
> + if (dev_priv->display.funcs.audio_codec_enable)
> + dev_priv->display.funcs.audio_codec_enable(encoder,
> crtc_state,
> conn_state);
>
> @@ -893,8 +893,8 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
> enum port port = encoder->port;
> enum pipe pipe = crtc->pipe;
>
> - if (dev_priv->display.audio_codec_disable)
> - dev_priv->display.audio_codec_disable(encoder,
> + if (dev_priv->display.funcs.audio_codec_disable)
> + dev_priv->display.funcs.audio_codec_disable(encoder,
> old_crtc_state,
> old_conn_state);
>
> @@ -922,17 +922,17 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
> void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
> {
> if (IS_G4X(dev_priv)) {
> - dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
> - dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
> + dev_priv->display.funcs.audio_codec_enable = g4x_audio_codec_enable;
> + dev_priv->display.funcs.audio_codec_disable = g4x_audio_codec_disable;
> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> - dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
> - dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
> + dev_priv->display.funcs.audio_codec_enable = ilk_audio_codec_enable;
> + dev_priv->display.funcs.audio_codec_disable = ilk_audio_codec_disable;
> } else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
> - dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
> - dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
> + dev_priv->display.funcs.audio_codec_enable = hsw_audio_codec_enable;
> + dev_priv->display.funcs.audio_codec_disable = hsw_audio_codec_disable;
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> - dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
> - dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
> + dev_priv->display.funcs.audio_codec_enable = ilk_audio_codec_enable;
> + dev_priv->display.funcs.audio_codec_disable = ilk_audio_codec_disable;
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 34fa4130d5c4..becbf0fc4c4d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1466,7 +1466,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> * at least what the CDCLK frequency requires.
> */
> cdclk_config->voltage_level =
> - dev_priv->display.calc_voltage_level(cdclk_config->cdclk);
> + dev_priv->display.funcs.calc_voltage_level(cdclk_config->cdclk);
> }
>
> static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
> @@ -1777,7 +1777,7 @@ static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
> cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
> cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
> cdclk_config.voltage_level =
> - dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
> + dev_priv->display.funcs.calc_voltage_level(cdclk_config.cdclk);
>
> bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
> }
> @@ -1789,7 +1789,7 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
> cdclk_config.cdclk = cdclk_config.bypass;
> cdclk_config.vco = 0;
> cdclk_config.voltage_level =
> - dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
> + dev_priv->display.funcs.calc_voltage_level(cdclk_config.cdclk);
>
> bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
> }
> @@ -1932,7 +1932,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
> if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
> return;
>
> - if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.set_cdclk))
> + if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.set_cdclk))
> return;
>
> intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
> @@ -1956,7 +1956,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
> &dev_priv->gmbus_mutex);
> }
>
> - dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
> + dev_priv->display.funcs.set_cdclk(dev_priv, cdclk_config, pipe);
>
> for_each_intel_dp(&dev_priv->drm, encoder) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> @@ -2414,7 +2414,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> cdclk_state->logical.cdclk = cdclk;
> cdclk_state->logical.voltage_level =
> max_t(int, min_voltage_level,
> - dev_priv->display.calc_voltage_level(cdclk));
> + dev_priv->display.funcs.calc_voltage_level(cdclk));
>
> if (!cdclk_state->active_pipes) {
> cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
> @@ -2423,7 +2423,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> cdclk_state->actual.vco = vco;
> cdclk_state->actual.cdclk = cdclk;
> cdclk_state->actual.voltage_level =
> - dev_priv->display.calc_voltage_level(cdclk);
> + dev_priv->display.funcs.calc_voltage_level(cdclk);
> } else {
> cdclk_state->actual = cdclk_state->logical;
> }
> @@ -2515,7 +2515,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> new_cdclk_state->active_pipes =
> intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
>
> - ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
> + ret = dev_priv->display.funcs.modeset_calc_cdclk(new_cdclk_state);
> if (ret)
> return ret;
>
> @@ -2695,7 +2695,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> */
> void intel_update_cdclk(struct drm_i915_private *dev_priv)
> {
> - dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
> + dev_priv->display.funcs.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
>
> /*
> * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
> @@ -2852,119 +2852,119 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
> void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> {
> if (IS_DG2(dev_priv)) {
> - dev_priv->display.set_cdclk = bxt_set_cdclk;
> - dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> - dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> - dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
> + dev_priv->display.funcs.set_cdclk = bxt_set_cdclk;
> + dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> + dev_priv->display.funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> + dev_priv->display.funcs.calc_voltage_level = tgl_calc_voltage_level;
> dev_priv->cdclk.table = dg2_cdclk_table;
> } else if (IS_ALDERLAKE_P(dev_priv)) {
> - dev_priv->display.set_cdclk = bxt_set_cdclk;
> - dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> - dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> - dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
> + dev_priv->display.funcs.set_cdclk = bxt_set_cdclk;
> + dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> + dev_priv->display.funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> + dev_priv->display.funcs.calc_voltage_level = tgl_calc_voltage_level;
> /* Wa_22011320316:adl-p[a0] */
> if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> dev_priv->cdclk.table = adlp_a_step_cdclk_table;
> else
> dev_priv->cdclk.table = adlp_cdclk_table;
> } else if (IS_ROCKETLAKE(dev_priv)) {
> - dev_priv->display.set_cdclk = bxt_set_cdclk;
> - dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> - dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> - dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
> + dev_priv->display.funcs.set_cdclk = bxt_set_cdclk;
> + dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> + dev_priv->display.funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> + dev_priv->display.funcs.calc_voltage_level = tgl_calc_voltage_level;
> dev_priv->cdclk.table = rkl_cdclk_table;
> } else if (DISPLAY_VER(dev_priv) >= 12) {
> - dev_priv->display.set_cdclk = bxt_set_cdclk;
> - dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> - dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> - dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
> + dev_priv->display.funcs.set_cdclk = bxt_set_cdclk;
> + dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> + dev_priv->display.funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> + dev_priv->display.funcs.calc_voltage_level = tgl_calc_voltage_level;
> dev_priv->cdclk.table = icl_cdclk_table;
> } else if (IS_JSL_EHL(dev_priv)) {
> - dev_priv->display.set_cdclk = bxt_set_cdclk;
> - dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> - dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> - dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
> + dev_priv->display.funcs.set_cdclk = bxt_set_cdclk;
> + dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> + dev_priv->display.funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> + dev_priv->display.funcs.calc_voltage_level = ehl_calc_voltage_level;
> dev_priv->cdclk.table = icl_cdclk_table;
> } else if (DISPLAY_VER(dev_priv) >= 11) {
> - dev_priv->display.set_cdclk = bxt_set_cdclk;
> - dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> - dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> - dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
> + dev_priv->display.funcs.set_cdclk = bxt_set_cdclk;
> + dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> + dev_priv->display.funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> + dev_priv->display.funcs.calc_voltage_level = icl_calc_voltage_level;
> dev_priv->cdclk.table = icl_cdclk_table;
> } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
> - dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> - dev_priv->display.set_cdclk = bxt_set_cdclk;
> - dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> - dev_priv->display.calc_voltage_level = bxt_calc_voltage_level;
> + dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> + dev_priv->display.funcs.set_cdclk = bxt_set_cdclk;
> + dev_priv->display.funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> + dev_priv->display.funcs.calc_voltage_level = bxt_calc_voltage_level;
> if (IS_GEMINILAKE(dev_priv))
> dev_priv->cdclk.table = glk_cdclk_table;
> else
> dev_priv->cdclk.table = bxt_cdclk_table;
> } else if (DISPLAY_VER(dev_priv) == 9) {
> - dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> - dev_priv->display.set_cdclk = skl_set_cdclk;
> - dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
> + dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> + dev_priv->display.funcs.set_cdclk = skl_set_cdclk;
> + dev_priv->display.funcs.modeset_calc_cdclk = skl_modeset_calc_cdclk;
> } else if (IS_BROADWELL(dev_priv)) {
> - dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> - dev_priv->display.set_cdclk = bdw_set_cdclk;
> - dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
> + dev_priv->display.funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> + dev_priv->display.funcs.set_cdclk = bdw_set_cdclk;
> + dev_priv->display.funcs.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
> } else if (IS_CHERRYVIEW(dev_priv)) {
> - dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> - dev_priv->display.set_cdclk = chv_set_cdclk;
> - dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
> + dev_priv->display.funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> + dev_priv->display.funcs.set_cdclk = chv_set_cdclk;
> + dev_priv->display.funcs.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
> } else if (IS_VALLEYVIEW(dev_priv)) {
> - dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> - dev_priv->display.set_cdclk = vlv_set_cdclk;
> - dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
> + dev_priv->display.funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> + dev_priv->display.funcs.set_cdclk = vlv_set_cdclk;
> + dev_priv->display.funcs.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
> } else {
> - dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> - dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
> + dev_priv->display.funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> + dev_priv->display.funcs.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
> }
>
> if (DISPLAY_VER(dev_priv) >= 10 || IS_BROXTON(dev_priv))
> - dev_priv->display.get_cdclk = bxt_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = bxt_get_cdclk;
> else if (DISPLAY_VER(dev_priv) == 9)
> - dev_priv->display.get_cdclk = skl_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = skl_get_cdclk;
> else if (IS_BROADWELL(dev_priv))
> - dev_priv->display.get_cdclk = bdw_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = bdw_get_cdclk;
> else if (IS_HASWELL(dev_priv))
> - dev_priv->display.get_cdclk = hsw_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = hsw_get_cdclk;
> else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> - dev_priv->display.get_cdclk = vlv_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = vlv_get_cdclk;
> else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
> - dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = fixed_400mhz_get_cdclk;
> else if (IS_IRONLAKE(dev_priv))
> - dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = fixed_450mhz_get_cdclk;
> else if (IS_GM45(dev_priv))
> - dev_priv->display.get_cdclk = gm45_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = gm45_get_cdclk;
> else if (IS_G45(dev_priv))
> - dev_priv->display.get_cdclk = g33_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = g33_get_cdclk;
> else if (IS_I965GM(dev_priv))
> - dev_priv->display.get_cdclk = i965gm_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = i965gm_get_cdclk;
> else if (IS_I965G(dev_priv))
> - dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = fixed_400mhz_get_cdclk;
> else if (IS_PINEVIEW(dev_priv))
> - dev_priv->display.get_cdclk = pnv_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = pnv_get_cdclk;
> else if (IS_G33(dev_priv))
> - dev_priv->display.get_cdclk = g33_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = g33_get_cdclk;
> else if (IS_I945GM(dev_priv))
> - dev_priv->display.get_cdclk = i945gm_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = i945gm_get_cdclk;
> else if (IS_I945G(dev_priv))
> - dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = fixed_400mhz_get_cdclk;
> else if (IS_I915GM(dev_priv))
> - dev_priv->display.get_cdclk = i915gm_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = i915gm_get_cdclk;
> else if (IS_I915G(dev_priv))
> - dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = fixed_333mhz_get_cdclk;
> else if (IS_I865G(dev_priv))
> - dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = fixed_266mhz_get_cdclk;
> else if (IS_I85X(dev_priv))
> - dev_priv->display.get_cdclk = i85x_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = i85x_get_cdclk;
> else if (IS_I845G(dev_priv))
> - dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = fixed_200mhz_get_cdclk;
> else if (IS_I830(dev_priv))
> - dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = fixed_133mhz_get_cdclk;
>
> - if (drm_WARN(&dev_priv->drm, !dev_priv->display.get_cdclk,
> + if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.get_cdclk,
> "Unknown platform. Assuming 133 MHz CDCLK\n"))
> - dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
> + dev_priv->display.funcs.get_cdclk = fixed_133mhz_get_cdclk;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index afcb4bf3826c..8ac223156e31 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> - dev_priv->display.load_luts(crtc_state);
> + dev_priv->display.funcs.load_luts(crtc_state);
> }
>
> void intel_color_commit(const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> - dev_priv->display.color_commit(crtc_state);
> + dev_priv->display.funcs.color_commit(crtc_state);
> }
>
> static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
> @@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> - return dev_priv->display.color_check(crtc_state);
> + return dev_priv->display.funcs.color_check(crtc_state);
> }
>
> void intel_color_get_config(struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> - if (dev_priv->display.read_luts)
> - dev_priv->display.read_luts(crtc_state);
> + if (dev_priv->display.funcs.read_luts)
> + dev_priv->display.funcs.read_luts(crtc_state);
> }
>
> static bool need_plane_update(struct intel_plane *plane,
> @@ -2101,51 +2101,51 @@ void intel_color_init(struct intel_crtc *crtc)
>
> if (HAS_GMCH(dev_priv)) {
> if (IS_CHERRYVIEW(dev_priv)) {
> - dev_priv->display.color_check = chv_color_check;
> - dev_priv->display.color_commit = i9xx_color_commit;
> - dev_priv->display.load_luts = chv_load_luts;
> - dev_priv->display.read_luts = chv_read_luts;
> + dev_priv->display.funcs.color_check = chv_color_check;
> + dev_priv->display.funcs.color_commit = i9xx_color_commit;
> + dev_priv->display.funcs.load_luts = chv_load_luts;
> + dev_priv->display.funcs.read_luts = chv_read_luts;
> } else if (DISPLAY_VER(dev_priv) >= 4) {
> - dev_priv->display.color_check = i9xx_color_check;
> - dev_priv->display.color_commit = i9xx_color_commit;
> - dev_priv->display.load_luts = i965_load_luts;
> - dev_priv->display.read_luts = i965_read_luts;
> + dev_priv->display.funcs.color_check = i9xx_color_check;
> + dev_priv->display.funcs.color_commit = i9xx_color_commit;
> + dev_priv->display.funcs.load_luts = i965_load_luts;
> + dev_priv->display.funcs.read_luts = i965_read_luts;
> } else {
> - dev_priv->display.color_check = i9xx_color_check;
> - dev_priv->display.color_commit = i9xx_color_commit;
> - dev_priv->display.load_luts = i9xx_load_luts;
> - dev_priv->display.read_luts = i9xx_read_luts;
> + dev_priv->display.funcs.color_check = i9xx_color_check;
> + dev_priv->display.funcs.color_commit = i9xx_color_commit;
> + dev_priv->display.funcs.load_luts = i9xx_load_luts;
> + dev_priv->display.funcs.read_luts = i9xx_read_luts;
> }
> } else {
> if (DISPLAY_VER(dev_priv) >= 11)
> - dev_priv->display.color_check = icl_color_check;
> + dev_priv->display.funcs.color_check = icl_color_check;
> else if (DISPLAY_VER(dev_priv) >= 10)
> - dev_priv->display.color_check = glk_color_check;
> + dev_priv->display.funcs.color_check = glk_color_check;
> else if (DISPLAY_VER(dev_priv) >= 7)
> - dev_priv->display.color_check = ivb_color_check;
> + dev_priv->display.funcs.color_check = ivb_color_check;
> else
> - dev_priv->display.color_check = ilk_color_check;
> + dev_priv->display.funcs.color_check = ilk_color_check;
>
> if (DISPLAY_VER(dev_priv) >= 9)
> - dev_priv->display.color_commit = skl_color_commit;
> + dev_priv->display.funcs.color_commit = skl_color_commit;
> else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> - dev_priv->display.color_commit = hsw_color_commit;
> + dev_priv->display.funcs.color_commit = hsw_color_commit;
> else
> - dev_priv->display.color_commit = ilk_color_commit;
> + dev_priv->display.funcs.color_commit = ilk_color_commit;
>
> if (DISPLAY_VER(dev_priv) >= 11) {
> - dev_priv->display.load_luts = icl_load_luts;
> - dev_priv->display.read_luts = icl_read_luts;
> + dev_priv->display.funcs.load_luts = icl_load_luts;
> + dev_priv->display.funcs.read_luts = icl_read_luts;
> } else if (DISPLAY_VER(dev_priv) == 10) {
> - dev_priv->display.load_luts = glk_load_luts;
> - dev_priv->display.read_luts = glk_read_luts;
> + dev_priv->display.funcs.load_luts = glk_load_luts;
> + dev_priv->display.funcs.read_luts = glk_read_luts;
> } else if (DISPLAY_VER(dev_priv) >= 8) {
> - dev_priv->display.load_luts = bdw_load_luts;
> + dev_priv->display.funcs.load_luts = bdw_load_luts;
> } else if (DISPLAY_VER(dev_priv) >= 7) {
> - dev_priv->display.load_luts = ivb_load_luts;
> + dev_priv->display.funcs.load_luts = ivb_load_luts;
> } else {
> - dev_priv->display.load_luts = ilk_load_luts;
> - dev_priv->display.read_luts = ilk_read_luts;
> + dev_priv->display.funcs.load_luts = ilk_load_luts;
> + dev_priv->display.funcs.read_luts = ilk_read_luts;
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 1f447ba776c7..f31585e56e84 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2060,7 +2060,7 @@ static void ilk_pch_enable(const struct intel_atomic_state *state,
> assert_pch_transcoder_disabled(dev_priv, pipe);
>
> /* For PCH output, training FDI link */
> - dev_priv->display.fdi_link_train(crtc, crtc_state);
> + dev_priv->display.funcs.fdi_link_train(crtc, crtc_state);
>
> /* We need to program the right clock selection before writing the pixel
> * mutliplier into the DPLL. */
> @@ -2526,8 +2526,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
> * we'll continue to update watermarks the old way, if flags tell
> * us to.
> */
> - if (dev_priv->display.initial_watermarks)
> - dev_priv->display.initial_watermarks(state, crtc);
> + if (dev_priv->display.funcs.initial_watermarks)
> + dev_priv->display.funcs.initial_watermarks(state, crtc);
> else if (new_crtc_state->update_wm_pre)
> intel_update_watermarks(crtc);
> }
> @@ -2901,8 +2901,8 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
> /* update DSPCNTR to configure gamma for pipe bottom color */
> intel_disable_primary_plane(new_crtc_state);
>
> - if (dev_priv->display.initial_watermarks)
> - dev_priv->display.initial_watermarks(state, crtc);
> + if (dev_priv->display.funcs.initial_watermarks)
> + dev_priv->display.funcs.initial_watermarks(state, crtc);
> intel_enable_pipe(new_crtc_state);
>
> if (new_crtc_state->has_pch_encoder)
> @@ -3112,8 +3112,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> if (DISPLAY_VER(dev_priv) >= 11)
> icl_set_pipe_chicken(new_crtc_state);
>
> - if (dev_priv->display.initial_watermarks)
> - dev_priv->display.initial_watermarks(state, crtc);
> + if (dev_priv->display.funcs.initial_watermarks)
> + dev_priv->display.funcs.initial_watermarks(state, crtc);
>
> if (DISPLAY_VER(dev_priv) >= 11) {
> const struct intel_dbuf_state *dbuf_state =
> @@ -3530,7 +3530,7 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
> /* update DSPCNTR to configure gamma for pipe bottom color */
> intel_disable_primary_plane(new_crtc_state);
>
> - dev_priv->display.initial_watermarks(state, crtc);
> + dev_priv->display.funcs.initial_watermarks(state, crtc);
> intel_enable_pipe(new_crtc_state);
>
> intel_crtc_vblank_on(new_crtc_state);
> @@ -3573,8 +3573,8 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
> /* update DSPCNTR to configure gamma for pipe bottom color */
> intel_disable_primary_plane(new_crtc_state);
>
> - if (dev_priv->display.initial_watermarks)
> - dev_priv->display.initial_watermarks(state, crtc);
> + if (dev_priv->display.funcs.initial_watermarks)
> + dev_priv->display.funcs.initial_watermarks(state, crtc);
> else
> intel_update_watermarks(crtc);
> intel_enable_pipe(new_crtc_state);
> @@ -3642,7 +3642,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
> if (DISPLAY_VER(dev_priv) != 2)
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
>
> - if (!dev_priv->display.initial_watermarks)
> + if (!dev_priv->display.funcs.initial_watermarks)
> intel_update_watermarks(crtc);
>
> /* clock the pipe down to 640x480@60 to potentially save power */
> @@ -3696,7 +3696,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
>
> drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
>
> - dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
> + dev_priv->display.funcs.crtc_disable(to_intel_atomic_state(state), crtc);
>
> drm_atomic_state_put(state);
>
> @@ -5901,7 +5901,7 @@ static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>
> - if (!i915->display.get_pipe_config(crtc, crtc_state))
> + if (!i915->display.funcs.get_pipe_config(crtc, crtc_state))
> return false;
>
> crtc_state->hw.active = true;
> @@ -6728,10 +6728,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
> crtc_state->update_wm_post = true;
>
> if (mode_changed && crtc_state->hw.enable &&
> - dev_priv->display.crtc_compute_clock &&
> + dev_priv->display.funcs.crtc_compute_clock &&
> !crtc_state->bigjoiner_slave &&
> !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
> - ret = dev_priv->display.crtc_compute_clock(crtc_state);
> + ret = dev_priv->display.funcs.crtc_compute_clock(crtc_state);
> if (ret)
> return ret;
> }
> @@ -6750,8 +6750,8 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
> return ret;
> }
>
> - if (dev_priv->display.compute_pipe_wm) {
> - ret = dev_priv->display.compute_pipe_wm(state, crtc);
> + if (dev_priv->display.funcs.compute_pipe_wm) {
> + ret = dev_priv->display.funcs.compute_pipe_wm(state, crtc);
> if (ret) {
> drm_dbg_kms(&dev_priv->drm,
> "Target pipe watermarks are invalid\n");
> @@ -6760,9 +6760,9 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>
> }
>
> - if (dev_priv->display.compute_intermediate_wm) {
> + if (dev_priv->display.funcs.compute_intermediate_wm) {
> if (drm_WARN_ON(&dev_priv->drm,
> - !dev_priv->display.compute_pipe_wm))
> + !dev_priv->display.funcs.compute_pipe_wm))
> return 0;
>
> /*
> @@ -6770,7 +6770,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
> * old state and the new state. We can program these
> * immediately.
> */
> - ret = dev_priv->display.compute_intermediate_wm(state, crtc);
> + ret = dev_priv->display.funcs.compute_intermediate_wm(state, crtc);
> if (ret) {
> drm_dbg_kms(&dev_priv->drm,
> "No valid intermediate pipe watermarks are possible\n");
> @@ -8767,7 +8767,7 @@ static void intel_modeset_clear_plls(struct intel_atomic_state *state)
> struct intel_crtc *crtc;
> int i;
>
> - if (!dev_priv->display.crtc_compute_clock)
> + if (!dev_priv->display.funcs.crtc_compute_clock)
> return;
>
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> @@ -8879,8 +8879,8 @@ static int calc_watermark_data(struct intel_atomic_state *state)
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> /* Is there platform-specific watermark information to calculate? */
> - if (dev_priv->display.compute_global_watermarks)
> - return dev_priv->display.compute_global_watermarks(state);
> + if (dev_priv->display.funcs.compute_global_watermarks)
> + return dev_priv->display.funcs.compute_global_watermarks(state);
>
> return 0;
> }
> @@ -9080,7 +9080,7 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
> old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
> *need_cdclk_calc = true;
>
> - ret = dev_priv->display.bw_calc_min_cdclk(state);
> + ret = dev_priv->display.funcs.bw_calc_min_cdclk(state);
> if (ret)
> return ret;
>
> @@ -9705,8 +9705,8 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state,
> intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
> }
>
> - if (dev_priv->display.atomic_update_watermarks)
> - dev_priv->display.atomic_update_watermarks(state, crtc);
> + if (dev_priv->display.funcs.atomic_update_watermarks)
> + dev_priv->display.funcs.atomic_update_watermarks(state, crtc);
> }
>
> static void commit_pipe_post_planes(struct intel_atomic_state *state,
> @@ -9738,7 +9738,7 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
>
> intel_crtc_update_active_timings(new_crtc_state);
>
> - dev_priv->display.crtc_enable(state, crtc);
> + dev_priv->display.funcs.crtc_enable(state, crtc);
>
> if (new_crtc_state->bigjoiner_slave)
> return;
> @@ -9826,7 +9826,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> */
> intel_crtc_disable_pipe_crc(crtc);
>
> - dev_priv->display.crtc_disable(state, crtc);
> + dev_priv->display.funcs.crtc_disable(state, crtc);
> crtc->active = false;
> intel_fbc_disable(crtc);
> intel_disable_shared_dpll(old_crtc_state);
> @@ -9834,8 +9834,8 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> /* FIXME unify this for all platforms */
> if (!new_crtc_state->hw.active &&
> !HAS_GMCH(dev_priv) &&
> - dev_priv->display.initial_watermarks)
> - dev_priv->display.initial_watermarks(state, crtc);
> + dev_priv->display.funcs.initial_watermarks)
> + dev_priv->display.funcs.initial_watermarks(state, crtc);
> }
>
> static void intel_commit_modeset_disables(struct intel_atomic_state *state)
> @@ -10206,7 +10206,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> }
>
> /* Now enable the clocks, plane, pipe, and connectors that we set up. */
> - dev_priv->display.commit_modeset_enables(state);
> + dev_priv->display.funcs.commit_modeset_enables(state);
>
> if (state->modeset) {
> intel_encoders_update_complete(state);
> @@ -10257,8 +10257,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
> intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
>
> - if (dev_priv->display.optimize_watermarks)
> - dev_priv->display.optimize_watermarks(state, crtc);
> + if (dev_priv->display.funcs.optimize_watermarks)
> + dev_priv->display.funcs.optimize_watermarks(state, crtc);
> }
>
> intel_dbuf_post_plane_update(state);
> @@ -11225,36 +11225,36 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
> intel_dpll_init_clock_hook(dev_priv);
>
> if (DISPLAY_VER(dev_priv) >= 9) {
> - dev_priv->display.get_pipe_config = hsw_get_pipe_config;
> - dev_priv->display.crtc_enable = hsw_crtc_enable;
> - dev_priv->display.crtc_disable = hsw_crtc_disable;
> + dev_priv->display.funcs.get_pipe_config = hsw_get_pipe_config;
> + dev_priv->display.funcs.crtc_enable = hsw_crtc_enable;
> + dev_priv->display.funcs.crtc_disable = hsw_crtc_disable;
> } else if (HAS_DDI(dev_priv)) {
> - dev_priv->display.get_pipe_config = hsw_get_pipe_config;
> - dev_priv->display.crtc_enable = hsw_crtc_enable;
> - dev_priv->display.crtc_disable = hsw_crtc_disable;
> + dev_priv->display.funcs.get_pipe_config = hsw_get_pipe_config;
> + dev_priv->display.funcs.crtc_enable = hsw_crtc_enable;
> + dev_priv->display.funcs.crtc_disable = hsw_crtc_disable;
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> - dev_priv->display.get_pipe_config = ilk_get_pipe_config;
> - dev_priv->display.crtc_enable = ilk_crtc_enable;
> - dev_priv->display.crtc_disable = ilk_crtc_disable;
> + dev_priv->display.funcs.get_pipe_config = ilk_get_pipe_config;
> + dev_priv->display.funcs.crtc_enable = ilk_crtc_enable;
> + dev_priv->display.funcs.crtc_disable = ilk_crtc_disable;
> } else if (IS_CHERRYVIEW(dev_priv) ||
> IS_VALLEYVIEW(dev_priv)) {
> - dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
> - dev_priv->display.crtc_enable = valleyview_crtc_enable;
> - dev_priv->display.crtc_disable = i9xx_crtc_disable;
> + dev_priv->display.funcs.get_pipe_config = i9xx_get_pipe_config;
> + dev_priv->display.funcs.crtc_enable = valleyview_crtc_enable;
> + dev_priv->display.funcs.crtc_disable = i9xx_crtc_disable;
> } else {
> - dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
> - dev_priv->display.crtc_enable = i9xx_crtc_enable;
> - dev_priv->display.crtc_disable = i9xx_crtc_disable;
> + dev_priv->display.funcs.get_pipe_config = i9xx_get_pipe_config;
> + dev_priv->display.funcs.crtc_enable = i9xx_crtc_enable;
> + dev_priv->display.funcs.crtc_disable = i9xx_crtc_disable;
> }
>
> intel_fdi_init_hook(dev_priv);
>
> if (DISPLAY_VER(dev_priv) >= 9) {
> - dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
> - dev_priv->display.get_initial_plane_config = skl_get_initial_plane_config;
> + dev_priv->display.funcs.commit_modeset_enables = skl_commit_modeset_enables;
> + dev_priv->display.funcs.get_initial_plane_config = skl_get_initial_plane_config;
> } else {
> - dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
> - dev_priv->display.get_initial_plane_config = i9xx_get_initial_plane_config;
> + dev_priv->display.funcs.commit_modeset_enables = intel_commit_modeset_enables;
> + dev_priv->display.funcs.get_initial_plane_config = i9xx_get_initial_plane_config;
> }
>
> }
> @@ -11326,7 +11326,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
> int i;
>
> /* Only supported on platforms that use atomic watermark design */
> - if (!dev_priv->display.optimize_watermarks)
> + if (!dev_priv->display.funcs.optimize_watermarks)
> return;
>
> state = drm_atomic_state_alloc(&dev_priv->drm);
> @@ -11359,7 +11359,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
> /* Write calculated watermark values back */
> for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
> crtc_state->wm.need_postvbl_update = true;
> - dev_priv->display.optimize_watermarks(intel_state, crtc);
> + dev_priv->display.funcs.optimize_watermarks(intel_state, crtc);
>
> to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
> }
> @@ -11683,7 +11683,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
> * can even allow for smooth boot transitions if the BIOS
> * fb is large enough for the active pipe configuration.
> */
> - i915->display.get_initial_plane_config(crtc, &plane_config);
> + i915->display.funcs.get_initial_plane_config(crtc, &plane_config);
>
> /*
> * If the fb is shared between multiple heads, we'll
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index cce1a926fcc1..ebe4fee6d680 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1195,7 +1195,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv))
> return;
>
> - dev_priv->display.get_cdclk(dev_priv, &cdclk_config);
> + dev_priv->display.funcs.get_cdclk(dev_priv, &cdclk_config);
> /* Can't read out voltage_level so can't use intel_cdclk_changed() */
> drm_WARN_ON(&dev_priv->drm,
> intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 210f91f4a576..2dc7c0f95103 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1367,21 +1367,21 @@ void
> intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
> {
> if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
> - dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
> + dev_priv->display.funcs.crtc_compute_clock = hsw_crtc_compute_clock;
> else if (HAS_PCH_SPLIT(dev_priv))
> - dev_priv->display.crtc_compute_clock = ilk_crtc_compute_clock;
> + dev_priv->display.funcs.crtc_compute_clock = ilk_crtc_compute_clock;
> else if (IS_CHERRYVIEW(dev_priv))
> - dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
> + dev_priv->display.funcs.crtc_compute_clock = chv_crtc_compute_clock;
> else if (IS_VALLEYVIEW(dev_priv))
> - dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
> + dev_priv->display.funcs.crtc_compute_clock = vlv_crtc_compute_clock;
> else if (IS_G4X(dev_priv))
> - dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
> + dev_priv->display.funcs.crtc_compute_clock = g4x_crtc_compute_clock;
> else if (IS_PINEVIEW(dev_priv))
> - dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
> + dev_priv->display.funcs.crtc_compute_clock = pnv_crtc_compute_clock;
> else if (DISPLAY_VER(dev_priv) != 2)
> - dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
> + dev_priv->display.funcs.crtc_compute_clock = i9xx_crtc_compute_clock;
> else
> - dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
> + dev_priv->display.funcs.crtc_compute_clock = i8xx_crtc_compute_clock;
> }
>
> static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index fc09b781f15f..aaa0207f483e 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -1009,11 +1009,11 @@ void
> intel_fdi_init_hook(struct drm_i915_private *dev_priv)
> {
> if (IS_IRONLAKE(dev_priv)) {
> - dev_priv->display.fdi_link_train = ilk_fdi_link_train;
> + dev_priv->display.funcs.fdi_link_train = ilk_fdi_link_train;
> } else if (IS_SANDYBRIDGE(dev_priv)) {
> - dev_priv->display.fdi_link_train = gen6_fdi_link_train;
> + dev_priv->display.funcs.fdi_link_train = gen6_fdi_link_train;
> } else if (IS_IVYBRIDGE(dev_priv)) {
> /* FIXME: detect B0+ stepping and use auto training */
> - dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
> + dev_priv->display.funcs.fdi_link_train = ivb_manual_fdi_link_train;
> }
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
> index 47c85ac97c87..6c65efcb8a9c 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> @@ -215,8 +215,8 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
>
> static void intel_hpd_irq_setup(struct drm_i915_private *i915)
> {
> - if (i915->display_irqs_enabled && i915->display.hpd_irq_setup)
> - i915->display.hpd_irq_setup(i915);
> + if (i915->display_irqs_enabled && i915->display.funcs.hpd_irq_setup)
> + i915->display.funcs.hpd_irq_setup(i915);
> }
>
> static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index be2392bbcecc..04335bace0e3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -825,6 +825,11 @@ struct i915_selftest_stash {
> struct ida mock_region_instances;
> };
>
> +struct drm_i915_display {
> + /* Display functions */
> + struct drm_i915_display_funcs funcs;
> +};
> +
> struct drm_i915_private {
> struct drm_device drm;
>
> @@ -838,6 +843,8 @@ struct drm_i915_private {
> struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
> struct intel_driver_caps caps;
>
> + struct drm_i915_display display;
> +
> /**
> * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
> * end of stolen which we can optionally use to create GEM objects
> @@ -971,9 +978,6 @@ struct drm_i915_private {
> /* unbound hipri wq for page flips/plane updates */
> struct workqueue_struct *flip_wq;
>
> - /* Display functions */
> - struct drm_i915_display_funcs display;
> -
> /* PCH chipset type */
> enum intel_pch pch_type;
> unsigned short pch_id;
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 0a1681384c84..b1e3f51dc593 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -4395,20 +4395,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>
> if (HAS_GMCH(dev_priv)) {
> if (I915_HAS_HOTPLUG(dev_priv))
> - dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> + dev_priv->display.funcs.hpd_irq_setup = i915_hpd_irq_setup;
> } else {
> if (HAS_PCH_DG1(dev_priv))
> - dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
> + dev_priv->display.funcs.hpd_irq_setup = dg1_hpd_irq_setup;
> else if (DISPLAY_VER(dev_priv) >= 11)
> - dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
> + dev_priv->display.funcs.hpd_irq_setup = gen11_hpd_irq_setup;
> else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> - dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> + dev_priv->display.funcs.hpd_irq_setup = bxt_hpd_irq_setup;
> else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> - dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
> + dev_priv->display.funcs.hpd_irq_setup = icp_hpd_irq_setup;
> else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
> - dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> + dev_priv->display.funcs.hpd_irq_setup = spt_hpd_irq_setup;
> else
> - dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
> + dev_priv->display.funcs.hpd_irq_setup = ilk_hpd_irq_setup;
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index cfc41f8fa74a..0c64b3a94cf1 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2347,7 +2347,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> else
> wm_info = &i830_a_wm_info;
>
> - fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
> + fifo_size = dev_priv->display.funcs.get_fifo_size(dev_priv, PLANE_A);
> crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
> if (intel_crtc_active(crtc)) {
> const struct drm_display_mode *pipe_mode =
> @@ -2374,7 +2374,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> if (DISPLAY_VER(dev_priv) == 2)
> wm_info = &i830_bc_wm_info;
>
> - fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
> + fifo_size = dev_priv->display.funcs.get_fifo_size(dev_priv, PLANE_B);
> crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
> if (intel_crtc_active(crtc)) {
> const struct drm_display_mode *pipe_mode =
> @@ -2490,7 +2490,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
> pipe_mode = &crtc->config->hw.pipe_mode;
> planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
> &i845_wm_info,
> - dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
> + dev_priv->display.funcs.get_fifo_size(dev_priv, PLANE_A),
> 4, pessimal_latency_ns);
> fwater_lo = intel_uncore_read(&dev_priv->uncore, FW_BLC) & ~0xfff;
> fwater_lo |= (3<<8) | planea_wm;
> @@ -7167,8 +7167,8 @@ void intel_update_watermarks(struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - if (dev_priv->display.update_wm)
> - dev_priv->display.update_wm(crtc);
> + if (dev_priv->display.funcs.update_wm)
> + dev_priv->display.funcs.update_wm(crtc);
> }
>
> void intel_enable_ipc(struct drm_i915_private *dev_priv)
> @@ -7910,7 +7910,7 @@ static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
>
> void intel_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> - dev_priv->display.init_clock_gating(dev_priv);
> + dev_priv->display.funcs.init_clock_gating(dev_priv);
> }
>
> void intel_suspend_hw(struct drm_i915_private *dev_priv)
> @@ -7937,52 +7937,52 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
> void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> {
> if (IS_ALDERLAKE_P(dev_priv))
> - dev_priv->display.init_clock_gating = adlp_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = adlp_init_clock_gating;
> else if (IS_DG1(dev_priv))
> - dev_priv->display.init_clock_gating = dg1_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = dg1_init_clock_gating;
> else if (GRAPHICS_VER(dev_priv) == 12)
> - dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = gen12lp_init_clock_gating;
> else if (GRAPHICS_VER(dev_priv) == 11)
> - dev_priv->display.init_clock_gating = icl_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = icl_init_clock_gating;
> else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
> - dev_priv->display.init_clock_gating = cfl_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = cfl_init_clock_gating;
> else if (IS_SKYLAKE(dev_priv))
> - dev_priv->display.init_clock_gating = skl_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = skl_init_clock_gating;
> else if (IS_KABYLAKE(dev_priv))
> - dev_priv->display.init_clock_gating = kbl_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = kbl_init_clock_gating;
> else if (IS_BROXTON(dev_priv))
> - dev_priv->display.init_clock_gating = bxt_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = bxt_init_clock_gating;
> else if (IS_GEMINILAKE(dev_priv))
> - dev_priv->display.init_clock_gating = glk_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = glk_init_clock_gating;
> else if (IS_BROADWELL(dev_priv))
> - dev_priv->display.init_clock_gating = bdw_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = bdw_init_clock_gating;
> else if (IS_CHERRYVIEW(dev_priv))
> - dev_priv->display.init_clock_gating = chv_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = chv_init_clock_gating;
> else if (IS_HASWELL(dev_priv))
> - dev_priv->display.init_clock_gating = hsw_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = hsw_init_clock_gating;
> else if (IS_IVYBRIDGE(dev_priv))
> - dev_priv->display.init_clock_gating = ivb_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = ivb_init_clock_gating;
> else if (IS_VALLEYVIEW(dev_priv))
> - dev_priv->display.init_clock_gating = vlv_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = vlv_init_clock_gating;
> else if (GRAPHICS_VER(dev_priv) == 6)
> - dev_priv->display.init_clock_gating = gen6_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = gen6_init_clock_gating;
> else if (GRAPHICS_VER(dev_priv) == 5)
> - dev_priv->display.init_clock_gating = ilk_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = ilk_init_clock_gating;
> else if (IS_G4X(dev_priv))
> - dev_priv->display.init_clock_gating = g4x_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = g4x_init_clock_gating;
> else if (IS_I965GM(dev_priv))
> - dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = i965gm_init_clock_gating;
> else if (IS_I965G(dev_priv))
> - dev_priv->display.init_clock_gating = i965g_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = i965g_init_clock_gating;
> else if (GRAPHICS_VER(dev_priv) == 3)
> - dev_priv->display.init_clock_gating = gen3_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = gen3_init_clock_gating;
> else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
> - dev_priv->display.init_clock_gating = i85x_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = i85x_init_clock_gating;
> else if (GRAPHICS_VER(dev_priv) == 2)
> - dev_priv->display.init_clock_gating = i830_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = i830_init_clock_gating;
> else {
> MISSING_CASE(INTEL_DEVID(dev_priv));
> - dev_priv->display.init_clock_gating = nop_init_clock_gating;
> + dev_priv->display.funcs.init_clock_gating = nop_init_clock_gating;
> }
> }
>
> @@ -8001,7 +8001,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
> /* For FIFO watermark updates */
> if (DISPLAY_VER(dev_priv) >= 9) {
> skl_setup_wm_latency(dev_priv);
> - dev_priv->display.compute_global_watermarks = skl_compute_wm;
> + dev_priv->display.funcs.compute_global_watermarks = skl_compute_wm;
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> ilk_setup_wm_latency(dev_priv);
>
> @@ -8009,12 +8009,12 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
> dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
> (DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] &&
> dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
> - dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
> - dev_priv->display.compute_intermediate_wm =
> + dev_priv->display.funcs.compute_pipe_wm = ilk_compute_pipe_wm;
> + dev_priv->display.funcs.compute_intermediate_wm =
> ilk_compute_intermediate_wm;
> - dev_priv->display.initial_watermarks =
> + dev_priv->display.funcs.initial_watermarks =
> ilk_initial_watermarks;
> - dev_priv->display.optimize_watermarks =
> + dev_priv->display.funcs.optimize_watermarks =
> ilk_optimize_watermarks;
> } else {
> drm_dbg_kms(&dev_priv->drm,
> @@ -8023,17 +8023,17 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
> }
> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> vlv_setup_wm_latency(dev_priv);
> - dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;
> - dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;
> - dev_priv->display.initial_watermarks = vlv_initial_watermarks;
> - dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;
> - dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;
> + dev_priv->display.funcs.compute_pipe_wm = vlv_compute_pipe_wm;
> + dev_priv->display.funcs.compute_intermediate_wm = vlv_compute_intermediate_wm;
> + dev_priv->display.funcs.initial_watermarks = vlv_initial_watermarks;
> + dev_priv->display.funcs.optimize_watermarks = vlv_optimize_watermarks;
> + dev_priv->display.funcs.atomic_update_watermarks = vlv_atomic_update_fifo;
> } else if (IS_G4X(dev_priv)) {
> g4x_setup_wm_latency(dev_priv);
> - dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm;
> - dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm;
> - dev_priv->display.initial_watermarks = g4x_initial_watermarks;
> - dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
> + dev_priv->display.funcs.compute_pipe_wm = g4x_compute_pipe_wm;
> + dev_priv->display.funcs.compute_intermediate_wm = g4x_compute_intermediate_wm;
> + dev_priv->display.funcs.initial_watermarks = g4x_initial_watermarks;
> + dev_priv->display.funcs.optimize_watermarks = g4x_optimize_watermarks;
> } else if (IS_PINEVIEW(dev_priv)) {
> if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
> dev_priv->is_ddr3,
> @@ -8047,21 +8047,21 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
> dev_priv->fsb_freq, dev_priv->mem_freq);
> /* Disable CxSR and never update its watermark again */
> intel_set_memory_cxsr(dev_priv, false);
> - dev_priv->display.update_wm = NULL;
> + dev_priv->display.funcs.update_wm = NULL;
> } else
> - dev_priv->display.update_wm = pnv_update_wm;
> + dev_priv->display.funcs.update_wm = pnv_update_wm;
> } else if (DISPLAY_VER(dev_priv) == 4) {
> - dev_priv->display.update_wm = i965_update_wm;
> + dev_priv->display.funcs.update_wm = i965_update_wm;
> } else if (DISPLAY_VER(dev_priv) == 3) {
> - dev_priv->display.update_wm = i9xx_update_wm;
> - dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
> + dev_priv->display.funcs.update_wm = i9xx_update_wm;
> + dev_priv->display.funcs.get_fifo_size = i9xx_get_fifo_size;
> } else if (DISPLAY_VER(dev_priv) == 2) {
> if (INTEL_NUM_PIPES(dev_priv) == 1) {
> - dev_priv->display.update_wm = i845_update_wm;
> - dev_priv->display.get_fifo_size = i845_get_fifo_size;
> + dev_priv->display.funcs.update_wm = i845_update_wm;
> + dev_priv->display.funcs.get_fifo_size = i845_get_fifo_size;
> } else {
> - dev_priv->display.update_wm = i9xx_update_wm;
> - dev_priv->display.get_fifo_size = i830_get_fifo_size;
> + dev_priv->display.funcs.update_wm = i9xx_update_wm;
> + dev_priv->display.funcs.get_fifo_size = i830_get_fifo_size;
> }
> } else {
> drm_err(&dev_priv->drm,
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Intel-gfx] [PATCH 01/10] drm/i915: move display funcs into a display struct.
2021-09-06 8:18 ` Jani Nikula
@ 2021-09-06 19:44 ` Dave Airlie
2021-09-07 8:14 ` Daniel Vetter
0 siblings, 1 reply; 20+ messages in thread
From: Dave Airlie @ 2021-09-06 19:44 UTC (permalink / raw)
To: Jani Nikula
Cc: Intel Graphics Development, Syrjala, Ville, Rodrigo Vivi,
Joonas Lahtinen, Daniel Vetter
On Mon, 6 Sept 2021 at 18:18, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>
> On Mon, 06 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> > From: Dave Airlie <airlied@redhat.com>
> >
> > This is the first step in an idea to refactor the display code
> > into a bit more of a corner.
>
> So, do we want to make i915->display a pointer?
>
> If we do, and we're about to touch every place accessing the display
> struct, we might just as well have:
>
> struct drm_i915_private {
> struct drm_i915_display _display;
> struct drm_i915_display *display;
> };
>
> and initialize i915->display = &i915->_display, and make all access
> happen via the pointer. If we want to allocate it dynamically at some
> point, it'll be a *much* easier task.
>
> But the first question to figure out is whether we want to do that or
> not.
I think the advantage is that we can hide a lot more structs from the
main struct,
the disadvantage is additional pointer chasing, esp for the drm_device and other
i915_priv members.
Has anyone any non-anecdotal knowledge of how bad the latter problem
actually is?
Other drivers seem to do a lot of it and nobody has complained about it.
I'm happy to move to a pointer for it all to be honest,
Dave.
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Intel-gfx] [PATCH 01/10] drm/i915: move display funcs into a display struct.
2021-09-06 19:44 ` Dave Airlie
@ 2021-09-07 8:14 ` Daniel Vetter
2021-09-07 9:52 ` Dave Airlie
0 siblings, 1 reply; 20+ messages in thread
From: Daniel Vetter @ 2021-09-07 8:14 UTC (permalink / raw)
To: Dave Airlie
Cc: Jani Nikula, Intel Graphics Development, Syrjala, Ville,
Rodrigo Vivi, Joonas Lahtinen, Daniel Vetter
On Mon, Sep 6, 2021 at 9:45 PM Dave Airlie <airlied@gmail.com> wrote:
> On Mon, 6 Sept 2021 at 18:18, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> > On Mon, 06 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> > > From: Dave Airlie <airlied@redhat.com>
> > >
> > > This is the first step in an idea to refactor the display code
> > > into a bit more of a corner.
> >
> > So, do we want to make i915->display a pointer?
> >
> > If we do, and we're about to touch every place accessing the display
> > struct, we might just as well have:
> >
> > struct drm_i915_private {
> > struct drm_i915_display _display;
> > struct drm_i915_display *display;
> > };
> >
> > and initialize i915->display = &i915->_display, and make all access
> > happen via the pointer. If we want to allocate it dynamically at some
> > point, it'll be a *much* easier task.
> >
> > But the first question to figure out is whether we want to do that or
> > not.
>
> I think the advantage is that we can hide a lot more structs from the
> main struct,
> the disadvantage is additional pointer chasing, esp for the drm_device and other
> i915_priv members.
For display pointer chasing doesn't matter at all. Imo the case is
more what make sense as object hierarchy, and embedding vs pointer has
quite different meaning. We've discussed in the past that the split
into display/gem with branches seems to work ok-ish, but could
probably be improved a lot in code org. If we make display a lot more
a free-standing thing (i.e. pointer, not embedding) with a much more
clearer/cleaner api contract to other pieces, then maybe there's some
case to be made for all this churn.
The problem with all that is that we'd then essentially need to
backpointers everywhere in all display structures: One to the
drm_device provided by base structs, and the other to the i915_display
struct, which is what our code uses. This way display would stay
display. In a way this would then look similarly-ish to amdgpu's DC.
But I'm honestly not sure how much that would improve anything, and
whether it's worth all the churn to make drm/i915/display more
self-contained.
-Daniel
> Has anyone any non-anecdotal knowledge of how bad the latter problem
> actually is?
> Other drivers seem to do a lot of it and nobody has complained about it.
>
> I'm happy to move to a pointer for it all to be honest,
> Dave.
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Intel-gfx] [PATCH 01/10] drm/i915: move display funcs into a display struct.
2021-09-07 8:14 ` Daniel Vetter
@ 2021-09-07 9:52 ` Dave Airlie
2021-09-07 18:14 ` Ville Syrjälä
0 siblings, 1 reply; 20+ messages in thread
From: Dave Airlie @ 2021-09-07 9:52 UTC (permalink / raw)
To: Daniel Vetter
Cc: Jani Nikula, Intel Graphics Development, Syrjala, Ville,
Rodrigo Vivi, Joonas Lahtinen, Daniel Vetter
On Tue, 7 Sept 2021 at 18:15, Daniel Vetter <daniel@ffwll.ch> wrote:
>
> On Mon, Sep 6, 2021 at 9:45 PM Dave Airlie <airlied@gmail.com> wrote:
> > On Mon, 6 Sept 2021 at 18:18, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> > > On Mon, 06 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> > > > From: Dave Airlie <airlied@redhat.com>
> > > >
> > > > This is the first step in an idea to refactor the display code
> > > > into a bit more of a corner.
> > >
> > > So, do we want to make i915->display a pointer?
> > >
> > > If we do, and we're about to touch every place accessing the display
> > > struct, we might just as well have:
> > >
> > > struct drm_i915_private {
> > > struct drm_i915_display _display;
> > > struct drm_i915_display *display;
> > > };
> > >
> > > and initialize i915->display = &i915->_display, and make all access
> > > happen via the pointer. If we want to allocate it dynamically at some
> > > point, it'll be a *much* easier task.
> > >
> > > But the first question to figure out is whether we want to do that or
> > > not.
> >
> > I think the advantage is that we can hide a lot more structs from the
> > main struct,
> > the disadvantage is additional pointer chasing, esp for the drm_device and other
> > i915_priv members.
>
> For display pointer chasing doesn't matter at all. Imo the case is
> more what make sense as object hierarchy, and embedding vs pointer has
> quite different meaning. We've discussed in the past that the split
> into display/gem with branches seems to work ok-ish, but could
> probably be improved a lot in code org. If we make display a lot more
> a free-standing thing (i.e. pointer, not embedding) with a much more
> clearer/cleaner api contract to other pieces, then maybe there's some
> case to be made for all this churn.
I'd like to make it at least have some form of API between display and core/gt.
I think the main things I've noticed where it's kinda free for all at
the moment are:
- display funcs has pm internal funcs, display<->pm funcs, display
only audio funcs,
display only color funcs, other display internal funcs all mixed into
one super struct.
There's no split between things that provide service to display and vice-versa.
I've started looking at splitting this.
- tracepoints - i915_trace.h pulls in display and gt stuff, no idea if
we can split that,
but lots of things include i915_trace.h which means everyone sees
everyone elses guts.
One problem area I've noticed after hacking on making display more
contained, was for
lots of things dev_priv can go away, however you'd have to duplicate
all the GRAPHICS_
and IS_* macros which might get messy quick, having access to core
stuff like device_info
and params might need more thought.
> The problem with all that is that we'd then essentially need to
> backpointers everywhere in all display structures: One to the
> drm_device provided by base structs, and the other to the i915_display
> struct, which is what our code uses. This way display would stay
> display. In a way this would then look similarly-ish to amdgpu's DC.
>
> But I'm honestly not sure how much that would improve anything, and
> whether it's worth all the churn to make drm/i915/display more
> self-contained.
It might make display more manageable or future proof if we have
distinct interfaces into it, instead of the free for all we have now.
Dave.
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Intel-gfx] [PATCH 01/10] drm/i915: move display funcs into a display struct.
2021-09-07 9:52 ` Dave Airlie
@ 2021-09-07 18:14 ` Ville Syrjälä
2021-09-08 1:05 ` Dave Airlie
0 siblings, 1 reply; 20+ messages in thread
From: Ville Syrjälä @ 2021-09-07 18:14 UTC (permalink / raw)
To: Dave Airlie
Cc: Daniel Vetter, Jani Nikula, Intel Graphics Development,
Rodrigo Vivi, Joonas Lahtinen, Daniel Vetter
On Tue, Sep 07, 2021 at 07:52:17PM +1000, Dave Airlie wrote:
> On Tue, 7 Sept 2021 at 18:15, Daniel Vetter <daniel@ffwll.ch> wrote:
> >
> > On Mon, Sep 6, 2021 at 9:45 PM Dave Airlie <airlied@gmail.com> wrote:
> > > On Mon, 6 Sept 2021 at 18:18, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> > > > On Mon, 06 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> > > > > From: Dave Airlie <airlied@redhat.com>
> > > > >
> > > > > This is the first step in an idea to refactor the display code
> > > > > into a bit more of a corner.
> > > >
> > > > So, do we want to make i915->display a pointer?
> > > >
> > > > If we do, and we're about to touch every place accessing the display
> > > > struct, we might just as well have:
> > > >
> > > > struct drm_i915_private {
> > > > struct drm_i915_display _display;
> > > > struct drm_i915_display *display;
> > > > };
> > > >
> > > > and initialize i915->display = &i915->_display, and make all access
> > > > happen via the pointer. If we want to allocate it dynamically at some
> > > > point, it'll be a *much* easier task.
> > > >
> > > > But the first question to figure out is whether we want to do that or
> > > > not.
> > >
> > > I think the advantage is that we can hide a lot more structs from the
> > > main struct,
> > > the disadvantage is additional pointer chasing, esp for the drm_device and other
> > > i915_priv members.
> >
> > For display pointer chasing doesn't matter at all. Imo the case is
> > more what make sense as object hierarchy, and embedding vs pointer has
> > quite different meaning. We've discussed in the past that the split
> > into display/gem with branches seems to work ok-ish, but could
> > probably be improved a lot in code org. If we make display a lot more
> > a free-standing thing (i.e. pointer, not embedding) with a much more
> > clearer/cleaner api contract to other pieces, then maybe there's some
> > case to be made for all this churn.
>
> I'd like to make it at least have some form of API between display and core/gt.
>
> I think the main things I've noticed where it's kinda free for all at
> the moment are:
> - display funcs has pm internal funcs, display<->pm funcs, display
> only audio funcs,
> display only color funcs, other display internal funcs all mixed into
> one super struct.
I think the solution for these is mostly just more localized function
pointer structs/etc. Never been a fan of the old catch-all display
funcs thing. Pretty sure I even have eg. a cdclk_funcs struct sitting
in some branch somewhere.
> There's no split between things that provide service to display and vice-versa.
> I've started looking at splitting this.
> - tracepoints - i915_trace.h pulls in display and gt stuff, no idea if
> we can split that,
> but lots of things include i915_trace.h which means everyone sees
> everyone elses guts.
Yeah, I've been thinking of splitting this but haven't actually looked
into how feasible it is. The convoluted macro stuff makes it hard to
see how any of it really works, and in the past I did have some real
include order problems with it.
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Intel-gfx] [PATCH 01/10] drm/i915: move display funcs into a display struct.
2021-09-07 18:14 ` Ville Syrjälä
@ 2021-09-08 1:05 ` Dave Airlie
0 siblings, 0 replies; 20+ messages in thread
From: Dave Airlie @ 2021-09-08 1:05 UTC (permalink / raw)
To: Ville Syrjälä
Cc: Daniel Vetter, Jani Nikula, Intel Graphics Development,
Rodrigo Vivi, Joonas Lahtinen, Daniel Vetter
On Wed, 8 Sept 2021 at 04:14, Ville Syrjälä <ville.syrjala@intel.com> wrote:
>
> On Tue, Sep 07, 2021 at 07:52:17PM +1000, Dave Airlie wrote:
> > On Tue, 7 Sept 2021 at 18:15, Daniel Vetter <daniel@ffwll.ch> wrote:
> > >
> > > On Mon, Sep 6, 2021 at 9:45 PM Dave Airlie <airlied@gmail.com> wrote:
> > > > On Mon, 6 Sept 2021 at 18:18, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> > > > > On Mon, 06 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> > > > > > From: Dave Airlie <airlied@redhat.com>
> > > > > >
> > > > > > This is the first step in an idea to refactor the display code
> > > > > > into a bit more of a corner.
> > > > >
> > > > > So, do we want to make i915->display a pointer?
> > > > >
> > > > > If we do, and we're about to touch every place accessing the display
> > > > > struct, we might just as well have:
> > > > >
> > > > > struct drm_i915_private {
> > > > > struct drm_i915_display _display;
> > > > > struct drm_i915_display *display;
> > > > > };
> > > > >
> > > > > and initialize i915->display = &i915->_display, and make all access
> > > > > happen via the pointer. If we want to allocate it dynamically at some
> > > > > point, it'll be a *much* easier task.
> > > > >
> > > > > But the first question to figure out is whether we want to do that or
> > > > > not.
> > > >
> > > > I think the advantage is that we can hide a lot more structs from the
> > > > main struct,
> > > > the disadvantage is additional pointer chasing, esp for the drm_device and other
> > > > i915_priv members.
> > >
> > > For display pointer chasing doesn't matter at all. Imo the case is
> > > more what make sense as object hierarchy, and embedding vs pointer has
> > > quite different meaning. We've discussed in the past that the split
> > > into display/gem with branches seems to work ok-ish, but could
> > > probably be improved a lot in code org. If we make display a lot more
> > > a free-standing thing (i.e. pointer, not embedding) with a much more
> > > clearer/cleaner api contract to other pieces, then maybe there's some
> > > case to be made for all this churn.
> >
> > I'd like to make it at least have some form of API between display and core/gt.
> >
> > I think the main things I've noticed where it's kinda free for all at
> > the moment are:
> > - display funcs has pm internal funcs, display<->pm funcs, display
> > only audio funcs,
> > display only color funcs, other display internal funcs all mixed into
> > one super struct.
>
> I think the solution for these is mostly just more localized function
> pointer structs/etc. Never been a fan of the old catch-all display
> funcs thing. Pretty sure I even have eg. a cdclk_funcs struct sitting
> in some branch somewhere.
I've just posted a series cleaning this out, I've got some followups
that more of an RFC
https://cgit.freedesktop.org/~airlied/linux/log/?h=drm-i915-display-funcs-constify
(the last 7 patches there).
Those move the struct defs that are internal vtables into the display headers.
> > There's no split between things that provide service to display and vice-versa.
> > I've started looking at splitting this.
> > - tracepoints - i915_trace.h pulls in display and gt stuff, no idea if
> > we can split that,
> > but lots of things include i915_trace.h which means everyone sees
> > everyone elses guts.
>
> Yeah, I've been thinking of splitting this but haven't actually looked
> into how feasible it is. The convoluted macro stuff makes it hard to
> see how any of it really works, and in the past I did have some real
> include order problems with it.
Yeah I started looking yesterday and ran into macro pain, I might try
another run at it.
Dave.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 02/10] drm/i915/display: move cdclk info into display
2021-09-06 3:43 [Intel-gfx] [RFC PATCH 00/10] refactor display structs a little bit Dave Airlie
2021-09-06 3:43 ` [Intel-gfx] [PATCH 01/10] drm/i915: move display funcs into a display struct Dave Airlie
@ 2021-09-06 3:43 ` Dave Airlie
2021-09-06 3:43 ` [Intel-gfx] [PATCH 03/10] drm/i915: move more pll/clocks into display struct Dave Airlie
` (10 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Dave Airlie @ 2021-09-06 3:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_audio.c | 4 +-
.../gpu/drm/i915/display/intel_backlight.c | 4 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 196 +++++++++---------
drivers/gpu/drm/i915/display/intel_cdclk.h | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 16 +-
.../drm/i915/display/intel_display_power.c | 4 +-
drivers/gpu/drm/i915/display/intel_dp.c | 4 +-
drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 4 +-
drivers/gpu/drm/i915/i915_debugfs.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 23 +-
13 files changed, 136 insertions(+), 135 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index fd56191c8a68..8ccf765840da 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -530,7 +530,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
vdsc_bpp = crtc_state->dsc.compressed_bpp;
- cdclk = i915->cdclk.hw.cdclk;
+ cdclk = i915->display.cdclk.hw.cdclk;
/* fec= 0.972261, using rounding multiplier of 1000000 */
fec_coeff = 972261;
link_clk = crtc_state->port_clock;
@@ -1076,7 +1076,7 @@ static int i915_audio_component_get_cdclk_freq(struct device *kdev)
if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DDI(dev_priv)))
return -ENODEV;
- return dev_priv->cdclk.hw.cdclk;
+ return dev_priv->display.cdclk.hw.cdclk;
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index 9523411cddd8..d4d5cd9fdefb 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -1108,7 +1108,7 @@ static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
if (IS_PINEVIEW(dev_priv))
clock = KHz(RUNTIME_INFO(dev_priv)->rawclk_freq);
else
- clock = KHz(dev_priv->cdclk.hw.cdclk);
+ clock = KHz(dev_priv->display.cdclk.hw.cdclk);
return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 32);
}
@@ -1126,7 +1126,7 @@ static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
if (IS_G4X(dev_priv))
clock = KHz(RUNTIME_INFO(dev_priv)->rawclk_freq);
else
- clock = KHz(dev_priv->cdclk.hw.cdclk);
+ clock = KHz(dev_priv->display.cdclk.hw.cdclk);
return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 128);
}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index becbf0fc4c4d..cb54a0c8b4e0 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -506,7 +506,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
else
default_credits = PFI_CREDIT(8);
- if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
+ if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) {
/* CHV suggested value is 31 or 63 */
if (IS_CHERRYVIEW(dev_priv))
credits = PFI_CREDIT_63;
@@ -985,7 +985,7 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
drm_err(&dev_priv->drm, "DPLL0 not locked\n");
- dev_priv->cdclk.hw.vco = vco;
+ dev_priv->display.cdclk.hw.vco = vco;
/* We'll want to keep using the current vco from now on. */
skl_set_preferred_cdclk_vco(dev_priv, vco);
@@ -999,7 +999,7 @@ static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n");
- dev_priv->cdclk.hw.vco = 0;
+ dev_priv->display.cdclk.hw.vco = 0;
}
static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv,
@@ -1008,7 +1008,7 @@ static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv,
switch (cdclk) {
default:
drm_WARN_ON(&dev_priv->drm,
- cdclk != dev_priv->cdclk.hw.bypass);
+ cdclk != dev_priv->display.cdclk.hw.bypass);
drm_WARN_ON(&dev_priv->drm, vco != 0);
fallthrough;
case 308571:
@@ -1057,13 +1057,13 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco);
- if (dev_priv->cdclk.hw.vco != 0 &&
- dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display.cdclk.hw.vco != 0 &&
+ dev_priv->display.cdclk.hw.vco != vco)
skl_dpll0_disable(dev_priv);
cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL);
- if (dev_priv->cdclk.hw.vco != vco) {
+ if (dev_priv->display.cdclk.hw.vco != vco) {
/* Wa Display #1183: skl,kbl,cfl */
cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
@@ -1075,7 +1075,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
intel_de_posting_read(dev_priv, CDCLK_CTL);
- if (dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display.cdclk.hw.vco != vco)
skl_dpll0_enable(dev_priv, vco);
/* Wa Display #1183: skl,kbl,cfl */
@@ -1110,11 +1110,11 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
goto sanitize;
intel_update_cdclk(dev_priv);
- intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
+ intel_dump_cdclk_config(&dev_priv->display.cdclk.hw, "Current CDCLK");
/* Is PLL enabled and locked ? */
- if (dev_priv->cdclk.hw.vco == 0 ||
- dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
+ if (dev_priv->display.cdclk.hw.vco == 0 ||
+ dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
goto sanitize;
/* DPLL okay; verify the cdclock
@@ -1125,7 +1125,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
*/
cdctl = intel_de_read(dev_priv, CDCLK_CTL);
expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
- skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
+ skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk);
if (cdctl == expected)
/* All well; nothing to sanitize */
return;
@@ -1134,9 +1134,9 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
/* force cdclk programming */
- dev_priv->cdclk.hw.cdclk = 0;
+ dev_priv->display.cdclk.hw.cdclk = 0;
/* force full PLL disable + enable */
- dev_priv->cdclk.hw.vco = -1;
+ dev_priv->display.cdclk.hw.vco = -1;
}
static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
@@ -1145,19 +1145,19 @@ static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
skl_sanitize_cdclk(dev_priv);
- if (dev_priv->cdclk.hw.cdclk != 0 &&
- dev_priv->cdclk.hw.vco != 0) {
+ if (dev_priv->display.cdclk.hw.cdclk != 0 &&
+ dev_priv->display.cdclk.hw.vco != 0) {
/*
* Use the current vco as our initial
* guess as to what the preferred vco is.
*/
if (dev_priv->skl_preferred_vco_freq == 0)
skl_set_preferred_cdclk_vco(dev_priv,
- dev_priv->cdclk.hw.vco);
+ dev_priv->display.cdclk.hw.vco);
return;
}
- cdclk_config = dev_priv->cdclk.hw;
+ cdclk_config = dev_priv->display.cdclk.hw;
cdclk_config.vco = dev_priv->skl_preferred_vco_freq;
if (cdclk_config.vco == 0)
@@ -1170,7 +1170,7 @@ static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
{
- struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
+ struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
cdclk_config.cdclk = cdclk_config.bypass;
cdclk_config.vco = 0;
@@ -1291,35 +1291,35 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
- const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
+ const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
int i;
for (i = 0; table[i].refclk; i++)
- if (table[i].refclk == dev_priv->cdclk.hw.ref &&
+ if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
table[i].cdclk >= min_cdclk)
return table[i].cdclk;
drm_WARN(&dev_priv->drm, 1,
"Cannot satisfy minimum cdclk %d with refclk %u\n",
- min_cdclk, dev_priv->cdclk.hw.ref);
+ min_cdclk, dev_priv->display.cdclk.hw.ref);
return 0;
}
static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
{
- const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
+ const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
int i;
- if (cdclk == dev_priv->cdclk.hw.bypass)
+ if (cdclk == dev_priv->display.cdclk.hw.bypass)
return 0;
for (i = 0; table[i].refclk; i++)
- if (table[i].refclk == dev_priv->cdclk.hw.ref &&
+ if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
table[i].cdclk == cdclk)
- return dev_priv->cdclk.hw.ref * table[i].ratio;
+ return dev_priv->display.cdclk.hw.ref * table[i].ratio;
drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
- cdclk, dev_priv->cdclk.hw.ref);
+ cdclk, dev_priv->display.cdclk.hw.ref);
return 0;
}
@@ -1478,12 +1478,12 @@ static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n");
- dev_priv->cdclk.hw.vco = 0;
+ dev_priv->display.cdclk.hw.vco = 0;
}
static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
{
- int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
+ int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
intel_de_rmw(dev_priv, BXT_DE_PLL_CTL,
BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio));
@@ -1495,7 +1495,7 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n");
- dev_priv->cdclk.hw.vco = vco;
+ dev_priv->display.cdclk.hw.vco = vco;
}
static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
@@ -1507,12 +1507,12 @@ static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n");
- dev_priv->cdclk.hw.vco = 0;
+ dev_priv->display.cdclk.hw.vco = 0;
}
static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
{
- int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
+ int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
u32 val;
val = ICL_CDCLK_PLL_RATIO(ratio);
@@ -1525,12 +1525,12 @@ static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n");
- dev_priv->cdclk.hw.vco = vco;
+ dev_priv->display.cdclk.hw.vco = vco;
}
static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
{
- int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
+ int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
u32 val;
/* Write PLL ratio without disabling */
@@ -1549,7 +1549,7 @@ static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
val &= ~BXT_DE_PLL_FREQ_REQ;
intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
- dev_priv->cdclk.hw.vco = vco;
+ dev_priv->display.cdclk.hw.vco = vco;
}
static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
@@ -1579,7 +1579,7 @@ static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv,
switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
default:
drm_WARN_ON(&dev_priv->drm,
- cdclk != dev_priv->cdclk.hw.bypass);
+ cdclk != dev_priv->display.cdclk.hw.bypass);
drm_WARN_ON(&dev_priv->drm, vco != 0);
fallthrough;
case 2:
@@ -1624,22 +1624,22 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
return;
}
- if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
- if (dev_priv->cdclk.hw.vco != vco)
+ if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0) {
+ if (dev_priv->display.cdclk.hw.vco != vco)
adlp_cdclk_pll_crawl(dev_priv, vco);
} else if (DISPLAY_VER(dev_priv) >= 11) {
- if (dev_priv->cdclk.hw.vco != 0 &&
- dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display.cdclk.hw.vco != 0 &&
+ dev_priv->display.cdclk.hw.vco != vco)
icl_cdclk_pll_disable(dev_priv);
- if (dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display.cdclk.hw.vco != vco)
icl_cdclk_pll_enable(dev_priv, vco);
} else {
- if (dev_priv->cdclk.hw.vco != 0 &&
- dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display.cdclk.hw.vco != 0 &&
+ dev_priv->display.cdclk.hw.vco != vco)
bxt_de_pll_disable(dev_priv);
- if (dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display.cdclk.hw.vco != vco)
bxt_de_pll_enable(dev_priv, vco);
}
@@ -1689,7 +1689,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
* Can't read out the voltage level :(
* Let's just assume everything is as expected.
*/
- dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level;
+ dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level;
}
static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
@@ -1698,10 +1698,10 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
int cdclk, vco;
intel_update_cdclk(dev_priv);
- intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
+ intel_dump_cdclk_config(&dev_priv->display.cdclk.hw, "Current CDCLK");
- if (dev_priv->cdclk.hw.vco == 0 ||
- dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
+ if (dev_priv->display.cdclk.hw.vco == 0 ||
+ dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
goto sanitize;
/* DPLL okay; verify the cdclock
@@ -1719,28 +1719,28 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
/* Make sure this is a legal cdclk value for the platform */
- cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk);
- if (cdclk != dev_priv->cdclk.hw.cdclk)
+ cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk);
+ if (cdclk != dev_priv->display.cdclk.hw.cdclk)
goto sanitize;
/* Make sure the VCO is correct for the cdclk */
vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
- if (vco != dev_priv->cdclk.hw.vco)
+ if (vco != dev_priv->display.cdclk.hw.vco)
goto sanitize;
expected = skl_cdclk_decimal(cdclk);
/* Figure out what CD2X divider we should be using for this cdclk */
expected |= bxt_cdclk_cd2x_div_sel(dev_priv,
- dev_priv->cdclk.hw.cdclk,
- dev_priv->cdclk.hw.vco);
+ dev_priv->display.cdclk.hw.cdclk,
+ dev_priv->display.cdclk.hw.vco);
/*
* Disable SSA Precharge when CD clock frequency < 500 MHz,
* enable otherwise.
*/
if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
- dev_priv->cdclk.hw.cdclk >= 500000)
+ dev_priv->display.cdclk.hw.cdclk >= 500000)
expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
if (cdctl == expected)
@@ -1751,10 +1751,10 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
/* force cdclk programming */
- dev_priv->cdclk.hw.cdclk = 0;
+ dev_priv->display.cdclk.hw.cdclk = 0;
/* force full PLL disable + enable */
- dev_priv->cdclk.hw.vco = -1;
+ dev_priv->display.cdclk.hw.vco = -1;
}
static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
@@ -1763,11 +1763,11 @@ static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
bxt_sanitize_cdclk(dev_priv);
- if (dev_priv->cdclk.hw.cdclk != 0 &&
- dev_priv->cdclk.hw.vco != 0)
+ if (dev_priv->display.cdclk.hw.cdclk != 0 &&
+ dev_priv->display.cdclk.hw.vco != 0)
return;
- cdclk_config = dev_priv->cdclk.hw;
+ cdclk_config = dev_priv->display.cdclk.hw;
/*
* FIXME:
@@ -1784,7 +1784,7 @@ static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
{
- struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
+ struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
cdclk_config.cdclk = cdclk_config.bypass;
cdclk_config.vco = 0;
@@ -1798,7 +1798,7 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
* intel_cdclk_init_hw - Initialize CDCLK hardware
* @i915: i915 device
*
- * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and
+ * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and
* sanitizing the state of the hardware if needed. This is generally done only
* during the display core initialization sequence, after which the DMC will
* take care of turning CDCLK off/on as needed.
@@ -1929,7 +1929,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
{
struct intel_encoder *encoder;
- if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
+ if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config))
return;
if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.set_cdclk))
@@ -1972,9 +1972,9 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
}
if (drm_WARN(&dev_priv->drm,
- intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config),
+ intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config),
"cdclk state doesn't match!\n")) {
- intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]");
+ intel_dump_cdclk_config(&dev_priv->display.cdclk.hw, "[hw state]");
intel_dump_cdclk_config(cdclk_config, "[sw state]");
}
}
@@ -2155,13 +2155,13 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
*/
min_cdclk = max_t(int, min_cdclk,
min_t(int, crtc_state->pixel_rate,
- dev_priv->max_cdclk_freq));
+ dev_priv->display.max_cdclk_freq));
}
- if (min_cdclk > dev_priv->max_cdclk_freq) {
+ if (min_cdclk > dev_priv->display.max_cdclk_freq) {
drm_dbg_kms(&dev_priv->drm,
"required cdclk (%d kHz) exceeds max (%d kHz)\n",
- min_cdclk, dev_priv->max_cdclk_freq);
+ min_cdclk, dev_priv->display.max_cdclk_freq);
return -EINVAL;
}
@@ -2477,7 +2477,7 @@ intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_global_state *cdclk_state;
- cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj);
+ cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj);
if (IS_ERR(cdclk_state))
return ERR_CAST(cdclk_state);
@@ -2492,7 +2492,7 @@ int intel_cdclk_init(struct drm_i915_private *dev_priv)
if (!cdclk_state)
return -ENOMEM;
- intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj,
+ intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj,
&cdclk_state->base, &intel_cdclk_funcs);
return 0;
@@ -2593,7 +2593,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
{
- int max_cdclk_freq = dev_priv->max_cdclk_freq;
+ int max_cdclk_freq = dev_priv->display.max_cdclk_freq;
if (DISPLAY_VER(dev_priv) >= 10)
return 2 * max_cdclk_freq;
@@ -2619,19 +2619,19 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
{
if (IS_JSL_EHL(dev_priv)) {
- if (dev_priv->cdclk.hw.ref == 24000)
- dev_priv->max_cdclk_freq = 552000;
+ if (dev_priv->display.cdclk.hw.ref == 24000)
+ dev_priv->display.max_cdclk_freq = 552000;
else
- dev_priv->max_cdclk_freq = 556800;
+ dev_priv->display.max_cdclk_freq = 556800;
} else if (DISPLAY_VER(dev_priv) >= 11) {
- if (dev_priv->cdclk.hw.ref == 24000)
- dev_priv->max_cdclk_freq = 648000;
+ if (dev_priv->display.cdclk.hw.ref == 24000)
+ dev_priv->display.max_cdclk_freq = 648000;
else
- dev_priv->max_cdclk_freq = 652800;
+ dev_priv->display.max_cdclk_freq = 652800;
} else if (IS_GEMINILAKE(dev_priv)) {
- dev_priv->max_cdclk_freq = 316800;
+ dev_priv->display.max_cdclk_freq = 316800;
} else if (IS_BROXTON(dev_priv)) {
- dev_priv->max_cdclk_freq = 624000;
+ dev_priv->display.max_cdclk_freq = 624000;
} else if (DISPLAY_VER(dev_priv) == 9) {
u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
int max_cdclk, vco;
@@ -2653,7 +2653,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
else
max_cdclk = 308571;
- dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
+ dev_priv->display.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
} else if (IS_BROADWELL(dev_priv)) {
/*
* FIXME with extra cooling we can allow
@@ -2662,26 +2662,26 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
* available? PCI ID, VTB, something else?
*/
if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
- dev_priv->max_cdclk_freq = 450000;
+ dev_priv->display.max_cdclk_freq = 450000;
else if (IS_BDW_ULX(dev_priv))
- dev_priv->max_cdclk_freq = 450000;
+ dev_priv->display.max_cdclk_freq = 450000;
else if (IS_BDW_ULT(dev_priv))
- dev_priv->max_cdclk_freq = 540000;
+ dev_priv->display.max_cdclk_freq = 540000;
else
- dev_priv->max_cdclk_freq = 675000;
+ dev_priv->display.max_cdclk_freq = 675000;
} else if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->max_cdclk_freq = 320000;
+ dev_priv->display.max_cdclk_freq = 320000;
} else if (IS_VALLEYVIEW(dev_priv)) {
- dev_priv->max_cdclk_freq = 400000;
+ dev_priv->display.max_cdclk_freq = 400000;
} else {
/* otherwise assume cdclk is fixed */
- dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
+ dev_priv->display.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk;
}
dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n",
- dev_priv->max_cdclk_freq);
+ dev_priv->display.max_cdclk_freq);
drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n",
dev_priv->max_dotclk_freq);
@@ -2695,7 +2695,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
*/
void intel_update_cdclk(struct drm_i915_private *dev_priv)
{
- dev_priv->display.funcs.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
+ dev_priv->display.funcs.get_cdclk(dev_priv, &dev_priv->display.cdclk.hw);
/*
* 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
@@ -2705,7 +2705,7 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
*/
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
intel_de_write(dev_priv, GMBUSFREQ_VLV,
- DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
+ DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000));
}
static int dg1_rawclk(struct drm_i915_private *dev_priv)
@@ -2856,7 +2856,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.funcs.calc_voltage_level = tgl_calc_voltage_level;
- dev_priv->cdclk.table = dg2_cdclk_table;
+ dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
dev_priv->display.funcs.set_cdclk = bxt_set_cdclk;
dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
@@ -2864,42 +2864,42 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
dev_priv->display.funcs.calc_voltage_level = tgl_calc_voltage_level;
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
- dev_priv->cdclk.table = adlp_a_step_cdclk_table;
+ dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
else
- dev_priv->cdclk.table = adlp_cdclk_table;
+ dev_priv->display.cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
dev_priv->display.funcs.set_cdclk = bxt_set_cdclk;
dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.funcs.calc_voltage_level = tgl_calc_voltage_level;
- dev_priv->cdclk.table = rkl_cdclk_table;
+ dev_priv->display.cdclk.table = rkl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 12) {
dev_priv->display.funcs.set_cdclk = bxt_set_cdclk;
dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.funcs.calc_voltage_level = tgl_calc_voltage_level;
- dev_priv->cdclk.table = icl_cdclk_table;
+ dev_priv->display.cdclk.table = icl_cdclk_table;
} else if (IS_JSL_EHL(dev_priv)) {
dev_priv->display.funcs.set_cdclk = bxt_set_cdclk;
dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.funcs.calc_voltage_level = ehl_calc_voltage_level;
- dev_priv->cdclk.table = icl_cdclk_table;
+ dev_priv->display.cdclk.table = icl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 11) {
dev_priv->display.funcs.set_cdclk = bxt_set_cdclk;
dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.funcs.calc_voltage_level = icl_calc_voltage_level;
- dev_priv->cdclk.table = icl_cdclk_table;
+ dev_priv->display.cdclk.table = icl_cdclk_table;
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.funcs.set_cdclk = bxt_set_cdclk;
dev_priv->display.funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.funcs.calc_voltage_level = bxt_calc_voltage_level;
if (IS_GEMINILAKE(dev_priv))
- dev_priv->cdclk.table = glk_cdclk_table;
+ dev_priv->display.cdclk.table = glk_cdclk_table;
else
- dev_priv->cdclk.table = bxt_cdclk_table;
+ dev_priv->display.cdclk.table = bxt_cdclk_table;
} else if (DISPLAY_VER(dev_priv) == 9) {
dev_priv->display.funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.funcs.set_cdclk = skl_set_cdclk;
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index b34eb00fb327..e29f7bc0cc39 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -74,9 +74,9 @@ intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
#define to_intel_cdclk_state(x) container_of((x), struct intel_cdclk_state, base)
#define intel_atomic_get_old_cdclk_state(state) \
- to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
+ to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
#define intel_atomic_get_new_cdclk_state(state) \
- to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
+ to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
int intel_cdclk_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f31585e56e84..035a55c8abec 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3658,7 +3658,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
struct intel_bw_state *bw_state =
to_intel_bw_state(dev_priv->bw_obj.state);
struct intel_cdclk_state *cdclk_state =
- to_intel_cdclk_state(dev_priv->cdclk.obj.state);
+ to_intel_cdclk_state(dev_priv->display.cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
to_intel_dbuf_state(dev_priv->dbuf.obj.state);
struct intel_crtc_state *crtc_state =
@@ -3827,7 +3827,7 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
* Should measure whether using a lower cdclk w/o IPS
*/
if (IS_BROADWELL(dev_priv) &&
- crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
+ crtc_state->pixel_rate > dev_priv->display.max_cdclk_freq * 95 / 100)
return false;
return true;
@@ -4038,7 +4038,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
if (DISPLAY_VER(dev_priv) < 4) {
- clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
+ clock_limit = dev_priv->display.max_cdclk_freq * 9 / 10;
/*
* Enable double wide mode when the dot clock
@@ -11266,11 +11266,11 @@ void intel_modeset_init_hw(struct drm_i915_private *i915)
if (!HAS_DISPLAY(i915))
return;
- cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state);
+ cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state);
intel_update_cdclk(i915);
- intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
- cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
+ intel_dump_cdclk_config(&i915->display.cdclk.hw, "Current CDCLK");
+ cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw;
}
static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
@@ -11652,7 +11652,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
intel_hdcp_component_init(i915);
- if (i915->max_cdclk_freq == 0)
+ if (i915->display.max_cdclk_freq == 0)
intel_update_max_cdclk(i915);
/*
@@ -12146,7 +12146,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_cdclk_state *cdclk_state =
- to_intel_cdclk_state(dev_priv->cdclk.obj.state);
+ to_intel_cdclk_state(dev_priv->display.cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
to_intel_dbuf_state(dev_priv->dbuf.obj.state);
enum pipe pipe;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index ebe4fee6d680..04cf1c0a6da1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1198,7 +1198,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
dev_priv->display.funcs.get_cdclk(dev_priv, &cdclk_config);
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
drm_WARN_ON(&dev_priv->drm,
- intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,
+ intel_cdclk_needs_modeset(&dev_priv->display.cdclk.hw,
&cdclk_config));
gen9_assert_dbuf_enabled(dev_priv);
@@ -5482,7 +5482,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
intel_update_cdclk(dev_priv);
- intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
+ intel_dump_cdclk_config(&dev_priv->display.cdclk.hw, "Current CDCLK");
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4f2fd33529ca..40a8e7cef42a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -576,7 +576,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
if (bigjoiner) {
u32 max_bpp_bigjoiner =
- i915->max_cdclk_freq * 48 /
+ i915->display.max_cdclk_freq * 48 /
intel_dp_mode_to_fec_clock(mode_clock);
DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
@@ -1348,7 +1348,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
* is greater than the maximum Cdclock and if slice count is even
* then we need to use 2 VDSC instances.
*/
- if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
+ if (adjusted_mode->crtc_clock > dev_priv->display.max_cdclk_freq ||
pipe_config->bigjoiner) {
if (pipe_config->dsc.slice_count < 2) {
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index f483f479dd0b..b0025dd3cb4a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -86,7 +86,7 @@ static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
* divide by 2000 and use that
*/
if (dig_port->aux_ch == AUX_CH_A)
- freq = dev_priv->cdclk.hw.cdclk;
+ freq = dev_priv->display.cdclk.hw.cdclk;
else
freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
return DIV_ROUND_CLOSEST(freq, 2000);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 055992d099c7..178dcacbb061 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1782,7 +1782,7 @@ static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
{
/* No SSC ref */
- i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
+ i915->dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;
}
static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
@@ -3867,7 +3867,7 @@ static void mg_pll_disable(struct drm_i915_private *dev_priv,
static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
{
/* No SSC ref */
- i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
+ i915->dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;
}
static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index b1c1a23c36be..7e52858399c9 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -874,7 +874,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
/* WaFbcExceedCdClockThreshold:hsw,bdw */
if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
- cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
+ cache->crtc.hsw_bdw_pixel_rate >= dev_priv->display.cdclk.hw.cdclk * 95 / 100) {
fbc->no_fbc_reason = "pixel rate is too big";
return false;
}
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index d6f5836396f8..352989fefe60 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -474,8 +474,8 @@ static int frequency_show(struct seq_file *m, void *unused)
seq_puts(m, "no P-state info available\n");
}
- seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->cdclk.hw.cdclk);
- seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->max_cdclk_freq);
+ seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk);
+ seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.max_cdclk_freq);
seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq);
intel_runtime_pm_put(uncore->rpm, wakeref);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 44969f5dde50..7610defe855b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -575,8 +575,8 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
seq_puts(m, "no P-state info available\n");
}
- seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
- seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
+ seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->display.cdclk.hw.cdclk);
+ seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->display.max_cdclk_freq);
seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 04335bace0e3..b99a8edd1ca2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -826,8 +826,20 @@ struct i915_selftest_stash {
};
struct drm_i915_display {
+ struct drm_device *drm;
/* Display functions */
struct drm_i915_display_funcs funcs;
+
+ struct {
+ /* The current hardware cdclk configuration */
+ struct intel_cdclk_config hw;
+
+ /* cdclk, divider, and ratio table from bspec */
+ const struct intel_cdclk_vals *table;
+
+ struct intel_global_obj obj;
+ } cdclk;
+ unsigned int max_cdclk_freq;
};
struct drm_i915_private {
@@ -940,23 +952,12 @@ struct drm_i915_private {
unsigned int fsb_freq, mem_freq, is_ddr3;
unsigned int skl_preferred_vco_freq;
- unsigned int max_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int hpll_freq;
unsigned int fdi_pll_freq;
unsigned int czclk_freq;
- struct {
- /* The current hardware cdclk configuration */
- struct intel_cdclk_config hw;
-
- /* cdclk, divider, and ratio table from bspec */
- const struct intel_cdclk_vals *table;
-
- struct intel_global_obj obj;
- } cdclk;
-
struct {
/* The current hardware dbuf configuration */
u8 enabled_slices;
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Intel-gfx] [PATCH 03/10] drm/i915: move more pll/clocks into display struct.
2021-09-06 3:43 [Intel-gfx] [RFC PATCH 00/10] refactor display structs a little bit Dave Airlie
2021-09-06 3:43 ` [Intel-gfx] [PATCH 01/10] drm/i915: move display funcs into a display struct Dave Airlie
2021-09-06 3:43 ` [Intel-gfx] [PATCH 02/10] drm/i915/display: move cdclk info into display Dave Airlie
@ 2021-09-06 3:43 ` Dave Airlie
2021-09-06 3:43 ` [Intel-gfx] [PATCH 04/10] drm/i915/display: move gmbus " Dave Airlie
` (9 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Dave Airlie @ 2021-09-06 3:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 24 ++++++++++----------
drivers/gpu/drm/i915/display/intel_crt.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++------
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/display/intel_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_dvo.c | 2 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 8 +++----
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +-
drivers/gpu/drm/i915/display/intel_tv.c | 2 +-
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 4 ++--
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 13 ++++++-----
17 files changed, 45 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index cb54a0c8b4e0..e52f97c3ecab 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -434,7 +434,7 @@ static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
- int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
+ int freq_320 = (dev_priv->display.hpll_freq << 1) % 320000 != 0 ?
333333 : 320000;
/*
@@ -467,7 +467,7 @@ static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
* hardware has shown that we just need to write the desired
* CCK divider into the Punit register.
*/
- return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
+ return DIV_ROUND_CLOSEST(dev_priv->display.hpll_freq << 1, cdclk) - 1;
}
}
@@ -506,7 +506,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
else
default_credits = PFI_CREDIT(8);
- if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) {
+ if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->display.czclk_freq) {
/* CHV suggested value is 31 or 63 */
if (IS_CHERRYVIEW(dev_priv))
credits = PFI_CREDIT_63;
@@ -581,7 +581,7 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
if (cdclk == 400000) {
u32 divider;
- divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
+ divider = DIV_ROUND_CLOSEST(dev_priv->display.hpll_freq << 1,
cdclk) - 1;
/* adjust cdclk divider */
@@ -942,9 +942,9 @@ static int skl_cdclk_decimal(int cdclk)
static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
int vco)
{
- bool changed = dev_priv->skl_preferred_vco_freq != vco;
+ bool changed = dev_priv->display.skl_preferred_vco_freq != vco;
- dev_priv->skl_preferred_vco_freq = vco;
+ dev_priv->display.skl_preferred_vco_freq = vco;
if (changed)
intel_update_max_cdclk(dev_priv);
@@ -1151,7 +1151,7 @@ static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
* Use the current vco as our initial
* guess as to what the preferred vco is.
*/
- if (dev_priv->skl_preferred_vco_freq == 0)
+ if (dev_priv->display.skl_preferred_vco_freq == 0)
skl_set_preferred_cdclk_vco(dev_priv,
dev_priv->display.cdclk.hw.vco);
return;
@@ -1159,7 +1159,7 @@ static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
cdclk_config = dev_priv->display.cdclk.hw;
- cdclk_config.vco = dev_priv->skl_preferred_vco_freq;
+ cdclk_config.vco = dev_priv->display.skl_preferred_vco_freq;
if (cdclk_config.vco == 0)
cdclk_config.vco = 8100000;
cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
@@ -2331,7 +2331,7 @@ static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state)
vco = cdclk_state->logical.vco;
if (!vco)
- vco = dev_priv->skl_preferred_vco_freq;
+ vco = dev_priv->display.skl_preferred_vco_freq;
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
if (!crtc_state->hw.enable)
@@ -2636,7 +2636,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
int max_cdclk, vco;
- vco = dev_priv->skl_preferred_vco_freq;
+ vco = dev_priv->display.skl_preferred_vco_freq;
drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
/*
@@ -2678,13 +2678,13 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
dev_priv->display.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk;
}
- dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
+ dev_priv->display.max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n",
dev_priv->display.max_cdclk_freq);
drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n",
- dev_priv->max_dotclk_freq);
+ dev_priv->display.max_dotclk_freq);
}
/**
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 408f82b0dc7d..466ce68ae5e0 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -342,7 +342,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
{
struct drm_device *dev = connector->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- int max_dotclk = dev_priv->max_dotclk_freq;
+ int max_dotclk = dev_priv->display.max_dotclk_freq;
int max_clock;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 035a55c8abec..f421bc69e197 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -160,10 +160,10 @@ int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
vlv_cck_get(dev_priv);
- if (dev_priv->hpll_freq == 0)
- dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
+ if (dev_priv->display.hpll_freq == 0)
+ dev_priv->display.hpll_freq = vlv_get_hpll_vco(dev_priv);
- hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
+ hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->display.hpll_freq);
vlv_cck_put(dev_priv);
@@ -175,11 +175,11 @@ static void intel_update_czclk(struct drm_i915_private *dev_priv)
if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
return;
- dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
+ dev_priv->display.czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
CCK_CZ_CLOCK_CONTROL);
drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
- dev_priv->czclk_freq);
+ dev_priv->display.czclk_freq);
}
/* WA Display #0827: Gen9:all */
@@ -4006,7 +4006,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
- int clock_limit = dev_priv->max_dotclk_freq;
+ int clock_limit = dev_priv->display.max_dotclk_freq;
drm_mode_copy(pipe_mode, &pipe_config->hw.adjusted_mode);
@@ -4046,7 +4046,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
*/
if (intel_crtc_supports_double_wide(crtc) &&
pipe_mode->crtc_clock > clock_limit) {
- clock_limit = dev_priv->max_dotclk_freq;
+ clock_limit = dev_priv->display.max_dotclk_freq;
pipe_config->double_wide = true;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 40a8e7cef42a..18f221d7f252 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -785,7 +785,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
struct drm_i915_private *dev_priv = to_i915(connector->dev);
int target_clock = mode->clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
- int max_dotclk = dev_priv->max_dotclk_freq;
+ int max_dotclk = dev_priv->display.max_dotclk_freq;
u16 dsc_max_output_bpp = 0;
u8 dsc_slice_count = 0;
enum drm_mode_status status;
@@ -1427,7 +1427,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
limits.max_lane_count, limits.max_rate,
limits.max_bpp, adjusted_mode->crtc_clock);
- if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq ||
+ if ((adjusted_mode->crtc_clock > i915->display.max_dotclk_freq ||
adjusted_mode->crtc_hdisplay > 5120) &&
intel_dp_can_bigjoiner(intel_dp))
pipe_config->bigjoiner = true;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index d104441344c0..99a127e8704a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -683,7 +683,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
struct drm_dp_mst_port *port = intel_connector->port;
const int min_bpp = 18;
- int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+ int max_dotclk = to_i915(connector->dev)->display.max_dotclk_freq;
int max_rate, mode_rate, max_lanes, max_link_clock;
int ret;
diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c
index f453ceb8d149..1b96d2aa0730 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi.c
@@ -59,7 +59,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
struct drm_i915_private *dev_priv = to_i915(connector->dev);
struct intel_connector *intel_connector = to_intel_connector(connector);
const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
- int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+ int max_dotclk = to_i915(connector->dev)->display.max_dotclk_freq;
drm_dbg_kms(&dev_priv->drm, "\n");
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index 86c903e9df60..e06de60f4970 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -226,7 +226,7 @@ intel_dvo_mode_valid(struct drm_connector *connector,
struct intel_dvo *intel_dvo = intel_attached_dvo(to_intel_connector(connector));
const struct drm_display_mode *fixed_mode =
to_intel_connector(connector)->panel.fixed_mode;
- int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+ int max_dotclk = to_i915(connector->dev)->display.max_dotclk_freq;
int target_clock = mode->clock;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index aaa0207f483e..58dfa97304c4 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -104,14 +104,14 @@ void intel_fdi_pll_freq_update(struct drm_i915_private *i915)
u32 fdi_pll_clk =
intel_de_read(i915, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
- i915->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
+ i915->display.fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
} else if (IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) {
- i915->fdi_pll_freq = 270000;
+ i915->display.fdi_pll_freq = 270000;
} else {
return;
}
- drm_dbg(&i915->drm, "FDI PLL freq=%d\n", i915->fdi_pll_freq);
+ drm_dbg(&i915->drm, "FDI PLL freq=%d\n", i915->display.fdi_pll_freq);
}
int intel_fdi_link_freq(struct drm_i915_private *i915,
@@ -120,7 +120,7 @@ int intel_fdi_link_freq(struct drm_i915_private *i915,
if (HAS_DDI(i915))
return pipe_config->port_clock; /* SPLL */
else
- return i915->fdi_pll_freq;
+ return i915->display.fdi_pll_freq;
}
int ilk_fdi_compute_config(struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 1bc33766ed39..f536da3d05d8 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1950,7 +1950,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
struct drm_i915_private *dev_priv = to_i915(dev);
enum drm_mode_status status;
int clock = mode->clock;
- int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+ int max_dotclk = to_i915(connector->dev)->display.max_dotclk_freq;
bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
bool ycbcr_420_only;
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index e9fb402708a7..137e11cc40b5 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -388,7 +388,7 @@ intel_lvds_mode_valid(struct drm_connector *connector,
{
struct intel_connector *intel_connector = to_intel_connector(connector);
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
- int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
+ int max_pixclk = to_i915(connector->dev)->display.max_dotclk_freq;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 6cb27599ea03..7691468571dc 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -1866,7 +1866,7 @@ intel_sdvo_mode_valid(struct drm_connector *connector,
struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
struct intel_sdvo_connector *intel_sdvo_connector =
to_intel_sdvo_connector(connector);
- int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+ int max_dotclk = to_i915(connector->dev)->display.max_dotclk_freq;
bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo, connector->state);
int clock = mode->clock;
diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
index d02f09f7e750..c2f317aa5840 100644
--- a/drivers/gpu/drm/i915/display/intel_tv.c
+++ b/drivers/gpu/drm/i915/display/intel_tv.c
@@ -956,7 +956,7 @@ intel_tv_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
- int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+ int max_dotclk = to_i915(connector->dev)->display.max_dotclk_freq;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index 352989fefe60..c95754aed784 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -476,7 +476,7 @@ static int frequency_show(struct seq_file *m, void *unused)
seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk);
seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.max_cdclk_freq);
- seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq);
+ seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->display.max_dotclk_freq);
intel_runtime_pm_put(uncore->rpm, wakeref);
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 799d382eea79..7fedff85e495 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -757,7 +757,7 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
mul = 1000000;
- div = i915->czclk_freq;
+ div = i915->display.czclk_freq;
overflow_hw = BIT_ULL(40);
time_hw = vlv_residency_raw(uncore, reg);
} else {
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index d812b27835f8..25f2767f582b 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1514,7 +1514,7 @@ static void vlv_init_gpll_ref_freq(struct intel_rps *rps)
rps->gpll_ref_freq =
vlv_get_cck_clock(i915, "GPLL ref",
CCK_GPLL_CLOCK_CONTROL,
- i915->czclk_freq);
+ i915->display.czclk_freq);
drm_dbg(&i915->drm, "GPLL reference freq: %d kHz\n",
rps->gpll_ref_freq);
@@ -1646,7 +1646,7 @@ static u32 vlv_wa_c0_ei(struct intel_rps *rps, u32 pm_iir)
time = ktime_us_delta(now.ktime, prev->ktime);
- time *= rps_to_i915(rps)->czclk_freq;
+ time *= rps_to_i915(rps)->display.czclk_freq;
/* Workload can be split between render + media,
* e.g. SwapBuffers being blitted in X after being rendered in
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 7610defe855b..37f5ab15a8d4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -577,7 +577,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->display.cdclk.hw.cdclk);
seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->display.max_cdclk_freq);
- seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
+ seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->display.max_dotclk_freq);
intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b99a8edd1ca2..424d06cdc4d6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -840,6 +840,13 @@ struct drm_i915_display {
struct intel_global_obj obj;
} cdclk;
unsigned int max_cdclk_freq;
+
+ unsigned int skl_preferred_vco_freq;
+
+ unsigned int max_dotclk_freq;
+ unsigned int hpll_freq;
+ unsigned int fdi_pll_freq;
+ unsigned int czclk_freq;
};
struct drm_i915_private {
@@ -951,12 +958,6 @@ struct drm_i915_private {
struct mutex pps_mutex;
unsigned int fsb_freq, mem_freq, is_ddr3;
- unsigned int skl_preferred_vco_freq;
-
- unsigned int max_dotclk_freq;
- unsigned int hpll_freq;
- unsigned int fdi_pll_freq;
- unsigned int czclk_freq;
struct {
/* The current hardware dbuf configuration */
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Intel-gfx] [PATCH 04/10] drm/i915/display: move gmbus into display struct
2021-09-06 3:43 [Intel-gfx] [RFC PATCH 00/10] refactor display structs a little bit Dave Airlie
` (2 preceding siblings ...)
2021-09-06 3:43 ` [Intel-gfx] [PATCH 03/10] drm/i915: move more pll/clocks into display struct Dave Airlie
@ 2021-09-06 3:43 ` Dave Airlie
2021-09-06 3:43 ` [Intel-gfx] [PATCH 05/10] drm/i915/display: move intel_dmc " Dave Airlie
` (8 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Dave Airlie @ 2021-09-06 3:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +--
drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
drivers/gpu/drm/i915/display/intel_gmbus.c | 42 ++++++++++-----------
drivers/gpu/drm/i915/i915_drv.h | 27 +++++++------
drivers/gpu/drm/i915/i915_irq.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 14 +++----
6 files changed, 47 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index e52f97c3ecab..f42e07824f01 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1948,12 +1948,12 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
* functions use cdclk. Not all platforms/ports do,
* but we'll lock them all for simplicity.
*/
- mutex_lock(&dev_priv->gmbus_mutex);
+ mutex_lock(&dev_priv->display.gmbus_mutex);
for_each_intel_dp(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
- &dev_priv->gmbus_mutex);
+ &dev_priv->display.gmbus_mutex);
}
dev_priv->display.funcs.set_cdclk(dev_priv, cdclk_config, pipe);
@@ -1963,7 +1963,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
mutex_unlock(&intel_dp->aux.hw_mutex);
}
- mutex_unlock(&dev_priv->gmbus_mutex);
+ mutex_unlock(&dev_priv->display.gmbus_mutex);
for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index b0025dd3cb4a..8695da511e63 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -42,7 +42,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
bool done;
#define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
- done = wait_event_timeout(i915->gmbus_wait_queue, C,
+ done = wait_event_timeout(i915->display.gmbus_wait_queue, C,
msecs_to_jiffies_timeout(timeout_ms));
/* just trace the final value */
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index ceb1bf8a8c3c..9d31f5322f2a 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -347,7 +347,7 @@ static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
if (!HAS_GMBUS_IRQ(dev_priv))
irq_en = 0;
- add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
+ add_wait_queue(&dev_priv->display.gmbus_wait_queue, &wait);
intel_de_write_fw(dev_priv, GMBUS4, irq_en);
status |= GMBUS_SATOER;
@@ -358,7 +358,7 @@ static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
50);
intel_de_write_fw(dev_priv, GMBUS4, 0);
- remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
+ remove_wait_queue(&dev_priv->display.gmbus_wait_queue, &wait);
if (gmbus2 & GMBUS_SATOER)
return -ENXIO;
@@ -378,7 +378,7 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
if (HAS_GMBUS_IRQ(dev_priv))
irq_enable = GMBUS_IDLE_EN;
- add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
+ add_wait_queue(&dev_priv->display.gmbus_wait_queue, &wait);
intel_de_write_fw(dev_priv, GMBUS4, irq_enable);
ret = intel_wait_for_register_fw(&dev_priv->uncore,
@@ -386,7 +386,7 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
10);
intel_de_write_fw(dev_priv, GMBUS4, 0);
- remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
+ remove_wait_queue(&dev_priv->display.gmbus_wait_queue, &wait);
return ret;
}
@@ -773,7 +773,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
int ret;
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
- mutex_lock(&dev_priv->gmbus_mutex);
+ mutex_lock(&dev_priv->display.gmbus_mutex);
/*
* In order to output Aksv to the receiver, use an indexed write to
@@ -782,7 +782,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
*/
ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
- mutex_unlock(&dev_priv->gmbus_mutex);
+ mutex_unlock(&dev_priv->display.gmbus_mutex);
intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
return ret;
@@ -808,7 +808,7 @@ static void gmbus_lock_bus(struct i2c_adapter *adapter,
struct intel_gmbus *bus = to_intel_gmbus(adapter);
struct drm_i915_private *dev_priv = bus->dev_priv;
- mutex_lock(&dev_priv->gmbus_mutex);
+ mutex_lock(&dev_priv->display.gmbus_mutex);
}
static int gmbus_trylock_bus(struct i2c_adapter *adapter,
@@ -817,7 +817,7 @@ static int gmbus_trylock_bus(struct i2c_adapter *adapter,
struct intel_gmbus *bus = to_intel_gmbus(adapter);
struct drm_i915_private *dev_priv = bus->dev_priv;
- return mutex_trylock(&dev_priv->gmbus_mutex);
+ return mutex_trylock(&dev_priv->display.gmbus_mutex);
}
static void gmbus_unlock_bus(struct i2c_adapter *adapter,
@@ -826,7 +826,7 @@ static void gmbus_unlock_bus(struct i2c_adapter *adapter,
struct intel_gmbus *bus = to_intel_gmbus(adapter);
struct drm_i915_private *dev_priv = bus->dev_priv;
- mutex_unlock(&dev_priv->gmbus_mutex);
+ mutex_unlock(&dev_priv->display.gmbus_mutex);
}
static const struct i2c_lock_operations gmbus_lock_ops = {
@@ -847,22 +847,22 @@ int intel_gmbus_setup(struct drm_i915_private *dev_priv)
int ret;
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
+ dev_priv->display.gpio_mmio_base = VLV_DISPLAY_BASE;
else if (!HAS_GMCH(dev_priv))
/*
* Broxton uses the same PCH offsets for South Display Engine,
* even though it doesn't have a PCH.
*/
- dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
+ dev_priv->display.gpio_mmio_base = PCH_DISPLAY_BASE;
- mutex_init(&dev_priv->gmbus_mutex);
- init_waitqueue_head(&dev_priv->gmbus_wait_queue);
+ mutex_init(&dev_priv->display.gmbus_mutex);
+ init_waitqueue_head(&dev_priv->display.gmbus_wait_queue);
- for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
+ for (pin = 0; pin < ARRAY_SIZE(dev_priv->display.gmbus); pin++) {
if (!intel_gmbus_is_valid_pin(dev_priv, pin))
continue;
- bus = &dev_priv->gmbus[pin];
+ bus = &dev_priv->display.gmbus[pin];
bus->adapter.owner = THIS_MODULE;
bus->adapter.class = I2C_CLASS_DDC;
@@ -906,7 +906,7 @@ int intel_gmbus_setup(struct drm_i915_private *dev_priv)
if (!intel_gmbus_is_valid_pin(dev_priv, pin))
continue;
- bus = &dev_priv->gmbus[pin];
+ bus = &dev_priv->display.gmbus[pin];
i2c_del_adapter(&bus->adapter);
}
return ret;
@@ -919,7 +919,7 @@ struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
!intel_gmbus_is_valid_pin(dev_priv, pin)))
return NULL;
- return &dev_priv->gmbus[pin].adapter;
+ return &dev_priv->display.gmbus[pin].adapter;
}
void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
@@ -934,7 +934,7 @@ void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
struct intel_gmbus *bus = to_intel_gmbus(adapter);
struct drm_i915_private *dev_priv = bus->dev_priv;
- mutex_lock(&dev_priv->gmbus_mutex);
+ mutex_lock(&dev_priv->display.gmbus_mutex);
bus->force_bit += force_bit ? 1 : -1;
drm_dbg_kms(&dev_priv->drm,
@@ -942,7 +942,7 @@ void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
force_bit ? "en" : "dis", adapter->name,
bus->force_bit);
- mutex_unlock(&dev_priv->gmbus_mutex);
+ mutex_unlock(&dev_priv->display.gmbus_mutex);
}
bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
@@ -957,11 +957,11 @@ void intel_gmbus_teardown(struct drm_i915_private *dev_priv)
struct intel_gmbus *bus;
unsigned int pin;
- for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
+ for (pin = 0; pin < ARRAY_SIZE(dev_priv->display.gmbus); pin++) {
if (!intel_gmbus_is_valid_pin(dev_priv, pin))
continue;
- bus = &dev_priv->gmbus[pin];
+ bus = &dev_priv->display.gmbus[pin];
i2c_del_adapter(&bus->adapter);
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 424d06cdc4d6..20520402c246 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -847,6 +847,19 @@ struct drm_i915_display {
unsigned int hpll_freq;
unsigned int fdi_pll_freq;
unsigned int czclk_freq;
+
+ /**
+ * Base address of where the gmbus and gpio blocks are located (either
+ * on PCH or on SoC for platforms without PCH).
+ */
+ u32 gpio_mmio_base;
+
+ struct intel_gmbus gmbus[GMBUS_NUM_PINS];
+
+ /** gmbus_mutex protects against concurrent usage of the single hw gmbus
+ * controller on different i2c buses. */
+ struct mutex gmbus_mutex;
+ wait_queue_head_t gmbus_wait_queue;
};
struct drm_i915_private {
@@ -899,25 +912,11 @@ struct drm_i915_private {
struct intel_dmc dmc;
- struct intel_gmbus gmbus[GMBUS_NUM_PINS];
-
- /** gmbus_mutex protects against concurrent usage of the single hw gmbus
- * controller on different i2c buses. */
- struct mutex gmbus_mutex;
-
- /**
- * Base address of where the gmbus and gpio blocks are located (either
- * on PCH or on SoC for platforms without PCH).
- */
- u32 gpio_mmio_base;
-
/* MMIO base address for MIPI regs */
u32 mipi_mmio_base;
u32 pps_mmio_base;
- wait_queue_head_t gmbus_wait_queue;
-
struct pci_dev *bridge_dev;
struct rb_root uabi_engines;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b1e3f51dc593..4ef644aeaf6c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1303,12 +1303,12 @@ static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
{
- wake_up_all(&dev_priv->gmbus_wait_queue);
+ wake_up_all(&dev_priv->display.gmbus_wait_queue);
}
static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
{
- wake_up_all(&dev_priv->gmbus_wait_queue);
+ wake_up_all(&dev_priv->display.gmbus_wait_queue);
}
#if defined(CONFIG_DEBUG_FS)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bd63760207b0..2e74c5c4699a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3403,7 +3403,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
/*
* GPIO regs
*/
-#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
+#define GPIO(gpio) _MMIO(dev_priv->display.gpio_mmio_base + 0x5010 + \
4 * (gpio))
# define GPIO_CLOCK_DIR_MASK (1 << 0)
@@ -3421,7 +3421,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
# define GPIO_DATA_VAL_IN (1 << 12)
# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
-#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
+#define GMBUS0 _MMIO(dev_priv->display.gpio_mmio_base + 0x5100) /* clock/port select */
#define GMBUS_AKSV_SELECT (1 << 11)
#define GMBUS_RATE_100KHZ (0 << 8)
#define GMBUS_RATE_50KHZ (1 << 8)
@@ -3430,7 +3430,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */
#define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
-#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
+#define GMBUS1 _MMIO(dev_priv->display.gpio_mmio_base + 0x5104) /* command/status */
#define GMBUS_SW_CLR_INT (1 << 31)
#define GMBUS_SW_RDY (1 << 30)
#define GMBUS_ENT (1 << 29) /* enable timeout */
@@ -3445,7 +3445,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GMBUS_SLAVE_ADDR_SHIFT 1
#define GMBUS_SLAVE_READ (1 << 0)
#define GMBUS_SLAVE_WRITE (0 << 0)
-#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
+#define GMBUS2 _MMIO(dev_priv->display.gpio_mmio_base + 0x5108) /* status */
#define GMBUS_INUSE (1 << 15)
#define GMBUS_HW_WAIT_PHASE (1 << 14)
#define GMBUS_STALL_TIMEOUT (1 << 13)
@@ -3453,14 +3453,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GMBUS_HW_RDY (1 << 11)
#define GMBUS_SATOER (1 << 10)
#define GMBUS_ACTIVE (1 << 9)
-#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
-#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
+#define GMBUS3 _MMIO(dev_priv->display.gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
+#define GMBUS4 _MMIO(dev_priv->display.gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
#define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
#define GMBUS_NAK_EN (1 << 3)
#define GMBUS_IDLE_EN (1 << 2)
#define GMBUS_HW_WAIT_EN (1 << 1)
#define GMBUS_HW_RDY_EN (1 << 0)
-#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
+#define GMBUS5 _MMIO(dev_priv->display.gpio_mmio_base + 0x5120) /* byte index */
#define GMBUS_2BYTE_INDEX_EN (1 << 31)
/*
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Intel-gfx] [PATCH 05/10] drm/i915/display: move intel_dmc into display struct
2021-09-06 3:43 [Intel-gfx] [RFC PATCH 00/10] refactor display structs a little bit Dave Airlie
` (3 preceding siblings ...)
2021-09-06 3:43 ` [Intel-gfx] [PATCH 04/10] drm/i915/display: move gmbus " Dave Airlie
@ 2021-09-06 3:43 ` Dave Airlie
2021-09-06 3:43 ` [Intel-gfx] [PATCH 06/10] drm/i915/display: move mipi_mmio_base to " Dave Airlie
` (7 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Dave Airlie @ 2021-09-06 3:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../drm/i915/display/intel_display_debugfs.c | 2 +-
.../drm/i915/display/intel_display_power.c | 38 +++++++--------
drivers/gpu/drm/i915/display/intel_dmc.c | 46 +++++++++----------
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
6 files changed, 47 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index ca819f9e353d..7221bf2e75b0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -539,7 +539,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
if (!HAS_DMC(dev_priv))
return -ENODEV;
- dmc = &dev_priv->dmc;
+ dmc = &dev_priv->display.dmc;
wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 04cf1c0a6da1..ccd0fa5c3e4c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -832,8 +832,8 @@ static void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm,
"Resetting DC state tracking from %02x to %02x\n",
- dev_priv->dmc.dc_state, val);
- dev_priv->dmc.dc_state = val;
+ dev_priv->display.dmc.dc_state, val);
+ dev_priv->display.dmc.dc_state = val;
}
/**
@@ -868,8 +868,8 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
return;
if (drm_WARN_ON_ONCE(&dev_priv->drm,
- state & ~dev_priv->dmc.allowed_dc_mask))
- state &= dev_priv->dmc.allowed_dc_mask;
+ state & ~dev_priv->display.dmc.allowed_dc_mask))
+ state &= dev_priv->display.dmc.allowed_dc_mask;
val = intel_de_read(dev_priv, DC_STATE_EN);
mask = gen9_dc_mask(dev_priv);
@@ -877,16 +877,16 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
val & mask, state);
/* Check if DMC is ignoring our DC state requests */
- if ((val & mask) != dev_priv->dmc.dc_state)
+ if ((val & mask) != dev_priv->display.dmc.dc_state)
drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n",
- dev_priv->dmc.dc_state, val & mask);
+ dev_priv->display.dmc.dc_state, val & mask);
val &= ~mask;
val |= state;
gen9_write_dc_state(dev_priv, val);
- dev_priv->dmc.dc_state = val & mask;
+ dev_priv->display.dmc.dc_state = val & mask;
}
static u32
@@ -905,7 +905,7 @@ sanitize_target_dc_state(struct drm_i915_private *dev_priv,
if (target_dc_state != states[i])
continue;
- if (dev_priv->dmc.allowed_dc_mask & target_dc_state)
+ if (dev_priv->display.dmc.allowed_dc_mask & target_dc_state)
break;
target_dc_state = states[i + 1];
@@ -965,7 +965,7 @@ static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
{
drm_WARN_ONCE(&dev_priv->drm,
!intel_de_read(dev_priv,
- DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
+ DMC_PROGRAM(dev_priv->display.dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
"DMC program storage start is NULL\n");
drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
"DMC SSP Base Not fine\n");
@@ -1020,7 +1020,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
state = sanitize_target_dc_state(dev_priv, state);
- if (state == dev_priv->dmc.target_dc_state)
+ if (state == dev_priv->display.dmc.target_dc_state)
goto unlock;
dc_off_enabled = power_well->desc->ops->is_enabled(dev_priv,
@@ -1032,7 +1032,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
if (!dc_off_enabled)
power_well->desc->ops->enable(dev_priv, power_well);
- dev_priv->dmc.target_dc_state = state;
+ dev_priv->display.dmc.target_dc_state = state;
if (!dc_off_enabled)
power_well->desc->ops->disable(dev_priv, power_well);
@@ -1185,7 +1185,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
{
struct intel_cdclk_config cdclk_config = {};
- if (dev_priv->dmc.target_dc_state == DC_STATE_EN_DC3CO) {
+ if (dev_priv->display.dmc.target_dc_state == DC_STATE_EN_DC3CO) {
tgl_disable_dc3co(dev_priv);
return;
}
@@ -1227,7 +1227,7 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
if (!intel_dmc_has_payload(dev_priv))
return;
- switch (dev_priv->dmc.target_dc_state) {
+ switch (dev_priv->display.dmc.target_dc_state) {
case DC_STATE_EN_DC3CO:
tgl_enable_dc3co(dev_priv);
break;
@@ -5108,10 +5108,10 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
dev_priv->params.disable_power_well =
sanitize_disable_power_well_option(dev_priv,
dev_priv->params.disable_power_well);
- dev_priv->dmc.allowed_dc_mask =
+ dev_priv->display.dmc.allowed_dc_mask =
get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc);
- dev_priv->dmc.target_dc_state =
+ dev_priv->display.dmc.target_dc_state =
sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
@@ -6181,7 +6181,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
* resources as required and also enable deeper system power states
* that would be blocked if the firmware was inactive.
*/
- if (!(i915->dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
+ if (!(i915->display.dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
suspend_mode == I915_DRM_SUSPEND_IDLE &&
intel_dmc_has_payload(i915)) {
intel_display_power_flush_work(i915);
@@ -6372,10 +6372,10 @@ void intel_display_power_resume(struct drm_i915_private *i915)
bxt_disable_dc9(i915);
icl_display_core_init(i915, true);
if (intel_dmc_has_payload(i915)) {
- if (i915->dmc.allowed_dc_mask &
+ if (i915->display.dmc.allowed_dc_mask &
DC_STATE_EN_UPTO_DC6)
skl_enable_dc6(i915);
- else if (i915->dmc.allowed_dc_mask &
+ else if (i915->display.dmc.allowed_dc_mask &
DC_STATE_EN_UPTO_DC5)
gen9_enable_dc5(i915);
}
@@ -6383,7 +6383,7 @@ void intel_display_power_resume(struct drm_i915_private *i915)
bxt_disable_dc9(i915);
bxt_display_core_init(i915, true);
if (intel_dmc_has_payload(i915) &&
- (i915->dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
+ (i915->display.dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
gen9_enable_dc5(i915);
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
hsw_disable_pc8(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 3c3c6cb5c0df..b42461d2bf96 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -239,7 +239,7 @@ struct stepping_info {
bool intel_dmc_has_payload(struct drm_i915_private *i915)
{
- return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
+ return i915->display.dmc.dmc_info[DMC_FW_MAIN].payload;
}
static const struct stepping_info *
@@ -281,7 +281,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
*/
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
- struct intel_dmc *dmc = &dev_priv->dmc;
+ struct intel_dmc *dmc = &dev_priv->display.dmc;
u32 id, i;
if (!HAS_DMC(dev_priv)) {
@@ -290,7 +290,7 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
return;
}
- if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
+ if (!dev_priv->display.dmc.dmc_info[DMC_FW_MAIN].payload) {
drm_err(&dev_priv->drm,
"Tried to program CSR with empty payload\n");
return;
@@ -317,7 +317,7 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
}
}
- dev_priv->dmc.dc_state = 0;
+ dev_priv->display.dmc.dc_state = 0;
gen9_set_dc_state_debugmask(dev_priv);
}
@@ -351,7 +351,7 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc,
{
unsigned int i, id;
- struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
for (i = 0; i < num_entries; i++) {
id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id;
@@ -379,7 +379,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
const struct intel_dmc_header_base *dmc_header,
size_t rem_size, u8 dmc_id)
{
- struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id];
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
@@ -484,7 +484,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
const struct stepping_info *si,
size_t rem_size)
{
- struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
u32 package_size = sizeof(struct intel_package_header);
u32 num_entries, max_entries;
const struct intel_fw_info *fw_info;
@@ -538,7 +538,7 @@ static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
struct intel_css_header *css_header,
size_t rem_size)
{
- struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
if (rem_size < sizeof(struct intel_css_header)) {
drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
@@ -575,7 +575,7 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
struct intel_css_header *css_header;
struct intel_package_header *package_header;
struct intel_dmc_header_base *dmc_header;
- struct intel_dmc *dmc = &dev_priv->dmc;
+ struct intel_dmc *dmc = &dev_priv->display.dmc;
struct stepping_info display_info = { '*', '*'};
const struct stepping_info *si = intel_get_stepping_info(dev_priv, &display_info);
u32 readcount = 0;
@@ -602,7 +602,7 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
readcount += r;
for (id = 0; id < DMC_FW_MAX; id++) {
- if (!dev_priv->dmc.dmc_info[id].present)
+ if (!dev_priv->display.dmc.dmc_info[id].present)
continue;
offset = readcount + dmc->dmc_info[id].dmc_offset * 4;
@@ -618,15 +618,15 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv)
{
- drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
- dev_priv->dmc.wakeref =
+ drm_WARN_ON(&dev_priv->drm, dev_priv->display.dmc.wakeref);
+ dev_priv->display.dmc.wakeref =
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
}
static void intel_dmc_runtime_pm_put(struct drm_i915_private *dev_priv)
{
intel_wakeref_t wakeref __maybe_unused =
- fetch_and_zero(&dev_priv->dmc.wakeref);
+ fetch_and_zero(&dev_priv->display.dmc.wakeref);
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
}
@@ -637,10 +637,10 @@ static void dmc_load_work_fn(struct work_struct *work)
struct intel_dmc *dmc;
const struct firmware *fw = NULL;
- dev_priv = container_of(work, typeof(*dev_priv), dmc.work);
- dmc = &dev_priv->dmc;
+ dev_priv = container_of(work, typeof(*dev_priv), display.dmc.work);
+ dmc = &dev_priv->display.dmc;
- request_firmware(&fw, dev_priv->dmc.fw_path, dev_priv->drm.dev);
+ request_firmware(&fw, dev_priv->display.dmc.fw_path, dev_priv->drm.dev);
parse_dmc_fw(dev_priv, fw);
if (intel_dmc_has_payload(dev_priv)) {
@@ -649,7 +649,7 @@ static void dmc_load_work_fn(struct work_struct *work)
drm_info(&dev_priv->drm,
"Finished loading DMC firmware %s (v%u.%u)\n",
- dev_priv->dmc.fw_path, DMC_VERSION_MAJOR(dmc->version),
+ dev_priv->display.dmc.fw_path, DMC_VERSION_MAJOR(dmc->version),
DMC_VERSION_MINOR(dmc->version));
} else {
drm_notice(&dev_priv->drm,
@@ -672,9 +672,9 @@ static void dmc_load_work_fn(struct work_struct *work)
*/
void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
{
- struct intel_dmc *dmc = &dev_priv->dmc;
+ struct intel_dmc *dmc = &dev_priv->display.dmc;
- INIT_WORK(&dev_priv->dmc.work, dmc_load_work_fn);
+ INIT_WORK(&dev_priv->display.dmc.work, dmc_load_work_fn);
if (!HAS_DMC(dev_priv))
return;
@@ -753,7 +753,7 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
}
drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path);
- schedule_work(&dev_priv->dmc.work);
+ schedule_work(&dev_priv->display.dmc.work);
}
/**
@@ -769,7 +769,7 @@ void intel_dmc_ucode_suspend(struct drm_i915_private *dev_priv)
if (!HAS_DMC(dev_priv))
return;
- flush_work(&dev_priv->dmc.work);
+ flush_work(&dev_priv->display.dmc.work);
/* Drop the reference held in case DMC isn't loaded. */
if (!intel_dmc_has_payload(dev_priv))
@@ -809,7 +809,7 @@ void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv)
return;
intel_dmc_ucode_suspend(dev_priv);
- drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
+ drm_WARN_ON(&dev_priv->drm, dev_priv->display.dmc.wakeref);
- kfree(dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload);
+ kfree(dev_priv->display.dmc.dmc_info[DMC_FW_MAIN].payload);
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 3f6fb7d67f84..b355c8d36b2d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -692,7 +692,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
if (crtc_state->enable_psr2_sel_fetch)
return;
- if (!(dev_priv->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO))
+ if (!(dev_priv->display.dmc.allowed_dc_mask & DC_STATE_EN_DC3CO))
return;
if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 20520402c246..b27d0857a038 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -860,6 +860,8 @@ struct drm_i915_display {
* controller on different i2c buses. */
struct mutex gmbus_mutex;
wait_queue_head_t gmbus_wait_queue;
+
+ struct intel_dmc dmc;
};
struct drm_i915_private {
@@ -910,8 +912,6 @@ struct drm_i915_private {
struct intel_wopcm wopcm;
- struct intel_dmc dmc;
-
/* MMIO base address for MIPI regs */
u32 mipi_mmio_base;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 9cf6ac575de1..cb72f84f4102 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -798,7 +798,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
if (HAS_DMC(m->i915)) {
- struct intel_dmc *dmc = &m->i915->dmc;
+ struct intel_dmc *dmc = &m->i915->display.dmc;
err_printf(m, "DMC loaded: %s\n",
yesno(intel_dmc_has_payload(m->i915) != 0));
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Intel-gfx] [PATCH 06/10] drm/i915/display: move mipi_mmio_base to display struct
2021-09-06 3:43 [Intel-gfx] [RFC PATCH 00/10] refactor display structs a little bit Dave Airlie
` (4 preceding siblings ...)
2021-09-06 3:43 ` [Intel-gfx] [PATCH 05/10] drm/i915/display: move intel_dmc " Dave Airlie
@ 2021-09-06 3:43 ` Dave Airlie
2021-09-06 3:43 ` [Intel-gfx] [PATCH 07/10] drm/i915/display: move pps_mmio_base " Dave Airlie
` (6 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Dave Airlie @ 2021-09-06 3:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/vlv_dsi.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/i915_reg.h | 186 ++++++++++++-------------
3 files changed, 98 insertions(+), 98 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index b0a2b6b96799..7c2a8ce97227 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -1843,9 +1843,9 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
return;
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
+ dev_priv->display.mipi_mmio_base = BXT_MIPI_BASE;
else
- dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
+ dev_priv->display.mipi_mmio_base = VLV_MIPI_BASE;
intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
if (!intel_dsi)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b27d0857a038..2d4cac666de9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -854,6 +854,9 @@ struct drm_i915_display {
*/
u32 gpio_mmio_base;
+ /* MMIO base address for MIPI regs */
+ u32 mipi_mmio_base;
+
struct intel_gmbus gmbus[GMBUS_NUM_PINS];
/** gmbus_mutex protects against concurrent usage of the single hw gmbus
@@ -912,9 +915,6 @@ struct drm_i915_private {
struct intel_wopcm wopcm;
- /* MMIO base address for MIPI regs */
- u32 mipi_mmio_base;
-
u32 pps_mmio_base;
struct pci_dev *bridge_dev;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2e74c5c4699a..948949c15396 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11731,8 +11731,8 @@ enum skl_power_gate {
/* MIPI DSI Controller and D-PHY registers */
-#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
-#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
+#define _MIPIA_DEVICE_READY (dev_priv->display.mipi_mmio_base + 0xb000)
+#define _MIPIC_DEVICE_READY (dev_priv->display.mipi_mmio_base + 0xb800)
#define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
#define ULPS_STATE_MASK (3 << 1)
@@ -11741,11 +11741,11 @@ enum skl_power_gate {
#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
#define DEVICE_READY (1 << 0)
-#define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
-#define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
+#define _MIPIA_INTR_STAT (dev_priv->display.mipi_mmio_base + 0xb004)
+#define _MIPIC_INTR_STAT (dev_priv->display.mipi_mmio_base + 0xb804)
#define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
-#define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
-#define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
+#define _MIPIA_INTR_EN (dev_priv->display.mipi_mmio_base + 0xb008)
+#define _MIPIC_INTR_EN (dev_priv->display.mipi_mmio_base + 0xb808)
#define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
#define TEARING_EFFECT (1 << 31)
#define SPL_PKT_SENT_INTERRUPT (1 << 30)
@@ -11780,8 +11780,8 @@ enum skl_power_gate {
#define RXSOT_SYNC_ERROR (1 << 1)
#define RXSOT_ERROR (1 << 0)
-#define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
-#define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
+#define _MIPIA_DSI_FUNC_PRG (dev_priv->display.mipi_mmio_base + 0xb00c)
+#define _MIPIC_DSI_FUNC_PRG (dev_priv->display.mipi_mmio_base + 0xb80c)
#define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
#define CMD_MODE_NOT_SUPPORTED (0 << 13)
@@ -11803,78 +11803,78 @@ enum skl_power_gate {
#define DATA_LANES_PRG_REG_SHIFT 0
#define DATA_LANES_PRG_REG_MASK (7 << 0)
-#define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
-#define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
+#define _MIPIA_HS_TX_TIMEOUT (dev_priv->display.mipi_mmio_base + 0xb010)
+#define _MIPIC_HS_TX_TIMEOUT (dev_priv->display.mipi_mmio_base + 0xb810)
#define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
-#define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
-#define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
+#define _MIPIA_LP_RX_TIMEOUT (dev_priv->display.mipi_mmio_base + 0xb014)
+#define _MIPIC_LP_RX_TIMEOUT (dev_priv->display.mipi_mmio_base + 0xb814)
#define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
-#define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
-#define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
+#define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->display.mipi_mmio_base + 0xb018)
+#define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->display.mipi_mmio_base + 0xb818)
#define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
#define TURN_AROUND_TIMEOUT_MASK 0x3f
-#define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
-#define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
+#define _MIPIA_DEVICE_RESET_TIMER (dev_priv->display.mipi_mmio_base + 0xb01c)
+#define _MIPIC_DEVICE_RESET_TIMER (dev_priv->display.mipi_mmio_base + 0xb81c)
#define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
#define DEVICE_RESET_TIMER_MASK 0xffff
-#define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
-#define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
+#define _MIPIA_DPI_RESOLUTION (dev_priv->display.mipi_mmio_base + 0xb020)
+#define _MIPIC_DPI_RESOLUTION (dev_priv->display.mipi_mmio_base + 0xb820)
#define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
#define VERTICAL_ADDRESS_SHIFT 16
#define VERTICAL_ADDRESS_MASK (0xffff << 16)
#define HORIZONTAL_ADDRESS_SHIFT 0
#define HORIZONTAL_ADDRESS_MASK 0xffff
-#define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
-#define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
+#define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->display.mipi_mmio_base + 0xb024)
+#define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->display.mipi_mmio_base + 0xb824)
#define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
#define DBI_FIFO_EMPTY_HALF (0 << 0)
#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
/* regs below are bits 15:0 */
-#define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
-#define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
+#define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->display.mipi_mmio_base + 0xb028)
+#define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->display.mipi_mmio_base + 0xb828)
#define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
-#define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
-#define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
+#define _MIPIA_HBP_COUNT (dev_priv->display.mipi_mmio_base + 0xb02c)
+#define _MIPIC_HBP_COUNT (dev_priv->display.mipi_mmio_base + 0xb82c)
#define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
-#define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
-#define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
+#define _MIPIA_HFP_COUNT (dev_priv->display.mipi_mmio_base + 0xb030)
+#define _MIPIC_HFP_COUNT (dev_priv->display.mipi_mmio_base + 0xb830)
#define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
-#define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
-#define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
+#define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->display.mipi_mmio_base + 0xb034)
+#define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->display.mipi_mmio_base + 0xb834)
#define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
-#define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
-#define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
+#define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->display.mipi_mmio_base + 0xb038)
+#define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->display.mipi_mmio_base + 0xb838)
#define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
-#define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
-#define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
+#define _MIPIA_VBP_COUNT (dev_priv->display.mipi_mmio_base + 0xb03c)
+#define _MIPIC_VBP_COUNT (dev_priv->display.mipi_mmio_base + 0xb83c)
#define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
-#define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
-#define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
+#define _MIPIA_VFP_COUNT (dev_priv->display.mipi_mmio_base + 0xb040)
+#define _MIPIC_VFP_COUNT (dev_priv->display.mipi_mmio_base + 0xb840)
#define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
-#define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
-#define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
+#define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->display.mipi_mmio_base + 0xb044)
+#define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->display.mipi_mmio_base + 0xb844)
#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
/* regs above are bits 15:0 */
-#define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
-#define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
+#define _MIPIA_DPI_CONTROL (dev_priv->display.mipi_mmio_base + 0xb048)
+#define _MIPIC_DPI_CONTROL (dev_priv->display.mipi_mmio_base + 0xb848)
#define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
#define DPI_LP_MODE (1 << 6)
#define BACKLIGHT_OFF (1 << 5)
@@ -11884,27 +11884,27 @@ enum skl_power_gate {
#define TURN_ON (1 << 1)
#define SHUTDOWN (1 << 0)
-#define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
-#define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
+#define _MIPIA_DPI_DATA (dev_priv->display.mipi_mmio_base + 0xb04c)
+#define _MIPIC_DPI_DATA (dev_priv->display.mipi_mmio_base + 0xb84c)
#define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
#define COMMAND_BYTE_SHIFT 0
#define COMMAND_BYTE_MASK (0x3f << 0)
-#define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
-#define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
+#define _MIPIA_INIT_COUNT (dev_priv->display.mipi_mmio_base + 0xb050)
+#define _MIPIC_INIT_COUNT (dev_priv->display.mipi_mmio_base + 0xb850)
#define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
#define MASTER_INIT_TIMER_SHIFT 0
#define MASTER_INIT_TIMER_MASK (0xffff << 0)
-#define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
-#define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
+#define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->display.mipi_mmio_base + 0xb054)
+#define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->display.mipi_mmio_base + 0xb854)
#define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \
_MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
#define MAX_RETURN_PKT_SIZE_SHIFT 0
#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
-#define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
-#define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
+#define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->display.mipi_mmio_base + 0xb058)
+#define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->display.mipi_mmio_base + 0xb858)
#define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
#define DISABLE_VIDEO_BTA (1 << 3)
@@ -11913,8 +11913,8 @@ enum skl_power_gate {
#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
#define VIDEO_MODE_BURST (3 << 0)
-#define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
-#define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
+#define _MIPIA_EOT_DISABLE (dev_priv->display.mipi_mmio_base + 0xb05c)
+#define _MIPIC_EOT_DISABLE (dev_priv->display.mipi_mmio_base + 0xb85c)
#define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
#define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9)
#define BXT_DPHY_DEFEATURE_EN (1 << 8)
@@ -11927,35 +11927,35 @@ enum skl_power_gate {
#define CLOCKSTOP (1 << 1)
#define EOT_DISABLE (1 << 0)
-#define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
-#define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
+#define _MIPIA_LP_BYTECLK (dev_priv->display.mipi_mmio_base + 0xb060)
+#define _MIPIC_LP_BYTECLK (dev_priv->display.mipi_mmio_base + 0xb860)
#define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
#define LP_BYTECLK_SHIFT 0
#define LP_BYTECLK_MASK (0xffff << 0)
-#define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4)
-#define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4)
+#define _MIPIA_TLPX_TIME_COUNT (dev_priv->display.mipi_mmio_base + 0xb0a4)
+#define _MIPIC_TLPX_TIME_COUNT (dev_priv->display.mipi_mmio_base + 0xb8a4)
#define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
-#define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098)
-#define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898)
+#define _MIPIA_CLK_LANE_TIMING (dev_priv->display.mipi_mmio_base + 0xb098)
+#define _MIPIC_CLK_LANE_TIMING (dev_priv->display.mipi_mmio_base + 0xb898)
#define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
/* bits 31:0 */
-#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
-#define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
+#define _MIPIA_LP_GEN_DATA (dev_priv->display.mipi_mmio_base + 0xb064)
+#define _MIPIC_LP_GEN_DATA (dev_priv->display.mipi_mmio_base + 0xb864)
#define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
/* bits 31:0 */
-#define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
-#define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
+#define _MIPIA_HS_GEN_DATA (dev_priv->display.mipi_mmio_base + 0xb068)
+#define _MIPIC_HS_GEN_DATA (dev_priv->display.mipi_mmio_base + 0xb868)
#define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
-#define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
-#define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
+#define _MIPIA_LP_GEN_CTRL (dev_priv->display.mipi_mmio_base + 0xb06c)
+#define _MIPIC_LP_GEN_CTRL (dev_priv->display.mipi_mmio_base + 0xb86c)
#define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
-#define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
-#define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
+#define _MIPIA_HS_GEN_CTRL (dev_priv->display.mipi_mmio_base + 0xb070)
+#define _MIPIC_HS_GEN_CTRL (dev_priv->display.mipi_mmio_base + 0xb870)
#define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
#define LONG_PACKET_WORD_COUNT_SHIFT 8
#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
@@ -11967,8 +11967,8 @@ enum skl_power_gate {
#define DATA_TYPE_MASK (0x3f << 0)
/* data type values, see include/video/mipi_display.h */
-#define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
-#define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
+#define _MIPIA_GEN_FIFO_STAT (dev_priv->display.mipi_mmio_base + 0xb074)
+#define _MIPIC_GEN_FIFO_STAT (dev_priv->display.mipi_mmio_base + 0xb874)
#define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
#define DPI_FIFO_EMPTY (1 << 28)
#define DBI_FIFO_EMPTY (1 << 27)
@@ -11985,15 +11985,15 @@ enum skl_power_gate {
#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
#define HS_DATA_FIFO_FULL (1 << 0)
-#define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
-#define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
+#define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->display.mipi_mmio_base + 0xb078)
+#define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->display.mipi_mmio_base + 0xb878)
#define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
#define DBI_HS_LP_MODE_MASK (1 << 0)
#define DBI_LP_MODE (1 << 0)
#define DBI_HS_MODE (0 << 0)
-#define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
-#define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
+#define _MIPIA_DPHY_PARAM (dev_priv->display.mipi_mmio_base + 0xb080)
+#define _MIPIC_DPHY_PARAM (dev_priv->display.mipi_mmio_base + 0xb880)
#define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
#define EXIT_ZERO_COUNT_SHIFT 24
#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
@@ -12242,34 +12242,34 @@ enum skl_power_gate {
#define TA_TIMEOUT_VALUE(x) ((x) << 0)
/* bits 31:0 */
-#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
-#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
+#define _MIPIA_DBI_BW_CTRL (dev_priv->display.mipi_mmio_base + 0xb084)
+#define _MIPIC_DBI_BW_CTRL (dev_priv->display.mipi_mmio_base + 0xb884)
#define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
-#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088)
-#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888)
+#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->display.mipi_mmio_base + 0xb088)
+#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->display.mipi_mmio_base + 0xb888)
#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
#define LP_HS_SSW_CNT_SHIFT 16
#define LP_HS_SSW_CNT_MASK (0xffff << 16)
#define HS_LP_PWR_SW_CNT_SHIFT 0
#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
-#define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
-#define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
+#define _MIPIA_STOP_STATE_STALL (dev_priv->display.mipi_mmio_base + 0xb08c)
+#define _MIPIC_STOP_STATE_STALL (dev_priv->display.mipi_mmio_base + 0xb88c)
#define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
#define STOP_STATE_STALL_COUNTER_SHIFT 0
#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
-#define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
-#define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
+#define _MIPIA_INTR_STAT_REG_1 (dev_priv->display.mipi_mmio_base + 0xb090)
+#define _MIPIC_INTR_STAT_REG_1 (dev_priv->display.mipi_mmio_base + 0xb890)
#define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
-#define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
-#define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
+#define _MIPIA_INTR_EN_REG_1 (dev_priv->display.mipi_mmio_base + 0xb094)
+#define _MIPIC_INTR_EN_REG_1 (dev_priv->display.mipi_mmio_base + 0xb894)
#define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
#define RX_CONTENTION_DETECTED (1 << 0)
/* XXX: only pipe A ?!? */
-#define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
+#define MIPIA_DBI_TYPEC_CTRL (dev_priv->display.mipi_mmio_base + 0xb100)
#define DBI_TYPEC_ENABLE (1 << 31)
#define DBI_TYPEC_WIP (1 << 30)
#define DBI_TYPEC_OPTION_SHIFT 28
@@ -12283,8 +12283,8 @@ enum skl_power_gate {
/* MIPI adapter registers */
-#define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
-#define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
+#define _MIPIA_CTRL (dev_priv->display.mipi_mmio_base + 0xb104)
+#define _MIPIC_CTRL (dev_priv->display.mipi_mmio_base + 0xb904)
#define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
@@ -12316,21 +12316,21 @@ enum skl_power_gate {
#define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */
#define GLK_MIPIIO_ENABLE (1 << 0)
-#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
-#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
+#define _MIPIA_DATA_ADDRESS (dev_priv->display.mipi_mmio_base + 0xb108)
+#define _MIPIC_DATA_ADDRESS (dev_priv->display.mipi_mmio_base + 0xb908)
#define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
#define DATA_MEM_ADDRESS_SHIFT 5
#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
#define DATA_VALID (1 << 0)
-#define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
-#define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
+#define _MIPIA_DATA_LENGTH (dev_priv->display.mipi_mmio_base + 0xb10c)
+#define _MIPIC_DATA_LENGTH (dev_priv->display.mipi_mmio_base + 0xb90c)
#define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
#define DATA_LENGTH_SHIFT 0
#define DATA_LENGTH_MASK (0xfffff << 0)
-#define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
-#define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
+#define _MIPIA_COMMAND_ADDRESS (dev_priv->display.mipi_mmio_base + 0xb110)
+#define _MIPIC_COMMAND_ADDRESS (dev_priv->display.mipi_mmio_base + 0xb910)
#define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
#define COMMAND_MEM_ADDRESS_SHIFT 5
#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
@@ -12338,18 +12338,18 @@ enum skl_power_gate {
#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
#define COMMAND_VALID (1 << 0)
-#define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
-#define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
+#define _MIPIA_COMMAND_LENGTH (dev_priv->display.mipi_mmio_base + 0xb114)
+#define _MIPIC_COMMAND_LENGTH (dev_priv->display.mipi_mmio_base + 0xb914)
#define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
-#define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
-#define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
+#define _MIPIA_READ_DATA_RETURN0 (dev_priv->display.mipi_mmio_base + 0xb118)
+#define _MIPIC_READ_DATA_RETURN0 (dev_priv->display.mipi_mmio_base + 0xb918)
#define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
-#define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
-#define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
+#define _MIPIA_READ_DATA_VALID (dev_priv->display.mipi_mmio_base + 0xb138)
+#define _MIPIC_READ_DATA_VALID (dev_priv->display.mipi_mmio_base + 0xb938)
#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
#define READ_DATA_VALID(n) (1 << (n))
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Intel-gfx] [PATCH 07/10] drm/i915/display: move pps_mmio_base to display struct
2021-09-06 3:43 [Intel-gfx] [RFC PATCH 00/10] refactor display structs a little bit Dave Airlie
` (5 preceding siblings ...)
2021-09-06 3:43 ` [Intel-gfx] [PATCH 06/10] drm/i915/display: move mipi_mmio_base to " Dave Airlie
@ 2021-09-06 3:43 ` Dave Airlie
2021-09-06 3:43 ` [Intel-gfx] [PATCH 08/10] drm/i915/drrs: just use some local vars to simplify drrs code Dave Airlie
` (5 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Dave Airlie @ 2021-09-06 3:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_pps.c | 6 +++---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index a36ec4a818ff..857f3da80e26 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1402,9 +1402,9 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
void intel_pps_setup(struct drm_i915_private *i915)
{
if (HAS_PCH_SPLIT(i915) || IS_GEMINILAKE(i915) || IS_BROXTON(i915))
- i915->pps_mmio_base = PCH_PPS_BASE;
+ i915->display.pps_mmio_base = PCH_PPS_BASE;
else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
- i915->pps_mmio_base = VLV_PPS_BASE;
+ i915->display.pps_mmio_base = VLV_PPS_BASE;
else
- i915->pps_mmio_base = PPS_BASE;
+ i915->display.pps_mmio_base = PPS_BASE;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2d4cac666de9..4194a2042abf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -857,6 +857,8 @@ struct drm_i915_display {
/* MMIO base address for MIPI regs */
u32 mipi_mmio_base;
+ u32 pps_mmio_base;
+
struct intel_gmbus gmbus[GMBUS_NUM_PINS];
/** gmbus_mutex protects against concurrent usage of the single hw gmbus
@@ -915,8 +917,6 @@ struct drm_i915_private {
struct intel_wopcm wopcm;
- u32 pps_mmio_base;
-
struct pci_dev *bridge_dev;
struct rb_root uabi_engines;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 948949c15396..7afb6aa554c0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5166,7 +5166,7 @@ enum {
#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
#define PCH_PPS_BASE 0xC7200
-#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
+#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->display.pps_mmio_base - \
PPS_BASE + (reg) + \
(pps_idx) * 0x100)
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Intel-gfx] [PATCH 08/10] drm/i915/drrs: just use some local vars to simplify drrs code
2021-09-06 3:43 [Intel-gfx] [RFC PATCH 00/10] refactor display structs a little bit Dave Airlie
` (6 preceding siblings ...)
2021-09-06 3:43 ` [Intel-gfx] [PATCH 07/10] drm/i915/display: move pps_mmio_base " Dave Airlie
@ 2021-09-06 3:43 ` Dave Airlie
2021-09-06 3:43 ` [Intel-gfx] [PATCH 09/10] drm/i915/display: move drrs into display struct Dave Airlie
` (4 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Dave Airlie @ 2021-09-06 3:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
this makes it easier to move this struct later.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_drrs.c | 90 ++++++++++++-----------
1 file changed, 49 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index a2b65eca1441..670bcd50a56f 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -191,15 +191,16 @@ void intel_drrs_enable(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct i915_drrs *drrs = &dev_priv->drrs;
if (!crtc_state->has_drrs)
return;
drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
- mutex_lock(&dev_priv->drrs.mutex);
+ mutex_lock(&drrs->mutex);
- if (dev_priv->drrs.dp) {
+ if (drrs->dp) {
drm_warn(&dev_priv->drm, "DRRS already enabled\n");
goto unlock;
}
@@ -207,7 +208,7 @@ void intel_drrs_enable(struct intel_dp *intel_dp,
intel_drrs_enable_locked(intel_dp);
unlock:
- mutex_unlock(&dev_priv->drrs.mutex);
+ mutex_unlock(&drrs->mutex);
}
static void
@@ -215,15 +216,16 @@ intel_drrs_disable_locked(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct i915_drrs *drrs = &dev_priv->drrs;
- if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
+ if (drrs->refresh_rate_type == DRRS_LOW_RR) {
int refresh;
refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
intel_drrs_set_state(dev_priv, crtc_state, refresh);
}
- dev_priv->drrs.dp = NULL;
+ drrs->dp = NULL;
}
/**
@@ -236,20 +238,21 @@ void intel_drrs_disable(struct intel_dp *intel_dp,
const struct intel_crtc_state *old_crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct i915_drrs *drrs = &dev_priv->drrs;
if (!old_crtc_state->has_drrs)
return;
- mutex_lock(&dev_priv->drrs.mutex);
- if (!dev_priv->drrs.dp) {
- mutex_unlock(&dev_priv->drrs.mutex);
+ mutex_lock(&drrs->mutex);
+ if (!drrs->dp) {
+ mutex_unlock(&drrs->mutex);
return;
}
intel_drrs_disable_locked(intel_dp, old_crtc_state);
- mutex_unlock(&dev_priv->drrs.mutex);
+ mutex_unlock(&drrs->mutex);
- cancel_delayed_work_sync(&dev_priv->drrs.work);
+ cancel_delayed_work_sync(&drrs->work);
}
/**
@@ -266,14 +269,15 @@ intel_drrs_update(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct i915_drrs *drrs = &dev_priv->drrs;
- if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
+ if (drrs->type != SEAMLESS_DRRS_SUPPORT)
return;
- mutex_lock(&dev_priv->drrs.mutex);
+ mutex_lock(&drrs->mutex);
/* New state matches current one? */
- if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
+ if (crtc_state->has_drrs == !!drrs->dp)
goto unlock;
if (crtc_state->has_drrs)
@@ -282,18 +286,19 @@ intel_drrs_update(struct intel_dp *intel_dp,
intel_drrs_disable_locked(intel_dp, crtc_state);
unlock:
- mutex_unlock(&dev_priv->drrs.mutex);
+ mutex_unlock(&drrs->mutex);
}
static void intel_drrs_downclock_work(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
container_of(work, typeof(*dev_priv), drrs.work.work);
+ struct i915_drrs *drrs = &dev_priv->drrs;
struct intel_dp *intel_dp;
- mutex_lock(&dev_priv->drrs.mutex);
+ mutex_lock(&drrs->mutex);
- intel_dp = dev_priv->drrs.dp;
+ intel_dp = drrs->dp;
if (!intel_dp)
goto unlock;
@@ -303,10 +308,10 @@ static void intel_drrs_downclock_work(struct work_struct *work)
* recheck.
*/
- if (dev_priv->drrs.busy_frontbuffer_bits)
+ if (drrs->busy_frontbuffer_bits)
goto unlock;
- if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
+ if (drrs->refresh_rate_type != DRRS_LOW_RR) {
struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
intel_drrs_set_state(dev_priv, to_intel_crtc(crtc)->config,
@@ -314,7 +319,7 @@ static void intel_drrs_downclock_work(struct work_struct *work)
}
unlock:
- mutex_unlock(&dev_priv->drrs.mutex);
+ mutex_unlock(&drrs->mutex);
}
/**
@@ -330,20 +335,21 @@ static void intel_drrs_downclock_work(struct work_struct *work)
void intel_drrs_invalidate(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits)
{
+ struct i915_drrs *drrs = &dev_priv->drrs;
struct intel_dp *intel_dp;
struct drm_crtc *crtc;
enum pipe pipe;
- if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
+ if (drrs->type == DRRS_NOT_SUPPORTED)
return;
- cancel_delayed_work(&dev_priv->drrs.work);
+ cancel_delayed_work(&drrs->work);
- mutex_lock(&dev_priv->drrs.mutex);
+ mutex_lock(&drrs->mutex);
- intel_dp = dev_priv->drrs.dp;
+ intel_dp = drrs->dp;
if (!intel_dp) {
- mutex_unlock(&dev_priv->drrs.mutex);
+ mutex_unlock(&drrs->mutex);
return;
}
@@ -351,14 +357,14 @@ void intel_drrs_invalidate(struct drm_i915_private *dev_priv,
pipe = to_intel_crtc(crtc)->pipe;
frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
- dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
+ drrs->busy_frontbuffer_bits |= frontbuffer_bits;
/* invalidate means busy screen hence upclock */
- if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
+ if (frontbuffer_bits && drrs->refresh_rate_type == DRRS_LOW_RR)
intel_drrs_set_state(dev_priv, to_intel_crtc(crtc)->config,
drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
- mutex_unlock(&dev_priv->drrs.mutex);
+ mutex_unlock(&drrs->mutex);
}
/**
@@ -376,20 +382,21 @@ void intel_drrs_invalidate(struct drm_i915_private *dev_priv,
void intel_drrs_flush(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits)
{
+ struct i915_drrs *drrs = &dev_priv->drrs;
struct intel_dp *intel_dp;
struct drm_crtc *crtc;
enum pipe pipe;
- if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
+ if (drrs->type == DRRS_NOT_SUPPORTED)
return;
- cancel_delayed_work(&dev_priv->drrs.work);
+ cancel_delayed_work(&drrs->work);
- mutex_lock(&dev_priv->drrs.mutex);
+ mutex_lock(&drrs->mutex);
- intel_dp = dev_priv->drrs.dp;
+ intel_dp = drrs->dp;
if (!intel_dp) {
- mutex_unlock(&dev_priv->drrs.mutex);
+ mutex_unlock(&drrs->mutex);
return;
}
@@ -397,10 +404,10 @@ void intel_drrs_flush(struct drm_i915_private *dev_priv,
pipe = to_intel_crtc(crtc)->pipe;
frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
- dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
+ drrs->busy_frontbuffer_bits &= ~frontbuffer_bits;
/* flush means busy screen hence upclock */
- if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
+ if (frontbuffer_bits && drrs->refresh_rate_type == DRRS_LOW_RR)
intel_drrs_set_state(dev_priv, to_intel_crtc(crtc)->config,
drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
@@ -408,10 +415,10 @@ void intel_drrs_flush(struct drm_i915_private *dev_priv,
* flush also means no more activity hence schedule downclock, if all
* other fbs are quiescent too
*/
- if (!dev_priv->drrs.busy_frontbuffer_bits)
- schedule_delayed_work(&dev_priv->drrs.work,
+ if (!drrs->busy_frontbuffer_bits)
+ schedule_delayed_work(&drrs->work,
msecs_to_jiffies(1000));
- mutex_unlock(&dev_priv->drrs.mutex);
+ mutex_unlock(&drrs->mutex);
}
/**
@@ -432,10 +439,11 @@ intel_drrs_init(struct intel_connector *connector,
struct drm_display_mode *fixed_mode)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct i915_drrs *drrs = &dev_priv->drrs;
struct drm_display_mode *downclock_mode = NULL;
- INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_drrs_downclock_work);
- mutex_init(&dev_priv->drrs.mutex);
+ INIT_DELAYED_WORK(&drrs->work, intel_drrs_downclock_work);
+ mutex_init(&drrs->mutex);
if (DISPLAY_VER(dev_priv) <= 6) {
drm_dbg_kms(&dev_priv->drm,
@@ -455,9 +463,9 @@ intel_drrs_init(struct intel_connector *connector,
return NULL;
}
- dev_priv->drrs.type = dev_priv->vbt.drrs_type;
+ drrs->type = dev_priv->vbt.drrs_type;
- dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
+ drrs->refresh_rate_type = DRRS_HIGH_RR;
drm_dbg_kms(&dev_priv->drm,
"seamless DRRS supported for eDP panel.\n");
return downclock_mode;
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Intel-gfx] [PATCH 09/10] drm/i915/display: move drrs into display struct
2021-09-06 3:43 [Intel-gfx] [RFC PATCH 00/10] refactor display structs a little bit Dave Airlie
` (7 preceding siblings ...)
2021-09-06 3:43 ` [Intel-gfx] [PATCH 08/10] drm/i915/drrs: just use some local vars to simplify drrs code Dave Airlie
@ 2021-09-06 3:43 ` Dave Airlie
2021-09-06 3:43 ` [Intel-gfx] [PATCH 10/10] drm/i915/display: move fbc " Dave Airlie
` (3 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Dave Airlie @ 2021-09-06 3:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../drm/i915/display/intel_display_debugfs.c | 2 +-
drivers/gpu/drm/i915/display/intel_drrs.c | 32 +++++++++----------
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
4 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 7221bf2e75b0..0fe8c1ec491f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1234,7 +1234,7 @@ static void drrs_status_per_crtc(struct seq_file *m,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct i915_drrs *drrs = &dev_priv->drrs;
+ struct i915_drrs *drrs = &dev_priv->display.drrs;
int vrefresh = 0;
struct drm_connector *connector;
struct drm_connector_list_iter conn_iter;
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index 670bcd50a56f..2430041f4c53 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -69,7 +69,7 @@ intel_drrs_compute_config(struct intel_dp *intel_dp,
return;
if (!intel_connector->panel.downclock_mode ||
- dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
+ dev_priv->display.drrs.type != SEAMLESS_DRRS_SUPPORT)
return;
pipe_config->has_drrs = true;
@@ -91,7 +91,7 @@ static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
int refresh_rate)
{
- struct intel_dp *intel_dp = dev_priv->drrs.dp;
+ struct intel_dp *intel_dp = dev_priv->display.drrs.dp;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
@@ -112,7 +112,7 @@ static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
return;
}
- if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
+ if (dev_priv->display.drrs.type < SEAMLESS_DRRS_SUPPORT) {
drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
return;
}
@@ -121,7 +121,7 @@ static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
refresh_rate)
index = DRRS_LOW_RR;
- if (index == dev_priv->drrs.refresh_rate_type) {
+ if (index == dev_priv->display.drrs.refresh_rate_type) {
drm_dbg_kms(&dev_priv->drm,
"DRRS requested for previously set RR...ignoring\n");
return;
@@ -165,7 +165,7 @@ static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
intel_de_write(dev_priv, reg, val);
}
- dev_priv->drrs.refresh_rate_type = index;
+ dev_priv->display.drrs.refresh_rate_type = index;
drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
refresh_rate);
@@ -176,8 +176,8 @@ intel_drrs_enable_locked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- dev_priv->drrs.busy_frontbuffer_bits = 0;
- dev_priv->drrs.dp = intel_dp;
+ dev_priv->display.drrs.busy_frontbuffer_bits = 0;
+ dev_priv->display.drrs.dp = intel_dp;
}
/**
@@ -191,7 +191,7 @@ void intel_drrs_enable(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct i915_drrs *drrs = &dev_priv->drrs;
+ struct i915_drrs *drrs = &dev_priv->display.drrs;
if (!crtc_state->has_drrs)
return;
@@ -216,7 +216,7 @@ intel_drrs_disable_locked(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct i915_drrs *drrs = &dev_priv->drrs;
+ struct i915_drrs *drrs = &dev_priv->display.drrs;
if (drrs->refresh_rate_type == DRRS_LOW_RR) {
int refresh;
@@ -238,7 +238,7 @@ void intel_drrs_disable(struct intel_dp *intel_dp,
const struct intel_crtc_state *old_crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct i915_drrs *drrs = &dev_priv->drrs;
+ struct i915_drrs *drrs = &dev_priv->display.drrs;
if (!old_crtc_state->has_drrs)
return;
@@ -269,7 +269,7 @@ intel_drrs_update(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct i915_drrs *drrs = &dev_priv->drrs;
+ struct i915_drrs *drrs = &dev_priv->display.drrs;
if (drrs->type != SEAMLESS_DRRS_SUPPORT)
return;
@@ -292,8 +292,8 @@ intel_drrs_update(struct intel_dp *intel_dp,
static void intel_drrs_downclock_work(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
- container_of(work, typeof(*dev_priv), drrs.work.work);
- struct i915_drrs *drrs = &dev_priv->drrs;
+ container_of(work, typeof(*dev_priv), display.drrs.work.work);
+ struct i915_drrs *drrs = &dev_priv->display.drrs;
struct intel_dp *intel_dp;
mutex_lock(&drrs->mutex);
@@ -335,7 +335,7 @@ static void intel_drrs_downclock_work(struct work_struct *work)
void intel_drrs_invalidate(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits)
{
- struct i915_drrs *drrs = &dev_priv->drrs;
+ struct i915_drrs *drrs = &dev_priv->display.drrs;
struct intel_dp *intel_dp;
struct drm_crtc *crtc;
enum pipe pipe;
@@ -382,7 +382,7 @@ void intel_drrs_invalidate(struct drm_i915_private *dev_priv,
void intel_drrs_flush(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits)
{
- struct i915_drrs *drrs = &dev_priv->drrs;
+ struct i915_drrs *drrs = &dev_priv->display.drrs;
struct intel_dp *intel_dp;
struct drm_crtc *crtc;
enum pipe pipe;
@@ -439,7 +439,7 @@ intel_drrs_init(struct intel_connector *connector,
struct drm_display_mode *fixed_mode)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- struct i915_drrs *drrs = &dev_priv->drrs;
+ struct i915_drrs *drrs = &dev_priv->display.drrs;
struct drm_display_mode *downclock_mode = NULL;
INIT_DELAYED_WORK(&drrs->work, intel_drrs_downclock_work);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b355c8d36b2d..be826ef8bd43 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1225,7 +1225,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
if (!crtc_state->has_psr)
return;
- drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp);
+ drm_WARN_ON(&dev_priv->drm, dev_priv->display.drrs.dp);
mutex_lock(&intel_dp->psr.lock);
intel_psr_enable_locked(intel_dp, crtc_state, conn_state);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4194a2042abf..daa289a0efab 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -867,6 +867,7 @@ struct drm_i915_display {
wait_queue_head_t gmbus_wait_queue;
struct intel_dmc dmc;
+ struct i915_drrs drrs;
};
struct drm_i915_private {
@@ -941,7 +942,6 @@ struct drm_i915_private {
struct i915_hotplug hotplug;
struct intel_fbc fbc;
- struct i915_drrs drrs;
struct intel_opregion opregion;
struct intel_vbt_data vbt;
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Intel-gfx] [PATCH 10/10] drm/i915/display: move fbc into display struct
2021-09-06 3:43 [Intel-gfx] [RFC PATCH 00/10] refactor display structs a little bit Dave Airlie
` (8 preceding siblings ...)
2021-09-06 3:43 ` [Intel-gfx] [PATCH 09/10] drm/i915/display: move drrs into display struct Dave Airlie
@ 2021-09-06 3:43 ` Dave Airlie
2021-09-06 4:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for refactor display structs a little bit Patchwork
` (2 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Dave Airlie @ 2021-09-06 3:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +-
.../drm/i915/display/intel_display_debugfs.c | 10 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 98 +++++++++----------
.../drm/i915/display/skl_universal_plane.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
5 files changed, 57 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index b1439ba78f67..6627ba207c4e 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -791,7 +791,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
if (plane->has_fbc) {
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 0fe8c1ec491f..f16ef3d91d0c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -43,7 +43,7 @@ static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
static int i915_fbc_status(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
intel_wakeref_t wakeref;
if (!HAS_FBC(dev_priv))
@@ -88,7 +88,7 @@ static int i915_fbc_false_color_get(void *data, u64 *val)
if (DISPLAY_VER(dev_priv) < 7 || !HAS_FBC(dev_priv))
return -ENODEV;
- *val = dev_priv->fbc.false_color;
+ *val = dev_priv->display.fbc.false_color;
return 0;
}
@@ -101,15 +101,15 @@ static int i915_fbc_false_color_set(void *data, u64 val)
if (DISPLAY_VER(dev_priv) < 7 || !HAS_FBC(dev_priv))
return -ENODEV;
- mutex_lock(&dev_priv->fbc.lock);
+ mutex_lock(&dev_priv->display.fbc.lock);
reg = intel_de_read(dev_priv, ILK_DPFC_CONTROL);
- dev_priv->fbc.false_color = val;
+ dev_priv->display.fbc.false_color = val;
intel_de_write(dev_priv, ILK_DPFC_CONTROL,
val ? (reg | FBC_CTL_FALSE_COLOR) : (reg & ~FBC_CTL_FALSE_COLOR));
- mutex_unlock(&dev_priv->fbc.lock);
+ mutex_unlock(&dev_priv->display.fbc.lock);
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7e52858399c9..b96b71be81d2 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -99,7 +99,7 @@ static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
{
- struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ struct intel_fbc_reg_params *params = &dev_priv->display.fbc.params;
int cfb_pitch;
int i;
u32 fbc_ctl;
@@ -150,8 +150,8 @@ static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
static u32 g4x_dpfc_ctl_limit(struct drm_i915_private *i915)
{
- const struct intel_fbc_reg_params *params = &i915->fbc.params;
- int limit = i915->fbc.limit;
+ const struct intel_fbc_reg_params *params = &i915->display.fbc.params;
+ int limit = i915->display.fbc.limit;
if (params->fb.format->cpp[0] == 2)
limit <<= 1;
@@ -171,7 +171,7 @@ static u32 g4x_dpfc_ctl_limit(struct drm_i915_private *i915)
static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
{
- struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ struct intel_fbc_reg_params *params = &dev_priv->display.fbc.params;
u32 dpfc_ctl;
dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane) | DPFC_SR_EN;
@@ -209,7 +209,7 @@ static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
static void i8xx_fbc_recompress(struct drm_i915_private *dev_priv)
{
- struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ struct intel_fbc_reg_params *params = &dev_priv->display.fbc.params;
enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
spin_lock_irq(&dev_priv->uncore.lock);
@@ -220,7 +220,7 @@ static void i8xx_fbc_recompress(struct drm_i915_private *dev_priv)
static void i965_fbc_recompress(struct drm_i915_private *dev_priv)
{
- struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ struct intel_fbc_reg_params *params = &dev_priv->display.fbc.params;
enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
spin_lock_irq(&dev_priv->uncore.lock);
@@ -238,7 +238,7 @@ static void snb_fbc_recompress(struct drm_i915_private *dev_priv)
static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
trace_intel_fbc_nuke(fbc->crtc);
@@ -252,7 +252,7 @@ static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
{
- struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ struct intel_fbc_reg_params *params = &dev_priv->display.fbc.params;
u32 dpfc_ctl;
dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane);
@@ -301,7 +301,7 @@ static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
{
- struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ struct intel_fbc_reg_params *params = &dev_priv->display.fbc.params;
u32 dpfc_ctl;
/* Display WA #0529: skl, kbl, bxt. */
@@ -334,7 +334,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
}
- if (dev_priv->fbc.false_color)
+ if (dev_priv->display.fbc.false_color)
dpfc_ctl |= FBC_CTL_FALSE_COLOR;
intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
@@ -352,7 +352,7 @@ static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
trace_intel_fbc_activate(fbc->crtc);
@@ -371,7 +371,7 @@ static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
trace_intel_fbc_deactivate(fbc->crtc);
@@ -396,7 +396,7 @@ static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
*/
bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
{
- return dev_priv->fbc.active;
+ return dev_priv->display.fbc.active;
}
static void intel_fbc_activate(struct drm_i915_private *dev_priv)
@@ -408,7 +408,7 @@ static void intel_fbc_activate(struct drm_i915_private *dev_priv)
static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
const char *reason)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
@@ -464,7 +464,7 @@ static int find_compression_limit(struct drm_i915_private *dev_priv,
unsigned int size,
unsigned int fb_cpp)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
u64 end = intel_fbc_stolen_end(dev_priv);
int ret, limit = 1;
@@ -487,7 +487,7 @@ static int find_compression_limit(struct drm_i915_private *dev_priv,
static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
unsigned int size, unsigned int fb_cpp)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
int ret;
drm_WARN_ON(&dev_priv->drm,
@@ -529,7 +529,7 @@ static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
static void intel_fbc_program_cfb(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
if (DISPLAY_VER(dev_priv) >= 5) {
intel_de_write(dev_priv, ILK_DPFC_CB_BASE,
@@ -554,7 +554,7 @@ static void intel_fbc_program_cfb(struct drm_i915_private *dev_priv)
static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
if (WARN_ON(intel_fbc_hw_is_active(dev_priv)))
return;
@@ -567,7 +567,7 @@ static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
if (!HAS_FBC(dev_priv))
return;
@@ -648,7 +648,7 @@ static bool rotation_is_valid(struct drm_i915_private *dev_priv,
static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
unsigned int effective_w, effective_h, max_w, max_h;
if (DISPLAY_VER(dev_priv) >= 10) {
@@ -692,7 +692,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
struct intel_fbc_state_cache *cache = &fbc->state_cache;
struct drm_framebuffer *fb = plane_state->hw.fb;
@@ -744,7 +744,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
return intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
fbc->compressed_fb.size * fbc->limit;
@@ -752,7 +752,7 @@ static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv)
static u16 intel_fbc_override_cfb_stride(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
struct intel_fbc_state_cache *cache = &fbc->state_cache;
if ((DISPLAY_VER(dev_priv) == 9) &&
@@ -764,14 +764,14 @@ static u16 intel_fbc_override_cfb_stride(struct drm_i915_private *dev_priv)
static bool intel_fbc_override_cfb_stride_changed(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
return fbc->params.override_cfb_stride != intel_fbc_override_cfb_stride(dev_priv);
}
static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
if (intel_vgpu_active(dev_priv)) {
fbc->no_fbc_reason = "VGPU is active";
@@ -794,7 +794,7 @@ static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
static bool intel_fbc_can_activate(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
struct intel_fbc_state_cache *cache = &fbc->state_cache;
if (!intel_fbc_can_enable(dev_priv))
@@ -929,7 +929,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
struct intel_fbc_reg_params *params)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
struct intel_fbc_state_cache *cache = &fbc->state_cache;
/* Since all our fields are integer types, use memset here so the
@@ -960,7 +960,7 @@ static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct intel_fbc *fbc = &dev_priv->fbc;
+ const struct intel_fbc *fbc = &dev_priv->display.fbc;
const struct intel_fbc_state_cache *cache = &fbc->state_cache;
const struct intel_fbc_reg_params *params = &fbc->params;
@@ -1000,7 +1000,7 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state,
const struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
const char *reason = "update pending";
bool need_vblank_wait = false;
@@ -1051,7 +1051,7 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state,
*/
static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
struct intel_crtc *crtc = fbc->crtc;
drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
@@ -1069,7 +1069,7 @@ static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
static void __intel_fbc_post_update(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
@@ -1103,7 +1103,7 @@ void intel_fbc_post_update(struct intel_atomic_state *state,
struct intel_plane *plane = to_intel_plane(crtc->base.primary);
const struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
if (!plane->has_fbc || !plane_state)
return;
@@ -1125,7 +1125,7 @@ void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits,
enum fb_op_origin origin)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
if (!HAS_FBC(dev_priv))
return;
@@ -1146,7 +1146,7 @@ void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
void intel_fbc_flush(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits, enum fb_op_origin origin)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
if (!HAS_FBC(dev_priv))
return;
@@ -1180,12 +1180,12 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv,
* true.
*
* Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
- * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
+ * enable FBC for the chosen CRTC. If it does, it will set dev_priv->display.fbc.crtc.
*/
void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
struct intel_atomic_state *state)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
struct intel_plane *plane;
struct intel_plane_state *plane_state;
bool crtc_chosen = false;
@@ -1248,7 +1248,7 @@ static void intel_fbc_enable(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
struct intel_fbc_state_cache *cache = &fbc->state_cache;
if (!plane->has_fbc || !plane_state)
@@ -1304,7 +1304,7 @@ void intel_fbc_disable(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_plane *plane = to_intel_plane(crtc->base.primary);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
if (!plane->has_fbc)
return;
@@ -1345,7 +1345,7 @@ void intel_fbc_update(struct intel_atomic_state *state,
*/
void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
if (!HAS_FBC(dev_priv))
return;
@@ -1361,8 +1361,8 @@ void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
static void intel_fbc_underrun_work_fn(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
- container_of(work, struct drm_i915_private, fbc.underrun_work);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ container_of(work, struct drm_i915_private, display.fbc.underrun_work);
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
mutex_lock(&fbc->lock);
@@ -1389,20 +1389,20 @@ int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv)
{
int ret;
- cancel_work_sync(&dev_priv->fbc.underrun_work);
+ cancel_work_sync(&dev_priv->display.fbc.underrun_work);
- ret = mutex_lock_interruptible(&dev_priv->fbc.lock);
+ ret = mutex_lock_interruptible(&dev_priv->display.fbc.lock);
if (ret)
return ret;
- if (dev_priv->fbc.underrun_detected) {
+ if (dev_priv->display.fbc.underrun_detected) {
drm_dbg_kms(&dev_priv->drm,
"Re-allowing FBC after fifo underrun\n");
- dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared";
+ dev_priv->display.fbc.no_fbc_reason = "FIFO underrun cleared";
}
- dev_priv->fbc.underrun_detected = false;
- mutex_unlock(&dev_priv->fbc.lock);
+ dev_priv->display.fbc.underrun_detected = false;
+ mutex_unlock(&dev_priv->display.fbc.lock);
return 0;
}
@@ -1423,7 +1423,7 @@ int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv)
*/
void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
if (!HAS_FBC(dev_priv))
return;
@@ -1484,7 +1484,7 @@ static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
*/
void intel_fbc_init(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
mutex_init(&fbc->lock);
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 724e7b04f3b6..a9c7fe4bcab7 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2067,7 +2067,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->has_fbc = skl_plane_has_fbc(dev_priv, pipe, plane_id);
if (plane->has_fbc) {
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display.fbc;
fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index daa289a0efab..e5dba4e7f636 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -868,6 +868,7 @@ struct drm_i915_display {
struct intel_dmc dmc;
struct i915_drrs drrs;
+ struct intel_fbc fbc;
};
struct drm_i915_private {
@@ -941,7 +942,6 @@ struct drm_i915_private {
u32 pipestat_irq_mask[I915_MAX_PIPES];
struct i915_hotplug hotplug;
- struct intel_fbc fbc;
struct intel_opregion opregion;
struct intel_vbt_data vbt;
--
2.31.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for refactor display structs a little bit
2021-09-06 3:43 [Intel-gfx] [RFC PATCH 00/10] refactor display structs a little bit Dave Airlie
` (9 preceding siblings ...)
2021-09-06 3:43 ` [Intel-gfx] [PATCH 10/10] drm/i915/display: move fbc " Dave Airlie
@ 2021-09-06 4:21 ` Patchwork
2021-09-06 4:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-06 6:07 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
12 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2021-09-06 4:21 UTC (permalink / raw)
To: Dave Airlie; +Cc: intel-gfx
== Series Details ==
Series: refactor display structs a little bit
URL : https://patchwork.freedesktop.org/series/94367/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f4fbd6000df1 drm/i915: move display funcs into a display struct.
76dc91485857 drm/i915/display: move cdclk info into display
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:662: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#662: FILE: drivers/gpu/drm/i915/display/intel_cdclk.h:77:
+ to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
-:665: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#665: FILE: drivers/gpu/drm/i915/display/intel_cdclk.h:79:
+ to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
-:711: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#711: FILE: drivers/gpu/drm/i915/display/intel_display.c:11273:
+ cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw;
total: 0 errors, 3 warnings, 1 checks, 782 lines checked
7b219ea05311 drm/i915: move more pll/clocks into display struct.
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:149: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#149: FILE: drivers/gpu/drm/i915/display/intel_display.c:179:
+ dev_priv->display.czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
CCK_CZ_CLOCK_CONTROL);
total: 0 errors, 1 warnings, 1 checks, 302 lines checked
38bff6053be9 drm/i915/display: move gmbus into display struct
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:231: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#231: FILE: drivers/gpu/drm/i915/i915_drv.h:860:
+ * controller on different i2c buses. */
-:300: WARNING:LONG_LINE_COMMENT: line length of 104 exceeds 100 columns
#300: FILE: drivers/gpu/drm/i915/i915_reg.h:3453:
+#define GMBUS0 _MMIO(dev_priv->display.gpio_mmio_base + 0x5100) /* clock/port select */
-:309: WARNING:LONG_LINE_COMMENT: line length of 101 exceeds 100 columns
#309: FILE: drivers/gpu/drm/i915/i915_reg.h:3462:
+#define GMBUS1 _MMIO(dev_priv->display.gpio_mmio_base + 0x5104) /* command/status */
-:328: WARNING:LONG_LINE_COMMENT: line length of 108 exceeds 100 columns
#328: FILE: drivers/gpu/drm/i915/i915_reg.h:3485:
+#define GMBUS3 _MMIO(dev_priv->display.gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
-:329: WARNING:LONG_LINE_COMMENT: line length of 113 exceeds 100 columns
#329: FILE: drivers/gpu/drm/i915/i915_reg.h:3486:
+#define GMBUS4 _MMIO(dev_priv->display.gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
total: 0 errors, 6 warnings, 0 checks, 282 lines checked
bb277479cb80 drm/i915/display: move intel_dmc into display struct
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:81: WARNING:LONG_LINE: line length of 113 exceeds 100 columns
#81: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:968:
+ DMC_PROGRAM(dev_priv->display.dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
total: 0 errors, 2 warnings, 0 checks, 322 lines checked
6ce1abe08452 drm/i915/display: move mipi_mmio_base to display struct
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 401 lines checked
f924c533b785 drm/i915/display: move pps_mmio_base to display struct
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 36 lines checked
00d5669bd6e9 drm/i915/drrs: just use some local vars to simplify drrs code
abfd2f3e84da drm/i915/display: move drrs into display struct
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 146 lines checked
bc448a9d147a drm/i915/display: move fbc into display struct
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 420 lines checked
^ permalink raw reply [flat|nested] 20+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for refactor display structs a little bit
2021-09-06 3:43 [Intel-gfx] [RFC PATCH 00/10] refactor display structs a little bit Dave Airlie
` (10 preceding siblings ...)
2021-09-06 4:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for refactor display structs a little bit Patchwork
@ 2021-09-06 4:51 ` Patchwork
2021-09-06 6:07 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
12 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2021-09-06 4:51 UTC (permalink / raw)
To: Dave Airlie; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 2671 bytes --]
== Series Details ==
Series: refactor display structs a little bit
URL : https://patchwork.freedesktop.org/series/94367/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10551 -> Patchwork_20963
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/index.html
Known issues
------------
Here are the changes found in Patchwork_20963 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][1] ([i915#1602] / [i915#2029])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/fi-bdw-5557u/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_module_load@reload:
- fi-kbl-soraka: [DMESG-WARN][2] ([i915#1982]) -> [PASS][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/fi-kbl-soraka/igt@i915_module_load@reload.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/fi-kbl-soraka/igt@i915_module_load@reload.html
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
Participating hosts (46 -> 39)
------------------------------
Missing (7): bat-adls-5 bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-4 fi-bdw-samus bat-jsl-1
Build changes
-------------
* Linux: CI_DRM_10551 -> Patchwork_20963
CI-20190529: 20190529
CI_DRM_10551: 2b58e5151c7043a45a02238d63f7e17cf5cad46a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6197: 40888f97a6ad219f4ed48a1830d0ef3c9617d006 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20963: bc448a9d147ac1f59962f69c2e22ccc012f93256 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bc448a9d147a drm/i915/display: move fbc into display struct
abfd2f3e84da drm/i915/display: move drrs into display struct
00d5669bd6e9 drm/i915/drrs: just use some local vars to simplify drrs code
f924c533b785 drm/i915/display: move pps_mmio_base to display struct
6ce1abe08452 drm/i915/display: move mipi_mmio_base to display struct
bb277479cb80 drm/i915/display: move intel_dmc into display struct
38bff6053be9 drm/i915/display: move gmbus into display struct
7b219ea05311 drm/i915: move more pll/clocks into display struct.
76dc91485857 drm/i915/display: move cdclk info into display
f4fbd6000df1 drm/i915: move display funcs into a display struct.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/index.html
[-- Attachment #2: Type: text/html, Size: 3339 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for refactor display structs a little bit
2021-09-06 3:43 [Intel-gfx] [RFC PATCH 00/10] refactor display structs a little bit Dave Airlie
` (11 preceding siblings ...)
2021-09-06 4:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-09-06 6:07 ` Patchwork
12 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2021-09-06 6:07 UTC (permalink / raw)
To: Dave Airlie; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 28475 bytes --]
== Series Details ==
Series: refactor display structs a little bit
URL : https://patchwork.freedesktop.org/series/94367/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10551_full -> Patchwork_20963_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_20963_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20963_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20963_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_whisper@basic-queues-forked-all:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-tglb5/igt@gem_exec_whisper@basic-queues-forked-all.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-tglb5/igt@gem_exec_whisper@basic-queues-forked-all.html
Known issues
------------
Here are the changes found in Patchwork_20963_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@chamelium:
- shard-tglb: NOTRUN -> [SKIP][3] ([fdo#111827])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-tglb6/igt@feature_discovery@chamelium.html
* igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +2 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-snb2/igt@gem_ctx_persistence@legacy-engines-queued.html
* igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2410])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-tglb5/igt@gem_ctx_persistence@many-contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-tglb8/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_eio@in-flight-suspend:
- shard-apl: NOTRUN -> [DMESG-WARN][7] ([i915#180])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-apl8/igt@gem_eio@in-flight-suspend.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][8] -> [TIMEOUT][9] ([i915#2369] / [i915#3063] / [i915#3648])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-tglb6/igt@gem_eio@unwedge-stress.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-tglb7/igt@gem_eio@unwedge-stress.html
- shard-iclb: [PASS][10] -> [TIMEOUT][11] ([i915#2369] / [i915#2481] / [i915#3070])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-iclb3/igt@gem_eio@unwedge-stress.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-iclb2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-skl: NOTRUN -> [FAIL][12] ([i915#2846])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-skl6/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842]) +5 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#2842])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][17] -> [FAIL][18] ([i915#2849])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_schedule@u-semaphore-user:
- shard-snb: NOTRUN -> [SKIP][19] ([fdo#109271]) +217 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-snb6/igt@gem_exec_schedule@u-semaphore-user.html
* igt@gem_userptr_blits@unsync-unmap-after-close:
- shard-tglb: NOTRUN -> [SKIP][20] ([i915#3297])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-tglb6/igt@gem_userptr_blits@unsync-unmap-after-close.html
* igt@gem_userptr_blits@vma-merge:
- shard-snb: NOTRUN -> [FAIL][21] ([i915#2724])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-snb6/igt@gem_userptr_blits@vma-merge.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [PASS][22] -> [INCOMPLETE][23] ([i915#3921])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-snb2/igt@i915_selftest@live@hangcheck.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-snb6/igt@i915_selftest@live@hangcheck.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][24] ([i915#3722])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-skl4/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#3777])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-apl6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3886]) +9 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-apl8/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3886]) +4 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-skl5/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][28] ([i915#3689]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-tglb6/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_ccs.html
* igt@kms_chamelium@dp-crc-single:
- shard-snb: NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +11 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-snb7/igt@kms_chamelium@dp-crc-single.html
* igt@kms_chamelium@vga-hpd:
- shard-apl: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +11 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-apl8/igt@kms_chamelium@vga-hpd.html
* igt@kms_chamelium@vga-hpd-after-suspend:
- shard-skl: NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) +3 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-skl4/igt@kms_chamelium@vga-hpd-after-suspend.html
* igt@kms_color_chamelium@pipe-b-ctm-negative:
- shard-tglb: NOTRUN -> [SKIP][32] ([fdo#109284] / [fdo#111827]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-tglb6/igt@kms_color_chamelium@pipe-b-ctm-negative.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: NOTRUN -> [TIMEOUT][33] ([i915#1319])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-apl6/igt@kms_content_protection@atomic-dpms.html
* igt@kms_cursor_crc@pipe-c-cursor-512x170-offscreen:
- shard-tglb: NOTRUN -> [SKIP][34] ([fdo#109279] / [i915#3359]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-tglb6/igt@kms_cursor_crc@pipe-c-cursor-512x170-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][35] -> [DMESG-WARN][36] ([i915#180]) +4 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_crc@pipe-d-cursor-max-size-sliding:
- shard-tglb: NOTRUN -> [SKIP][37] ([i915#3359])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-max-size-sliding.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [PASS][38] -> [FAIL][39] ([i915#79]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-apl: [PASS][40] -> [DMESG-WARN][41] ([i915#180] / [i915#1982])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: [PASS][42] -> [INCOMPLETE][43] ([i915#636])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-kbl2/igt@kms_flip@flip-vs-suspend@c-dp1.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-kbl2/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt:
- shard-skl: NOTRUN -> [SKIP][44] ([fdo#109271]) +42 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-skl4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt:
- shard-tglb: NOTRUN -> [SKIP][45] ([fdo#111825]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-tglb6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-move:
- shard-glk: NOTRUN -> [SKIP][46] ([fdo#109271])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-glk8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-skl: [PASS][47] -> [INCOMPLETE][48] ([i915#123] / [i915#146])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-skl7/igt@kms_frontbuffer_tracking@psr-suspend.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-skl7/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][49] -> [FAIL][50] ([i915#1188])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-iclb: [PASS][51] -> [INCOMPLETE][52] ([i915#1373] / [i915#2828])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-iclb5/igt@kms_hdr@bpc-switch-suspend.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-iclb3/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#533]) +2 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-apl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-apl: NOTRUN -> [FAIL][54] ([fdo#108145] / [i915#265])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-apl3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][55] -> [FAIL][56] ([fdo#108145] / [i915#265]) +3 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
- shard-apl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#658]) +3 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-apl8/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
- shard-skl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#658])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-skl5/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: [PASS][59] -> [SKIP][60] ([fdo#109441]) +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@kms_sysfs_edid_timing:
- shard-skl: NOTRUN -> [FAIL][61] ([IGT#2])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-skl4/igt@kms_sysfs_edid_timing.html
* igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame:
- shard-apl: NOTRUN -> [SKIP][62] ([fdo#109271]) +134 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-apl6/igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame.html
* igt@sysfs_clients@fair-1:
- shard-apl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#2994]) +2 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-apl1/igt@sysfs_clients@fair-1.html
* igt@sysfs_clients@split-10:
- shard-skl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#2994])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-skl5/igt@sysfs_clients@split-10.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-iclb: [DMESG-WARN][65] ([i915#2867]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-iclb1/igt@gem_ctx_isolation@preservation-s3@vecs0.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-iclb5/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][67] ([i915#2842]) -> [PASS][68] +3 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-tglb8/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [FAIL][69] ([i915#2842]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-glk7/igt@gem_exec_fair@basic-throttle@rcs0.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_mmap_gtt@big-bo-tiledy:
- shard-skl: [DMESG-WARN][71] ([i915#1982]) -> [PASS][72] +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-skl3/igt@gem_mmap_gtt@big-bo-tiledy.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-skl3/igt@gem_mmap_gtt@big-bo-tiledy.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- shard-glk: [DMESG-WARN][73] ([i915#118] / [i915#95]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-glk2/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-glk3/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [INCOMPLETE][75] ([i915#180]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-suspend@a-edp1:
- shard-skl: [INCOMPLETE][77] ([i915#198]) -> [PASS][78] +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-skl5/igt@kms_flip@flip-vs-suspend@a-edp1.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-skl6/igt@kms_flip@flip-vs-suspend@a-edp1.html
* igt@kms_flip@flip-vs-suspend@b-dp1:
- shard-apl: [DMESG-WARN][79] ([i915#180]) -> [PASS][80] +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-apl2/igt@kms_flip@flip-vs-suspend@b-dp1.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-apl8/igt@kms_flip@flip-vs-suspend@b-dp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [FAIL][81] ([i915#2122]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-skl4/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile:
- shard-iclb: [SKIP][83] -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][85] ([i915#1188]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-skl7/igt@kms_hdr@bpc-switch-suspend.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-kbl: [DMESG-WARN][87] ([i915#180]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][89] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-iclb3/igt@kms_psr2_su@frontbuffer.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [SKIP][91] ([fdo#109441]) -> [PASS][92] +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-iclb3/igt@kms_psr@psr2_suspend.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-iclb2/igt@kms_psr@psr2_suspend.html
* igt@kms_vblank@pipe-c-wait-forked-busy-hang:
- shard-tglb: [INCOMPLETE][93] -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-tglb7/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-tglb6/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html
* igt@perf@buffer-fill:
- shard-skl: [FAIL][95] -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-skl1/igt@perf@buffer-fill.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-skl10/igt@perf@buffer-fill.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][97] ([i915#2684]) -> [FAIL][98] ([i915#2680])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-iclb5/igt@i915_pm_rc6_residency@rc6-idle.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-iclb3/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-iclb: [SKIP][99] ([i915#2920]) -> [SKIP][100] ([i915#658]) +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-iclb6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][101], [FAIL][102], [FAIL][103], [FAIL][104], [FAIL][105]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#602]) -> ([FAIL][106], [FAIL][107], [FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111], [FAIL][112], [FAIL][113]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#602])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-kbl3/igt@runner@aborted.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-kbl6/igt@runner@aborted.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-kbl3/igt@runner@aborted.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-kbl6/igt@runner@aborted.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-kbl3/igt@runner@aborted.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-kbl3/igt@runner@aborted.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-kbl3/igt@runner@aborted.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-kbl3/igt@runner@aborted.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-kbl4/igt@runner@aborted.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-kbl3/igt@runner@aborted.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-kbl4/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-kbl3/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-kbl4/igt@runner@aborted.html
- shard-apl: ([FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121]) ([i915#1610] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-apl2/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-apl2/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-apl7/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10551/shard-apl8/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-apl8/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-apl8/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-apl2/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/shard-apl3/igt@runner@aborted.html
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1373]: https://gitlab.freedesktop.org/drm/intel/issues/1373
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2481]: https://gitlab.freedesktop.org/drm/intel/issues/2481
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2680]: https://gitlab.freedesktop.org/drm/intel/issues/2680
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724
[i915#2828]: https://gitlab.freedesktop.org/drm/intel/issues/2828
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3648]: https://gitlab.freedesktop.org/drm/intel/issues/3648
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3722]: https://gitlab.freedesktop.org/drm/intel/issues/3722
[i915#3777]: https://gitlab.freedesktop.org/drm/intel/issues/3777
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#602]: https://gitlab.freedesktop.org/drm/intel/issues/602
[i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 10)
------------------------------
Missing (1): shard-rkl
Build changes
-------------
* Linux: CI_DRM_10551 -> Patchwork_20963
CI-20190529: 20190529
CI_DRM_10551: 2b58e5151c7043a45a02238d63f7e17cf5cad46a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6197: 40888f97a6ad219f4ed48a1830d0ef3c9617d006 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20963: bc448a9d147ac1f59962f69c2e22ccc012f93256 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20963/index.html
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