* [Intel-gfx] [PATCH i-g-t 0/9] small BAR uapi bits
@ 2022-05-25 18:36 Matthew Auld
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 1/9] lib/i915_drm_local: Add I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS Matthew Auld
` (8 more replies)
0 siblings, 9 replies; 11+ messages in thread
From: Matthew Auld @ 2022-05-25 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: intel-gfx
--
2.34.3
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH i-g-t 1/9] lib/i915_drm_local: Add I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS
2022-05-25 18:36 [Intel-gfx] [PATCH i-g-t 0/9] small BAR uapi bits Matthew Auld
@ 2022-05-25 18:36 ` Matthew Auld
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 2/9] lib/i915: wire up optional flags for gem_create_ext Matthew Auld
` (7 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Matthew Auld @ 2022-05-25 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
For now dump into i915_drm_local.h. Once the uapi on the kernel side is
merged, and is part of drm-next, we can sync the kernel headers and
remove this.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
lib/i915/i915_drm_local.h | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/lib/i915/i915_drm_local.h b/lib/i915/i915_drm_local.h
index 9a2273c4..ac35abf6 100644
--- a/lib/i915/i915_drm_local.h
+++ b/lib/i915/i915_drm_local.h
@@ -23,6 +23,27 @@ extern "C" {
#define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6
+/*
+ * Signal to the kernel that the object will need to be accessed via
+ * the CPU.
+ *
+ * Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only
+ * strictly required on platforms where only some of the device memory
+ * is directly visible or mappable through the CPU, like on DG2+.
+ *
+ * One of the placements MUST also be I915_MEMORY_CLASS_SYSTEM, to
+ * ensure we can always spill the allocation to system memory, if we
+ * can't place the object in the mappable part of
+ * I915_MEMORY_CLASS_DEVICE.
+ *
+ * Without this hint, the kernel will assume that non-mappable
+ * I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the
+ * kernel can still migrate the object to the mappable part, as a last
+ * resort, if userspace ever CPU faults this object, but this might be
+ * expensive, and so ideally should be avoided.
+ */
+#define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0)
+
#if defined(__cplusplus)
}
#endif
--
2.34.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH i-g-t 2/9] lib/i915: wire up optional flags for gem_create_ext
2022-05-25 18:36 [Intel-gfx] [PATCH i-g-t 0/9] small BAR uapi bits Matthew Auld
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 1/9] lib/i915_drm_local: Add I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS Matthew Auld
@ 2022-05-25 18:36 ` Matthew Auld
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 3/9] tests/i915/gem_create: exercise NEEDS_CPU_ACCESS Matthew Auld
` (6 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Matthew Auld @ 2022-05-25 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
For now limit to direct callers.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
lib/i915/gem_create.c | 9 ++++++---
lib/i915/gem_create.h | 5 +++--
lib/i915/intel_memory_region.c | 2 +-
tests/i915/gem_create.c | 24 ++++++++++++------------
tests/i915/gem_pxp.c | 2 +-
5 files changed, 23 insertions(+), 19 deletions(-)
diff --git a/lib/i915/gem_create.c b/lib/i915/gem_create.c
index 605c4513..1f9b7fcc 100644
--- a/lib/i915/gem_create.c
+++ b/lib/i915/gem_create.c
@@ -61,11 +61,12 @@ uint32_t gem_create(int fd, uint64_t size)
return handle;
}
-int __gem_create_ext(int fd, uint64_t *size, uint32_t *handle,
+int __gem_create_ext(int fd, uint64_t *size, uint32_t flags, uint32_t *handle,
struct i915_user_extension *ext)
{
struct drm_i915_gem_create_ext create = {
.size = *size,
+ .flags = flags,
.extensions = to_user_pointer(ext),
};
int err = 0;
@@ -86,6 +87,7 @@ int __gem_create_ext(int fd, uint64_t *size, uint32_t *handle,
* gem_create_ext:
* @fd: open i915 drm file descriptor
* @size: desired size of the buffer
+ * @flags: optional flags
* @ext: optional extensions chain
*
* This wraps the GEM_CREATE_EXT ioctl, which allocates a new gem buffer object
@@ -93,11 +95,12 @@ int __gem_create_ext(int fd, uint64_t *size, uint32_t *handle,
*
* Returns: The file-private handle of the created buffer object
*/
-uint32_t gem_create_ext(int fd, uint64_t size, struct i915_user_extension *ext)
+uint32_t gem_create_ext(int fd, uint64_t size, uint32_t flags,
+ struct i915_user_extension *ext)
{
uint32_t handle;
- igt_assert_eq(__gem_create_ext(fd, &size, &handle, ext), 0);
+ igt_assert_eq(__gem_create_ext(fd, &size, flags, &handle, ext), 0);
return handle;
}
diff --git a/lib/i915/gem_create.h b/lib/i915/gem_create.h
index c32a815d..47a9a16d 100644
--- a/lib/i915/gem_create.h
+++ b/lib/i915/gem_create.h
@@ -12,9 +12,10 @@
int __gem_create(int fd, uint64_t *size, uint32_t *handle);
uint32_t gem_create(int fd, uint64_t size);
-int __gem_create_ext(int fd, uint64_t *size, uint32_t *handle,
+int __gem_create_ext(int fd, uint64_t *size, uint32_t flags, uint32_t *handle,
struct i915_user_extension *ext);
-uint32_t gem_create_ext(int fd, uint64_t size, struct i915_user_extension *ext);
+uint32_t gem_create_ext(int fd, uint64_t size, uint32_t flags,
+ struct i915_user_extension *ext);
void gem_pool_init(void);
void gem_pool_dump(void);
diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c
index 6bf6aab1..f0589e98 100644
--- a/lib/i915/intel_memory_region.c
+++ b/lib/i915/intel_memory_region.c
@@ -208,7 +208,7 @@ int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size,
};
int ret;
- ret = __gem_create_ext(fd, size, handle, &ext_regions.base);
+ ret = __gem_create_ext(fd, size, 0, handle, &ext_regions.base);
/*
* Provide fallback for stable kernels if region passed in the array
diff --git a/tests/i915/gem_create.c b/tests/i915/gem_create.c
index 31fd6526..f8ae7804 100644
--- a/tests/i915/gem_create.c
+++ b/tests/i915/gem_create.c
@@ -330,38 +330,38 @@ static void create_ext_placement_sanity_check(int fd)
* behaviour.
*/
size = PAGE_SIZE;
- igt_assert_eq(__gem_create_ext(fd, &size, &handle, 0), 0);
+ igt_assert_eq(__gem_create_ext(fd, &size, 0, &handle, 0), 0);
gem_close(fd, handle);
/* Try some uncreative invalid combinations */
setparam_region.regions = to_user_pointer(®ion_smem);
setparam_region.num_regions = 0;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
setparam_region.regions = to_user_pointer(®ion_smem);
setparam_region.num_regions = regions->num_regions + 1;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
setparam_region.regions = to_user_pointer(®ion_smem);
setparam_region.num_regions = -1;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
setparam_region.regions = to_user_pointer(®ion_invalid);
setparam_region.num_regions = 1;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
setparam_region.regions = to_user_pointer(®ion_invalid);
setparam_region.num_regions = 0;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
uregions = calloc(regions->num_regions + 1, sizeof(uint32_t));
@@ -372,7 +372,7 @@ static void create_ext_placement_sanity_check(int fd)
setparam_region.regions = to_user_pointer(uregions);
setparam_region.num_regions = regions->num_regions + 1;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
if (regions->num_regions > 1) {
@@ -385,7 +385,7 @@ static void create_ext_placement_sanity_check(int fd)
setparam_region.regions = to_user_pointer(dups);
setparam_region.num_regions = 2;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
}
}
@@ -395,7 +395,7 @@ static void create_ext_placement_sanity_check(int fd)
setparam_region.regions = to_user_pointer(uregions);
setparam_region.num_regions = regions->num_regions;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
free(uregions);
@@ -411,7 +411,7 @@ static void create_ext_placement_sanity_check(int fd)
to_user_pointer(&setparam_region_next);
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
setparam_region.base.next_extension = 0;
}
@@ -443,7 +443,7 @@ static void create_ext_placement_all(int fd)
setparam_region.num_regions = regions->num_regions;
size = PAGE_SIZE;
- igt_assert_eq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_eq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
gem_close(fd, handle);
free(uregions);
@@ -472,7 +472,7 @@ static void create_ext_placement_each(int fd)
setparam_region.num_regions = 1;
size = PAGE_SIZE;
- igt_assert_eq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_eq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
gem_close(fd, handle);
}
diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 5f269bab..65618556 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -40,7 +40,7 @@ static int create_bo_ext(int i915, uint32_t size, bool protected_is_true, uint32
ext = &protected_ext.base;
*bo_out = 0;
- ret = __gem_create_ext(i915, &size64, bo_out, ext);
+ ret = __gem_create_ext(i915, &size64, 0, bo_out, ext);
return ret;
}
--
2.34.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH i-g-t 3/9] tests/i915/gem_create: exercise NEEDS_CPU_ACCESS
2022-05-25 18:36 [Intel-gfx] [PATCH i-g-t 0/9] small BAR uapi bits Matthew Auld
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 1/9] lib/i915_drm_local: Add I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS Matthew Auld
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 2/9] lib/i915: wire up optional flags for gem_create_ext Matthew Auld
@ 2022-05-25 18:36 ` Matthew Auld
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 4/9] lib/i915: add gem_create_with_cpu_access_in_memory_regions Matthew Auld
` (5 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Matthew Auld @ 2022-05-25 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
Add some basic tests for this new flag.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
tests/i915/gem_create.c | 309 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 308 insertions(+), 1 deletion(-)
diff --git a/tests/i915/gem_create.c b/tests/i915/gem_create.c
index f8ae7804..5cfbd611 100644
--- a/tests/i915/gem_create.c
+++ b/tests/i915/gem_create.c
@@ -43,6 +43,8 @@
#include <getopt.h>
#include <pthread.h>
#include <stdatomic.h>
+#include <setjmp.h>
+#include <signal.h>
#include "drm.h"
#include "drmtest.h"
@@ -317,8 +319,8 @@ static void create_ext_placement_sanity_check(int fd)
.memory_class = -1,
.memory_instance = -1,
};
+ uint32_t handle, create_ext_supported_flags;
uint64_t size;
- uint32_t handle;
int i;
regions = gem_get_query_memory_regions(fd);
@@ -334,6 +336,11 @@ static void create_ext_placement_sanity_check(int fd)
gem_close(fd, handle);
/* Try some uncreative invalid combinations */
+ create_ext_supported_flags =
+ I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS;
+ igt_assert_neq(__gem_create_ext(fd, &size, ~create_ext_supported_flags,
+ &handle, 0), 0);
+
setparam_region.regions = to_user_pointer(®ion_smem);
setparam_region.num_regions = 0;
size = PAGE_SIZE;
@@ -480,6 +487,295 @@ static void create_ext_placement_each(int fd)
free(regions);
}
+static bool supports_needs_cpu_access(int fd)
+{
+ struct drm_i915_gem_memory_class_instance regions[] = {
+ { I915_MEMORY_CLASS_DEVICE, },
+ { I915_MEMORY_CLASS_SYSTEM, },
+ };
+ struct drm_i915_gem_create_ext_memory_regions setparam_region = {
+ .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS },
+ .regions = to_user_pointer(®ions),
+ .num_regions = ARRAY_SIZE(regions),
+ };
+ uint64_t size = PAGE_SIZE;
+ uint32_t handle;
+ int ret;
+
+ ret = __gem_create_ext(fd, &size,
+ I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS,
+ &handle, &setparam_region.base);
+ if (!ret) {
+ gem_close(fd, handle);
+ igt_assert(gem_has_lmem(fd)); /* Should be dgpu only */
+ }
+
+ return ret == 0;
+}
+
+static uint32_t batch_create_size(int fd, uint64_t size)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t handle;
+
+ handle = gem_create(fd, size);
+ gem_write(fd, handle, 0, &bbe, sizeof(bbe));
+
+ return handle;
+}
+
+static int upload(int fd, uint32_t handle)
+{
+ struct drm_i915_gem_exec_object2 exec[2] = {};
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(&exec),
+ .buffer_count = 2,
+ };
+
+ /*
+ * To be reasonably sure that we are not being swindled, let's make
+ * sure to 'touch' the pages from the GPU first to ensure the object is
+ * for sure placed in one of requested regions.
+ */
+ exec[0].handle = handle;
+ exec[1].handle = batch_create_size(fd, PAGE_SIZE);
+
+ return __gem_execbuf(fd, &execbuf);
+}
+
+static int alloc_lmem(int fd, uint32_t *handle,
+ struct drm_i915_gem_memory_class_instance ci,
+ uint64_t size, bool cpu_access, bool do_upload)
+{
+ struct drm_i915_gem_memory_class_instance regions[] = {
+ ci, { I915_MEMORY_CLASS_SYSTEM, },
+ };
+ struct drm_i915_gem_create_ext_memory_regions setparam_region = {
+ .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS },
+ .regions = to_user_pointer(®ions),
+ };
+ uint32_t flags;
+
+ igt_assert_eq(ci.memory_class, I915_MEMORY_CLASS_DEVICE);
+
+ flags = 0;
+ setparam_region.num_regions = 1;
+ if (cpu_access) {
+ flags = I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS,
+ setparam_region.num_regions = 2;
+ }
+
+ *handle = gem_create_ext(fd, size, flags, &setparam_region.base);
+
+ if (do_upload)
+ return upload(fd, *handle);
+
+ return 0;
+}
+
+static void create_ext_cpu_access_sanity_check(int fd)
+{
+ struct drm_i915_gem_create_ext_memory_regions setparam_region = {
+ .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS },
+ };
+ struct drm_i915_query_memory_regions *regions;
+ uint64_t size = PAGE_SIZE;
+ uint32_t handle;
+ int i;
+
+ /*
+ * The ABI is that FLAG_NEEDS_CPU_ACCESS can only be applied to LMEM +
+ * SMEM objects. Make sure the kernel follows that, while also checking
+ * the basic CPU faulting behavour.
+ */
+
+ /* Implicit placement; should fail */
+ igt_assert_eq(__gem_create_ext(fd, &size,
+ I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS,
+ &handle, NULL), -EINVAL);
+
+ regions = gem_get_query_memory_regions(fd);
+ igt_assert(regions);
+ igt_assert(regions->num_regions);
+
+ for (i = 0; i < regions->num_regions; i++) {
+ struct drm_i915_gem_memory_class_instance ci_regions[2] = {
+ regions->regions[i].region,
+ { I915_MEMORY_CLASS_SYSTEM, },
+ };
+ uint32_t *ptr;
+
+ setparam_region.regions = to_user_pointer(ci_regions);
+ setparam_region.num_regions = 1;
+
+ /* Single explicit placement; should fail */
+ igt_assert_eq(__gem_create_ext(fd, &size,
+ I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS,
+ &handle, &setparam_region.base),
+ -EINVAL);
+
+ if (ci_regions[0].memory_class == I915_MEMORY_CLASS_SYSTEM)
+ continue;
+
+ /*
+ * Now combine with system memory; should pass. We should also
+ * be able to fault it.
+ */
+ setparam_region.num_regions = 2;
+ igt_assert_eq(__gem_create_ext(fd, &size,
+ I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS,
+ &handle, &setparam_region.base),
+ 0);
+ upload(fd, handle);
+ ptr = gem_mmap_offset__fixed(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+ ptr[0] = 0xdeadbeaf;
+ gem_close(fd, handle);
+
+ /*
+ * It should also work just fine without the flag, where in the
+ * worst case we need to migrate it when faulting it.
+ */
+ igt_assert_eq(__gem_create_ext(fd, &size,
+ 0,
+ &handle, &setparam_region.base),
+ 0);
+ upload(fd, handle);
+ ptr = gem_mmap_offset__fixed(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+ ptr[0] = 0xdeadbeaf;
+ gem_close(fd, handle);
+ }
+
+ free(regions);
+}
+
+static jmp_buf jmp;
+
+__noreturn static void sigtrap(int sig)
+{
+ siglongjmp(jmp, sig);
+}
+
+static void trap_sigbus(uint32_t *ptr)
+{
+ sighandler_t old_sigbus;
+
+ old_sigbus = signal(SIGBUS, sigtrap);
+ switch (sigsetjmp(jmp, SIGBUS)) {
+ case SIGBUS:
+ break;
+ case 0:
+ *ptr = 0xdeadbeaf;
+ default:
+ igt_assert(!"reached");
+ break;
+ }
+ signal(SIGBUS, old_sigbus);
+}
+
+/**
+ * XXX: Remove this once we can safely sync the uapi header with the kernel.
+ * Should be source compatible either way though.
+ */
+#define probed_cpu_visible_size rsvd1[0]
+static void create_ext_cpu_access_big(int fd)
+{
+ struct drm_i915_query_memory_regions *regions;
+ int i;
+
+ /*
+ * Sanity check that we can still CPU map an overly large object, even
+ * if it happens to be larger the CPU visible portion of LMEM. Also
+ * check that an overly large allocation, which can't be spilled into
+ * system memory does indeed fail.
+ */
+
+ regions = gem_get_query_memory_regions(fd);
+ igt_assert(regions);
+ igt_assert(regions->num_regions);
+
+ for (i = 0; i < regions->num_regions; i++) {
+ struct drm_i915_memory_region_info qmr = regions->regions[i];
+ struct drm_i915_gem_memory_class_instance ci = qmr.region;
+ uint64_t size, visible_size, lmem_size;
+ uint32_t handle;
+ uint32_t *ptr;
+
+ if (ci.memory_class == I915_MEMORY_CLASS_SYSTEM)
+ continue;
+
+ lmem_size = qmr.probed_size;
+ visible_size = qmr.probed_cpu_visible_size;
+ igt_assert_neq(visible_size, 0);
+
+ if (visible_size <= (0.70 * lmem_size)) {
+ /*
+ * Too big. We should still be able to allocate it just
+ * fine, but faulting should result in tears.
+ */
+ size = visible_size;
+ igt_assert_eq(alloc_lmem(fd, &handle, ci, size, false, true), 0);
+ ptr = gem_mmap_offset__fixed(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+ trap_sigbus(ptr);
+ gem_close(fd, handle);
+
+ /*
+ * Too big again, but this time we can spill to system
+ * memory when faulting the object.
+ */
+ size = visible_size;
+ igt_assert_eq(alloc_lmem(fd, &handle, ci, size, true, true), 0);
+ ptr = gem_mmap_offset__fixed(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+ ptr[0] = 0xdeadbeaf;
+ gem_close(fd, handle);
+
+ /*
+ * Let's also move the upload to after faulting the
+ * pages. The current behaviour is that the pages are
+ * only allocated in device memory when initially
+ * touched by the GPU. With this in mind we should also
+ * make sure that the pages are indeed migrated, as
+ * expected.
+ */
+ size = visible_size;
+ igt_assert_eq(alloc_lmem(fd, &handle, ci, size, false, false), 0);
+ ptr = gem_mmap_offset__fixed(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+ ptr[0] = 0xdeadbeaf; /* temp system memory */
+ igt_assert_eq(upload(fd, handle), 0);
+ trap_sigbus(ptr); /* non-mappable device memory */
+ gem_close(fd, handle);
+ }
+
+ /*
+ * Should fit. We likely need to migrate to the mappable portion
+ * on fault though, if this device has a small BAR, given how
+ * large the initial allocation is.
+ */
+ size = visible_size >> 1;
+ igt_assert_eq(alloc_lmem(fd, &handle, ci, size, false, true), 0);
+ ptr = gem_mmap_offset__fixed(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+ ptr[0] = 0xdeadbeaf;
+ gem_close(fd, handle);
+
+ /*
+ * And then with the CPU_ACCESS flag enabled; should also be no
+ * surprises here.
+ */
+ igt_assert_eq(alloc_lmem(fd, &handle, ci, size, true, true), 0);
+ ptr = gem_mmap_offset__fixed(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+ ptr[0] = 0xdeadbeaf;
+ gem_close(fd, handle);
+ }
+
+ free(regions);
+}
+
igt_main
{
int fd = -1;
@@ -531,4 +827,15 @@ igt_main
igt_subtest("create-ext-placement-all")
create_ext_placement_all(fd);
+ igt_describe("Verify the basic functionally and expected ABI contract around I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS");
+ igt_subtest("create-ext-cpu-access-sanity-check") {
+ igt_require(supports_needs_cpu_access(fd));
+ create_ext_cpu_access_sanity_check(fd);
+ }
+
+ igt_describe("Verify the extreme cases with very large objects and I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS");
+ igt_subtest("create-ext-cpu-access-big") {
+ igt_require(supports_needs_cpu_access(fd));
+ create_ext_cpu_access_big(fd);
+ }
}
--
2.34.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH i-g-t 4/9] lib/i915: add gem_create_with_cpu_access_in_memory_regions
2022-05-25 18:36 [Intel-gfx] [PATCH i-g-t 0/9] small BAR uapi bits Matthew Auld
` (2 preceding siblings ...)
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 3/9] tests/i915/gem_create: exercise NEEDS_CPU_ACCESS Matthew Auld
@ 2022-05-25 18:36 ` Matthew Auld
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 5/9] tests/i915/query: sanity check the probed_cpu_visible_size Matthew Auld
` (4 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Matthew Auld @ 2022-05-25 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
Most users shouldn't care about such an interface, but where required,
this should be useful to aid in setting NEEDS_CPU_ACCESS for a given BO.
Underneath we try to smooth over needing to provide an explicit SMEM
region, or if this is SMEM-only, we don't want the kernel to throw an
error.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
lib/i915/intel_memory_region.c | 10 +++++---
lib/i915/intel_memory_region.h | 46 +++++++++++++++++++++++++++++++---
tests/i915/gem_eio.c | 1 +
tests/i915/gem_lmem_swapping.c | 2 +-
tests/i915/i915_pm_rpm.c | 6 ++---
5 files changed, 53 insertions(+), 12 deletions(-)
diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c
index f0589e98..da81650d 100644
--- a/lib/i915/intel_memory_region.c
+++ b/lib/i915/intel_memory_region.c
@@ -197,7 +197,7 @@ bool gem_has_lmem(int fd)
/* A version of gem_create_in_memory_region_list which can be allowed to
fail so that the object creation can be retried */
-int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size,
+int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size, uint32_t flags,
struct drm_i915_gem_memory_class_instance *mem_regions,
int num_regions)
{
@@ -208,7 +208,9 @@ int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size,
};
int ret;
- ret = __gem_create_ext(fd, size, 0, handle, &ext_regions.base);
+ ret = __gem_create_ext(fd, size, flags, handle, &ext_regions.base);
+ if (flags && ret == -EINVAL)
+ ret = __gem_create_ext(fd, size, 0, handle, &ext_regions.base);
/*
* Provide fallback for stable kernels if region passed in the array
@@ -231,12 +233,12 @@ int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size,
* @mem_regions: memory regions array (priority list)
* @num_regions: @mem_regions length
*/
-uint32_t gem_create_in_memory_region_list(int fd, uint64_t size,
+uint32_t gem_create_in_memory_region_list(int fd, uint64_t size, uint32_t flags,
struct drm_i915_gem_memory_class_instance *mem_regions,
int num_regions)
{
uint32_t handle;
- int ret = __gem_create_in_memory_region_list(fd, &handle, &size,
+ int ret = __gem_create_in_memory_region_list(fd, &handle, &size, flags,
mem_regions, num_regions);
igt_assert_eq(ret, 0);
return handle;
diff --git a/lib/i915/intel_memory_region.h b/lib/i915/intel_memory_region.h
index f9af9401..5aa163dd 100644
--- a/lib/i915/intel_memory_region.h
+++ b/lib/i915/intel_memory_region.h
@@ -21,6 +21,7 @@
* IN THE SOFTWARE.
*/
#include "igt_collection.h"
+#include "i915_drm_local.h"
#ifndef INTEL_MEMORY_REGION_H
#define INTEL_MEMORY_REGION_H
@@ -64,11 +65,11 @@ bool gem_has_lmem(int fd);
struct drm_i915_gem_memory_class_instance;
-int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size,
+int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size, uint32_t flags,
struct drm_i915_gem_memory_class_instance *mem_regions,
int num_regions);
-uint32_t gem_create_in_memory_region_list(int fd, uint64_t size,
+uint32_t gem_create_in_memory_region_list(int fd, uint64_t size, uint32_t flags,
struct drm_i915_gem_memory_class_instance *mem_regions,
int num_regions);
@@ -84,7 +85,7 @@ uint32_t gem_create_in_memory_region_list(int fd, uint64_t size,
arr_query__[i__].memory_class = MEMORY_TYPE_FROM_REGION(arr__[i__]); \
arr_query__[i__].memory_instance = MEMORY_INSTANCE_FROM_REGION(arr__[i__]); \
} \
- __gem_create_in_memory_region_list(fd, handle, size, arr_query__, ARRAY_SIZE(arr_query__)); \
+ __gem_create_in_memory_region_list(fd, handle, size, 0, arr_query__, ARRAY_SIZE(arr_query__)); \
})
#define gem_create_in_memory_regions(fd, size, regions...) ({ \
unsigned int arr__[] = { regions }; \
@@ -93,7 +94,44 @@ uint32_t gem_create_in_memory_region_list(int fd, uint64_t size,
arr_query__[i__].memory_class = MEMORY_TYPE_FROM_REGION(arr__[i__]); \
arr_query__[i__].memory_instance = MEMORY_INSTANCE_FROM_REGION(arr__[i__]); \
} \
- gem_create_in_memory_region_list(fd, size, arr_query__, ARRAY_SIZE(arr_query__)); \
+ gem_create_in_memory_region_list(fd, size, 0, arr_query__, ARRAY_SIZE(arr_query__)); \
+})
+
+/*
+ * Create an object that requires CPU access. This only becomes interesting on
+ * platforms that have a small BAR for LMEM CPU access. Without this the object
+ * might need to be migrated when CPU faulting the object, or if that is not
+ * possible we hit SIGBUS. Most users should be fine with this. If enabled the
+ * kernel will never allocate this object in the non-CPU visible portion of
+ * LMEM.
+ *
+ * Underneath this just enables the I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS
+ * flag, if we also have an LMEM placement. Also since the kernel requires SMEM
+ * as a potential placement, we automatically attach that as a possible
+ * placement, if not already provided. If this happens to be an SMEM-only
+ * placement then we don't supply the flag, and instead just treat as normal
+ * allocation.
+ */
+#define gem_create_with_cpu_access_in_memory_regions(fd, size, regions...) ({ \
+ unsigned int arr__[] = { regions }; \
+ struct drm_i915_gem_memory_class_instance arr_query__[ARRAY_SIZE(arr__) + 1]; \
+ int i__, arr_query_size__ = ARRAY_SIZE(arr__); \
+ uint32_t ext_flags__ = 0; \
+ bool ext_found_smem__ = false; \
+ for (i__ = 0; i__ < arr_query_size__; ++i__) { \
+ arr_query__[i__].memory_class = MEMORY_TYPE_FROM_REGION(arr__[i__]); \
+ if (arr_query__[i__].memory_class == I915_MEMORY_CLASS_DEVICE) \
+ ext_flags__ = I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS; \
+ else \
+ ext_found_smem__ = true; \
+ arr_query__[i__].memory_instance = MEMORY_INSTANCE_FROM_REGION(arr__[i__]); \
+ } \
+ if (ext_flags__ && !ext_found_smem__) { \
+ arr_query__[i__].memory_class = I915_MEMORY_CLASS_SYSTEM; \
+ arr_query__[i__].memory_instance = 0; \
+ arr_query_size__++; \
+ } \
+ gem_create_in_memory_region_list(fd, size, ext_flags__, arr_query__, arr_query_size__); \
})
struct igt_collection *
diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c
index 913a21f9..a9641cca 100644
--- a/tests/i915/gem_eio.c
+++ b/tests/i915/gem_eio.c
@@ -146,6 +146,7 @@ static void test_create_ext(int fd)
igt_assert_eq(__gem_create_in_memory_region_list(fd,
&handle,
&size,
+ 0,
&r->ci, 1),
0);
diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c
index 5d93e9da..bb9e69db 100644
--- a/tests/i915/gem_lmem_swapping.c
+++ b/tests/i915/gem_lmem_swapping.c
@@ -131,7 +131,7 @@ static uint32_t create_bo(int i915,
int ret;
retry:
- ret = __gem_create_in_memory_region_list(i915, &handle, size, region, 1);
+ ret = __gem_create_in_memory_region_list(i915, &handle, size, 0, region, 1);
if (do_oom_test && ret == -ENOMEM)
goto retry;
igt_assert_eq(ret, 0);
diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
index bf145b6c..e95875dc 100644
--- a/tests/i915/i915_pm_rpm.c
+++ b/tests/i915/i915_pm_rpm.c
@@ -1117,7 +1117,7 @@ static void gem_mmap_args(const struct mmap_offset *t,
/* Create, map and set data while the device is active. */
enable_one_screen_or_forcewake_get_and_wait(&ms_data);
- handle = gem_create_in_memory_region_list(drm_fd, buf_size, mem_regions, 1);
+ handle = gem_create_in_memory_region_list(drm_fd, buf_size, 0, mem_regions, 1);
gem_buf = __gem_mmap_offset(drm_fd, handle, 0, buf_size,
PROT_READ | PROT_WRITE, t->type);
@@ -1348,7 +1348,7 @@ static void gem_execbuf_subtest(struct drm_i915_gem_memory_class_instance *mem_r
/* Create and set data while the device is active. */
enable_one_screen_or_forcewake_get_and_wait(&ms_data);
- handle = gem_create_in_memory_region_list(drm_fd, dst_size, mem_regions, 1);
+ handle = gem_create_in_memory_region_list(drm_fd, dst_size, 0, mem_regions, 1);
cpu_buf = malloc(dst_size);
igt_assert(cpu_buf);
@@ -1453,7 +1453,7 @@ gem_execbuf_stress_subtest(int rounds, int wait_flags,
if (wait_flags & WAIT_PC8_RES)
handle = gem_create(drm_fd, batch_size);
else
- handle = gem_create_in_memory_region_list(drm_fd, batch_size, mem_regions, 1);
+ handle = gem_create_in_memory_region_list(drm_fd, batch_size, 0, mem_regions, 1);
gem_write(drm_fd, handle, 0, batch_buf, batch_size);
--
2.34.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH i-g-t 5/9] tests/i915/query: sanity check the probed_cpu_visible_size
2022-05-25 18:36 [Intel-gfx] [PATCH i-g-t 0/9] small BAR uapi bits Matthew Auld
` (3 preceding siblings ...)
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 4/9] lib/i915: add gem_create_with_cpu_access_in_memory_regions Matthew Auld
@ 2022-05-25 18:36 ` Matthew Auld
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 6/9] tests/i915/query: sanity check the unallocated tracking Matthew Auld
` (3 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Matthew Auld @ 2022-05-25 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
Add some basic sanity checks for this, like checking if this falls
within the probed_size. On older kernels the value reported here should
be zero.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
tests/i915/i915_query.c | 19 ++++++++++++++++---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index 246a979a..6b036241 100644
--- a/tests/i915/i915_query.c
+++ b/tests/i915/i915_query.c
@@ -513,6 +513,11 @@ static bool query_regions_supported(int fd)
return __i915_query_items(fd, &item, 1) == 0 && item.length > 0;
}
+/**
+ * XXX: Remove these once we can safely sync the uapi header with the kernel.
+ * Should be source compatible either way though.
+ */
+#define probed_cpu_visible_size rsvd1[0]
static void test_query_regions_garbage_items(int fd)
{
struct drm_i915_query_memory_regions *regions;
@@ -551,7 +556,10 @@ static void test_query_regions_garbage_items(int fd)
igt_assert_eq_u32(info.rsvd0, 0);
- for (j = 0; j < ARRAY_SIZE(info.rsvd1); j++)
+ /*
+ * rsvd1[0] : probed_cpu_visible_size
+ */
+ for (j = 1; j < ARRAY_SIZE(info.rsvd1); j++)
igt_assert_eq_u32(info.rsvd1[j], 0);
}
@@ -586,13 +594,18 @@ static void test_query_regions_sanity_check(int fd)
found_system = false;
for (i = 0; i < regions->num_regions; i++) {
- struct drm_i915_gem_memory_class_instance r1 =
- regions->regions[i].region;
+ struct drm_i915_memory_region_info info = regions->regions[i];
+ struct drm_i915_gem_memory_class_instance r1 = info.region;
int j;
if (r1.memory_class == I915_MEMORY_CLASS_SYSTEM) {
igt_assert_eq(r1.memory_instance, 0);
found_system = true;
+
+ igt_assert(info.probed_cpu_visible_size ==
+ info.probed_size);
+ } else {
+ igt_assert(info.probed_cpu_visible_size <= info.probed_size);
}
igt_assert(r1.memory_class == I915_MEMORY_CLASS_SYSTEM ||
--
2.34.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH i-g-t 6/9] tests/i915/query: sanity check the unallocated tracking
2022-05-25 18:36 [Intel-gfx] [PATCH i-g-t 0/9] small BAR uapi bits Matthew Auld
` (4 preceding siblings ...)
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 5/9] tests/i915/query: sanity check the probed_cpu_visible_size Matthew Auld
@ 2022-05-25 18:36 ` Matthew Auld
2022-05-25 18:37 ` [Intel-gfx] [PATCH i-g-t 7/9] lib/i915/intel_memory_region: plumb through the cpu_size Matthew Auld
` (2 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Matthew Auld @ 2022-05-25 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
tests/i915/i915_query.c | 273 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 272 insertions(+), 1 deletion(-)
diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index 6b036241..77cbd93e 100644
--- a/tests/i915/i915_query.c
+++ b/tests/i915/i915_query.c
@@ -22,6 +22,8 @@
*/
#include "igt.h"
+#include "i915/gem.h"
+#include "i915/gem_create.h"
#include <limits.h>
@@ -518,6 +520,36 @@ static bool query_regions_supported(int fd)
* Should be source compatible either way though.
*/
#define probed_cpu_visible_size rsvd1[0]
+#define unallocated_cpu_visible_size rsvd1[1]
+static bool query_regions_unallocated_supported(int fd)
+{
+ struct drm_i915_query_memory_regions *regions;
+ struct drm_i915_query_item item;
+ int i, ret = false;
+
+ memset(&item, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_MEMORY_REGIONS;
+ i915_query_items(fd, &item, 1);
+ igt_assert(item.length > 0);
+
+ regions = calloc(1, item.length);
+
+ item.data_ptr = to_user_pointer(regions);
+ i915_query_items(fd, &item, 1);
+
+ for (i = 0; i < regions->num_regions; i++) {
+ struct drm_i915_memory_region_info info = regions->regions[i];
+
+ if (info.unallocated_cpu_visible_size) {
+ ret = true;
+ break;
+ }
+ }
+
+ free(regions);
+ return ret;
+}
+
static void test_query_regions_garbage_items(int fd)
{
struct drm_i915_query_memory_regions *regions;
@@ -558,8 +590,9 @@ static void test_query_regions_garbage_items(int fd)
/*
* rsvd1[0] : probed_cpu_visible_size
+ * rsvd1[1] : unallocated_cpu_visible_size
*/
- for (j = 1; j < ARRAY_SIZE(info.rsvd1); j++)
+ for (j = 2; j < ARRAY_SIZE(info.rsvd1); j++)
igt_assert_eq_u32(info.rsvd1[j], 0);
}
@@ -572,6 +605,46 @@ static void test_query_regions_garbage_items(int fd)
free(regions);
}
+struct object_handle {
+ uint32_t handle;
+ struct igt_list_head link;
+};
+
+static uint32_t batch_create_size(int fd, uint64_t size)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t handle;
+
+ handle = gem_create(fd, size);
+ gem_write(fd, handle, 0, &bbe, sizeof(bbe));
+
+ return handle;
+}
+
+static void upload(int fd, struct igt_list_head *handles, uint32_t num_handles)
+{
+ struct drm_i915_gem_exec_object2 *exec;
+ struct drm_i915_gem_execbuffer2 execbuf = {};
+ struct object_handle *iter;
+ uint32_t i;
+
+ exec = calloc(num_handles + 1,
+ sizeof(struct drm_i915_gem_exec_object2));
+
+ i = 0;
+ igt_list_for_each_entry(iter, handles, link)
+ exec[i++].handle = iter->handle;
+
+ exec[i].handle = batch_create_size(fd, 4096);
+
+ execbuf.buffers_ptr = to_user_pointer(exec);
+ execbuf.buffer_count = num_handles + 1;
+
+ gem_execbuf(fd, &execbuf);
+ gem_close(fd, exec[i].handle);
+ free(exec);
+}
+
static void test_query_regions_sanity_check(int fd)
{
struct drm_i915_query_memory_regions *regions;
@@ -604,8 +677,19 @@ static void test_query_regions_sanity_check(int fd)
igt_assert(info.probed_cpu_visible_size ==
info.probed_size);
+ igt_assert(info.unallocated_size == info.probed_size);
+ igt_assert(info.unallocated_cpu_visible_size ==
+ info.unallocated_size);
} else {
igt_assert(info.probed_cpu_visible_size <= info.probed_size);
+ igt_assert(info.unallocated_size <= info.probed_size);
+ if (info.probed_cpu_visible_size < info.probed_size) {
+ igt_assert(info.unallocated_cpu_visible_size <
+ info.unallocated_size);
+ } else {
+ igt_assert(info.unallocated_cpu_visible_size ==
+ info.unallocated_size);
+ }
}
igt_assert(r1.memory_class == I915_MEMORY_CLASS_SYSTEM ||
@@ -622,6 +706,58 @@ static void test_query_regions_sanity_check(int fd)
igt_assert(!(r1.memory_class == r2.memory_class &&
r1.memory_instance == r2.memory_instance));
}
+
+ {
+ struct igt_list_head handles;
+ struct object_handle oh = {};
+
+ IGT_INIT_LIST_HEAD(&handles);
+
+ oh.handle =
+ gem_create_with_cpu_access_in_memory_regions
+ (fd, 4096,
+ INTEL_MEMORY_REGION_ID(r1.memory_class,
+ r1.memory_instance));
+ igt_list_add(&oh.link, &handles);
+ upload(fd, &handles, 1);
+
+ /*
+ * System wide metrics should be censored if we
+ * lack the correct permissions.
+ */
+ igt_fork(child, 1) {
+ igt_drop_root();
+
+ memset(regions, 0, item.length);
+ i915_query_items(fd, &item, 1);
+ info = regions->regions[i];
+
+ igt_assert(info.unallocated_cpu_visible_size ==
+ info.probed_cpu_visible_size);
+ igt_assert(info.unallocated_size ==
+ info.probed_size);
+ }
+
+ igt_waitchildren();
+
+ memset(regions, 0, item.length);
+ i915_query_items(fd, &item, 1);
+ info = regions->regions[i];
+
+ if (r1.memory_class == I915_MEMORY_CLASS_DEVICE) {
+ igt_assert(info.unallocated_cpu_visible_size <
+ info.probed_cpu_visible_size);
+ igt_assert(info.unallocated_size <
+ info.probed_size);
+ } else {
+ igt_assert(info.unallocated_cpu_visible_size ==
+ info.probed_cpu_visible_size);
+ igt_assert(info.unallocated_size ==
+ info.probed_size);
+ }
+
+ gem_close(fd, oh.handle);
+ }
}
/* All devices should at least have system memory */
@@ -630,6 +766,134 @@ static void test_query_regions_sanity_check(int fd)
free(regions);
}
+#define rounddown(x, y) (x - (x % y))
+#define SZ_64K (1ULL << 16)
+
+static void fill_unallocated(int fd, struct drm_i915_query_item *item, int idx,
+ bool cpu_access)
+{
+ struct drm_i915_memory_region_info new_info, old_info;
+ struct drm_i915_query_memory_regions *regions;
+ struct drm_i915_gem_memory_class_instance ci;
+ struct object_handle *iter, *tmp;
+ struct igt_list_head handles;
+ uint32_t num_handles;
+ uint64_t rem, total;
+ int id;
+
+ srand(time(NULL));
+
+ IGT_INIT_LIST_HEAD(&handles);
+
+ regions = (struct drm_i915_query_memory_regions *)item->data_ptr;
+ memset(regions, 0, item->length);
+ i915_query_items(fd, item, 1);
+ new_info = regions->regions[idx];
+ ci = new_info.region;
+
+ id = INTEL_MEMORY_REGION_ID(ci.memory_class, ci.memory_instance);
+
+ if (cpu_access)
+ rem = new_info.unallocated_cpu_visible_size / 4;
+ else
+ rem = new_info.unallocated_size / 4;
+
+ rem = rounddown(rem, SZ_64K);
+ igt_assert_neq(rem, 0);
+ num_handles = 0;
+ total = 0;
+ do {
+ struct object_handle *oh;
+ uint64_t size;
+
+ size = rand() % rem;
+ size = rounddown(size, SZ_64K);
+ size = max_t(uint64_t, size, SZ_64K);
+
+ oh = malloc(sizeof(struct object_handle));
+ if (cpu_access)
+ oh->handle = gem_create_with_cpu_access_in_memory_regions(fd, size, id);
+ else
+ oh->handle = gem_create_in_memory_region_list(fd, size, 0, &ci, 1);
+ igt_list_add(&oh->link, &handles);
+
+ num_handles++;
+ total += size;
+ rem -= size;
+ } while (rem);
+
+ upload(fd, &handles, num_handles);
+
+ old_info = new_info;
+ memset(regions, 0, item->length);
+ i915_query_items(fd, item, 1);
+ new_info = regions->regions[idx];
+
+ igt_assert_lte(new_info.unallocated_size,
+ new_info.probed_size - total);
+ igt_assert_lt(new_info.unallocated_size, old_info.unallocated_size);
+ if (new_info.probed_cpu_visible_size ==
+ new_info.probed_size) { /* full BAR */
+ igt_assert_eq(new_info.unallocated_cpu_visible_size,
+ new_info.unallocated_size);
+ } else if (cpu_access) {
+ igt_assert_lt(new_info.unallocated_cpu_visible_size,
+ old_info.unallocated_cpu_visible_size);
+ igt_assert_lte(new_info.unallocated_cpu_visible_size,
+ new_info.probed_cpu_visible_size - total);
+ }
+
+ igt_debug("fill completed with idx=%d, total=%luKiB, num_handles=%u\n",
+ idx, total >> 10, num_handles);
+
+ igt_list_for_each_entry_safe(iter, tmp, &handles, link) {
+ gem_close(fd, iter->handle);
+ free(iter);
+ }
+
+ igt_drop_caches_set(fd, DROP_ALL);
+
+ old_info = new_info;
+ memset(regions, 0, item->length);
+ i915_query_items(fd, item, 1);
+ new_info = regions->regions[idx];
+
+ igt_assert(new_info.unallocated_size >=
+ old_info.unallocated_size + total);
+ if (cpu_access)
+ igt_assert(new_info.unallocated_cpu_visible_size >=
+ old_info.unallocated_cpu_visible_size + total);
+}
+
+static void test_query_regions_unallocated(int fd)
+{
+ struct drm_i915_query_memory_regions *regions;
+ struct drm_i915_query_item item;
+ int i;
+
+ memset(&item, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_MEMORY_REGIONS;
+ i915_query_items(fd, &item, 1);
+ igt_assert(item.length > 0);
+
+ regions = calloc(1, item.length);
+
+ item.data_ptr = to_user_pointer(regions);
+ i915_query_items(fd, &item, 1);
+
+ igt_assert(regions->num_regions);
+
+ for (i = 0; i < regions->num_regions; i++) {
+ struct drm_i915_memory_region_info info = regions->regions[i];
+ struct drm_i915_gem_memory_class_instance ci = info.region;
+
+ if (ci.memory_class == I915_MEMORY_CLASS_DEVICE) {
+ fill_unallocated(fd, &item, i, true);
+ fill_unallocated(fd, &item, i, false);
+ }
+ }
+}
+
static bool query_engine_info_supported(int fd)
{
struct drm_i915_query_item item = {
@@ -987,6 +1251,13 @@ igt_main
test_query_regions_sanity_check(fd);
}
+ igt_describe("Sanity check the region unallocated tracking");
+ igt_subtest("query-regions-unallocated") {
+ igt_require(query_regions_supported(fd));
+ igt_require(query_regions_unallocated_supported(fd));
+ test_query_regions_unallocated(fd);
+ }
+
igt_subtest_group {
igt_fixture {
igt_require(query_engine_info_supported(fd));
--
2.34.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH i-g-t 7/9] lib/i915/intel_memory_region: plumb through the cpu_size
2022-05-25 18:36 [Intel-gfx] [PATCH i-g-t 0/9] small BAR uapi bits Matthew Auld
` (5 preceding siblings ...)
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 6/9] tests/i915/query: sanity check the unallocated tracking Matthew Auld
@ 2022-05-25 18:37 ` Matthew Auld
2022-05-25 18:37 ` [Intel-gfx] [PATCH i-g-t 8/9] tests/i915/capture: handle uapi changes Matthew Auld
2022-05-25 18:37 ` [Intel-gfx] [PATCH i-g-t 9/9] lib/i915: request CPU_ACCESS for fb objects Matthew Auld
8 siblings, 0 replies; 11+ messages in thread
From: Matthew Auld @ 2022-05-25 18:37 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
Will be useful later.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
lib/i915/intel_memory_region.c | 2 ++
lib/i915/intel_memory_region.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c
index da81650d..2dd4c156 100644
--- a/lib/i915/intel_memory_region.c
+++ b/lib/i915/intel_memory_region.c
@@ -956,6 +956,8 @@ struct gem_memory_region *__gem_get_memory_regions(int i915)
r->ci = info->regions[i].region;
r->size = info->regions[i].probed_size;
+ /* XXX: replace with probed_cpu_visible_size */
+ r->cpu_size = info->regions[i].rsvd1[0];
if (r->size == -1ull)
r->size = intel_get_avail_ram_mb() << 20;
diff --git a/lib/i915/intel_memory_region.h b/lib/i915/intel_memory_region.h
index 5aa163dd..8ee1ed9b 100644
--- a/lib/i915/intel_memory_region.h
+++ b/lib/i915/intel_memory_region.h
@@ -155,6 +155,7 @@ struct gem_memory_region {
struct drm_i915_gem_memory_class_instance ci;
uint64_t size;
+ uint64_t cpu_size;
};
struct igt_collection *
--
2.34.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH i-g-t 8/9] tests/i915/capture: handle uapi changes
2022-05-25 18:36 [Intel-gfx] [PATCH i-g-t 0/9] small BAR uapi bits Matthew Auld
` (6 preceding siblings ...)
2022-05-25 18:37 ` [Intel-gfx] [PATCH i-g-t 7/9] lib/i915/intel_memory_region: plumb through the cpu_size Matthew Auld
@ 2022-05-25 18:37 ` Matthew Auld
2022-05-25 18:37 ` [Intel-gfx] [PATCH i-g-t 9/9] lib/i915: request CPU_ACCESS for fb objects Matthew Auld
8 siblings, 0 replies; 11+ messages in thread
From: Matthew Auld @ 2022-05-25 18:37 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
We should mark the objects that need to be captured with
NEEDS_CPU_ACCESS to ensure we can capture them if they are allocated in
lmem. We also need to consider that capture only properly works on
non-recoverable context, for discrete platforms. We can now also expect
CPU invisible objects to be skipped, for now at least.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
tests/i915/gem_exec_capture.c | 143 ++++++++++++++++++++++++++++++++--
1 file changed, 135 insertions(+), 8 deletions(-)
diff --git a/tests/i915/gem_exec_capture.c b/tests/i915/gem_exec_capture.c
index 60f8df04..6ee6a155 100644
--- a/tests/i915/gem_exec_capture.c
+++ b/tests/i915/gem_exec_capture.c
@@ -268,13 +268,13 @@ static void __capture1(int fd, int dir, uint64_t ahnd, const intel_ctx_t *ctx,
saved_engine = configure_hangs(fd, e, ctx->id);
memset(obj, 0, sizeof(obj));
- obj[SCRATCH].handle = gem_create_in_memory_regions(fd, 4096, region);
+ obj[SCRATCH].handle = gem_create_with_cpu_access_in_memory_regions(fd, 4096, region);
obj[SCRATCH].flags = EXEC_OBJECT_WRITE;
obj[CAPTURE].handle = target;
obj[CAPTURE].flags = EXEC_OBJECT_CAPTURE;
obj[NOCAPTURE].handle = gem_create(fd, 4096);
- obj[BATCH].handle = gem_create_in_memory_regions(fd, 4096, region);
+ obj[BATCH].handle = gem_create_with_cpu_access_in_memory_regions(fd, 4096, region);
obj[BATCH].relocs_ptr = (uintptr_t)reloc;
obj[BATCH].relocation_count = !ahnd ? ARRAY_SIZE(reloc) : 0;
@@ -387,9 +387,9 @@ static void capture(int fd, int dir, const intel_ctx_t *ctx,
const struct intel_execution_engine2 *e, uint32_t region)
{
uint32_t handle;
- uint64_t ahnd, obj_size = 4096;
+ uint64_t ahnd, obj_size = 16 * 4096;
- igt_assert_eq(__gem_create_in_memory_regions(fd, &handle, &obj_size, region), 0);
+ handle = gem_create_with_cpu_access_in_memory_regions(fd, obj_size, region);
ahnd = get_reloc_ahnd(fd, ctx->id);
__capture1(fd, dir, ahnd, ctx, e, handle, obj_size, region);
@@ -415,7 +415,8 @@ static struct offset *
__captureN(int fd, int dir, uint64_t ahnd, const intel_ctx_t *ctx,
const struct intel_execution_engine2 *e,
unsigned int size, int count,
- unsigned int flags, int *_fence_out)
+ unsigned int flags, int *_fence_out, uint32_t region,
+ bool force_cpu_access)
#define INCREMENTAL 0x1
#define ASYNC 0x2
{
@@ -441,7 +442,10 @@ __captureN(int fd, int dir, uint64_t ahnd, const intel_ctx_t *ctx,
obj[0].flags = EXEC_OBJECT_WRITE | (ahnd ? EXEC_OBJECT_PINNED : 0);
for (i = 0; i < count; i++) {
- obj[i + 1].handle = gem_create(fd, size);
+ if (force_cpu_access)
+ obj[i + 1].handle = gem_create_with_cpu_access_in_memory_regions(fd, size, region);
+ else
+ obj[i + 1].handle = gem_create_in_memory_regions(fd, size, region);
obj[i + 1].offset = get_offset(ahnd, obj[i + 1].handle, size, 0);
obj[i + 1].flags =
EXEC_OBJECT_CAPTURE | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
@@ -595,6 +599,15 @@ static void many(int fd, int dir, uint64_t size, unsigned int flags)
struct gem_engine_properties saved_engine;
find_first_available_engine(fd, ctx, e, saved_engine);
+ if (gem_has_lmem(fd)) {
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = ctx->id,
+ .param = I915_CONTEXT_PARAM_RECOVERABLE,
+ .value = 0,
+ };
+
+ gem_context_set_param(fd, ¶m);
+ }
gtt = gem_aperture_size(fd) / size;
ram = (intel_get_avail_ram_mb() << 20) / size;
@@ -607,7 +620,8 @@ static void many(int fd, int dir, uint64_t size, unsigned int flags)
intel_require_memory(count, size, CHECK_RAM);
ahnd = get_reloc_ahnd(fd, ctx->id);
- offsets = __captureN(fd, dir, ahnd, ctx, e, size, count, flags, NULL);
+ offsets = __captureN(fd, dir, ahnd, ctx, e, size, count, flags, NULL,
+ REGION_SMEM, true);
blobs = check_error_state(dir, offsets, count, size, !!(flags & INCREMENTAL));
igt_info("Captured %lu %"PRId64"-blobs out of a total of %lu\n",
@@ -677,7 +691,8 @@ static void prioinv(int fd, int dir, const intel_ctx_t *ctx,
/* Reopen the allocator in the new process. */
ahnd = get_reloc_ahnd(fd, ctx2->id);
- free(__captureN(fd, dir, ahnd, ctx2, e, size, count, ASYNC, &fence_out));
+ free(__captureN(fd, dir, ahnd, ctx2, e, size, count, ASYNC,
+ &fence_out, REGION_SMEM, true));
put_ahnd(ahnd);
write(link[1], &fd, sizeof(fd)); /* wake the parent up */
@@ -720,6 +735,15 @@ static void userptr(int fd, int dir)
struct gem_engine_properties saved_engine;
find_first_available_engine(fd, ctx, e, saved_engine);
+ if (gem_has_lmem(fd)) {
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = ctx->id,
+ .param = I915_CONTEXT_PARAM_RECOVERABLE,
+ .value = 0,
+ };
+
+ gem_context_set_param(fd, ¶m);
+ }
igt_assert(posix_memalign(&ptr, obj_size, obj_size) == 0);
memset(ptr, 0, obj_size);
@@ -735,6 +759,84 @@ static void userptr(int fd, int dir)
gem_engine_properties_restore(fd, &saved_engine);
}
+static uint32_t batch_create_size(int fd, uint64_t size)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t handle;
+
+ handle = gem_create(fd, size);
+ gem_write(fd, handle, 0, &bbe, sizeof(bbe));
+
+ return handle;
+}
+
+static void capture_recoverable_discrete(int fd)
+{
+ struct drm_i915_gem_exec_object2 exec[2] = {};
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(&exec),
+ .buffer_count = 2,
+ };
+
+ /*
+ * I915_CONTEXT_PARAM_RECOVERABLE should be enabled by default. On
+ * discrete the kernel will only capture objects associated with the
+ * batch, if the context we is configured as non-recoverable.
+ */
+
+ exec[0].handle = gem_create(fd, 4096);
+ exec[0].flags = EXEC_OBJECT_CAPTURE;
+ exec[1].handle = batch_create_size(fd, 4096);
+
+ igt_assert_neq(__gem_execbuf(fd, &execbuf), 0);
+}
+
+static void capture_invisible(int fd, int dir, const intel_ctx_t *ctx,
+ struct gem_memory_region *mr)
+{
+ struct gem_engine_properties saved_engine;
+ const struct intel_execution_engine2 *e;
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = ctx->id,
+ .param = I915_CONTEXT_PARAM_RECOVERABLE,
+ .value = 0,
+ };
+ struct offset *offsets;
+ uint64_t ahnd;
+ char *error;
+
+ find_first_available_engine(fd, ctx, e, saved_engine);
+ gem_context_set_param(fd, ¶m);
+
+ ahnd = get_reloc_ahnd(fd, ctx->id);
+
+ igt_assert_eq(mr->ci.memory_class, I915_MEMORY_CLASS_DEVICE);
+
+ offsets = __captureN(fd, dir, ahnd, ctx, e, 1u << 16, 100, 0, NULL,
+ INTEL_MEMORY_REGION_ID(mr->ci.memory_class,
+ mr->ci.memory_instance),
+ false);
+
+ /*
+ * Make sure the error capture code doesn't crash-and-burn if it
+ * encounters an lmem object that can't be copied using the CPU. In such
+ * cases such objects will be skipped, otherwise we should see crashes
+ * here. Allocating a number of small objects should be enough to
+ * ensure that at least one or more end being allocated in the CPU
+ * invisible portion.
+ */
+
+ error = igt_sysfs_get(dir, "error");
+ igt_sysfs_set(dir, "error", "Begone!");
+ igt_assert(error);
+ igt_assert(errno != ENOMEM);
+
+ gem_engine_properties_restore(fd, &saved_engine);
+
+ free(offsets);
+ put_ahnd(ahnd);
+}
+
static bool has_capture(int fd)
{
drm_i915_getparam_t gp;
@@ -781,6 +883,15 @@ igt_main
gem_require_mmap_device_coherent(fd);
igt_require(has_capture(fd));
ctx = intel_ctx_create_all_physical(fd);
+ if (gem_has_lmem(fd)) {
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = ctx->id,
+ .param = I915_CONTEXT_PARAM_RECOVERABLE,
+ .value = 0,
+ };
+
+ gem_context_set_param(fd, ¶m);
+ }
igt_allow_hang(fd, ctx->id, HANG_ALLOW_CAPTURE | HANG_WANT_ENGINE_RESET);
dir = igt_sysfs_open(fd);
@@ -803,6 +914,22 @@ igt_main
}
}
+ igt_describe("Check that the kernel doesn't crash if the pages can't be copied from the CPU during error capture.");
+ igt_subtest_f("capture-invisible") {
+ igt_require(gem_has_lmem(fd));
+ for_each_memory_region(r, fd) {
+ igt_require(r->cpu_size && r->cpu_size < r->size);
+ igt_dynamic_f("%s", r->name)
+ capture_invisible(fd, dir, ctx, r);
+ }
+ }
+
+ igt_describe("Verify that the kernel rejects EXEC_OBJECT_CAPTURE with recoverable contexts.");
+ igt_subtest_f("capture-recoverable-discrete") {
+ igt_require(gem_has_lmem(fd));
+ capture_recoverable_discrete(fd);
+ }
+
igt_subtest_f("many-4K-zero") {
igt_require(gem_can_store_dword(fd, 0));
many(fd, dir, 1<<12, 0);
--
2.34.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH i-g-t 9/9] lib/i915: request CPU_ACCESS for fb objects
2022-05-25 18:36 [Intel-gfx] [PATCH i-g-t 0/9] small BAR uapi bits Matthew Auld
` (7 preceding siblings ...)
2022-05-25 18:37 ` [Intel-gfx] [PATCH i-g-t 8/9] tests/i915/capture: handle uapi changes Matthew Auld
@ 2022-05-25 18:37 ` Matthew Auld
2022-06-08 13:25 ` Das, Nirmoy
8 siblings, 1 reply; 11+ messages in thread
From: Matthew Auld @ 2022-05-25 18:37 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
kms_frontbuffer_tracking@basic falls over if the fb needs to be migrated
from non-mappable device memory, to the mappable part, due to being
temporarily pinned for scanout, when hitting the CPU fault handler,
which just gives us SIGBUS. If the device has a small BAR let's attempt
to use the mappable portion, if possible.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
lib/ioctl_wrappers.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 09eb3ce7..7713e78b 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -635,7 +635,8 @@ uint32_t gem_buffer_create_fb_obj(int fd, uint64_t size)
uint32_t handle;
if (gem_has_lmem(fd))
- handle = gem_create_in_memory_regions(fd, size, REGION_LMEM(0));
+ handle = gem_create_with_cpu_access_in_memory_regions(fd, size,
+ REGION_LMEM(0));
else
handle = gem_create(fd, size);
--
2.34.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t 9/9] lib/i915: request CPU_ACCESS for fb objects
2022-05-25 18:37 ` [Intel-gfx] [PATCH i-g-t 9/9] lib/i915: request CPU_ACCESS for fb objects Matthew Auld
@ 2022-06-08 13:25 ` Das, Nirmoy
0 siblings, 0 replies; 11+ messages in thread
From: Das, Nirmoy @ 2022-06-08 13:25 UTC (permalink / raw)
To: Matthew Auld, igt-dev; +Cc: Thomas Hellström, intel-gfx
Patch 6 is missing commit message, with that and the GitLab.Pipeline
warning fix the series LGTM
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
On 5/25/2022 8:37 PM, Matthew Auld wrote:
> kms_frontbuffer_tracking@basic falls over if the fb needs to be migrated
> from non-mappable device memory, to the mappable part, due to being
> temporarily pinned for scanout, when hitting the CPU fault handler,
> which just gives us SIGBUS. If the device has a small BAR let's attempt
> to use the mappable portion, if possible.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
> lib/ioctl_wrappers.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
> index 09eb3ce7..7713e78b 100644
> --- a/lib/ioctl_wrappers.c
> +++ b/lib/ioctl_wrappers.c
> @@ -635,7 +635,8 @@ uint32_t gem_buffer_create_fb_obj(int fd, uint64_t size)
> uint32_t handle;
>
> if (gem_has_lmem(fd))
> - handle = gem_create_in_memory_regions(fd, size, REGION_LMEM(0));
> + handle = gem_create_with_cpu_access_in_memory_regions(fd, size,
> + REGION_LMEM(0));
> else
> handle = gem_create(fd, size);
>
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2022-06-08 13:25 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
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2022-05-25 18:36 [Intel-gfx] [PATCH i-g-t 0/9] small BAR uapi bits Matthew Auld
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2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 2/9] lib/i915: wire up optional flags for gem_create_ext Matthew Auld
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 3/9] tests/i915/gem_create: exercise NEEDS_CPU_ACCESS Matthew Auld
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 4/9] lib/i915: add gem_create_with_cpu_access_in_memory_regions Matthew Auld
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 5/9] tests/i915/query: sanity check the probed_cpu_visible_size Matthew Auld
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 6/9] tests/i915/query: sanity check the unallocated tracking Matthew Auld
2022-05-25 18:37 ` [Intel-gfx] [PATCH i-g-t 7/9] lib/i915/intel_memory_region: plumb through the cpu_size Matthew Auld
2022-05-25 18:37 ` [Intel-gfx] [PATCH i-g-t 8/9] tests/i915/capture: handle uapi changes Matthew Auld
2022-05-25 18:37 ` [Intel-gfx] [PATCH i-g-t 9/9] lib/i915: request CPU_ACCESS for fb objects Matthew Auld
2022-06-08 13:25 ` Das, Nirmoy
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