* [Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend
@ 2022-06-10 0:32 Nerlige Ramappa, Umesh
2022-06-10 1:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend (rev2) Patchwork
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Nerlige Ramappa, Umesh @ 2022-06-10 0:32 UTC (permalink / raw)
To: intel-gfx
From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
For execlists backend, current implementation of Wa_22011802037 is to
stop the CS before doing a reset of the engine. This WA was further
extended to wait for any pending MI FORCE WAKEUPs before issuing a
reset. Add the extended steps in the execlist path of reset.
In addition, extend the WA to gen11.
v2: (Tvrtko)
- Clarify comments, commit message, fix typos
- Use IS_GRAPHICS_VER for gen 11/12 checks
v3: (Daneile)
- Drop changes to intel_ring_submission since WA does not apply to it
- Log an error if MSG IDLE is not defined for an engine
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Fixes: f6aa0d713c88 ("drm/i915: Add Wa_22011802037 force cs halt")
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine.h | 2 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 88 ++++++++++++++++++-
.../drm/i915/gt/intel_execlists_submission.c | 7 ++
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 81 ++---------------
5 files changed, 103 insertions(+), 79 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 1431f1e9dbee..04e435bce79b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -201,6 +201,8 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine);
int intel_engine_stop_cs(struct intel_engine_cs *engine);
void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
+void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine);
+
void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask);
u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f0acf8518a51..b3dc32fe6c51 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1375,10 +1375,10 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
/*
- * Wa_22011802037 : gen12, Prior to doing a reset, ensure CS is
+ * Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is
* stopped, set ring stop bit and prefetch disable bit to halt CS
*/
- if (GRAPHICS_VER(engine->i915) == 12)
+ if (IS_GRAPHICS_VER(engine->i915, 11, 12))
intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
_MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
@@ -1401,6 +1401,18 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine)
return -ENODEV;
ENGINE_TRACE(engine, "\n");
+ /*
+ * TODO: Find out why occasionally stopping the CS times out. Seen
+ * especially with gem_eio tests.
+ *
+ * Occasionally trying to stop the cs times out, but does not adversely
+ * affect functionality. The timeout is set as a config parameter that
+ * defaults to 100ms. In most cases the follow up operation is to wait
+ * for pending MI_FORCE_WAKES. The assumption is that this timeout is
+ * sufficient for any pending MI_FORCEWAKEs to complete. Once root
+ * caused, the caller must check and handle the return from this
+ * function.
+ */
if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
ENGINE_TRACE(engine,
"timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n",
@@ -1427,6 +1439,78 @@ void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
}
+static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
+{
+ static const i915_reg_t _reg[I915_NUM_ENGINES] = {
+ [RCS0] = MSG_IDLE_CS,
+ [BCS0] = MSG_IDLE_BCS,
+ [VCS0] = MSG_IDLE_VCS0,
+ [VCS1] = MSG_IDLE_VCS1,
+ [VCS2] = MSG_IDLE_VCS2,
+ [VCS3] = MSG_IDLE_VCS3,
+ [VCS4] = MSG_IDLE_VCS4,
+ [VCS5] = MSG_IDLE_VCS5,
+ [VCS6] = MSG_IDLE_VCS6,
+ [VCS7] = MSG_IDLE_VCS7,
+ [VECS0] = MSG_IDLE_VECS0,
+ [VECS1] = MSG_IDLE_VECS1,
+ [VECS2] = MSG_IDLE_VECS2,
+ [VECS3] = MSG_IDLE_VECS3,
+ [CCS0] = MSG_IDLE_CS,
+ [CCS1] = MSG_IDLE_CS,
+ [CCS2] = MSG_IDLE_CS,
+ [CCS3] = MSG_IDLE_CS,
+ };
+ u32 val;
+
+ if (!_reg[engine->id].reg) {
+ drm_err(&engine->i915->drm,
+ "MSG IDLE undefined for engine id %u\n", engine->id);
+ return 0;
+ }
+
+ val = intel_uncore_read(engine->uncore, _reg[engine->id]);
+
+ /* bits[29:25] & bits[13:9] >> shift */
+ return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
+}
+
+static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
+{
+ int ret;
+
+ /* Ensure GPM receives fw up/down after CS is stopped */
+ udelay(1);
+
+ /* Wait for forcewake request to complete in GPM */
+ ret = __intel_wait_for_register_fw(gt->uncore,
+ GEN9_PWRGT_DOMAIN_STATUS,
+ fw_mask, fw_mask, 5000, 0, NULL);
+
+ /* Ensure CS receives fw ack from GPM */
+ udelay(1);
+
+ if (ret)
+ GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);
+}
+
+/*
+ * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
+ * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
+ * pending status is indicated by bits[13:9] (masked by bits[29:25]) in the
+ * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
+ * are concerned only with the gt reset here, we use a logical OR of pending
+ * forcewakeups from all reset domains and then wait for them to complete by
+ * querying PWRGT_DOMAIN_STATUS.
+ */
+void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine)
+{
+ u32 fw_pending = __cs_pending_mi_force_wakes(engine);
+
+ if (fw_pending)
+ __gpm_wait_for_fw_complete(engine->gt, fw_pending);
+}
+
static u32
read_subslice_reg(const struct intel_engine_cs *engine,
int slice, int subslice, i915_reg_t reg)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index a4510b5c0c3d..19beeb3bb99d 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2968,6 +2968,13 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
ring_set_paused(engine, 1);
intel_engine_stop_cs(engine);
+ /*
+ * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
+ * to wait for any pending mi force wakeups
+ */
+ if (IS_GRAPHICS_VER(engine->i915, 11, 12))
+ intel_engine_wait_for_pending_mi_fw(engine);
+
engine->execlists.reset_ccid = active_ccid(engine);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 35887cb53201..2706a8c65090 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -310,8 +310,8 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
if (IS_DG2(gt->i915))
flags |= GUC_WA_DUAL_QUEUE;
- /* Wa_22011802037: graphics version 12 */
- if (GRAPHICS_VER(gt->i915) == 12)
+ /* Wa_22011802037: graphics version 11/12 */
+ if (IS_GRAPHICS_VER(gt->i915, 11, 12))
flags |= GUC_WA_PRE_PARSER;
/* Wa_16011777198:dg2 */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 5a1dfacf24ea..b85d459bf4ba 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1527,87 +1527,18 @@ static void guc_reset_state(struct intel_context *ce, u32 head, bool scrub)
lrc_update_regs(ce, engine, head);
}
-static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
-{
- static const i915_reg_t _reg[I915_NUM_ENGINES] = {
- [RCS0] = MSG_IDLE_CS,
- [BCS0] = MSG_IDLE_BCS,
- [VCS0] = MSG_IDLE_VCS0,
- [VCS1] = MSG_IDLE_VCS1,
- [VCS2] = MSG_IDLE_VCS2,
- [VCS3] = MSG_IDLE_VCS3,
- [VCS4] = MSG_IDLE_VCS4,
- [VCS5] = MSG_IDLE_VCS5,
- [VCS6] = MSG_IDLE_VCS6,
- [VCS7] = MSG_IDLE_VCS7,
- [VECS0] = MSG_IDLE_VECS0,
- [VECS1] = MSG_IDLE_VECS1,
- [VECS2] = MSG_IDLE_VECS2,
- [VECS3] = MSG_IDLE_VECS3,
- [CCS0] = MSG_IDLE_CS,
- [CCS1] = MSG_IDLE_CS,
- [CCS2] = MSG_IDLE_CS,
- [CCS3] = MSG_IDLE_CS,
- };
- u32 val;
-
- if (!_reg[engine->id].reg)
- return 0;
-
- val = intel_uncore_read(engine->uncore, _reg[engine->id]);
-
- /* bits[29:25] & bits[13:9] >> shift */
- return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
-}
-
-static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
-{
- int ret;
-
- /* Ensure GPM receives fw up/down after CS is stopped */
- udelay(1);
-
- /* Wait for forcewake request to complete in GPM */
- ret = __intel_wait_for_register_fw(gt->uncore,
- GEN9_PWRGT_DOMAIN_STATUS,
- fw_mask, fw_mask, 5000, 0, NULL);
-
- /* Ensure CS receives fw ack from GPM */
- udelay(1);
-
- if (ret)
- GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);
-}
-
-/*
- * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
- * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
- * pending status is indicated by bits[13:9] (masked by bits[ 29:25]) in the
- * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
- * are concerned only with the gt reset here, we use a logical OR of pending
- * forcewakeups from all reset domains and then wait for them to complete by
- * querying PWRGT_DOMAIN_STATUS.
- */
static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
{
- u32 fw_pending;
-
- if (GRAPHICS_VER(engine->i915) != 12)
+ if (!IS_GRAPHICS_VER(engine->i915, 11, 12))
return;
- /*
- * Wa_22011802037
- * TODO: Occasionally trying to stop the cs times out, but does not
- * adversely affect functionality. The timeout is set as a config
- * parameter that defaults to 100ms. Assuming that this timeout is
- * sufficient for any pending MI_FORCEWAKEs to complete, ignore the
- * timeout returned here until it is root caused.
- */
intel_engine_stop_cs(engine);
- fw_pending = __cs_pending_mi_force_wakes(engine);
- if (fw_pending)
- __gpm_wait_for_fw_complete(engine->gt, fw_pending);
+ /*
+ * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
+ * to wait for any pending mi force wakeups
+ */
+ intel_engine_wait_for_pending_mi_fw(engine);
}
static void guc_reset_nop(struct intel_engine_cs *engine)
--
2.35.3
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend (rev2)
2022-06-10 0:32 [Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend Nerlige Ramappa, Umesh
@ 2022-06-10 1:03 ` Patchwork
2022-06-10 8:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-06-11 8:10 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2022-06-10 1:03 UTC (permalink / raw)
To: Nerlige Ramappa, Umesh; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend (rev2)
URL : https://patchwork.freedesktop.org/series/103837/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend (rev2)
2022-06-10 0:32 [Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend Nerlige Ramappa, Umesh
2022-06-10 1:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend (rev2) Patchwork
@ 2022-06-10 8:03 ` Patchwork
2022-06-11 8:10 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2022-06-10 8:03 UTC (permalink / raw)
To: Nerlige Ramappa, Umesh; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 10142 bytes --]
== Series Details ==
Series: drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend (rev2)
URL : https://patchwork.freedesktop.org/series/103837/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11750 -> Patchwork_103837v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/index.html
Participating hosts (40 -> 41)
------------------------------
Additional (3): bat-dg2-8 bat-dg2-9 fi-ilk-650
Missing (2): bat-atsm-1 fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_103837v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-ilk-650: NOTRUN -> [SKIP][1] ([fdo#109271]) +22 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/fi-ilk-650/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510: [PASS][2] -> [DMESG-FAIL][3] ([i915#4528])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/fi-pnv-d510/igt@i915_selftest@live@requests.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/fi-pnv-d510/igt@i915_selftest@live@requests.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [PASS][4] -> [INCOMPLETE][5] ([i915#5982])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/fi-hsw-g3258/igt@kms_chamelium@common-hpd-after-suspend.html
- fi-snb-2600: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/fi-snb-2600/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-ilk-650: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/fi-ilk-650/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- bat-adlp-4: [PASS][9] -> [DMESG-WARN][10] ([i915#3576]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/bat-adlp-4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/bat-adlp-4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
* igt@runner@aborted:
- fi-pnv-d510: NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#2403] / [i915#4312])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/fi-pnv-d510/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u: [DMESG-FAIL][12] ([i915#62]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@gem_contexts:
- {fi-tgl-dsi}: [INCOMPLETE][14] -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/fi-tgl-dsi/igt@i915_selftest@live@gem_contexts.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/fi-tgl-dsi/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258: [INCOMPLETE][16] ([i915#4785]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
- fi-snb-2600: [INCOMPLETE][18] ([i915#3921]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
- bat-dg1-6: [DMESG-FAIL][20] ([i915#4494] / [i915#4957]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@ring_submission:
- fi-cfl-8109u: [DMESG-WARN][22] ([i915#5904]) -> [PASS][23] +11 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u: [DMESG-WARN][24] ([i915#5904] / [i915#62]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/fi-cfl-8109u/igt@i915_suspend@basic-s2idle-without-i915.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/fi-cfl-8109u/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@kms_busy@basic@flip:
- bat-adlp-4: [DMESG-WARN][26] ([i915#1982] / [i915#3576]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/bat-adlp-4/igt@kms_busy@basic@flip.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/bat-adlp-4/igt@kms_busy@basic@flip.html
* igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1:
- {bat-adlp-6}: [DMESG-WARN][28] ([i915#3576]) -> [PASS][29] +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/bat-adlp-6/igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/bat-adlp-6/igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-cfl-8109u: [DMESG-WARN][30] ([i915#62]) -> [PASS][31] +14 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/fi-cfl-8109u/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/fi-cfl-8109u/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
[i915#5174]: https://gitlab.freedesktop.org/drm/intel/issues/5174
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
[i915#5885]: https://gitlab.freedesktop.org/drm/intel/issues/5885
[i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
[i915#5904]: https://gitlab.freedesktop.org/drm/intel/issues/5904
[i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
Build changes
-------------
* Linux: CI_DRM_11750 -> Patchwork_103837v2
CI-20190529: 20190529
CI_DRM_11750: d9c6b670bba2e213d4303234654dc52c4dbc9662 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6518: 0189ca288f7188e60f5eda356b190040bf8ec704 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103837v2: d9c6b670bba2e213d4303234654dc52c4dbc9662 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
1de2e35f19fe drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/index.html
[-- Attachment #2: Type: text/html, Size: 10134 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend (rev2)
2022-06-10 0:32 [Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend Nerlige Ramappa, Umesh
2022-06-10 1:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend (rev2) Patchwork
2022-06-10 8:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-06-11 8:10 ` Patchwork
2 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2022-06-11 8:10 UTC (permalink / raw)
To: Nerlige Ramappa, Umesh; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 47488 bytes --]
== Series Details ==
Series: drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend (rev2)
URL : https://patchwork.freedesktop.org/series/103837/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11750_full -> Patchwork_103837v2_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_103837v2_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_103837v2_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_103837v2_full:
### IGT changes ###
#### Warnings ####
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-tglb: [SKIP][1] ([fdo#109506] / [i915#2411]) -> [SKIP][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-tglb5/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-tglb2/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_ccs@pipe-d-bad-pixel-format-4_tiled_dg2_rc_ccs:
- {shard-dg1}: [SKIP][3] ([i915#3689]) -> [SKIP][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-dg1-19/igt@kms_ccs@pipe-d-bad-pixel-format-4_tiled_dg2_rc_ccs.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-dg1-18/igt@kms_ccs@pipe-d-bad-pixel-format-4_tiled_dg2_rc_ccs.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
- {shard-dg1}: [PASS][5] -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-dg1-19/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-dg1-18/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
* igt@kms_flip@busy-flip@a-hdmi-a3:
- {shard-dg1}: NOTRUN -> [FAIL][7] +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-dg1-18/igt@kms_flip@busy-flip@a-hdmi-a3.html
* igt@kms_invalid_mode@zero-clock:
- {shard-dg1}: [PASS][8] -> [WARN][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-dg1-19/igt@kms_invalid_mode@zero-clock.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-dg1-18/igt@kms_invalid_mode@zero-clock.html
Known issues
------------
Here are the changes found in Patchwork_103837v2_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-skl: ([PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32]) -> ([PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [FAIL][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53]) ([i915#5032])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl9/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl9/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl7/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl7/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl7/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl6/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl6/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl6/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl5/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl4/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl4/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl4/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl3/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl3/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl2/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl2/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl1/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl1/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl1/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl1/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl10/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl10/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl10/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl9/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl9/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl7/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl7/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl6/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl6/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl6/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl6/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl5/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl5/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl5/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl5/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl4/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl4/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl3/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl2/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl1/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl1/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl1/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl10/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl10/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@in-flight-contexts-10ms:
- shard-iclb: [PASS][54] -> [TIMEOUT][55] ([i915#3070])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-iclb6/igt@gem_eio@in-flight-contexts-10ms.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-iclb5/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_eio@kms:
- shard-tglb: [PASS][56] -> [FAIL][57] ([i915#5784])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-tglb7/igt@gem_eio@kms.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-tglb5/igt@gem_eio@kms.html
* igt@gem_exec_balancer@parallel-contexts:
- shard-iclb: [PASS][58] -> [SKIP][59] ([i915#4525]) +2 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-iclb1/igt@gem_exec_balancer@parallel-contexts.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-iclb8/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: [PASS][60] -> [FAIL][61] ([i915#2842])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-iclb7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-iclb8/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk: [PASS][62] -> [FAIL][63] ([i915#2842])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-glk5/igt@gem_exec_fair@basic-none-vip@rcs0.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-glk2/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][64] -> [FAIL][65] ([i915#2842])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][66] -> [FAIL][67] ([i915#2849])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_lmem_swapping@random:
- shard-apl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#4613])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-apl8/igt@gem_lmem_swapping@random.html
* igt@gem_mmap_gtt@fault-concurrent-y:
- shard-snb: [PASS][69] -> [INCOMPLETE][70] ([i915#5161])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-snb6/igt@gem_mmap_gtt@fault-concurrent-y.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-snb6/igt@gem_mmap_gtt@fault-concurrent-y.html
* igt@gem_pwrite@basic-exhaustion:
- shard-apl: NOTRUN -> [WARN][71] ([i915#2658])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-apl7/igt@gem_pwrite@basic-exhaustion.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][72] -> [DMESG-WARN][73] ([i915#5566] / [i915#716])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl3/igt@gen9_exec_parse@allowed-single.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl5/igt@gen9_exec_parse@allowed-single.html
- shard-apl: [PASS][74] -> [DMESG-WARN][75] ([i915#5566] / [i915#716])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-apl1/igt@gen9_exec_parse@allowed-single.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-apl6/igt@gen9_exec_parse@allowed-single.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-tglb: [PASS][76] -> [TIMEOUT][77] ([i915#3953])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-tglb5/igt@i915_module_load@reload-with-fault-injection.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-tglb2/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_dc@dc6-psr:
- shard-skl: NOTRUN -> [FAIL][78] ([i915#454])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl1/igt@i915_pm_dc@dc6-psr.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][79] ([i915#3763])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#3886])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl6/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#3886]) +3 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-apl8/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@vga-hpd-fast:
- shard-snb: NOTRUN -> [SKIP][82] ([fdo#109271] / [fdo#111827]) +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-snb5/igt@kms_chamelium@vga-hpd-fast.html
* igt@kms_color_chamelium@pipe-d-ctm-green-to-red:
- shard-skl: NOTRUN -> [SKIP][83] ([fdo#109271] / [fdo#111827]) +3 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl1/igt@kms_color_chamelium@pipe-d-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
- shard-apl: NOTRUN -> [SKIP][84] ([fdo#109271] / [fdo#111827]) +3 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-apl8/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
* igt@kms_content_protection@srm:
- shard-apl: NOTRUN -> [TIMEOUT][85] ([i915#1319])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-apl7/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@pipe-d-cursor-max-size-onscreen:
- shard-snb: NOTRUN -> [SKIP][86] ([fdo#109271]) +68 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-snb5/igt@kms_cursor_crc@pipe-d-cursor-max-size-onscreen.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
- shard-iclb: [PASS][87] -> [FAIL][88] ([i915#5072])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-iclb5/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-iclb7/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
- shard-apl: NOTRUN -> [SKIP][89] ([fdo#109271]) +64 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-apl7/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: NOTRUN -> [FAIL][90] ([i915#2346])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: NOTRUN -> [FAIL][91] ([i915#2346] / [i915#533])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-apl: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#533])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-apl8/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-skl: NOTRUN -> [SKIP][93] ([fdo#109271]) +68 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl1/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [PASS][94] -> [DMESG-WARN][95] ([i915#180]) +2 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-apl3/igt@kms_flip@flip-vs-suspend@a-dp1.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-apl8/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1:
- shard-kbl: [PASS][96] -> [FAIL][97] ([i915#1188])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-kbl1/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-kbl6/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#533])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][99] ([fdo#108145] / [i915#265])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [PASS][100] -> [SKIP][101] ([fdo#109441]) +2 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-iclb2/igt@kms_psr@psr2_suspend.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-iclb6/igt@kms_psr@psr2_suspend.html
* igt@kms_sysfs_edid_timing:
- shard-skl: NOTRUN -> [FAIL][102] ([IGT#2])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl6/igt@kms_sysfs_edid_timing.html
* igt@kms_writeback@writeback-fb-id:
- shard-apl: NOTRUN -> [SKIP][103] ([fdo#109271] / [i915#2437])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-apl8/igt@kms_writeback@writeback-fb-id.html
* igt@perf@polling-parameterized:
- shard-skl: [PASS][104] -> [FAIL][105] ([i915#5639])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl4/igt@perf@polling-parameterized.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl2/igt@perf@polling-parameterized.html
#### Possible fixes ####
* igt@fbdev@eof:
- {shard-rkl}: [SKIP][106] ([i915#2582]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-rkl-1/igt@fbdev@eof.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-rkl-6/igt@fbdev@eof.html
* igt@gem_ctx_persistence@many-contexts:
- {shard-rkl}: [FAIL][108] ([i915#2410]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-rkl-6/igt@gem_ctx_persistence@many-contexts.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-rkl-2/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_eio@unwedge-stress:
- {shard-rkl}: [TIMEOUT][110] ([i915#3063]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-rkl-2/igt@gem_eio@unwedge-stress.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-rkl-1/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][112] ([i915#2842]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [FAIL][114] ([i915#2842]) -> [PASS][115] +1 similar issue
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-apl4/igt@gem_exec_fair@basic-none@vecs0.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-apl4/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][116] ([i915#2842]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
- {shard-rkl}: [FAIL][118] ([i915#2842]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-rkl-1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-rkl-6/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [SKIP][120] ([fdo#109271]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs0.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [FAIL][122] ([i915#2842]) -> [PASS][123] +1 similar issue
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-kbl3/igt@gem_exec_fair@basic-pace@vecs0.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- {shard-dg1}: [DMESG-WARN][124] ([i915#4936]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-dg1-15/igt@gem_lmem_swapping@smem-oom@lmem0.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-dg1-15/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@i915_pm_rpm@cursor:
- {shard-rkl}: [SKIP][126] ([i915#1849]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-rkl-2/igt@i915_pm_rpm@cursor.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-rkl-6/igt@i915_pm_rpm@cursor.html
* igt@i915_pm_rpm@dpms-lpsp:
- {shard-dg1}: [SKIP][128] ([i915#1397]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-dg1-18/igt@i915_pm_rpm@dpms-lpsp.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-dg1-13/igt@i915_pm_rpm@dpms-lpsp.html
* igt@i915_pm_rpm@i2c:
- {shard-rkl}: [SKIP][130] ([fdo#109308]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-rkl-2/igt@i915_pm_rpm@i2c.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-rkl-6/igt@i915_pm_rpm@i2c.html
* igt@i915_pm_rpm@system-suspend-modeset:
- shard-skl: [INCOMPLETE][132] ([i915#5420]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl1/igt@i915_pm_rpm@system-suspend-modeset.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl6/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][134] ([i915#3921]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-snb5/igt@i915_selftest@live@hangcheck.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-snb5/igt@i915_selftest@live@hangcheck.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-0:
- {shard-rkl}: [SKIP][136] ([i915#1845] / [i915#4098]) -> [PASS][137] +33 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-rkl-1/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-rkl-6/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
* igt@kms_color@pipe-b-ctm-negative:
- {shard-rkl}: [SKIP][138] ([i915#1149] / [i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-rkl-1/igt@kms_color@pipe-b-ctm-negative.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-rkl-6/igt@kms_color@pipe-b-ctm-negative.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen:
- {shard-rkl}: [SKIP][140] ([fdo#112022] / [i915#4070]) -> [PASS][141] +9 similar issues
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-rkl-2/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
* igt@kms_cursor_edge_walk@pipe-b-256x256-bottom-edge:
- {shard-rkl}: [SKIP][142] ([i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][143] +4 similar issues
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-rkl-2/igt@kms_cursor_edge_walk@pipe-b-256x256-bottom-edge.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-b-256x256-bottom-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-skl: [FAIL][144] ([i915#2346]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic:
- {shard-rkl}: [SKIP][146] ([fdo#111825] / [i915#4070]) -> [PASS][147] +1 similar issue
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-rkl-1/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-rkl-6/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled:
- {shard-rkl}: [SKIP][148] ([fdo#111314] / [i915#4098] / [i915#4369]) -> [PASS][149] +3 similar issues
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-rkl-1/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-rkl-6/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html
* igt@kms_fbcon_fbt@psr-suspend:
- {shard-rkl}: [SKIP][150] ([fdo#110189] / [i915#3955]) -> [PASS][151]
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-rkl-2/igt@kms_fbcon_fbt@psr-suspend.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-rkl-6/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][152] ([i915#79]) -> [PASS][153]
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1:
- shard-kbl: [FAIL][154] ([i915#79]) -> [PASS][155]
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-kbl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-kbl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [FAIL][156] ([i915#79]) -> [PASS][157]
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip@wf_vblank-ts-check-interruptible@c-edp1:
- shard-skl: [FAIL][158] ([i915#2122]) -> [PASS][159] +1 similar issue
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl3/igt@kms_flip@wf_vblank-ts-check-interruptible@c-edp1.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl5/igt@kms_flip@wf_vblank-ts-check-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling:
- {shard-rkl}: [SKIP][160] ([i915#3701]) -> [PASS][161]
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-rkl-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
- shard-iclb: [SKIP][162] ([i915#3701]) -> [PASS][163]
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-iclb7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
- {shard-rkl}: [SKIP][164] ([i915#1849] / [i915#4098]) -> [PASS][165] +25 similar issues
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html
* igt@kms_hdr@bpc-switch@pipe-a-dp-1:
- shard-kbl: [FAIL][166] ([i915#1188]) -> [PASS][167]
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-kbl6/igt@kms_hdr@bpc-switch@pipe-a-dp-1.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-kbl3/igt@kms_hdr@bpc-switch@pipe-a-dp-1.html
* igt@kms_invalid_mode@bad-vtotal:
- {shard-rkl}: [SKIP][168] ([i915#4278]) -> [PASS][169]
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-rkl-1/igt@kms_invalid_mode@bad-vtotal.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-rkl-6/igt@kms_invalid_mode@bad-vtotal.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-apl: [DMESG-WARN][170] ([i915#180]) -> [PASS][171] +1 similar issue
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-apl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-apl8/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][172] ([fdo#109441]) -> [PASS][173] +2 similar issues
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-iclb4/igt@kms_psr@psr2_sprite_plane_move.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_psr@sprite_render:
- {shard-rkl}: [SKIP][174] ([i915#1072]) -> [PASS][175]
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-rkl-1/igt@kms_psr@sprite_render.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-rkl-6/igt@kms_psr@sprite_render.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-iclb: [SKIP][176] ([i915#5519]) -> [PASS][177] +1 similar issue
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-iclb3/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-iclb3/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_universal_plane@universal-plane-pipe-a-sanity:
- {shard-rkl}: [SKIP][178] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][179]
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-rkl-2/igt@kms_universal_plane@universal-plane-pipe-a-sanity.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-rkl-6/igt@kms_universal_plane@universal-plane-pipe-a-sanity.html
* igt@perf@polling-small-buf:
- {shard-rkl}: [FAIL][180] ([i915#1722]) -> [PASS][181]
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-rkl-1/igt@perf@polling-small-buf.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-rkl-6/igt@perf@polling-small-buf.html
* igt@perf@short-reads:
- shard-skl: [FAIL][182] ([i915#51]) -> [PASS][183]
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl7/igt@perf@short-reads.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl6/igt@perf@short-reads.html
* igt@perf_pmu@idle@rcs0:
- {shard-dg1}: [FAIL][184] ([i915#4349]) -> [PASS][185]
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-dg1-15/igt@perf_pmu@idle@rcs0.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-dg1-15/igt@perf_pmu@idle@rcs0.html
* igt@sysfs_timeslice_duration@timeout@vecs0:
- shard-apl: [FAIL][186] ([i915#1755]) -> [PASS][187]
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-apl4/igt@sysfs_timeslice_duration@timeout@vecs0.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-apl6/igt@sysfs_timeslice_duration@timeout@vecs0.html
#### Warnings ####
* igt@gem_eio@unwedge-stress:
- shard-tglb: [FAIL][188] ([i915#5784]) -> [TIMEOUT][189] ([i915#3063])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-tglb2/igt@gem_eio@unwedge-stress.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-tglb7/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][190] ([i915#4525]) -> [FAIL][191] ([i915#6117])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-iclb6/igt@gem_exec_balancer@parallel-ordering.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-iclb: [SKIP][192] ([i915#658]) -> [SKIP][193] ([i915#2920])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-iclb4/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][194] ([fdo#111068] / [i915#658]) -> [SKIP][195] ([i915#2920]) +1 similar issue
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-iclb6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-iclb: [FAIL][196] ([i915#5939]) -> [SKIP][197] ([fdo#109642] / [fdo#111068] / [i915#658])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-iclb2/igt@kms_psr2_su@page_flip-nv12.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-iclb7/igt@kms_psr2_su@page_flip-nv12.html
* igt@runner@aborted:
- shard-skl: [FAIL][198] ([i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][199], [FAIL][200], [FAIL][201]) ([i915#2029] / [i915#3002] / [i915#4312] / [i915#5257])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-skl1/igt@runner@aborted.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl5/igt@runner@aborted.html
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl5/igt@runner@aborted.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-skl6/igt@runner@aborted.html
- shard-apl: ([FAIL][202], [FAIL][203], [FAIL][204]) ([fdo#109271] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][205], [FAIL][206], [FAIL][207], [FAIL][208]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-apl2/igt@runner@aborted.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-apl4/igt@runner@aborted.html
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11750/shard-apl8/igt@runner@aborted.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-apl6/igt@runner@aborted.html
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-apl6/igt@runner@aborted.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-apl8/igt@runner@aborted.html
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/shard-apl2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3763]: https://gitlab.freedesktop.org/drm/intel/issues/3763
[i915#3810]: https://gitlab.freedesktop.org/drm/intel/issues/3810
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#3953]: https://gitlab.freedesktop.org/drm/intel/issues/3953
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3963]: https://gitlab.freedesktop.org/drm/intel/issues/3963
[i915#4032]: https://gitlab.freedesktop.org/drm/intel/issues/4032
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4241]: https://gitlab.freedesktop.org/drm/intel/issues/4241
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
[i915#5032]: https://gitlab.freedesktop.org/drm/intel/issues/5032
[i915#5072]: https://gitlab.freedesktop.org/drm/intel/issues/5072
[i915#51]: https://gitlab.freedesktop.org/drm/intel/issues/51
[i915#5161]: https://gitlab.freedesktop.org/drm/intel/issues/5161
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5357]: https://gitlab.freedesktop.org/drm/intel/issues/5357
[i915#5420]: https://gitlab.freedesktop.org/drm/intel/issues/5420
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#5721]: https://gitlab.freedesktop.org/drm/intel/issues/5721
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
[i915#6011]: https://gitlab.freedesktop.org/drm/intel/issues/6011
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_11750 -> Patchwork_103837v2
CI-20190529: 20190529
CI_DRM_11750: d9c6b670bba2e213d4303234654dc52c4dbc9662 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6518: 0189ca288f7188e60f5eda356b190040bf8ec704 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103837v2: d9c6b670bba2e213d4303234654dc52c4dbc9662 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v2/index.html
[-- Attachment #2: Type: text/html, Size: 50203 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend
@ 2022-06-21 19:21 Nerlige Ramappa, Umesh
0 siblings, 0 replies; 8+ messages in thread
From: Nerlige Ramappa, Umesh @ 2022-06-21 19:21 UTC (permalink / raw)
To: intel-gfx
From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
For execlists backend, current implementation of Wa_22011802037 is to
stop the CS before doing a reset of the engine. This WA was further
extended to wait for any pending MI FORCE WAKEUPs before issuing a
reset. Add the extended steps in the execlist path of reset.
In addition, extend the WA to gen11.
v2: (Tvrtko)
- Clarify comments, commit message, fix typos
- Use IS_GRAPHICS_VER for gen 11/12 checks
v3: (Daneile)
- Drop changes to intel_ring_submission since WA does not apply to it
- Log an error if MSG IDLE is not defined for an engine
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Fixes: f6aa0d713c88 ("drm/i915: Add Wa_22011802037 force cs halt")
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine.h | 2 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 88 ++++++++++++++++++-
.../drm/i915/gt/intel_execlists_submission.c | 7 ++
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 81 ++---------------
5 files changed, 103 insertions(+), 79 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 1431f1e9dbee..04e435bce79b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -201,6 +201,8 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine);
int intel_engine_stop_cs(struct intel_engine_cs *engine);
void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
+void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine);
+
void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask);
u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 136cc44c3deb..283870c65991 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1376,10 +1376,10 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
/*
- * Wa_22011802037 : gen12, Prior to doing a reset, ensure CS is
+ * Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is
* stopped, set ring stop bit and prefetch disable bit to halt CS
*/
- if (GRAPHICS_VER(engine->i915) == 12)
+ if (IS_GRAPHICS_VER(engine->i915, 11, 12))
intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
_MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
@@ -1402,6 +1402,18 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine)
return -ENODEV;
ENGINE_TRACE(engine, "\n");
+ /*
+ * TODO: Find out why occasionally stopping the CS times out. Seen
+ * especially with gem_eio tests.
+ *
+ * Occasionally trying to stop the cs times out, but does not adversely
+ * affect functionality. The timeout is set as a config parameter that
+ * defaults to 100ms. In most cases the follow up operation is to wait
+ * for pending MI_FORCE_WAKES. The assumption is that this timeout is
+ * sufficient for any pending MI_FORCEWAKEs to complete. Once root
+ * caused, the caller must check and handle the return from this
+ * function.
+ */
if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
ENGINE_TRACE(engine,
"timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n",
@@ -1428,6 +1440,78 @@ void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
}
+static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
+{
+ static const i915_reg_t _reg[I915_NUM_ENGINES] = {
+ [RCS0] = MSG_IDLE_CS,
+ [BCS0] = MSG_IDLE_BCS,
+ [VCS0] = MSG_IDLE_VCS0,
+ [VCS1] = MSG_IDLE_VCS1,
+ [VCS2] = MSG_IDLE_VCS2,
+ [VCS3] = MSG_IDLE_VCS3,
+ [VCS4] = MSG_IDLE_VCS4,
+ [VCS5] = MSG_IDLE_VCS5,
+ [VCS6] = MSG_IDLE_VCS6,
+ [VCS7] = MSG_IDLE_VCS7,
+ [VECS0] = MSG_IDLE_VECS0,
+ [VECS1] = MSG_IDLE_VECS1,
+ [VECS2] = MSG_IDLE_VECS2,
+ [VECS3] = MSG_IDLE_VECS3,
+ [CCS0] = MSG_IDLE_CS,
+ [CCS1] = MSG_IDLE_CS,
+ [CCS2] = MSG_IDLE_CS,
+ [CCS3] = MSG_IDLE_CS,
+ };
+ u32 val;
+
+ if (!_reg[engine->id].reg) {
+ drm_err(&engine->i915->drm,
+ "MSG IDLE undefined for engine id %u\n", engine->id);
+ return 0;
+ }
+
+ val = intel_uncore_read(engine->uncore, _reg[engine->id]);
+
+ /* bits[29:25] & bits[13:9] >> shift */
+ return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
+}
+
+static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
+{
+ int ret;
+
+ /* Ensure GPM receives fw up/down after CS is stopped */
+ udelay(1);
+
+ /* Wait for forcewake request to complete in GPM */
+ ret = __intel_wait_for_register_fw(gt->uncore,
+ GEN9_PWRGT_DOMAIN_STATUS,
+ fw_mask, fw_mask, 5000, 0, NULL);
+
+ /* Ensure CS receives fw ack from GPM */
+ udelay(1);
+
+ if (ret)
+ GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);
+}
+
+/*
+ * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
+ * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
+ * pending status is indicated by bits[13:9] (masked by bits[29:25]) in the
+ * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
+ * are concerned only with the gt reset here, we use a logical OR of pending
+ * forcewakeups from all reset domains and then wait for them to complete by
+ * querying PWRGT_DOMAIN_STATUS.
+ */
+void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine)
+{
+ u32 fw_pending = __cs_pending_mi_force_wakes(engine);
+
+ if (fw_pending)
+ __gpm_wait_for_fw_complete(engine->gt, fw_pending);
+}
+
/* NB: please notice the memset */
void intel_engine_get_instdone(const struct intel_engine_cs *engine,
struct intel_instdone *instdone)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index ad72e2c5c4e7..4b909cb88cdf 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2968,6 +2968,13 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
ring_set_paused(engine, 1);
intel_engine_stop_cs(engine);
+ /*
+ * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
+ * to wait for any pending mi force wakeups
+ */
+ if (IS_GRAPHICS_VER(engine->i915, 11, 12))
+ intel_engine_wait_for_pending_mi_fw(engine);
+
engine->execlists.reset_ccid = active_ccid(engine);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 35887cb53201..2706a8c65090 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -310,8 +310,8 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
if (IS_DG2(gt->i915))
flags |= GUC_WA_DUAL_QUEUE;
- /* Wa_22011802037: graphics version 12 */
- if (GRAPHICS_VER(gt->i915) == 12)
+ /* Wa_22011802037: graphics version 11/12 */
+ if (IS_GRAPHICS_VER(gt->i915, 11, 12))
flags |= GUC_WA_PRE_PARSER;
/* Wa_16011777198:dg2 */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index e62ea35513ea..ef68f15a1b66 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1527,87 +1527,18 @@ static void guc_reset_state(struct intel_context *ce, u32 head, bool scrub)
lrc_update_regs(ce, engine, head);
}
-static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
-{
- static const i915_reg_t _reg[I915_NUM_ENGINES] = {
- [RCS0] = MSG_IDLE_CS,
- [BCS0] = MSG_IDLE_BCS,
- [VCS0] = MSG_IDLE_VCS0,
- [VCS1] = MSG_IDLE_VCS1,
- [VCS2] = MSG_IDLE_VCS2,
- [VCS3] = MSG_IDLE_VCS3,
- [VCS4] = MSG_IDLE_VCS4,
- [VCS5] = MSG_IDLE_VCS5,
- [VCS6] = MSG_IDLE_VCS6,
- [VCS7] = MSG_IDLE_VCS7,
- [VECS0] = MSG_IDLE_VECS0,
- [VECS1] = MSG_IDLE_VECS1,
- [VECS2] = MSG_IDLE_VECS2,
- [VECS3] = MSG_IDLE_VECS3,
- [CCS0] = MSG_IDLE_CS,
- [CCS1] = MSG_IDLE_CS,
- [CCS2] = MSG_IDLE_CS,
- [CCS3] = MSG_IDLE_CS,
- };
- u32 val;
-
- if (!_reg[engine->id].reg)
- return 0;
-
- val = intel_uncore_read(engine->uncore, _reg[engine->id]);
-
- /* bits[29:25] & bits[13:9] >> shift */
- return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
-}
-
-static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
-{
- int ret;
-
- /* Ensure GPM receives fw up/down after CS is stopped */
- udelay(1);
-
- /* Wait for forcewake request to complete in GPM */
- ret = __intel_wait_for_register_fw(gt->uncore,
- GEN9_PWRGT_DOMAIN_STATUS,
- fw_mask, fw_mask, 5000, 0, NULL);
-
- /* Ensure CS receives fw ack from GPM */
- udelay(1);
-
- if (ret)
- GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);
-}
-
-/*
- * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
- * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
- * pending status is indicated by bits[13:9] (masked by bits[ 29:25]) in the
- * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
- * are concerned only with the gt reset here, we use a logical OR of pending
- * forcewakeups from all reset domains and then wait for them to complete by
- * querying PWRGT_DOMAIN_STATUS.
- */
static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
{
- u32 fw_pending;
-
- if (GRAPHICS_VER(engine->i915) != 12)
+ if (!IS_GRAPHICS_VER(engine->i915, 11, 12))
return;
- /*
- * Wa_22011802037
- * TODO: Occasionally trying to stop the cs times out, but does not
- * adversely affect functionality. The timeout is set as a config
- * parameter that defaults to 100ms. Assuming that this timeout is
- * sufficient for any pending MI_FORCEWAKEs to complete, ignore the
- * timeout returned here until it is root caused.
- */
intel_engine_stop_cs(engine);
- fw_pending = __cs_pending_mi_force_wakes(engine);
- if (fw_pending)
- __gpm_wait_for_fw_complete(engine->gt, fw_pending);
+ /*
+ * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
+ * to wait for any pending mi force wakeups
+ */
+ intel_engine_wait_for_pending_mi_fw(engine);
}
static void guc_reset_nop(struct intel_engine_cs *engine)
--
2.35.3
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend
2022-05-10 22:14 Nerlige Ramappa, Umesh
2022-05-11 15:26 ` Tvrtko Ursulin
@ 2022-06-09 23:51 ` Ceraolo Spurio, Daniele
1 sibling, 0 replies; 8+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-06-09 23:51 UTC (permalink / raw)
To: Nerlige Ramappa, Umesh, intel-gfx, Tvrtko Ursulin
On 5/10/2022 3:14 PM, Nerlige Ramappa, Umesh wrote:
> From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>
> For execlists backend, current implementation of Wa_22011802037 is to
> stop the CS before doing a reset of the engine. This WA was further
> extended to wait for any pending MI FORCE WAKEUPs before issuing a
> reset. Add the extended steps in the execlist path of reset.
>
> In addition, extend the WA to gen11.
>
> v2: (Tvrtko)
> - Clarify comments, commit message, fix typos
> - Use IS_GRAPHICS_VER for gen 11/12 checks
>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> Fixes: f6aa0d713c88 ("drm/i915: Add Wa_22011802037 force cs halt")
> ---
> drivers/gpu/drm/i915/gt/intel_engine.h | 2 +
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 85 ++++++++++++++++++-
> .../drm/i915/gt/intel_execlists_submission.c | 7 ++
> .../gpu/drm/i915/gt/intel_ring_submission.c | 7 ++
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +-
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 81 ++----------------
> 6 files changed, 107 insertions(+), 79 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
> index 1431f1e9dbee..04e435bce79b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -201,6 +201,8 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine);
> int intel_engine_stop_cs(struct intel_engine_cs *engine);
> void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
>
> +void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine);
> +
> void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask);
>
> u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 14c6ddbbfde8..9943cf9655b2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1282,10 +1282,10 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
> intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
>
> /*
> - * Wa_22011802037 : gen12, Prior to doing a reset, ensure CS is
> + * Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is
> * stopped, set ring stop bit and prefetch disable bit to halt CS
> */
> - if (GRAPHICS_VER(engine->i915) == 12)
> + if (IS_GRAPHICS_VER(engine->i915, 11, 12))
> intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
> _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
>
> @@ -1308,6 +1308,18 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine)
> return -ENODEV;
>
> ENGINE_TRACE(engine, "\n");
> + /*
> + * TODO: Find out why occasionally stopping the CS times out. Seen
> + * especially with gem_eio tests.
> + *
> + * Occasionally trying to stop the cs times out, but does not adversely
> + * affect functionality. The timeout is set as a config parameter that
> + * defaults to 100ms. In most cases the follow up operation is to wait
> + * for pending MI_FORCE_WAKES. The assumption is that this timeout is
> + * sufficient for any pending MI_FORCEWAKEs to complete. Once root
> + * caused, the caller must check and handle the return from this
> + * function.
> + */
> if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
> ENGINE_TRACE(engine,
> "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n",
> @@ -1334,6 +1346,75 @@ void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
> ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
> }
>
> +static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
> +{
> + static const i915_reg_t _reg[I915_NUM_ENGINES] = {
> + [RCS0] = MSG_IDLE_CS,
> + [BCS0] = MSG_IDLE_BCS,
> + [VCS0] = MSG_IDLE_VCS0,
> + [VCS1] = MSG_IDLE_VCS1,
> + [VCS2] = MSG_IDLE_VCS2,
> + [VCS3] = MSG_IDLE_VCS3,
> + [VCS4] = MSG_IDLE_VCS4,
> + [VCS5] = MSG_IDLE_VCS5,
> + [VCS6] = MSG_IDLE_VCS6,
> + [VCS7] = MSG_IDLE_VCS7,
> + [VECS0] = MSG_IDLE_VECS0,
> + [VECS1] = MSG_IDLE_VECS1,
> + [VECS2] = MSG_IDLE_VECS2,
> + [VECS3] = MSG_IDLE_VECS3,
> + [CCS0] = MSG_IDLE_CS,
> + [CCS1] = MSG_IDLE_CS,
> + [CCS2] = MSG_IDLE_CS,
> + [CCS3] = MSG_IDLE_CS,
> + };
> + u32 val;
> +
> + if (!_reg[engine->id].reg)
> + return 0;
> +
> + val = intel_uncore_read(engine->uncore, _reg[engine->id]);
> +
> + /* bits[29:25] & bits[13:9] >> shift */
> + return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
> +}
> +
> +static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
> +{
> + int ret;
> +
> + /* Ensure GPM receives fw up/down after CS is stopped */
> + udelay(1);
> +
> + /* Wait for forcewake request to complete in GPM */
> + ret = __intel_wait_for_register_fw(gt->uncore,
> + GEN9_PWRGT_DOMAIN_STATUS,
> + fw_mask, fw_mask, 5000, 0, NULL);
> +
> + /* Ensure CS receives fw ack from GPM */
> + udelay(1);
> +
> + if (ret)
> + GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);
> +}
> +
> +/*
> + * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
> + * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
> + * pending status is indicated by bits[13:9] (masked by bits[29:25]) in the
> + * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
> + * are concerned only with the gt reset here, we use a logical OR of pending
> + * forcewakeups from all reset domains and then wait for them to complete by
> + * querying PWRGT_DOMAIN_STATUS.
> + */
> +void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine)
> +{
> + u32 fw_pending = __cs_pending_mi_force_wakes(engine);
> +
> + if (fw_pending)
> + __gpm_wait_for_fw_complete(engine->gt, fw_pending);
> +}
> +
> static u32
> read_subslice_reg(const struct intel_engine_cs *engine,
> int slice, int subslice, i915_reg_t reg)
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 86f7a9ac1c39..2caa1af77064 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2958,6 +2958,13 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
> ring_set_paused(engine, 1);
> intel_engine_stop_cs(engine);
>
> + /*
> + * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
> + * to wait for any pending mi force wakeups
> + */
> + if (IS_GRAPHICS_VER(engine->i915, 11, 12))
> + intel_engine_wait_for_pending_mi_fw(engine);
> +
> engine->execlists.reset_ccid = active_ccid(engine);
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 5423bfd301ad..a7808eff33c5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -323,6 +323,13 @@ static void reset_prepare(struct intel_engine_cs *engine)
> ENGINE_TRACE(engine, "\n");
> intel_engine_stop_cs(engine);
>
> + /*
> + * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
> + * to wait for any pending mi force wakeups
> + */
> + if (IS_GRAPHICS_VER(engine->i915, 11, 12))
> + intel_engine_wait_for_pending_mi_fw(engine);
> +
Ringbuffer submission is not supported on gen 11 and 12, so no need for
this.
With this removed:
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> if (!stop_ring(engine)) {
> /* G45 ring initialization often fails to reset head to zero */
> ENGINE_TRACE(engine,
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 2c4ad4a65089..8c6885f43d1a 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -310,8 +310,8 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
> if (IS_DG2(gt->i915))
> flags |= GUC_WA_DUAL_QUEUE;
>
> - /* Wa_22011802037: graphics version 12 */
> - if (GRAPHICS_VER(gt->i915) == 12)
> + /* Wa_22011802037: graphics version 11/12 */
> + if (IS_GRAPHICS_VER(gt->i915, 11, 12))
> flags |= GUC_WA_PRE_PARSER;
>
> /* Wa_16011777198:dg2 */
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 75291e9846c5..9b21c7345ffd 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1527,87 +1527,18 @@ static void guc_reset_state(struct intel_context *ce, u32 head, bool scrub)
> lrc_update_regs(ce, engine, head);
> }
>
> -static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
> -{
> - static const i915_reg_t _reg[I915_NUM_ENGINES] = {
> - [RCS0] = MSG_IDLE_CS,
> - [BCS0] = MSG_IDLE_BCS,
> - [VCS0] = MSG_IDLE_VCS0,
> - [VCS1] = MSG_IDLE_VCS1,
> - [VCS2] = MSG_IDLE_VCS2,
> - [VCS3] = MSG_IDLE_VCS3,
> - [VCS4] = MSG_IDLE_VCS4,
> - [VCS5] = MSG_IDLE_VCS5,
> - [VCS6] = MSG_IDLE_VCS6,
> - [VCS7] = MSG_IDLE_VCS7,
> - [VECS0] = MSG_IDLE_VECS0,
> - [VECS1] = MSG_IDLE_VECS1,
> - [VECS2] = MSG_IDLE_VECS2,
> - [VECS3] = MSG_IDLE_VECS3,
> - [CCS0] = MSG_IDLE_CS,
> - [CCS1] = MSG_IDLE_CS,
> - [CCS2] = MSG_IDLE_CS,
> - [CCS3] = MSG_IDLE_CS,
> - };
> - u32 val;
> -
> - if (!_reg[engine->id].reg)
> - return 0;
> -
> - val = intel_uncore_read(engine->uncore, _reg[engine->id]);
> -
> - /* bits[29:25] & bits[13:9] >> shift */
> - return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
> -}
> -
> -static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
> -{
> - int ret;
> -
> - /* Ensure GPM receives fw up/down after CS is stopped */
> - udelay(1);
> -
> - /* Wait for forcewake request to complete in GPM */
> - ret = __intel_wait_for_register_fw(gt->uncore,
> - GEN9_PWRGT_DOMAIN_STATUS,
> - fw_mask, fw_mask, 5000, 0, NULL);
> -
> - /* Ensure CS receives fw ack from GPM */
> - udelay(1);
> -
> - if (ret)
> - GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);
> -}
> -
> -/*
> - * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
> - * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
> - * pending status is indicated by bits[13:9] (masked by bits[ 29:25]) in the
> - * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
> - * are concerned only with the gt reset here, we use a logical OR of pending
> - * forcewakeups from all reset domains and then wait for them to complete by
> - * querying PWRGT_DOMAIN_STATUS.
> - */
> static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
> {
> - u32 fw_pending;
> -
> - if (GRAPHICS_VER(engine->i915) != 12)
> + if (!IS_GRAPHICS_VER(engine->i915, 11, 12))
> return;
>
> - /*
> - * Wa_22011802037
> - * TODO: Occasionally trying to stop the cs times out, but does not
> - * adversely affect functionality. The timeout is set as a config
> - * parameter that defaults to 100ms. Assuming that this timeout is
> - * sufficient for any pending MI_FORCEWAKEs to complete, ignore the
> - * timeout returned here until it is root caused.
> - */
> intel_engine_stop_cs(engine);
>
> - fw_pending = __cs_pending_mi_force_wakes(engine);
> - if (fw_pending)
> - __gpm_wait_for_fw_complete(engine->gt, fw_pending);
> + /*
> + * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
> + * to wait for any pending mi force wakeups
> + */
> + intel_engine_wait_for_pending_mi_fw(engine);
> }
>
> static void guc_reset_nop(struct intel_engine_cs *engine)
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend
2022-05-10 22:14 Nerlige Ramappa, Umesh
@ 2022-05-11 15:26 ` Tvrtko Ursulin
2022-06-09 23:51 ` Ceraolo Spurio, Daniele
1 sibling, 0 replies; 8+ messages in thread
From: Tvrtko Ursulin @ 2022-05-11 15:26 UTC (permalink / raw)
To: Nerlige Ramappa, Umesh, intel-gfx
On 10/05/2022 23:14, Nerlige Ramappa, Umesh wrote:
> From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>
> For execlists backend, current implementation of Wa_22011802037 is to
> stop the CS before doing a reset of the engine. This WA was further
> extended to wait for any pending MI FORCE WAKEUPs before issuing a
> reset. Add the extended steps in the execlist path of reset.
>
> In addition, extend the WA to gen11.
>
> v2: (Tvrtko)
> - Clarify comments, commit message, fix typos
> - Use IS_GRAPHICS_VER for gen 11/12 checks
>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> Fixes: f6aa0d713c88 ("drm/i915: Add Wa_22011802037 force cs halt")
> ---
> drivers/gpu/drm/i915/gt/intel_engine.h | 2 +
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 85 ++++++++++++++++++-
> .../drm/i915/gt/intel_execlists_submission.c | 7 ++
> .../gpu/drm/i915/gt/intel_ring_submission.c | 7 ++
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +-
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 81 ++----------------
> 6 files changed, 107 insertions(+), 79 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
> index 1431f1e9dbee..04e435bce79b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -201,6 +201,8 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine);
> int intel_engine_stop_cs(struct intel_engine_cs *engine);
> void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
>
> +void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine);
> +
> void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask);
>
> u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 14c6ddbbfde8..9943cf9655b2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1282,10 +1282,10 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
> intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
>
> /*
> - * Wa_22011802037 : gen12, Prior to doing a reset, ensure CS is
> + * Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is
> * stopped, set ring stop bit and prefetch disable bit to halt CS
> */
> - if (GRAPHICS_VER(engine->i915) == 12)
> + if (IS_GRAPHICS_VER(engine->i915, 11, 12))
> intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
> _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
>
> @@ -1308,6 +1308,18 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine)
> return -ENODEV;
>
> ENGINE_TRACE(engine, "\n");
> + /*
> + * TODO: Find out why occasionally stopping the CS times out. Seen
> + * especially with gem_eio tests.
> + *
> + * Occasionally trying to stop the cs times out, but does not adversely
> + * affect functionality. The timeout is set as a config parameter that
> + * defaults to 100ms. In most cases the follow up operation is to wait
> + * for pending MI_FORCE_WAKES. The assumption is that this timeout is
> + * sufficient for any pending MI_FORCEWAKEs to complete. Once root
> + * caused, the caller must check and handle the return from this
> + * function.
> + */
> if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
> ENGINE_TRACE(engine,
> "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n",
> @@ -1334,6 +1346,75 @@ void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
> ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
> }
>
> +static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
> +{
> + static const i915_reg_t _reg[I915_NUM_ENGINES] = {
> + [RCS0] = MSG_IDLE_CS,
> + [BCS0] = MSG_IDLE_BCS,
> + [VCS0] = MSG_IDLE_VCS0,
> + [VCS1] = MSG_IDLE_VCS1,
> + [VCS2] = MSG_IDLE_VCS2,
> + [VCS3] = MSG_IDLE_VCS3,
> + [VCS4] = MSG_IDLE_VCS4,
> + [VCS5] = MSG_IDLE_VCS5,
> + [VCS6] = MSG_IDLE_VCS6,
> + [VCS7] = MSG_IDLE_VCS7,
> + [VECS0] = MSG_IDLE_VECS0,
> + [VECS1] = MSG_IDLE_VECS1,
> + [VECS2] = MSG_IDLE_VECS2,
> + [VECS3] = MSG_IDLE_VECS3,
> + [CCS0] = MSG_IDLE_CS,
> + [CCS1] = MSG_IDLE_CS,
> + [CCS2] = MSG_IDLE_CS,
> + [CCS3] = MSG_IDLE_CS,
> + };
> + u32 val;
> +
> + if (!_reg[engine->id].reg)
> + return 0;
Should this actually be a GEM_WARN_ON condition, to catch failures to
update for new platforms?
> +
> + val = intel_uncore_read(engine->uncore, _reg[engine->id]);
> +
> + /* bits[29:25] & bits[13:9] >> shift */
> + return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
> +}
> +
> +static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
> +{
> + int ret;
> +
> + /* Ensure GPM receives fw up/down after CS is stopped */
> + udelay(1);
> +
> + /* Wait for forcewake request to complete in GPM */
> + ret = __intel_wait_for_register_fw(gt->uncore,
> + GEN9_PWRGT_DOMAIN_STATUS,
> + fw_mask, fw_mask, 5000, 0, NULL);
No fast-slow split as discussed but okay, it's not making anything worse
that it already is.
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
> +
> + /* Ensure CS receives fw ack from GPM */
> + udelay(1);
> +
> + if (ret)
> + GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);
> +}
> +
> +/*
> + * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
> + * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
> + * pending status is indicated by bits[13:9] (masked by bits[29:25]) in the
> + * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
> + * are concerned only with the gt reset here, we use a logical OR of pending
> + * forcewakeups from all reset domains and then wait for them to complete by
> + * querying PWRGT_DOMAIN_STATUS.
> + */
> +void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine)
> +{
> + u32 fw_pending = __cs_pending_mi_force_wakes(engine);
> +
> + if (fw_pending)
> + __gpm_wait_for_fw_complete(engine->gt, fw_pending);
> +}
> +
> static u32
> read_subslice_reg(const struct intel_engine_cs *engine,
> int slice, int subslice, i915_reg_t reg)
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 86f7a9ac1c39..2caa1af77064 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2958,6 +2958,13 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
> ring_set_paused(engine, 1);
> intel_engine_stop_cs(engine);
>
> + /*
> + * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
> + * to wait for any pending mi force wakeups
> + */
> + if (IS_GRAPHICS_VER(engine->i915, 11, 12))
> + intel_engine_wait_for_pending_mi_fw(engine);
> +
> engine->execlists.reset_ccid = active_ccid(engine);
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 5423bfd301ad..a7808eff33c5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -323,6 +323,13 @@ static void reset_prepare(struct intel_engine_cs *engine)
> ENGINE_TRACE(engine, "\n");
> intel_engine_stop_cs(engine);
>
> + /*
> + * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
> + * to wait for any pending mi force wakeups
> + */
> + if (IS_GRAPHICS_VER(engine->i915, 11, 12))
> + intel_engine_wait_for_pending_mi_fw(engine);
> +
> if (!stop_ring(engine)) {
> /* G45 ring initialization often fails to reset head to zero */
> ENGINE_TRACE(engine,
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 2c4ad4a65089..8c6885f43d1a 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -310,8 +310,8 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
> if (IS_DG2(gt->i915))
> flags |= GUC_WA_DUAL_QUEUE;
>
> - /* Wa_22011802037: graphics version 12 */
> - if (GRAPHICS_VER(gt->i915) == 12)
> + /* Wa_22011802037: graphics version 11/12 */
> + if (IS_GRAPHICS_VER(gt->i915, 11, 12))
> flags |= GUC_WA_PRE_PARSER;
>
> /* Wa_16011777198:dg2 */
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 75291e9846c5..9b21c7345ffd 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1527,87 +1527,18 @@ static void guc_reset_state(struct intel_context *ce, u32 head, bool scrub)
> lrc_update_regs(ce, engine, head);
> }
>
> -static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
> -{
> - static const i915_reg_t _reg[I915_NUM_ENGINES] = {
> - [RCS0] = MSG_IDLE_CS,
> - [BCS0] = MSG_IDLE_BCS,
> - [VCS0] = MSG_IDLE_VCS0,
> - [VCS1] = MSG_IDLE_VCS1,
> - [VCS2] = MSG_IDLE_VCS2,
> - [VCS3] = MSG_IDLE_VCS3,
> - [VCS4] = MSG_IDLE_VCS4,
> - [VCS5] = MSG_IDLE_VCS5,
> - [VCS6] = MSG_IDLE_VCS6,
> - [VCS7] = MSG_IDLE_VCS7,
> - [VECS0] = MSG_IDLE_VECS0,
> - [VECS1] = MSG_IDLE_VECS1,
> - [VECS2] = MSG_IDLE_VECS2,
> - [VECS3] = MSG_IDLE_VECS3,
> - [CCS0] = MSG_IDLE_CS,
> - [CCS1] = MSG_IDLE_CS,
> - [CCS2] = MSG_IDLE_CS,
> - [CCS3] = MSG_IDLE_CS,
> - };
> - u32 val;
> -
> - if (!_reg[engine->id].reg)
> - return 0;
> -
> - val = intel_uncore_read(engine->uncore, _reg[engine->id]);
> -
> - /* bits[29:25] & bits[13:9] >> shift */
> - return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
> -}
> -
> -static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
> -{
> - int ret;
> -
> - /* Ensure GPM receives fw up/down after CS is stopped */
> - udelay(1);
> -
> - /* Wait for forcewake request to complete in GPM */
> - ret = __intel_wait_for_register_fw(gt->uncore,
> - GEN9_PWRGT_DOMAIN_STATUS,
> - fw_mask, fw_mask, 5000, 0, NULL);
> -
> - /* Ensure CS receives fw ack from GPM */
> - udelay(1);
> -
> - if (ret)
> - GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);
> -}
> -
> -/*
> - * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
> - * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
> - * pending status is indicated by bits[13:9] (masked by bits[ 29:25]) in the
> - * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
> - * are concerned only with the gt reset here, we use a logical OR of pending
> - * forcewakeups from all reset domains and then wait for them to complete by
> - * querying PWRGT_DOMAIN_STATUS.
> - */
> static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
> {
> - u32 fw_pending;
> -
> - if (GRAPHICS_VER(engine->i915) != 12)
> + if (!IS_GRAPHICS_VER(engine->i915, 11, 12))
> return;
>
> - /*
> - * Wa_22011802037
> - * TODO: Occasionally trying to stop the cs times out, but does not
> - * adversely affect functionality. The timeout is set as a config
> - * parameter that defaults to 100ms. Assuming that this timeout is
> - * sufficient for any pending MI_FORCEWAKEs to complete, ignore the
> - * timeout returned here until it is root caused.
> - */
> intel_engine_stop_cs(engine);
>
> - fw_pending = __cs_pending_mi_force_wakes(engine);
> - if (fw_pending)
> - __gpm_wait_for_fw_complete(engine->gt, fw_pending);
> + /*
> + * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
> + * to wait for any pending mi force wakeups
> + */
> + intel_engine_wait_for_pending_mi_fw(engine);
> }
>
> static void guc_reset_nop(struct intel_engine_cs *engine)
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend
@ 2022-05-10 22:14 Nerlige Ramappa, Umesh
2022-05-11 15:26 ` Tvrtko Ursulin
2022-06-09 23:51 ` Ceraolo Spurio, Daniele
0 siblings, 2 replies; 8+ messages in thread
From: Nerlige Ramappa, Umesh @ 2022-05-10 22:14 UTC (permalink / raw)
To: intel-gfx, Tvrtko Ursulin
From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
For execlists backend, current implementation of Wa_22011802037 is to
stop the CS before doing a reset of the engine. This WA was further
extended to wait for any pending MI FORCE WAKEUPs before issuing a
reset. Add the extended steps in the execlist path of reset.
In addition, extend the WA to gen11.
v2: (Tvrtko)
- Clarify comments, commit message, fix typos
- Use IS_GRAPHICS_VER for gen 11/12 checks
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Fixes: f6aa0d713c88 ("drm/i915: Add Wa_22011802037 force cs halt")
---
drivers/gpu/drm/i915/gt/intel_engine.h | 2 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 85 ++++++++++++++++++-
.../drm/i915/gt/intel_execlists_submission.c | 7 ++
.../gpu/drm/i915/gt/intel_ring_submission.c | 7 ++
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 81 ++----------------
6 files changed, 107 insertions(+), 79 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 1431f1e9dbee..04e435bce79b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -201,6 +201,8 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine);
int intel_engine_stop_cs(struct intel_engine_cs *engine);
void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
+void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine);
+
void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask);
u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 14c6ddbbfde8..9943cf9655b2 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1282,10 +1282,10 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
/*
- * Wa_22011802037 : gen12, Prior to doing a reset, ensure CS is
+ * Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is
* stopped, set ring stop bit and prefetch disable bit to halt CS
*/
- if (GRAPHICS_VER(engine->i915) == 12)
+ if (IS_GRAPHICS_VER(engine->i915, 11, 12))
intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
_MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
@@ -1308,6 +1308,18 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine)
return -ENODEV;
ENGINE_TRACE(engine, "\n");
+ /*
+ * TODO: Find out why occasionally stopping the CS times out. Seen
+ * especially with gem_eio tests.
+ *
+ * Occasionally trying to stop the cs times out, but does not adversely
+ * affect functionality. The timeout is set as a config parameter that
+ * defaults to 100ms. In most cases the follow up operation is to wait
+ * for pending MI_FORCE_WAKES. The assumption is that this timeout is
+ * sufficient for any pending MI_FORCEWAKEs to complete. Once root
+ * caused, the caller must check and handle the return from this
+ * function.
+ */
if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
ENGINE_TRACE(engine,
"timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n",
@@ -1334,6 +1346,75 @@ void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
}
+static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
+{
+ static const i915_reg_t _reg[I915_NUM_ENGINES] = {
+ [RCS0] = MSG_IDLE_CS,
+ [BCS0] = MSG_IDLE_BCS,
+ [VCS0] = MSG_IDLE_VCS0,
+ [VCS1] = MSG_IDLE_VCS1,
+ [VCS2] = MSG_IDLE_VCS2,
+ [VCS3] = MSG_IDLE_VCS3,
+ [VCS4] = MSG_IDLE_VCS4,
+ [VCS5] = MSG_IDLE_VCS5,
+ [VCS6] = MSG_IDLE_VCS6,
+ [VCS7] = MSG_IDLE_VCS7,
+ [VECS0] = MSG_IDLE_VECS0,
+ [VECS1] = MSG_IDLE_VECS1,
+ [VECS2] = MSG_IDLE_VECS2,
+ [VECS3] = MSG_IDLE_VECS3,
+ [CCS0] = MSG_IDLE_CS,
+ [CCS1] = MSG_IDLE_CS,
+ [CCS2] = MSG_IDLE_CS,
+ [CCS3] = MSG_IDLE_CS,
+ };
+ u32 val;
+
+ if (!_reg[engine->id].reg)
+ return 0;
+
+ val = intel_uncore_read(engine->uncore, _reg[engine->id]);
+
+ /* bits[29:25] & bits[13:9] >> shift */
+ return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
+}
+
+static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
+{
+ int ret;
+
+ /* Ensure GPM receives fw up/down after CS is stopped */
+ udelay(1);
+
+ /* Wait for forcewake request to complete in GPM */
+ ret = __intel_wait_for_register_fw(gt->uncore,
+ GEN9_PWRGT_DOMAIN_STATUS,
+ fw_mask, fw_mask, 5000, 0, NULL);
+
+ /* Ensure CS receives fw ack from GPM */
+ udelay(1);
+
+ if (ret)
+ GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);
+}
+
+/*
+ * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
+ * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
+ * pending status is indicated by bits[13:9] (masked by bits[29:25]) in the
+ * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
+ * are concerned only with the gt reset here, we use a logical OR of pending
+ * forcewakeups from all reset domains and then wait for them to complete by
+ * querying PWRGT_DOMAIN_STATUS.
+ */
+void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine)
+{
+ u32 fw_pending = __cs_pending_mi_force_wakes(engine);
+
+ if (fw_pending)
+ __gpm_wait_for_fw_complete(engine->gt, fw_pending);
+}
+
static u32
read_subslice_reg(const struct intel_engine_cs *engine,
int slice, int subslice, i915_reg_t reg)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 86f7a9ac1c39..2caa1af77064 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2958,6 +2958,13 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
ring_set_paused(engine, 1);
intel_engine_stop_cs(engine);
+ /*
+ * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
+ * to wait for any pending mi force wakeups
+ */
+ if (IS_GRAPHICS_VER(engine->i915, 11, 12))
+ intel_engine_wait_for_pending_mi_fw(engine);
+
engine->execlists.reset_ccid = active_ccid(engine);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 5423bfd301ad..a7808eff33c5 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -323,6 +323,13 @@ static void reset_prepare(struct intel_engine_cs *engine)
ENGINE_TRACE(engine, "\n");
intel_engine_stop_cs(engine);
+ /*
+ * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
+ * to wait for any pending mi force wakeups
+ */
+ if (IS_GRAPHICS_VER(engine->i915, 11, 12))
+ intel_engine_wait_for_pending_mi_fw(engine);
+
if (!stop_ring(engine)) {
/* G45 ring initialization often fails to reset head to zero */
ENGINE_TRACE(engine,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 2c4ad4a65089..8c6885f43d1a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -310,8 +310,8 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
if (IS_DG2(gt->i915))
flags |= GUC_WA_DUAL_QUEUE;
- /* Wa_22011802037: graphics version 12 */
- if (GRAPHICS_VER(gt->i915) == 12)
+ /* Wa_22011802037: graphics version 11/12 */
+ if (IS_GRAPHICS_VER(gt->i915, 11, 12))
flags |= GUC_WA_PRE_PARSER;
/* Wa_16011777198:dg2 */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 75291e9846c5..9b21c7345ffd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1527,87 +1527,18 @@ static void guc_reset_state(struct intel_context *ce, u32 head, bool scrub)
lrc_update_regs(ce, engine, head);
}
-static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
-{
- static const i915_reg_t _reg[I915_NUM_ENGINES] = {
- [RCS0] = MSG_IDLE_CS,
- [BCS0] = MSG_IDLE_BCS,
- [VCS0] = MSG_IDLE_VCS0,
- [VCS1] = MSG_IDLE_VCS1,
- [VCS2] = MSG_IDLE_VCS2,
- [VCS3] = MSG_IDLE_VCS3,
- [VCS4] = MSG_IDLE_VCS4,
- [VCS5] = MSG_IDLE_VCS5,
- [VCS6] = MSG_IDLE_VCS6,
- [VCS7] = MSG_IDLE_VCS7,
- [VECS0] = MSG_IDLE_VECS0,
- [VECS1] = MSG_IDLE_VECS1,
- [VECS2] = MSG_IDLE_VECS2,
- [VECS3] = MSG_IDLE_VECS3,
- [CCS0] = MSG_IDLE_CS,
- [CCS1] = MSG_IDLE_CS,
- [CCS2] = MSG_IDLE_CS,
- [CCS3] = MSG_IDLE_CS,
- };
- u32 val;
-
- if (!_reg[engine->id].reg)
- return 0;
-
- val = intel_uncore_read(engine->uncore, _reg[engine->id]);
-
- /* bits[29:25] & bits[13:9] >> shift */
- return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
-}
-
-static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
-{
- int ret;
-
- /* Ensure GPM receives fw up/down after CS is stopped */
- udelay(1);
-
- /* Wait for forcewake request to complete in GPM */
- ret = __intel_wait_for_register_fw(gt->uncore,
- GEN9_PWRGT_DOMAIN_STATUS,
- fw_mask, fw_mask, 5000, 0, NULL);
-
- /* Ensure CS receives fw ack from GPM */
- udelay(1);
-
- if (ret)
- GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);
-}
-
-/*
- * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
- * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
- * pending status is indicated by bits[13:9] (masked by bits[ 29:25]) in the
- * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
- * are concerned only with the gt reset here, we use a logical OR of pending
- * forcewakeups from all reset domains and then wait for them to complete by
- * querying PWRGT_DOMAIN_STATUS.
- */
static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
{
- u32 fw_pending;
-
- if (GRAPHICS_VER(engine->i915) != 12)
+ if (!IS_GRAPHICS_VER(engine->i915, 11, 12))
return;
- /*
- * Wa_22011802037
- * TODO: Occasionally trying to stop the cs times out, but does not
- * adversely affect functionality. The timeout is set as a config
- * parameter that defaults to 100ms. Assuming that this timeout is
- * sufficient for any pending MI_FORCEWAKEs to complete, ignore the
- * timeout returned here until it is root caused.
- */
intel_engine_stop_cs(engine);
- fw_pending = __cs_pending_mi_force_wakes(engine);
- if (fw_pending)
- __gpm_wait_for_fw_complete(engine->gt, fw_pending);
+ /*
+ * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
+ * to wait for any pending mi force wakeups
+ */
+ intel_engine_wait_for_pending_mi_fw(engine);
}
static void guc_reset_nop(struct intel_engine_cs *engine)
--
2.35.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-06-21 19:21 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-10 0:32 [Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend Nerlige Ramappa, Umesh
2022-06-10 1:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend (rev2) Patchwork
2022-06-10 8:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-06-11 8:10 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2022-06-21 19:21 [Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend Nerlige Ramappa, Umesh
2022-05-10 22:14 Nerlige Ramappa, Umesh
2022-05-11 15:26 ` Tvrtko Ursulin
2022-06-09 23:51 ` Ceraolo Spurio, Daniele
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