* [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk
@ 2022-10-26 23:22 Anusha Srivatsa
2022-10-26 23:22 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
` (5 more replies)
0 siblings, 6 replies; 17+ messages in thread
From: Anusha Srivatsa @ 2022-10-26 23:22 UTC (permalink / raw)
To: intel-gfx; +Cc: Balasubramani Vivekanandan
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
For MTL, changing cdclk from between certain frequencies has
both squash and crawl. Use the current cdclk config and
the new(desired) cdclk config to construtc a mid cdclk config.
Set the cdclk twice:
- Current cdclk -> mid cdclk
- mid cdclk -> desired cdclk
v2: Add check in intel_modeset_calc_cdclk() to avoid cdclk
change via modeset for platforms that support squash_crawl sequences(Ville)
v3: Add checks for:
- scenario where only slow clock is used and
cdclk is actually 0 (bringing up display).
- PLLs are on before looking up the waveform.
- Squash and crawl capability checks.(Ville)
v4: Rebase
- Move checks to be more consistent (Ville)
- Add comments (Bala)
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 157 +++++++++++++++++----
1 file changed, 129 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index eada931cb1c8..6a775367f02a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1716,37 +1716,74 @@ static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
}
-static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_config *cdclk_config,
- enum pipe pipe)
+static int cdclk_squash_divider(u16 waveform)
+{
+ return hweight16(waveform ?: 0xffff);
+}
+
+static bool cdclk_crawl_and_squash(struct drm_i915_private *i915,
+ const struct intel_cdclk_config *old_cdclk_config,
+ const struct intel_cdclk_config *new_cdclk_config,
+ struct intel_cdclk_config *mid_cdclk_config)
+{
+ u16 old_waveform, new_waveform, mid_waveform;
+ int size = 16;
+ int div = 2;
+
+ /* Return if both Squash and Crawl are not present */
+ if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
+ return false;
+
+ /* Return if Squash only or Crawl only is the desired action */
+ if (old_cdclk_config->vco <= 0 || new_cdclk_config->vco <= 0 ||
+ old_cdclk_config->vco == new_cdclk_config->vco ||
+ old_waveform == new_waveform)
+ return false;
+
+ old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk);
+ new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk);
+
+ *mid_cdclk_config = *new_cdclk_config;
+
+ /* Populate the mid_cdclk_config accordingly.
+ * - If moving to a higher cdclk, the desired action is squashing.
+ * The mid cdclk config should have the new (squash) waveform.
+ * - If moving to a lower cdclk, the desired action is crawling.
+ * The mid cdclk config should have the new vco.
+ */
+
+ if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) {
+ mid_cdclk_config->vco = old_cdclk_config->vco;
+ mid_waveform = new_waveform;
+ } else {
+ mid_cdclk_config->vco = new_cdclk_config->vco;
+ mid_waveform = old_waveform;
+ }
+
+ mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
+ mid_cdclk_config->vco, size * div);
+
+ /* make sure the mid clock came out sane */
+
+ drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk <
+ min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
+ drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk >
+ i915->display.cdclk.max_cdclk_freq);
+ drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) !=
+ mid_waveform);
+
+ return true;
+}
+
+static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_config *cdclk_config,
+ enum pipe pipe)
{
int cdclk = cdclk_config->cdclk;
int vco = cdclk_config->vco;
u32 val;
u16 waveform;
int clock;
- int ret;
-
- /* Inform power controller of upcoming frequency change. */
- if (DISPLAY_VER(dev_priv) >= 11)
- ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
- SKL_CDCLK_PREPARE_FOR_CHANGE,
- SKL_CDCLK_READY_FOR_CHANGE,
- SKL_CDCLK_READY_FOR_CHANGE, 3);
- else
- /*
- * BSpec requires us to wait up to 150usec, but that leads to
- * timeouts; the 2ms used here is based on experiment.
- */
- ret = snb_pcode_write_timeout(&dev_priv->uncore,
- HSW_PCODE_DE_WRITE_FREQ_REQ,
- 0x80000000, 150, 2);
- if (ret) {
- drm_err(&dev_priv->drm,
- "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
- ret, cdclk);
- return;
- }
if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0) {
if (dev_priv->display.cdclk.hw.vco != vco)
@@ -1781,6 +1818,44 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
if (pipe != INVALID_PIPE)
intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
+}
+
+static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_config *cdclk_config,
+ enum pipe pipe)
+{
+ struct intel_cdclk_config mid_cdclk_config;
+ int cdclk = cdclk_config->cdclk;
+ int ret;
+
+ /* Inform power controller of upcoming frequency change. */
+ if (DISPLAY_VER(dev_priv) >= 11)
+ ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
+ SKL_CDCLK_PREPARE_FOR_CHANGE,
+ SKL_CDCLK_READY_FOR_CHANGE,
+ SKL_CDCLK_READY_FOR_CHANGE, 3);
+ else
+ /*
+ * BSpec requires us to wait up to 150usec, but that leads to
+ * timeouts; the 2ms used here is based on experiment.
+ */
+ ret = snb_pcode_write_timeout(&dev_priv->uncore,
+ HSW_PCODE_DE_WRITE_FREQ_REQ,
+ 0x80000000, 150, 2);
+ if (ret) {
+ drm_err(&dev_priv->drm,
+ "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
+ ret, cdclk);
+ return;
+ }
+
+ if (cdclk_crawl_and_squash(dev_priv, &dev_priv->display.cdclk.hw,
+ cdclk_config, &mid_cdclk_config)) {
+ _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe);
+ _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
+ } else {
+ _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
+ }
if (DISPLAY_VER(dev_priv) >= 11) {
ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
@@ -1953,6 +2028,27 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
skl_cdclk_uninit_hw(i915);
}
+static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private *i915,
+ const struct intel_cdclk_config *a,
+ const struct intel_cdclk_config *b)
+{
+ u16 old_waveform;
+ u16 new_waveform;
+
+ if (a->vco == 0 || b->vco == 0)
+ return false;
+
+ if (HAS_CDCLK_CRAWL(i915) && HAS_CDCLK_SQUASH(i915)) {
+ old_waveform = cdclk_squash_waveform(i915, a->cdclk);
+ new_waveform = cdclk_squash_waveform(i915, b->cdclk);
+ } else {
+ return false;
+ }
+
+ return a->vco != b->vco &&
+ old_waveform != new_waveform;
+}
+
static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *a,
const struct intel_cdclk_config *b)
@@ -2759,9 +2855,14 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
pipe = INVALID_PIPE;
}
- if (intel_cdclk_can_squash(dev_priv,
- &old_cdclk_state->actual,
- &new_cdclk_state->actual)) {
+ if (intel_cdclk_can_crawl_and_squash(dev_priv,
+ &old_cdclk_state->actual,
+ &new_cdclk_state->actual)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Can change cdclk via crawling and squashing\n");
+ } else if (intel_cdclk_can_squash(dev_priv,
+ &old_cdclk_state->actual,
+ &new_cdclk_state->actual)) {
drm_dbg_kms(&dev_priv->drm,
"Can change cdclk via squashing\n");
} else if (intel_cdclk_can_crawl(dev_priv,
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
2022-10-26 23:22 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
@ 2022-10-26 23:22 ` Anusha Srivatsa
2022-10-27 5:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk Patchwork
` (4 subsequent siblings)
5 siblings, 0 replies; 17+ messages in thread
From: Anusha Srivatsa @ 2022-10-26 23:22 UTC (permalink / raw)
To: intel-gfx
As per bSpec MTL has 38.4 MHz Reference clock.
MTL does support squasher like DG2 but only for lower
frequencies. Change the has_cdclk_squasher()
helper to reflect this.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 6a775367f02a..28253cb310ca 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1345,6 +1345,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals mtl_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -3160,6 +3170,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level,
+};
+
static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3295,7 +3312,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_DG2(dev_priv)) {
+ if (IS_METEORLAKE(dev_priv)) {
+ dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+ dev_priv->display.cdclk.table = mtl_cdclk_table;
+ } else if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk
2022-10-26 23:22 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
2022-10-26 23:22 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
@ 2022-10-27 5:11 ` Patchwork
2022-10-27 17:16 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (3 subsequent siblings)
5 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2022-10-27 5:11 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 12023 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk
URL : https://patchwork.freedesktop.org/series/110199/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12304 -> Patchwork_110199v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/index.html
Participating hosts (39 -> 38)
------------------------------
Additional (2): fi-rkl-11600 fi-icl-u2
Missing (3): fi-ctg-p8600 fi-hsw-4770 fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_110199v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}: [DMESG-WARN][1] ([i915#5537]) -> [WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/bat-rpls-2/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/bat-rpls-2/igt@i915_pm_rpm@module-reload.html
Known issues
------------
Here are the changes found in Patchwork_110199v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-rkl-11600: NOTRUN -> [SKIP][3] ([i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html
- fi-icl-u2: NOTRUN -> [SKIP][4] ([i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-rkl-11600: NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-11600/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-icl-u2/igt@gem_lmem_swapping@random-engines.html
* igt@gem_tiled_pread_basic:
- fi-rkl-11600: NOTRUN -> [SKIP][7] ([i915#3282])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- fi-rkl-11600: NOTRUN -> [SKIP][8] ([i915#3012])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-11600/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258: [PASS][9] -> [INCOMPLETE][10] ([i915#3303] / [i915#4785])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: NOTRUN -> [INCOMPLETE][11] ([i915#4817])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-rkl-guc: NOTRUN -> [SKIP][12] ([fdo#111827])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-guc/igt@kms_chamelium@common-hpd-after-suspend.html
- bat-adlp-4: NOTRUN -> [SKIP][13] ([fdo#111827])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/bat-adlp-4/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-rkl-11600: NOTRUN -> [SKIP][14] ([fdo#111827]) +7 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-11600/igt@kms_chamelium@hdmi-hpd-fast.html
- fi-icl-u2: NOTRUN -> [SKIP][15] ([fdo#111827]) +8 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-rkl-11600: NOTRUN -> [SKIP][16] ([i915#4103])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html
- fi-icl-u2: NOTRUN -> [SKIP][17] ([i915#4103])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-rkl-11600: NOTRUN -> [SKIP][18] ([fdo#109285] / [i915#4098])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html
- fi-icl-u2: NOTRUN -> [SKIP][19] ([fdo#109285])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlp-4: NOTRUN -> [SKIP][20] ([i915#3546])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/bat-adlp-4/igt@kms_pipe_crc_basic@suspend-read-crc.html
* igt@kms_psr@sprite_plane_onoff:
- fi-rkl-11600: NOTRUN -> [SKIP][21] ([i915#1072]) +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-11600/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-rkl-11600: NOTRUN -> [SKIP][22] ([i915#3555] / [i915#4098])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-11600/igt@kms_setmode@basic-clone-single-crtc.html
- fi-icl-u2: NOTRUN -> [SKIP][23] ([i915#3555])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-icl-u2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-read:
- fi-rkl-11600: NOTRUN -> [SKIP][24] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-11600/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-userptr:
- fi-icl-u2: NOTRUN -> [SKIP][25] ([fdo#109295] / [i915#3301])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-icl-u2/igt@prime_vgem@basic-userptr.html
- fi-rkl-11600: NOTRUN -> [SKIP][26] ([fdo#109295] / [i915#3301] / [i915#3708])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-11600/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-hsw-g3258: NOTRUN -> [FAIL][27] ([fdo#109271] / [i915#4312] / [i915#4991])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-hsw-g3258/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rplp-1}: [DMESG-WARN][28] ([i915#2867]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/bat-rplp-1/igt@gem_exec_suspend@basic-s0@smem.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/bat-rplp-1/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-rpls-1}: [DMESG-WARN][30] ([i915#6687]) -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_selftest@live@gt_lrc:
- fi-rkl-guc: [INCOMPLETE][32] ([i915#4983]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@hangcheck:
- {bat-dg2-9}: [INCOMPLETE][34] -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/bat-dg2-9/igt@i915_selftest@live@hangcheck.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/bat-dg2-9/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@migrate:
- bat-adlp-4: [INCOMPLETE][36] ([i915#7308]) -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/bat-adlp-4/igt@i915_selftest@live@migrate.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/bat-adlp-4/igt@i915_selftest@live@migrate.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka: [FAIL][38] ([i915#6298]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5134]: https://gitlab.freedesktop.org/drm/intel/issues/5134
[i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7308]: https://gitlab.freedesktop.org/drm/intel/issues/7308
Build changes
-------------
* Linux: CI_DRM_12304 -> Patchwork_110199v1
CI-20190529: 20190529
CI_DRM_12304: 29da184cfd1f57054340b6452921f79af68a1a44 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7027: e38045c24405e70fed6cfeec2f616454c68e6512 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_110199v1: 29da184cfd1f57054340b6452921f79af68a1a44 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
4a3470db5401 drm/i915/display: Add CDCLK Support for MTL
46fe690d63e7 drm/i915/display: Do both crawl and squash when changing cdclk
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/index.html
[-- Attachment #2: Type: text/html, Size: 13974 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk
2022-10-26 23:22 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
2022-10-26 23:22 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
2022-10-27 5:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk Patchwork
@ 2022-10-27 17:16 ` Patchwork
2022-10-27 20:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk (rev2) Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2022-10-27 17:16 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 34624 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk
URL : https://patchwork.freedesktop.org/series/110199/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12304_full -> Patchwork_110199v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_110199v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_110199v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_110199v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_create@hog-create@smem0:
- shard-apl: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-apl3/igt@gem_create@hog-create@smem0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-apl1/igt@gem_create@hog-create@smem0.html
#### Warnings ####
* igt@i915_pm_lpsp@screens-disabled:
- shard-tglb: [SKIP][3] ([i915#1902]) -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-tglb2/igt@i915_pm_lpsp@screens-disabled.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-tglb8/igt@i915_pm_lpsp@screens-disabled.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_cursor_legacy@short-flip-before-cursor:
- {shard-dg1}: NOTRUN -> [INCOMPLETE][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-dg1-16/igt@kms_cursor_legacy@short-flip-before-cursor.html
Known issues
------------
Here are the changes found in Patchwork_110199v1_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-glk: ([PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30]) -> ([PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [FAIL][52], [PASS][53], [PASS][54], [PASS][55]) ([i915#4392])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk9/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk9/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk9/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk8/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk8/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk8/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk7/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk7/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk7/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk6/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk6/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk6/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk5/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk5/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk5/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk3/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk3/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk3/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk3/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk2/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk2/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk2/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk1/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk1/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk1/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk9/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk9/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk9/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk8/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk8/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk8/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk7/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk7/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk7/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk6/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk6/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk6/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk5/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk5/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk3/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk3/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk3/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk3/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk2/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk2/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk2/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk2/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk1/boot.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk1/boot.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk1/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_balancer@parallel-contexts:
- shard-iclb: [PASS][56] -> [SKIP][57] ([i915#4525])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-iclb2/igt@gem_exec_balancer@parallel-contexts.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-iclb3/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][58] -> [FAIL][59] ([i915#2842]) +3 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk9/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs:
- shard-skl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#4613])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-skl6/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-glk: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#4613])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk7/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_userptr_blits@probe:
- shard-skl: NOTRUN -> [FAIL][62] ([i915#7224] / [i915#7247])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-skl7/igt@gem_userptr_blits@probe.html
* igt@i915_pm_dc@dc6-dpms:
- shard-skl: NOTRUN -> [FAIL][63] ([i915#454])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-skl6/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- shard-skl: [PASS][64] -> [WARN][65] ([i915#1804])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-skl6/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-skl9/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#3886]) +3 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk7/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#3886]) +4 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-skl6/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@hdmi-crc-nonplanar-formats:
- shard-glk: NOTRUN -> [SKIP][68] ([fdo#109271] / [fdo#111827]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk7/igt@kms_chamelium@hdmi-crc-nonplanar-formats.html
* igt@kms_chamelium@hdmi-hpd-with-enabled-mode:
- shard-skl: NOTRUN -> [SKIP][69] ([fdo#109271] / [fdo#111827]) +2 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-skl7/igt@kms_chamelium@hdmi-hpd-with-enabled-mode.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [PASS][70] -> [FAIL][71] ([i915#79])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@plain-flip-ts-check@c-edp1:
- shard-skl: [PASS][72] -> [FAIL][73] ([i915#2122]) +2 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-skl1/igt@kms_flip@plain-flip-ts-check@c-edp1.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-skl3/igt@kms_flip@plain-flip-ts-check@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][74] ([i915#2587] / [i915#2672]) +2 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-iclb7/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][75] ([i915#2672]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
- shard-glk: NOTRUN -> [SKIP][76] ([fdo#109271]) +33 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-skl: NOTRUN -> [SKIP][77] ([fdo#109271]) +88 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-skl7/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1:
- shard-iclb: [PASS][78] -> [SKIP][79] ([i915#5235]) +5 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-iclb3/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html
* igt@kms_prop_blob@basic:
- shard-skl: [PASS][80] -> [DMESG-WARN][81] ([i915#1982]) +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-skl9/igt@kms_prop_blob@basic.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-skl9/igt@kms_prop_blob@basic.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-skl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#658])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-skl6/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-p010:
- shard-glk: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#658])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk7/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][84] -> [SKIP][85] ([fdo#109441]) +2 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: [PASS][86] -> [DMESG-WARN][87] ([i915#180])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-apl6/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-apl3/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@perf@polling-small-buf:
- shard-skl: NOTRUN -> [FAIL][88] ([i915#1722])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-skl6/igt@perf@polling-small-buf.html
* igt@perf@stress-open-close:
- shard-glk: [PASS][89] -> [INCOMPLETE][90] ([i915#5213])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk1/igt@perf@stress-open-close.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk8/igt@perf@stress-open-close.html
* igt@sysfs_clients@pidname:
- shard-skl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#2994])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-skl7/igt@sysfs_clients@pidname.html
#### Possible fixes ####
* igt@fbdev@eof:
- {shard-rkl}: [SKIP][92] ([i915#2582]) -> [PASS][93] +1 similar issue
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-rkl-1/igt@fbdev@eof.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-rkl-6/igt@fbdev@eof.html
* igt@gem_ctx_persistence@legacy-engines-hang@blt:
- {shard-rkl}: [SKIP][94] ([i915#6252]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-rkl-5/igt@gem_ctx_persistence@legacy-engines-hang@blt.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-rkl-3/igt@gem_ctx_persistence@legacy-engines-hang@blt.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [SKIP][96] ([i915#4525]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-iclb6/igt@gem_exec_balancer@parallel-bb-first.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-iclb2/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [FAIL][98] ([i915#2842]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk2/igt@gem_exec_fair@basic-none-share@rcs0.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk2/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_reloc@basic-gtt-read-noreloc:
- {shard-rkl}: [SKIP][100] ([i915#3281]) -> [PASS][101] +12 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-rkl-3/igt@gem_exec_reloc@basic-gtt-read-noreloc.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-rkl-5/igt@gem_exec_reloc@basic-gtt-read-noreloc.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][102] ([i915#2190]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-tglb6/igt@gem_huc_copy@huc-copy.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-tglb3/igt@gem_huc_copy@huc-copy.html
* igt@gem_readwrite@new-obj:
- {shard-rkl}: [SKIP][104] ([i915#3282]) -> [PASS][105] +2 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-rkl-6/igt@gem_readwrite@new-obj.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-rkl-5/igt@gem_readwrite@new-obj.html
* igt@gem_workarounds@suspend-resume-fd:
- {shard-rkl}: [DMESG-WARN][106] ([i915#5122]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-rkl-3/igt@gem_workarounds@suspend-resume-fd.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-rkl-5/igt@gem_workarounds@suspend-resume-fd.html
* igt@gen9_exec_parse@secure-batches:
- {shard-rkl}: [SKIP][108] ([i915#2527]) -> [PASS][109] +4 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-rkl-1/igt@gen9_exec_parse@secure-batches.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-rkl-5/igt@gen9_exec_parse@secure-batches.html
* igt@i915_pm_rpm@system-suspend:
- {shard-rkl}: [FAIL][110] ([fdo#103375]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-rkl-4/igt@i915_pm_rpm@system-suspend.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-rkl-1/igt@i915_pm_rpm@system-suspend.html
* igt@kms_cursor_legacy@cursor-vs-flip@toggle:
- shard-glk: [DMESG-WARN][112] ([i915#118]) -> [PASS][113] +1 similar issue
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk6/igt@kms_cursor_legacy@cursor-vs-flip@toggle.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk1/igt@kms_cursor_legacy@cursor-vs-flip@toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-glk: [FAIL][114] ([i915#2346]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [FAIL][116] ([i915#2122]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- {shard-rkl}: [SKIP][118] ([i915#1849] / [i915#4098]) -> [PASS][119] +10 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1:
- shard-iclb: [SKIP][120] ([i915#5235]) -> [PASS][121] +2 similar issues
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-iclb2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-iclb8/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1.html
* igt@kms_psr@primary_blt:
- {shard-rkl}: [SKIP][122] ([i915#1072]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-rkl-4/igt@kms_psr@primary_blt.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-rkl-6/igt@kms_psr@primary_blt.html
* igt@kms_psr@psr2_primary_blt:
- shard-iclb: [SKIP][124] ([fdo#109441]) -> [PASS][125] +1 similar issue
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-iclb6/igt@kms_psr@psr2_primary_blt.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-iclb2/igt@kms_psr@psr2_primary_blt.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-tglb: [SKIP][126] ([i915#5519]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-tglb1/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-tglb7/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_vblank@pipe-b-ts-continuation-idle:
- {shard-rkl}: [SKIP][128] ([i915#1845] / [i915#4098]) -> [PASS][129] +19 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-rkl-4/igt@kms_vblank@pipe-b-ts-continuation-idle.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-rkl-6/igt@kms_vblank@pipe-b-ts-continuation-idle.html
* igt@perf@gen12-mi-rpc:
- {shard-rkl}: [SKIP][130] ([fdo#109289]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-rkl-5/igt@perf@gen12-mi-rpc.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-rkl-4/igt@perf@gen12-mi-rpc.html
* igt@perf@polling-small-buf:
- {shard-rkl}: [FAIL][132] ([i915#1722]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-rkl-4/igt@perf@polling-small-buf.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-rkl-6/igt@perf@polling-small-buf.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [FAIL][134] ([i915#6117]) -> [SKIP][135] ([i915#4525])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-iclb5/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_pwrite@basic-exhaustion:
- shard-glk: [WARN][136] ([i915#2658]) -> [INCOMPLETE][137] ([i915#7248])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-glk3/igt@gem_pwrite@basic-exhaustion.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-glk7/igt@gem_pwrite@basic-exhaustion.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][138] ([i915#588]) -> [SKIP][139] ([i915#658])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-iclb6/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_dc@dc6-psr:
- shard-skl: [FAIL][140] ([i915#454]) -> [INCOMPLETE][141] ([i915#1982])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-skl9/igt@i915_pm_dc@dc6-psr.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-skl9/igt@i915_pm_dc@dc6-psr.html
* igt@kms_cursor_legacy@cursor-vs-flip@atomic-transitions-varying-size:
- shard-skl: [INCOMPLETE][142] -> [INCOMPLETE][143] ([i915#7096])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-skl5/igt@kms_cursor_legacy@cursor-vs-flip@atomic-transitions-varying-size.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-skl4/igt@kms_cursor_legacy@cursor-vs-flip@atomic-transitions-varying-size.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-iclb: [SKIP][144] ([i915#2920]) -> [SKIP][145] ([i915#658])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-iclb3/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][146] ([fdo#111068] / [i915#658]) -> [SKIP][147] ([i915#2920]) +1 similar issue
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/shard-iclb6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2232]: https://gitlab.freedesktop.org/drm/intel/issues/2232
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2532]: https://gitlab.freedesktop.org/drm/intel/issues/2532
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3639]: https://gitlab.freedesktop.org/drm/intel/issues/3639
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4392]: https://gitlab.freedesktop.org/drm/intel/issues/4392
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
[i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052
[i915#7096]: https://gitlab.freedesktop.org/drm/intel/issues/7096
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7224]: https://gitlab.freedesktop.org/drm/intel/issues/7224
[i915#7247]: https://gitlab.freedesktop.org/drm/intel/issues/7247
[i915#7248]: https://gitlab.freedesktop.org/drm/intel/issues/7248
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12304 -> Patchwork_110199v1
CI-20190529: 20190529
CI_DRM_12304: 29da184cfd1f57054340b6452921f79af68a1a44 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7027: e38045c24405e70fed6cfeec2f616454c68e6512 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_110199v1: 29da184cfd1f57054340b6452921f79af68a1a44 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v1/index.html
[-- Attachment #2: Type: text/html, Size: 33988 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk (rev2)
2022-10-26 23:22 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
` (2 preceding siblings ...)
2022-10-27 17:16 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2022-10-27 20:32 ` Patchwork
2022-10-28 8:11 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-10-28 9:05 ` [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Ville Syrjälä
5 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2022-10-27 20:32 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7581 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk (rev2)
URL : https://patchwork.freedesktop.org/series/110199/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12311 -> Patchwork_110199v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/index.html
Participating hosts (43 -> 40)
------------------------------
Missing (3): fi-kbl-soraka fi-ctg-p8600 bat-atsm-1
Known issues
------------
Here are the changes found in Patchwork_110199v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@unbind-rebind:
- fi-icl-u2: NOTRUN -> [DMESG-WARN][1] ([i915#4890])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
* igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u: [PASS][2] -> [DMESG-FAIL][3] ([i915#62])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@guc_multi_lrc:
- fi-cfl-8109u: [PASS][4] -> [DMESG-WARN][5] ([i915#5904] / [i915#7174]) +2 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/fi-cfl-8109u/igt@i915_selftest@live@guc_multi_lrc.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/fi-cfl-8109u/igt@i915_selftest@live@guc_multi_lrc.html
* igt@i915_selftest@live@late_gt_pm:
- fi-cfl-8109u: [PASS][6] -> [DMESG-WARN][7] ([i915#5904]) +27 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u: [PASS][8] -> [DMESG-WARN][9] ([i915#5904] / [i915#62])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/fi-cfl-8109u/igt@i915_suspend@basic-s2idle-without-i915.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/fi-cfl-8109u/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@kms_addfb_basic@too-high:
- fi-cfl-8109u: [PASS][10] -> [DMESG-WARN][11] ([i915#62]) +80 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/fi-cfl-8109u/igt@kms_addfb_basic@too-high.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/fi-cfl-8109u/igt@kms_addfb_basic@too-high.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/fi-hsw-4770/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2: NOTRUN -> [SKIP][13] ([fdo#109285])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2: NOTRUN -> [SKIP][14] ([i915#3555])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/fi-icl-u2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-userptr:
- fi-icl-u2: NOTRUN -> [SKIP][15] ([fdo#109295] / [i915#3301])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/fi-icl-u2/igt@prime_vgem@basic-userptr.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-adlm-1}: [DMESG-WARN][16] ([i915#2867]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [INCOMPLETE][18] ([i915#4785]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@migrate:
- {bat-dg2-11}: [DMESG-WARN][20] -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/bat-dg2-11/igt@i915_selftest@live@migrate.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/bat-dg2-11/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@slpc:
- {bat-rpls-1}: [DMESG-FAIL][22] ([i915#6367] / [i915#6997]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/bat-rpls-1/igt@i915_selftest@live@slpc.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/bat-rpls-1/igt@i915_selftest@live@slpc.html
* igt@kms_cursor_legacy@basic-flip-before-cursor@varying-size:
- fi-icl-u2: [DMESG-WARN][24] ([i915#4890]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor@varying-size.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor@varying-size.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4890]: https://gitlab.freedesktop.org/drm/intel/issues/4890
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5278]: https://gitlab.freedesktop.org/drm/intel/issues/5278
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5904]: https://gitlab.freedesktop.org/drm/intel/issues/5904
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7174]: https://gitlab.freedesktop.org/drm/intel/issues/7174
Build changes
-------------
* Linux: CI_DRM_12311 -> Patchwork_110199v2
CI-20190529: 20190529
CI_DRM_12311: 7e39cc6b9ee11e867ec5bd4910b65cefa7c644cc @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7028: 9e635a1c502970e7e6d64112d409392a2f01c688 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_110199v2: 7e39cc6b9ee11e867ec5bd4910b65cefa7c644cc @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
87a73c742bd2 drm/i915/display: Add CDCLK Support for MTL
b8ee837eb1e3 drm/i915/display: Do both crawl and squash when changing cdclk
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/index.html
[-- Attachment #2: Type: text/html, Size: 8626 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk (rev2)
2022-10-26 23:22 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
` (3 preceding siblings ...)
2022-10-27 20:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk (rev2) Patchwork
@ 2022-10-28 8:11 ` Patchwork
2022-10-28 9:05 ` [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Ville Syrjälä
5 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2022-10-28 8:11 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 52672 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk (rev2)
URL : https://patchwork.freedesktop.org/series/110199/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12311_full -> Patchwork_110199v2_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_110199v2_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_110199v2_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 11)
------------------------------
Additional (2): shard-rkl shard-dg1
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_110199v2_full:
### IGT changes ###
#### Warnings ####
* igt@runner@aborted:
- shard-skl: ([FAIL][1], [FAIL][2], [FAIL][3], [FAIL][4], [FAIL][5], [FAIL][6], [FAIL][7], [FAIL][8]) ([i915#3002] / [i915#4312] / [i915#6949]) -> ([FAIL][9], [FAIL][10], [FAIL][11], [FAIL][12], [FAIL][13], [FAIL][14], [FAIL][15]) ([i915#3002] / [i915#4312])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-skl7/igt@runner@aborted.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-skl9/igt@runner@aborted.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-skl7/igt@runner@aborted.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-skl9/igt@runner@aborted.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-skl7/igt@runner@aborted.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-skl1/igt@runner@aborted.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-skl4/igt@runner@aborted.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-skl6/igt@runner@aborted.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl9/igt@runner@aborted.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl9/igt@runner@aborted.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl9/igt@runner@aborted.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl7/igt@runner@aborted.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl9/igt@runner@aborted.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl6/igt@runner@aborted.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl6/igt@runner@aborted.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_pwrite@basic-exhaustion:
- {shard-rkl}: NOTRUN -> [INCOMPLETE][16] +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-rkl-5/igt@gem_pwrite@basic-exhaustion.html
New tests
---------
New tests have been introduced between CI_DRM_12311_full and Patchwork_110199v2_full:
### New IGT tests (1) ###
* igt@kms_content_protection@legacy@pipe-c-dp-1:
- Statuses : 1 dmesg-fail(s)
- Exec time: [95.75] s
Known issues
------------
Here are the changes found in Patchwork_110199v2_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-glk: ([PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41]) -> ([PASS][42], [FAIL][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66]) ([i915#4392])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk1/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk1/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk1/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk9/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk9/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk9/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk8/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk8/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk8/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk7/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk7/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk7/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk6/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk6/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk6/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk1/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk5/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk5/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk5/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk3/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk3/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk3/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk2/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk2/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk2/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk1/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk1/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk1/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk1/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk9/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk9/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk8/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk8/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk8/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk7/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk7/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk7/boot.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk7/boot.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk6/boot.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk6/boot.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk6/boot.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk5/boot.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk5/boot.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk5/boot.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk3/boot.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk3/boot.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk3/boot.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk2/boot.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk2/boot.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk2/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-iclb: [PASS][67] -> [SKIP][68] ([i915#4525])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb2/igt@gem_exec_balancer@parallel-keep-submit-fence.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb8/igt@gem_exec_balancer@parallel-keep-submit-fence.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][69] -> [FAIL][70] ([i915#2842])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-tglb: NOTRUN -> [FAIL][71] ([i915#2842])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-skl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#4613])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl6/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-tglb: NOTRUN -> [SKIP][73] ([i915#4613])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@verify-random-ccs:
- shard-apl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#4613]) +3 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-apl6/igt@gem_lmem_swapping@verify-random-ccs.html
* igt@gem_media_vme:
- shard-tglb: NOTRUN -> [SKIP][75] ([i915#284])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@gem_media_vme.html
* igt@gem_softpin@evict-single-offset:
- shard-tglb: [PASS][76] -> [FAIL][77] ([i915#4171])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-tglb7/igt@gem_softpin@evict-single-offset.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb3/igt@gem_softpin@evict-single-offset.html
* igt@gem_userptr_blits@input-checking:
- shard-tglb: NOTRUN -> [DMESG-WARN][78] ([i915#4991])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb5/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@unsync-unmap:
- shard-tglb: NOTRUN -> [SKIP][79] ([i915#3297])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@gem_userptr_blits@unsync-unmap.html
* igt@gen3_render_tiledx_blits:
- shard-tglb: NOTRUN -> [SKIP][80] ([fdo#109289])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@gen3_render_tiledx_blits.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][81] -> [DMESG-WARN][82] ([i915#5566] / [i915#716])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk9/igt@gen9_exec_parse@allowed-single.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk8/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-secure:
- shard-tglb: NOTRUN -> [SKIP][83] ([i915#2527] / [i915#2856])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@gen9_exec_parse@bb-secure.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][84] -> [FAIL][85] ([i915#3989] / [i915#454])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_freq_mult@media-freq@gt0:
- shard-tglb: NOTRUN -> [SKIP][86] ([i915#6590])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@i915_pm_freq_mult@media-freq@gt0.html
* igt@i915_pm_rps@engine-order:
- shard-apl: [PASS][87] -> [FAIL][88] ([i915#6537])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-apl8/igt@i915_pm_rps@engine-order.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-apl1/igt@i915_pm_rps@engine-order.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-skl: [PASS][89] -> [DMESG-FAIL][90] ([i915#5334])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-skl4/igt@i915_selftest@live@gt_heartbeat.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl10/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-90:
- shard-apl: NOTRUN -> [SKIP][91] ([fdo#109271]) +72 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-apl2/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-tglb: NOTRUN -> [SKIP][92] ([i915#5286]) +1 similar issue
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][93] ([fdo#111614])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
- shard-skl: NOTRUN -> [SKIP][94] ([fdo#109271]) +29 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl7/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-tglb: NOTRUN -> [SKIP][95] ([fdo#111615])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][96] ([i915#3689] / [i915#3886]) +1 similar issue
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#3886]) +5 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-apl2/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][98] ([i915#3689]) +1 similar issue
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc:
- shard-tglb: NOTRUN -> [SKIP][99] ([i915#6095])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@kms_ccs@pipe-b-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-primary-basic-4_tiled_dg2_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][100] ([i915#3689] / [i915#6095])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@kms_ccs@pipe-c-crc-primary-basic-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][101] ([fdo#109271] / [i915#3886]) +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl7/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-bad-aux-stride-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][102] ([fdo#111615] / [i915#3689]) +1 similar issue
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@kms_ccs@pipe-d-bad-aux-stride-yf_tiled_ccs.html
* igt@kms_cdclk@mode-transition:
- shard-glk: NOTRUN -> [SKIP][103] ([fdo#109271]) +37 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk3/igt@kms_cdclk@mode-transition.html
* igt@kms_cdclk@plane-scaling:
- shard-tglb: NOTRUN -> [SKIP][104] ([i915#3742])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@kms_cdclk@plane-scaling.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-glk: NOTRUN -> [SKIP][105] ([fdo#109271] / [fdo#111827])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk3/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_color_chamelium@ctm-0-50:
- shard-tglb: NOTRUN -> [SKIP][106] ([fdo#109284] / [fdo#111827]) +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@kms_color_chamelium@ctm-0-50.html
* igt@kms_color_chamelium@ctm-blue-to-red:
- shard-apl: NOTRUN -> [SKIP][107] ([fdo#109271] / [fdo#111827]) +5 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-apl6/igt@kms_color_chamelium@ctm-blue-to-red.html
* igt@kms_content_protection@atomic@pipe-a-dp-1:
- shard-apl: NOTRUN -> [INCOMPLETE][108] ([i915#7121] / [i915#7173])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-apl2/igt@kms_content_protection@atomic@pipe-a-dp-1.html
* {igt@kms_content_protection@legacy@pipe-c-dp-1} (NEW):
- shard-apl: NOTRUN -> [DMESG-FAIL][109] ([i915#62])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-apl8/igt@kms_content_protection@legacy@pipe-c-dp-1.html
* igt@kms_cursor_crc@cursor-onscreen-32x32:
- shard-tglb: NOTRUN -> [SKIP][110] ([i915#3555]) +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@kms_cursor_crc@cursor-onscreen-32x32.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
- shard-tglb: NOTRUN -> [SKIP][111] ([fdo#109274] / [fdo#111825]) +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-glk: [PASS][112] -> [FAIL][113] ([i915#2346])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_flip@2x-flip-vs-suspend-interruptible:
- shard-tglb: NOTRUN -> [SKIP][114] ([fdo#109274] / [fdo#111825] / [i915#3637]) +1 similar issue
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@kms_flip@2x-flip-vs-suspend-interruptible.html
* igt@kms_flip@plain-flip-fb-recreate@c-edp1:
- shard-skl: [PASS][115] -> [FAIL][116] ([i915#2122]) +1 similar issue
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-skl9/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl1/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][117] ([i915#2672] / [i915#3555]) +1 similar issue
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-default-mode:
- shard-iclb: [PASS][118] -> [SKIP][119] ([i915#3555])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-default-mode.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][120] ([i915#2672]) +2 similar issues
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][121] ([i915#2587] / [i915#2672]) +3 similar issues
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
- shard-tglb: NOTRUN -> [SKIP][122] ([i915#6497]) +2 similar issues
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-render:
- shard-tglb: NOTRUN -> [SKIP][123] ([fdo#109280] / [fdo#111825]) +7 similar issues
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-render.html
* igt@kms_plane_alpha_blend@alpha-basic@pipe-a-edp-1:
- shard-skl: NOTRUN -> [FAIL][124] ([i915#4573]) +2 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl7/igt@kms_plane_alpha_blend@alpha-basic@pipe-a-edp-1.html
* igt@kms_plane_lowres@tiling-none@pipe-b-dp-1:
- shard-apl: [PASS][125] -> [DMESG-WARN][126] ([i915#62]) +20 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-apl2/igt@kms_plane_lowres@tiling-none@pipe-b-dp-1.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-apl8/igt@kms_plane_lowres@tiling-none@pipe-b-dp-1.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1:
- shard-iclb: [PASS][127] -> [SKIP][128] ([i915#5176]) +2 similar issues
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb3/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf:
- shard-skl: NOTRUN -> [SKIP][129] ([fdo#109271] / [i915#658])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl7/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-apl: NOTRUN -> [SKIP][130] ([fdo#109271] / [i915#658])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-apl6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-iclb: NOTRUN -> [SKIP][131] ([fdo#109642] / [fdo#111068] / [i915#658])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb6/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][132] -> [SKIP][133] ([fdo#109441]) +3 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb5/igt@kms_psr@psr2_no_drrs.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-tglb: NOTRUN -> [FAIL][134] ([i915#132] / [i915#3467])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-tglb: NOTRUN -> [SKIP][135] ([fdo#111615] / [i915#5289])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb7/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_vblank@pipe-c-wait-forked-busy-hang:
- shard-skl: [PASS][136] -> [DMESG-WARN][137] ([i915#1982])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-skl7/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl9/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html
* igt@kms_writeback@writeback-fb-id:
- shard-skl: NOTRUN -> [SKIP][138] ([fdo#109271] / [i915#2437]) +1 similar issue
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl4/igt@kms_writeback@writeback-fb-id.html
* igt@perf@blocking:
- shard-skl: [PASS][139] -> [FAIL][140] ([i915#1542])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-skl4/igt@perf@blocking.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl7/igt@perf@blocking.html
* igt@perf_pmu@interrupts:
- shard-skl: [PASS][141] -> [FAIL][142] ([i915#7318])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-skl6/igt@perf_pmu@interrupts.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl4/igt@perf_pmu@interrupts.html
* igt@sysfs_clients@fair-1:
- shard-glk: NOTRUN -> [SKIP][143] ([fdo#109271] / [i915#2994])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk3/igt@sysfs_clients@fair-1.html
* igt@sysfs_clients@fair-7:
- shard-skl: NOTRUN -> [SKIP][144] ([fdo#109271] / [i915#2994])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl6/igt@sysfs_clients@fair-7.html
* igt@sysfs_clients@sema-10:
- shard-apl: NOTRUN -> [SKIP][145] ([fdo#109271] / [i915#2994])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-apl2/igt@sysfs_clients@sema-10.html
#### Possible fixes ####
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [SKIP][146] ([i915#4525]) -> [PASS][147] +1 similar issue
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb8/igt@gem_exec_balancer@parallel-keep-in-fence.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb1/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][148] ([i915#2842]) -> [PASS][149] +1 similar issue
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][150] ([i915#180]) -> [PASS][151] +2 similar issues
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-apl6/igt@gem_workarounds@suspend-resume-context.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-apl6/igt@gem_workarounds@suspend-resume-context.html
* igt@gen9_exec_parse@allowed-all:
- shard-skl: [DMESG-WARN][152] ([i915#5566] / [i915#716]) -> [PASS][153]
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-skl4/igt@gen9_exec_parse@allowed-all.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl7/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [DMESG-WARN][154] ([i915#5566] / [i915#716]) -> [PASS][155]
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-apl2/igt@gen9_exec_parse@allowed-single.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-apl8/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [SKIP][156] ([i915#4281]) -> [PASS][157]
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb6/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-skl: [INCOMPLETE][158] ([i915#7253] / [i915#7299]) -> [PASS][159]
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-skl4/igt@i915_pm_rpm@system-suspend-execbuf.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl6/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@i915_suspend@basic-s2idle-without-i915:
- shard-skl: [DMESG-WARN][160] ([i915#1982]) -> [PASS][161]
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-skl9/igt@i915_suspend@basic-s2idle-without-i915.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl1/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1:
- shard-skl: [FAIL][162] ([i915#2521]) -> [PASS][163] +1 similar issue
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-skl4/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl7/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [FAIL][164] ([i915#79]) -> [PASS][165] +2 similar issues
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-skl: [FAIL][166] ([i915#2122]) -> [PASS][167]
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
* igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset@d-edp1:
- shard-tglb: [INCOMPLETE][168] -> [PASS][169] +1 similar issue
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-tglb6/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset@d-edp1.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb5/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset@d-edp1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1:
- shard-iclb: [SKIP][170] ([i915#5235]) -> [PASS][171] +2 similar issues
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb5/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][172] ([fdo#109441]) -> [PASS][173] +4 similar issues
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb3/igt@kms_psr@psr2_primary_mmap_cpu.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@perf@polling-parameterized:
- shard-iclb: [FAIL][174] ([i915#5639]) -> [PASS][175]
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb8/igt@perf@polling-parameterized.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb8/igt@perf@polling-parameterized.html
- shard-skl: [FAIL][176] ([i915#5639]) -> [PASS][177]
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-skl4/igt@perf@polling-parameterized.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl4/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@dmabuf@all@dma_fence_chain:
- shard-skl: [INCOMPLETE][178] ([i915#6949] / [i915#7065] / [i915#7165]) -> [INCOMPLETE][179] ([i915#6949] / [i915#7165])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-skl6/igt@dmabuf@all@dma_fence_chain.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-skl7/igt@dmabuf@all@dma_fence_chain.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][180] ([i915#4525]) -> [FAIL][181] ([i915#6117])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb7/igt@gem_exec_balancer@parallel-ordering.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglb: [FAIL][182] ([i915#2842]) -> [FAIL][183] ([i915#2876])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-tglb3/igt@gem_exec_fair@basic-pace@rcs0.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-tglb8/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_pwrite@basic-exhaustion:
- shard-glk: [WARN][184] ([i915#2658]) -> [INCOMPLETE][185] ([i915#7248])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-glk3/igt@gem_pwrite@basic-exhaustion.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-glk3/igt@gem_pwrite@basic-exhaustion.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][186] ([i915#2920]) -> [SKIP][187] ([fdo#111068] / [i915#658]) +1 similar issue
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb5/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-iclb: [SKIP][188] ([fdo#111068] / [i915#658]) -> [SKIP][189] ([i915#2920])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb3/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
* igt@runner@aborted:
- shard-apl: ([FAIL][190], [FAIL][191], [FAIL][192], [FAIL][193], [FAIL][194], [FAIL][195], [FAIL][196], [FAIL][197]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312]) -> ([FAIL][198], [FAIL][199], [FAIL][200], [FAIL][201], [FAIL][202], [FAIL][203]) ([i915#3002] / [i915#4312])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-apl7/igt@runner@aborted.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-apl7/igt@runner@aborted.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-apl6/igt@runner@aborted.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-apl6/igt@runner@aborted.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-apl3/igt@runner@aborted.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-apl2/igt@runner@aborted.html
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-apl3/igt@runner@aborted.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-apl6/igt@runner@aborted.html
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-apl1/igt@runner@aborted.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-apl1/igt@runner@aborted.html
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-apl2/igt@runner@aborted.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-apl3/igt@runner@aborted.html
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-apl1/igt@runner@aborted.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-apl2/igt@runner@aborted.html
- shard-iclb: ([FAIL][204], [FAIL][205], [FAIL][206], [FAIL][207], [FAIL][208], [FAIL][209], [FAIL][210], [FAIL][211]) ([i915#3002] / [i915#4312]) -> ([FAIL][212], [FAIL][213], [FAIL][214], [FAIL][215], [FAIL][216], [FAIL][217], [FAIL][218], [FAIL][219]) ([i915#3002] / [i915#4312] / [i915#7300])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb7/igt@runner@aborted.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb1/igt@runner@aborted.html
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb2/igt@runner@aborted.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb6/igt@runner@aborted.html
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb1/igt@runner@aborted.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb7/igt@runner@aborted.html
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb6/igt@runner@aborted.html
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/shard-iclb6/igt@runner@aborted.html
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb1/igt@runner@aborted.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb7/igt@runner@aborted.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb7/igt@runner@aborted.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb5/igt@runner@aborted.html
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb8/igt@runner@aborted.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb8/igt@runner@aborted.html
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb6/igt@runner@aborted.html
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/shard-iclb2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2876]: https://gitlab.freedesktop.org/drm/intel/issues/2876
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3467]: https://gitlab.freedesktop.org/drm/intel/issues/3467
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4392]: https://gitlab.freedesktop.org/drm/intel/issues/4392
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#6537]: https://gitlab.freedesktop.org/drm/intel/issues/6537
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6949]: https://gitlab.freedesktop.org/drm/intel/issues/6949
[i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052
[i915#7065]: https://gitlab.freedesktop.org/drm/intel/issues/7065
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7121]: https://gitlab.freedesktop.org/drm/intel/issues/7121
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#7165]: https://gitlab.freedesktop.org/drm/intel/issues/7165
[i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
[i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178
[i915#7247]: https://gitlab.freedesktop.org/drm/intel/issues/7247
[i915#7248]: https://gitlab.freedesktop.org/drm/intel/issues/7248
[i915#7253]: https://gitlab.freedesktop.org/drm/intel/issues/7253
[i915#7299]: https://gitlab.freedesktop.org/drm/intel/issues/7299
[i915#7300]: https://gitlab.freedesktop.org/drm/intel/issues/7300
[i915#7316]: https://gitlab.freedesktop.org/drm/intel/issues/7316
[i915#7318]: https://gitlab.freedesktop.org/drm/intel/issues/7318
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12311 -> Patchwork_110199v2
CI-20190529: 20190529
CI_DRM_12311: 7e39cc6b9ee11e867ec5bd4910b65cefa7c644cc @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7028: 9e635a1c502970e7e6d64112d409392a2f01c688 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_110199v2: 7e39cc6b9ee11e867ec5bd4910b65cefa7c644cc @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110199v2/index.html
[-- Attachment #2: Type: text/html, Size: 52779 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk
2022-10-26 23:22 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
` (4 preceding siblings ...)
2022-10-28 8:11 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2022-10-28 9:05 ` Ville Syrjälä
2022-10-28 21:27 ` Srivatsa, Anusha
5 siblings, 1 reply; 17+ messages in thread
From: Ville Syrjälä @ 2022-10-28 9:05 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx, Balasubramani Vivekanandan
On Wed, Oct 26, 2022 at 04:22:56PM -0700, Anusha Srivatsa wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> For MTL, changing cdclk from between certain frequencies has
> both squash and crawl. Use the current cdclk config and
> the new(desired) cdclk config to construtc a mid cdclk config.
> Set the cdclk twice:
> - Current cdclk -> mid cdclk
> - mid cdclk -> desired cdclk
>
> v2: Add check in intel_modeset_calc_cdclk() to avoid cdclk
> change via modeset for platforms that support squash_crawl sequences(Ville)
>
> v3: Add checks for:
> - scenario where only slow clock is used and
> cdclk is actually 0 (bringing up display).
> - PLLs are on before looking up the waveform.
> - Squash and crawl capability checks.(Ville)
>
> v4: Rebase
> - Move checks to be more consistent (Ville)
> - Add comments (Bala)
>
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 157 +++++++++++++++++----
> 1 file changed, 129 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index eada931cb1c8..6a775367f02a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1716,37 +1716,74 @@ static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
> intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
> }
>
> -static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> - const struct intel_cdclk_config *cdclk_config,
> - enum pipe pipe)
> +static int cdclk_squash_divider(u16 waveform)
> +{
> + return hweight16(waveform ?: 0xffff);
> +}
> +
> +static bool cdclk_crawl_and_squash(struct drm_i915_private *i915,
> + const struct intel_cdclk_config *old_cdclk_config,
> + const struct intel_cdclk_config *new_cdclk_config,
> + struct intel_cdclk_config *mid_cdclk_config)
> +{
> + u16 old_waveform, new_waveform, mid_waveform;
> + int size = 16;
> + int div = 2;
> +
> + /* Return if both Squash and Crawl are not present */
> + if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
> + return false;
> +
> + /* Return if Squash only or Crawl only is the desired action */
> + if (old_cdclk_config->vco <= 0 || new_cdclk_config->vco <= 0 ||
> + old_cdclk_config->vco == new_cdclk_config->vco ||
> + old_waveform == new_waveform)
Those are not yet initialized.
> + return false;
> +
> + old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk);
> + new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk);
> +
> + *mid_cdclk_config = *new_cdclk_config;
> +
> + /* Populate the mid_cdclk_config accordingly.
> + * - If moving to a higher cdclk, the desired action is squashing.
> + * The mid cdclk config should have the new (squash) waveform.
> + * - If moving to a lower cdclk, the desired action is crawling.
> + * The mid cdclk config should have the new vco.
> + */
> +
> + if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) {
> + mid_cdclk_config->vco = old_cdclk_config->vco;
> + mid_waveform = new_waveform;
> + } else {
> + mid_cdclk_config->vco = new_cdclk_config->vco;
> + mid_waveform = old_waveform;
> + }
> +
> + mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
> + mid_cdclk_config->vco, size * div);
> +
> + /* make sure the mid clock came out sane */
> +
> + drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk <
> + min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
> + drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk >
> + i915->display.cdclk.max_cdclk_freq);
> + drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) !=
> + mid_waveform);
> +
> + return true;
> +}
> +
> +static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
> + const struct intel_cdclk_config *cdclk_config,
> + enum pipe pipe)
> {
> int cdclk = cdclk_config->cdclk;
> int vco = cdclk_config->vco;
> u32 val;
> u16 waveform;
> int clock;
> - int ret;
> -
> - /* Inform power controller of upcoming frequency change. */
> - if (DISPLAY_VER(dev_priv) >= 11)
> - ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
> - SKL_CDCLK_PREPARE_FOR_CHANGE,
> - SKL_CDCLK_READY_FOR_CHANGE,
> - SKL_CDCLK_READY_FOR_CHANGE, 3);
> - else
> - /*
> - * BSpec requires us to wait up to 150usec, but that leads to
> - * timeouts; the 2ms used here is based on experiment.
> - */
> - ret = snb_pcode_write_timeout(&dev_priv->uncore,
> - HSW_PCODE_DE_WRITE_FREQ_REQ,
> - 0x80000000, 150, 2);
> - if (ret) {
> - drm_err(&dev_priv->drm,
> - "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
> - ret, cdclk);
> - return;
> - }
>
> if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0) {
> if (dev_priv->display.cdclk.hw.vco != vco)
> @@ -1781,6 +1818,44 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>
> if (pipe != INVALID_PIPE)
> intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
> +}
> +
> +static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> + const struct intel_cdclk_config *cdclk_config,
> + enum pipe pipe)
> +{
> + struct intel_cdclk_config mid_cdclk_config;
> + int cdclk = cdclk_config->cdclk;
> + int ret;
> +
> + /* Inform power controller of upcoming frequency change. */
> + if (DISPLAY_VER(dev_priv) >= 11)
> + ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
> + SKL_CDCLK_PREPARE_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE, 3);
> + else
> + /*
> + * BSpec requires us to wait up to 150usec, but that leads to
> + * timeouts; the 2ms used here is based on experiment.
> + */
> + ret = snb_pcode_write_timeout(&dev_priv->uncore,
> + HSW_PCODE_DE_WRITE_FREQ_REQ,
> + 0x80000000, 150, 2);
> + if (ret) {
> + drm_err(&dev_priv->drm,
> + "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
> + ret, cdclk);
> + return;
> + }
> +
> + if (cdclk_crawl_and_squash(dev_priv, &dev_priv->display.cdclk.hw,
> + cdclk_config, &mid_cdclk_config)) {
> + _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe);
> + _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
> + } else {
> + _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
> + }
>
> if (DISPLAY_VER(dev_priv) >= 11) {
> ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
> @@ -1953,6 +2028,27 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
> skl_cdclk_uninit_hw(i915);
> }
>
> +static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private *i915,
> + const struct intel_cdclk_config *a,
> + const struct intel_cdclk_config *b)
> +{
> + u16 old_waveform;
> + u16 new_waveform;
> +
> + if (a->vco == 0 || b->vco == 0)
> + return false;
> +
> + if (HAS_CDCLK_CRAWL(i915) && HAS_CDCLK_SQUASH(i915)) {
> + old_waveform = cdclk_squash_waveform(i915, a->cdclk);
> + new_waveform = cdclk_squash_waveform(i915, b->cdclk);
> + } else {
> + return false;
> + }
Still weird.
> +
> + return a->vco != b->vco &&
> + old_waveform != new_waveform;
> +}
> +
> static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
> const struct intel_cdclk_config *a,
> const struct intel_cdclk_config *b)
> @@ -2759,9 +2855,14 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> pipe = INVALID_PIPE;
> }
>
> - if (intel_cdclk_can_squash(dev_priv,
> - &old_cdclk_state->actual,
> - &new_cdclk_state->actual)) {
> + if (intel_cdclk_can_crawl_and_squash(dev_priv,
> + &old_cdclk_state->actual,
> + &new_cdclk_state->actual)) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Can change cdclk via crawling and squashing\n");
> + } else if (intel_cdclk_can_squash(dev_priv,
> + &old_cdclk_state->actual,
> + &new_cdclk_state->actual)) {
> drm_dbg_kms(&dev_priv->drm,
> "Can change cdclk via squashing\n");
> } else if (intel_cdclk_can_crawl(dev_priv,
> --
> 2.25.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk
2022-10-28 9:05 ` [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Ville Syrjälä
@ 2022-10-28 21:27 ` Srivatsa, Anusha
0 siblings, 0 replies; 17+ messages in thread
From: Srivatsa, Anusha @ 2022-10-28 21:27 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Vivekanandan, Balasubramani
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Friday, October 28, 2022 2:05 AM
> To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Vivekanandan, Balasubramani
> <balasubramani.vivekanandan@intel.com>
> Subject: Re: [PATCH 1/2] drm/i915/display: Do both crawl and squash when
> changing cdclk
>
> On Wed, Oct 26, 2022 at 04:22:56PM -0700, Anusha Srivatsa wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > For MTL, changing cdclk from between certain frequencies has both
> > squash and crawl. Use the current cdclk config and the new(desired)
> > cdclk config to construtc a mid cdclk config.
> > Set the cdclk twice:
> > - Current cdclk -> mid cdclk
> > - mid cdclk -> desired cdclk
> >
> > v2: Add check in intel_modeset_calc_cdclk() to avoid cdclk change via
> > modeset for platforms that support squash_crawl sequences(Ville)
> >
> > v3: Add checks for:
> > - scenario where only slow clock is used and cdclk is actually 0
> > (bringing up display).
> > - PLLs are on before looking up the waveform.
> > - Squash and crawl capability checks.(Ville)
> >
> > v4: Rebase
> > - Move checks to be more consistent (Ville)
> > - Add comments (Bala)
> >
> > Cc: Balasubramani Vivekanandan
> <balasubramani.vivekanandan@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 157
> > +++++++++++++++++----
> > 1 file changed, 129 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index eada931cb1c8..6a775367f02a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1716,37 +1716,74 @@ static void dg2_cdclk_squash_program(struct
> drm_i915_private *i915,
> > intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl); }
> >
> > -static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> > - const struct intel_cdclk_config *cdclk_config,
> > - enum pipe pipe)
> > +static int cdclk_squash_divider(u16 waveform) {
> > + return hweight16(waveform ?: 0xffff); }
> > +
> > +static bool cdclk_crawl_and_squash(struct drm_i915_private *i915,
> > + const struct intel_cdclk_config
> *old_cdclk_config,
> > + const struct intel_cdclk_config
> *new_cdclk_config,
> > + struct intel_cdclk_config *mid_cdclk_config)
> {
> > + u16 old_waveform, new_waveform, mid_waveform;
> > + int size = 16;
> > + int div = 2;
> > +
> > + /* Return if both Squash and Crawl are not present */
> > + if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
> > + return false;
> > +
> > + /* Return if Squash only or Crawl only is the desired action */
> > + if (old_cdclk_config->vco <= 0 || new_cdclk_config->vco <= 0 ||
> > + old_cdclk_config->vco == new_cdclk_config->vco ||
> > + old_waveform == new_waveform)
>
> Those are not yet initialized.
*facepalm*
> > + return false;
> > +
> > + old_waveform = cdclk_squash_waveform(i915, old_cdclk_config-
> >cdclk);
> > + new_waveform = cdclk_squash_waveform(i915, new_cdclk_config-
> >cdclk);
> > +
> > + *mid_cdclk_config = *new_cdclk_config;
> > +
> > + /* Populate the mid_cdclk_config accordingly.
> > + * - If moving to a higher cdclk, the desired action is squashing.
> > + * The mid cdclk config should have the new (squash) waveform.
> > + * - If moving to a lower cdclk, the desired action is crawling.
> > + * The mid cdclk config should have the new vco.
> > + */
> > +
> > + if (cdclk_squash_divider(new_waveform) >
> cdclk_squash_divider(old_waveform)) {
> > + mid_cdclk_config->vco = old_cdclk_config->vco;
> > + mid_waveform = new_waveform;
> > + } else {
> > + mid_cdclk_config->vco = new_cdclk_config->vco;
> > + mid_waveform = old_waveform;
> > + }
> > +
> > + mid_cdclk_config->cdclk =
> DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
> > + mid_cdclk_config->vco, size
> * div);
> > +
> > + /* make sure the mid clock came out sane */
> > +
> > + drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk <
> > + min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
> > + drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk >
> > + i915->display.cdclk.max_cdclk_freq);
> > + drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915,
> mid_cdclk_config->cdclk) !=
> > + mid_waveform);
> > +
> > + return true;
> > +}
> > +
> > +static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
> > + const struct intel_cdclk_config *cdclk_config,
> > + enum pipe pipe)
> > {
> > int cdclk = cdclk_config->cdclk;
> > int vco = cdclk_config->vco;
> > u32 val;
> > u16 waveform;
> > int clock;
> > - int ret;
> > -
> > - /* Inform power controller of upcoming frequency change. */
> > - if (DISPLAY_VER(dev_priv) >= 11)
> > - ret = skl_pcode_request(&dev_priv->uncore,
> SKL_PCODE_CDCLK_CONTROL,
> > - SKL_CDCLK_PREPARE_FOR_CHANGE,
> > - SKL_CDCLK_READY_FOR_CHANGE,
> > - SKL_CDCLK_READY_FOR_CHANGE, 3);
> > - else
> > - /*
> > - * BSpec requires us to wait up to 150usec, but that leads to
> > - * timeouts; the 2ms used here is based on experiment.
> > - */
> > - ret = snb_pcode_write_timeout(&dev_priv->uncore,
> > -
> HSW_PCODE_DE_WRITE_FREQ_REQ,
> > - 0x80000000, 150, 2);
> > - if (ret) {
> > - drm_err(&dev_priv->drm,
> > - "Failed to inform PCU about cdclk change (err %d,
> freq %d)\n",
> > - ret, cdclk);
> > - return;
> > - }
> >
> > if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco
> > 0 && vco > 0) {
> > if (dev_priv->display.cdclk.hw.vco != vco) @@ -1781,6
> +1818,44 @@
> > static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> >
> > if (pipe != INVALID_PIPE)
> >
> intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv,
> > pipe));
> > +}
> > +
> > +static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> > + const struct intel_cdclk_config *cdclk_config,
> > + enum pipe pipe)
> > +{
> > + struct intel_cdclk_config mid_cdclk_config;
> > + int cdclk = cdclk_config->cdclk;
> > + int ret;
> > +
> > + /* Inform power controller of upcoming frequency change. */
> > + if (DISPLAY_VER(dev_priv) >= 11)
> > + ret = skl_pcode_request(&dev_priv->uncore,
> SKL_PCODE_CDCLK_CONTROL,
> > + SKL_CDCLK_PREPARE_FOR_CHANGE,
> > + SKL_CDCLK_READY_FOR_CHANGE,
> > + SKL_CDCLK_READY_FOR_CHANGE, 3);
> > + else
> > + /*
> > + * BSpec requires us to wait up to 150usec, but that leads to
> > + * timeouts; the 2ms used here is based on experiment.
> > + */
> > + ret = snb_pcode_write_timeout(&dev_priv->uncore,
> > +
> HSW_PCODE_DE_WRITE_FREQ_REQ,
> > + 0x80000000, 150, 2);
> > + if (ret) {
> > + drm_err(&dev_priv->drm,
> > + "Failed to inform PCU about cdclk change (err %d,
> freq %d)\n",
> > + ret, cdclk);
> > + return;
> > + }
> > +
> > + if (cdclk_crawl_and_squash(dev_priv, &dev_priv->display.cdclk.hw,
> > + cdclk_config, &mid_cdclk_config)) {
> > + _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe);
> > + _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
> > + } else {
> > + _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
> > + }
> >
> > if (DISPLAY_VER(dev_priv) >= 11) {
> > ret = snb_pcode_write(&dev_priv->uncore,
> SKL_PCODE_CDCLK_CONTROL,
> > @@ -1953,6 +2028,27 @@ void intel_cdclk_uninit_hw(struct
> drm_i915_private *i915)
> > skl_cdclk_uninit_hw(i915);
> > }
> >
> > +static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private
> *i915,
> > + const struct intel_cdclk_config *a,
> > + const struct intel_cdclk_config *b) {
> > + u16 old_waveform;
> > + u16 new_waveform;
> > +
> > + if (a->vco == 0 || b->vco == 0)
> > + return false;
> > +
> > + if (HAS_CDCLK_CRAWL(i915) && HAS_CDCLK_SQUASH(i915)) {
> > + old_waveform = cdclk_squash_waveform(i915, a->cdclk);
> > + new_waveform = cdclk_squash_waveform(i915, b->cdclk);
> > + } else {
> > + return false;
> > + }
>
> Still weird.
Agreed. Changing this.
Anusha
> > +
> > + return a->vco != b->vco &&
> > + old_waveform != new_waveform; }
> > +
> > static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
> > const struct intel_cdclk_config *a,
> > const struct intel_cdclk_config *b) @@ -
> 2759,9 +2855,14 @@ int
> > intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> > pipe = INVALID_PIPE;
> > }
> >
> > - if (intel_cdclk_can_squash(dev_priv,
> > - &old_cdclk_state->actual,
> > - &new_cdclk_state->actual)) {
> > + if (intel_cdclk_can_crawl_and_squash(dev_priv,
> > + &old_cdclk_state->actual,
> > + &new_cdclk_state->actual)) {
> > + drm_dbg_kms(&dev_priv->drm,
> > + "Can change cdclk via crawling and squashing\n");
> > + } else if (intel_cdclk_can_squash(dev_priv,
> > + &old_cdclk_state->actual,
> > + &new_cdclk_state->actual)) {
> > drm_dbg_kms(&dev_priv->drm,
> > "Can change cdclk via squashing\n");
> > } else if (intel_cdclk_can_crawl(dev_priv,
> > --
> > 2.25.1
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
2022-11-04 22:26 Anusha Srivatsa
@ 2022-11-04 22:26 ` Anusha Srivatsa
0 siblings, 0 replies; 17+ messages in thread
From: Anusha Srivatsa @ 2022-11-04 22:26 UTC (permalink / raw)
To: intel-gfx
As per bSpec MTL has 38.4 MHz Reference clock.
Adding the cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d1e0763513be..e7374fd92da9 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1345,6 +1345,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals mtl_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -3164,6 +3174,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level,
+};
+
static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3299,7 +3316,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_DG2(dev_priv)) {
+ if (IS_METEORLAKE(dev_priv)) {
+ dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+ dev_priv->display.cdclk.table = mtl_cdclk_table;
+ } else if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
2022-10-31 22:56 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
@ 2022-10-31 22:56 ` Anusha Srivatsa
0 siblings, 0 replies; 17+ messages in thread
From: Anusha Srivatsa @ 2022-10-31 22:56 UTC (permalink / raw)
To: intel-gfx
As per bSpec MTL has 38.4 MHz Reference clock.
Adding the cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d79cf282faa8..54ac7f9a1253 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1345,6 +1345,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals mtl_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -3159,6 +3169,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level,
+};
+
static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3294,7 +3311,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_DG2(dev_priv)) {
+ if (IS_METEORLAKE(dev_priv)) {
+ dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+ dev_priv->display.cdclk.table = mtl_cdclk_table;
+ } else if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
2022-10-28 21:32 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
@ 2022-10-31 17:58 ` Taylor, Clinton A
0 siblings, 0 replies; 17+ messages in thread
From: Taylor, Clinton A @ 2022-10-31 17:58 UTC (permalink / raw)
To: Srivatsa, Anusha, intel-gfx
See below
-----Original Message-----
From: Srivatsa, Anusha <anusha.srivatsa@intel.com>
Sent: Friday, October 28, 2022 2:32 PM
To: intel-gfx@lists.freedesktop.org
Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Taylor, Clinton A <clinton.a.taylor@intel.com>
Subject: [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
As per bSpec MTL has 38.4 MHz Reference clock.
Addin gthe cdclk tables and cdclk_funcs that MTL will use.
Spelling issue here. With this fixed
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
-Clint
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d79cf282faa8..54ac7f9a1253 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1345,6 +1345,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals mtl_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) {
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; @@ -3159,6 +3169,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level, };
+
static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3294,7 +3311,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) {
- if (IS_DG2(dev_priv)) {
+ if (IS_METEORLAKE(dev_priv)) {
+ dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+ dev_priv->display.cdclk.table = mtl_cdclk_table;
+ } else if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
2022-10-28 21:32 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
@ 2022-10-28 21:32 ` Anusha Srivatsa
2022-10-31 17:58 ` Taylor, Clinton A
0 siblings, 1 reply; 17+ messages in thread
From: Anusha Srivatsa @ 2022-10-28 21:32 UTC (permalink / raw)
To: intel-gfx
As per bSpec MTL has 38.4 MHz Reference clock.
Addin gthe cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d79cf282faa8..54ac7f9a1253 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1345,6 +1345,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals mtl_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -3159,6 +3169,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level,
+};
+
static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3294,7 +3311,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_DG2(dev_priv)) {
+ if (IS_METEORLAKE(dev_priv)) {
+ dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+ dev_priv->display.cdclk.table = mtl_cdclk_table;
+ } else if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
2022-10-13 23:32 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
@ 2022-10-13 23:32 ` Anusha Srivatsa
0 siblings, 0 replies; 17+ messages in thread
From: Anusha Srivatsa @ 2022-10-13 23:32 UTC (permalink / raw)
To: intel-gfx
As per bSpec MTL has 38.4 MHz Reference clock.
MTL does support squasher like DG2 but only for lower
frequencies. Change the has_cdclk_squasher()
helper to reflect this.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 24 ++++++++++++++++++++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 430b4cb0a8ab..f44cffeb1f94 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1222,7 +1222,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
static bool has_cdclk_squasher(struct drm_i915_private *i915)
{
- return IS_DG2(i915);
+ return DISPLAY_VER(i915) >= 14 || IS_DG2(i915);
}
struct intel_cdclk_vals {
@@ -1350,6 +1350,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals mtl_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -3149,6 +3159,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level,
+};
+
static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3284,7 +3301,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_DG2(dev_priv)) {
+ if (IS_METEORLAKE(dev_priv)) {
+ dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+ dev_priv->display.cdclk.table = mtl_cdclk_table;
+ } else if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
2022-09-30 21:34 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
@ 2022-09-30 21:34 ` Anusha Srivatsa
0 siblings, 0 replies; 17+ messages in thread
From: Anusha Srivatsa @ 2022-09-30 21:34 UTC (permalink / raw)
To: intel-gfx
As per bSpec MTL has 38.4 MHz Reference clock.
MTL does support squasher like DG2 but only for lower
frequencies. Change the has_cdclk_squasher()
helper to reflect this.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 25 ++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f7bc1013b149..b467aade750a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1222,7 +1222,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
static bool has_cdclk_squasher(struct drm_i915_private *i915)
{
- return IS_DG2(i915);
+ return DISPLAY_VER(i915) >= 14 || IS_DG2(i915);
}
struct intel_cdclk_vals {
@@ -1350,6 +1350,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals mtl_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -3138,6 +3148,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level,
+};
+
static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3273,7 +3290,11 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_DG2(dev_priv)) {
+
+ if (IS_METEORLAKE(dev_priv)) {
+ dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+ dev_priv->display.cdclk.table = mtl_cdclk_table;
+ } else if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
2022-09-28 19:23 ` Ville Syrjälä
@ 2022-09-28 21:16 ` Srivatsa, Anusha
0 siblings, 0 replies; 17+ messages in thread
From: Srivatsa, Anusha @ 2022-09-28 21:16 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Wednesday, September 28, 2022 12:24 PM
> To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for
> MTL
>
> On Wed, Sep 28, 2022 at 12:04:15PM -0700, Anusha Srivatsa wrote:
> > As per bSpec MTL has 38.4 MHz Reference clock.
> > MTL does support squasher like DG2 but only for lower frequencies.
> > Change the has_cdclk_squasher() helper to reflect this.
> >
> > bxt_get_cdclk() is not properly calculating HW clock for MTL, because
> > the squash formula is only prepared for DG2.
> > Apart from adding the cdclk table, align cdclk support with the new
> > cdclk_crawl_and_squash() introduced in previous patch.
> >
> > BSpec: 65243
> > Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 95
> > +++++++++++++++++++++-
> > 1 file changed, 93 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index f7bc1013b149..6271eed0d7cf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1222,7 +1222,7 @@ static void skl_cdclk_uninit_hw(struct
> > drm_i915_private *dev_priv)
> >
> > static bool has_cdclk_squasher(struct drm_i915_private *i915) {
> > - return IS_DG2(i915);
> > + return DISPLAY_VER(i915) >= 14 || IS_DG2(i915);
> > }
> >
> > struct intel_cdclk_vals {
> > @@ -1350,6 +1350,16 @@ static const struct intel_cdclk_vals
> dg2_cdclk_table[] = {
> > {}
> > };
> >
> > +static const struct intel_cdclk_vals mtl_cdclk_table[] = {
> > + { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform
> = 0xad5a },
> > + { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform
> = 0xb6b6 },
> > + { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform
> = 0x0000 },
> > + { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform
> = 0x0000 },
> > + { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform
> = 0x0000 },
> > + { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform
> = 0x0000 },
> > + {}
> > +};
> > +
> > static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int
> > min_cdclk) {
> > const struct intel_cdclk_vals *table =
> > dev_priv->display.cdclk.table; @@ -1479,6 +1489,76 @@ static void
> bxt_de_pll_readout(struct drm_i915_private *dev_priv,
> > cdclk_config->vco = ratio * cdclk_config->ref; }
> >
> > +static void mtl_get_cdclk(struct drm_i915_private *i915,
> > + struct intel_cdclk_config *cdclk_config) {
> > + const struct intel_cdclk_vals *table = i915->display.cdclk.table;
> > + u32 squash_ctl, divider, waveform;
> > + int div, i, ratio;
> > +
> > + bxt_de_pll_readout(i915, cdclk_config);
> > +
> > + cdclk_config->bypass = cdclk_config->ref / 2;
> > +
> > + if (cdclk_config->vco == 0) {
> > + cdclk_config->cdclk = cdclk_config->bypass;
> > + goto out;
> > + }
> > +
> > + divider = intel_de_read(i915, CDCLK_CTL) &
> BXT_CDCLK_CD2X_DIV_SEL_MASK;
> > + switch (divider) {
> > + case BXT_CDCLK_CD2X_DIV_SEL_1:
> > + div = 2;
> > + break;
> > + case BXT_CDCLK_CD2X_DIV_SEL_1_5:
> > + div = 3;
> > + break;
> > + case BXT_CDCLK_CD2X_DIV_SEL_2:
> > + div = 4;
> > + break;
> > + case BXT_CDCLK_CD2X_DIV_SEL_4:
> > + div = 8;
> > + break;
> > + default:
> > + MISSING_CASE(divider);
> > + return;
> > + }
> > +
> > + squash_ctl = intel_de_read(i915, CDCLK_SQUASH_CTL);
> > + if (squash_ctl & CDCLK_SQUASH_ENABLE)
> > + waveform = squash_ctl &
> CDCLK_SQUASH_WAVEFORM_MASK;
> > + else
> > + waveform = 0;
> > +
> > + ratio = cdclk_config->vco / cdclk_config->ref;
> > +
> > + for (i = 0, cdclk_config->cdclk = 0; table[i].refclk; i++) {
> > + if (table[i].refclk != cdclk_config->ref)
> > + continue;
> > +
> > + if (table[i].divider != div)
> > + continue;
> > +
> > + if (table[i].waveform != waveform)
> > + continue;
> > +
> > + if (table[i].ratio != ratio)
> > + continue;
> > +
> > + cdclk_config->cdclk = table[i].cdclk;
> > + break;
> > + }
>
> NAK. Readout must not depend on these tables. Otherwise it's not proper
> readout and bugs can slip through. What is the supposed problem with the
> already existing code?
IIRC we were getting wrong values with the existing mathematical calculations for cdclk. This way we force to pick an entry from the table.
Anusha
> > +out:
> > + /*
> > + * Can't read this out :( Let's assume it's
> > + * at least what the CDCLK frequency requires.
> > + */
> > + cdclk_config->voltage_level =
> > + intel_cdclk_calc_voltage_level(i915, cdclk_config->cdclk); }
> > +
> > +
> > static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> > struct intel_cdclk_config *cdclk_config) { @@ -
> 3138,6 +3218,13
> > @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
> > return freq;
> > }
> >
> > +static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
> > + .get_cdclk = mtl_get_cdclk,
> > + .set_cdclk = bxt_set_cdclk,
> > + .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
> > + .calc_voltage_level = tgl_calc_voltage_level, };
> > +
> > static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
> > .get_cdclk = bxt_get_cdclk,
> > .set_cdclk = bxt_set_cdclk,
> > @@ -3273,7 +3360,11 @@ static const struct intel_cdclk_funcs
> i830_cdclk_funcs = {
> > */
> > void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) {
> > - if (IS_DG2(dev_priv)) {
> > +
> > + if (IS_METEORLAKE(dev_priv)) {
> > + dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
> > + dev_priv->display.cdclk.table = mtl_cdclk_table;
> > + } else if (IS_DG2(dev_priv)) {
> > dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> > dev_priv->display.cdclk.table = dg2_cdclk_table;
> > } else if (IS_ALDERLAKE_P(dev_priv)) {
> > --
> > 2.25.1
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
2022-09-28 19:04 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
@ 2022-09-28 19:23 ` Ville Syrjälä
2022-09-28 21:16 ` Srivatsa, Anusha
0 siblings, 1 reply; 17+ messages in thread
From: Ville Syrjälä @ 2022-09-28 19:23 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Wed, Sep 28, 2022 at 12:04:15PM -0700, Anusha Srivatsa wrote:
> As per bSpec MTL has 38.4 MHz Reference clock.
> MTL does support squasher like DG2 but only for lower
> frequencies. Change the has_cdclk_squasher()
> helper to reflect this.
>
> bxt_get_cdclk() is not properly calculating HW clock for MTL,
> because the squash formula is only prepared for DG2.
> Apart from adding the cdclk table, align cdclk support with the
> new cdclk_crawl_and_squash() introduced in previous patch.
>
> BSpec: 65243
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 95 +++++++++++++++++++++-
> 1 file changed, 93 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index f7bc1013b149..6271eed0d7cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1222,7 +1222,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
>
> static bool has_cdclk_squasher(struct drm_i915_private *i915)
> {
> - return IS_DG2(i915);
> + return DISPLAY_VER(i915) >= 14 || IS_DG2(i915);
> }
>
> struct intel_cdclk_vals {
> @@ -1350,6 +1350,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
> {}
> };
>
> +static const struct intel_cdclk_vals mtl_cdclk_table[] = {
> + { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> + { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> + { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
> + { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
> + { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
> + { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
> + {}
> +};
> +
> static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
> {
> const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
> @@ -1479,6 +1489,76 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
> cdclk_config->vco = ratio * cdclk_config->ref;
> }
>
> +static void mtl_get_cdclk(struct drm_i915_private *i915,
> + struct intel_cdclk_config *cdclk_config)
> +{
> + const struct intel_cdclk_vals *table = i915->display.cdclk.table;
> + u32 squash_ctl, divider, waveform;
> + int div, i, ratio;
> +
> + bxt_de_pll_readout(i915, cdclk_config);
> +
> + cdclk_config->bypass = cdclk_config->ref / 2;
> +
> + if (cdclk_config->vco == 0) {
> + cdclk_config->cdclk = cdclk_config->bypass;
> + goto out;
> + }
> +
> + divider = intel_de_read(i915, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
> + switch (divider) {
> + case BXT_CDCLK_CD2X_DIV_SEL_1:
> + div = 2;
> + break;
> + case BXT_CDCLK_CD2X_DIV_SEL_1_5:
> + div = 3;
> + break;
> + case BXT_CDCLK_CD2X_DIV_SEL_2:
> + div = 4;
> + break;
> + case BXT_CDCLK_CD2X_DIV_SEL_4:
> + div = 8;
> + break;
> + default:
> + MISSING_CASE(divider);
> + return;
> + }
> +
> + squash_ctl = intel_de_read(i915, CDCLK_SQUASH_CTL);
> + if (squash_ctl & CDCLK_SQUASH_ENABLE)
> + waveform = squash_ctl & CDCLK_SQUASH_WAVEFORM_MASK;
> + else
> + waveform = 0;
> +
> + ratio = cdclk_config->vco / cdclk_config->ref;
> +
> + for (i = 0, cdclk_config->cdclk = 0; table[i].refclk; i++) {
> + if (table[i].refclk != cdclk_config->ref)
> + continue;
> +
> + if (table[i].divider != div)
> + continue;
> +
> + if (table[i].waveform != waveform)
> + continue;
> +
> + if (table[i].ratio != ratio)
> + continue;
> +
> + cdclk_config->cdclk = table[i].cdclk;
> + break;
> + }
NAK. Readout must not depend on these tables. Otherwise it's not
proper readout and bugs can slip through. What is the supposed problem
with the already existing code?
> +out:
> + /*
> + * Can't read this out :( Let's assume it's
> + * at least what the CDCLK frequency requires.
> + */
> + cdclk_config->voltage_level =
> + intel_cdclk_calc_voltage_level(i915, cdclk_config->cdclk);
> +}
> +
> +
> static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> struct intel_cdclk_config *cdclk_config)
> {
> @@ -3138,6 +3218,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
> return freq;
> }
>
> +static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
> + .get_cdclk = mtl_get_cdclk,
> + .set_cdclk = bxt_set_cdclk,
> + .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
> + .calc_voltage_level = tgl_calc_voltage_level,
> +};
> +
> static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
> .get_cdclk = bxt_get_cdclk,
> .set_cdclk = bxt_set_cdclk,
> @@ -3273,7 +3360,11 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
> */
> void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> {
> - if (IS_DG2(dev_priv)) {
> +
> + if (IS_METEORLAKE(dev_priv)) {
> + dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
> + dev_priv->display.cdclk.table = mtl_cdclk_table;
> + } else if (IS_DG2(dev_priv)) {
> dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> dev_priv->display.cdclk.table = dg2_cdclk_table;
> } else if (IS_ALDERLAKE_P(dev_priv)) {
> --
> 2.25.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL
2022-09-28 19:04 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
@ 2022-09-28 19:04 ` Anusha Srivatsa
2022-09-28 19:23 ` Ville Syrjälä
0 siblings, 1 reply; 17+ messages in thread
From: Anusha Srivatsa @ 2022-09-28 19:04 UTC (permalink / raw)
To: intel-gfx
As per bSpec MTL has 38.4 MHz Reference clock.
MTL does support squasher like DG2 but only for lower
frequencies. Change the has_cdclk_squasher()
helper to reflect this.
bxt_get_cdclk() is not properly calculating HW clock for MTL,
because the squash formula is only prepared for DG2.
Apart from adding the cdclk table, align cdclk support with the
new cdclk_crawl_and_squash() introduced in previous patch.
BSpec: 65243
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 95 +++++++++++++++++++++-
1 file changed, 93 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f7bc1013b149..6271eed0d7cf 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1222,7 +1222,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
static bool has_cdclk_squasher(struct drm_i915_private *i915)
{
- return IS_DG2(i915);
+ return DISPLAY_VER(i915) >= 14 || IS_DG2(i915);
}
struct intel_cdclk_vals {
@@ -1350,6 +1350,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals mtl_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -1479,6 +1489,76 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
cdclk_config->vco = ratio * cdclk_config->ref;
}
+static void mtl_get_cdclk(struct drm_i915_private *i915,
+ struct intel_cdclk_config *cdclk_config)
+{
+ const struct intel_cdclk_vals *table = i915->display.cdclk.table;
+ u32 squash_ctl, divider, waveform;
+ int div, i, ratio;
+
+ bxt_de_pll_readout(i915, cdclk_config);
+
+ cdclk_config->bypass = cdclk_config->ref / 2;
+
+ if (cdclk_config->vco == 0) {
+ cdclk_config->cdclk = cdclk_config->bypass;
+ goto out;
+ }
+
+ divider = intel_de_read(i915, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
+ switch (divider) {
+ case BXT_CDCLK_CD2X_DIV_SEL_1:
+ div = 2;
+ break;
+ case BXT_CDCLK_CD2X_DIV_SEL_1_5:
+ div = 3;
+ break;
+ case BXT_CDCLK_CD2X_DIV_SEL_2:
+ div = 4;
+ break;
+ case BXT_CDCLK_CD2X_DIV_SEL_4:
+ div = 8;
+ break;
+ default:
+ MISSING_CASE(divider);
+ return;
+ }
+
+ squash_ctl = intel_de_read(i915, CDCLK_SQUASH_CTL);
+ if (squash_ctl & CDCLK_SQUASH_ENABLE)
+ waveform = squash_ctl & CDCLK_SQUASH_WAVEFORM_MASK;
+ else
+ waveform = 0;
+
+ ratio = cdclk_config->vco / cdclk_config->ref;
+
+ for (i = 0, cdclk_config->cdclk = 0; table[i].refclk; i++) {
+ if (table[i].refclk != cdclk_config->ref)
+ continue;
+
+ if (table[i].divider != div)
+ continue;
+
+ if (table[i].waveform != waveform)
+ continue;
+
+ if (table[i].ratio != ratio)
+ continue;
+
+ cdclk_config->cdclk = table[i].cdclk;
+ break;
+ }
+
+out:
+ /*
+ * Can't read this out :( Let's assume it's
+ * at least what the CDCLK frequency requires.
+ */
+ cdclk_config->voltage_level =
+ intel_cdclk_calc_voltage_level(i915, cdclk_config->cdclk);
+}
+
+
static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
@@ -3138,6 +3218,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+ .get_cdclk = mtl_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level,
+};
+
static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3273,7 +3360,11 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_DG2(dev_priv)) {
+
+ if (IS_METEORLAKE(dev_priv)) {
+ dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+ dev_priv->display.cdclk.table = mtl_cdclk_table;
+ } else if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
end of thread, other threads:[~2022-11-04 22:26 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-26 23:22 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
2022-10-26 23:22 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
2022-10-27 5:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk Patchwork
2022-10-27 17:16 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-10-27 20:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk (rev2) Patchwork
2022-10-28 8:11 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-10-28 9:05 ` [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Ville Syrjälä
2022-10-28 21:27 ` Srivatsa, Anusha
-- strict thread matches above, loose matches on Subject: below --
2022-11-04 22:26 Anusha Srivatsa
2022-11-04 22:26 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
2022-10-31 22:56 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
2022-10-31 22:56 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
2022-10-28 21:32 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
2022-10-28 21:32 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
2022-10-31 17:58 ` Taylor, Clinton A
2022-10-13 23:32 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
2022-10-13 23:32 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
2022-09-30 21:34 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
2022-09-30 21:34 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
2022-09-28 19:04 [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk Anusha Srivatsa
2022-09-28 19:04 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL Anusha Srivatsa
2022-09-28 19:23 ` Ville Syrjälä
2022-09-28 21:16 ` Srivatsa, Anusha
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