From: "Jouni Högander" <jouni.hogander@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v5 4/6] drm/i915/psr: Add helpers for block count number handling
Date: Wed, 22 Mar 2023 12:34:10 +0200 [thread overview]
Message-ID: <20230322103412.123943-5-jouni.hogander@intel.com> (raw)
In-Reply-To: <20230322103412.123943-1-jouni.hogander@intel.com>
Add helpers to make it more clear how PSR2_CTL[Block Count Number]
is configured.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index dfac546d983b..4b7c946a9a25 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -519,6 +519,17 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
return val;
}
+static int psr2_block_count_lines(struct intel_dp *intel_dp)
+{
+ return intel_dp->psr.io_wake_lines < 9 &&
+ intel_dp->psr.fast_wake_lines < 9 ? 8 : 12;
+}
+
+static int psr2_block_count(struct intel_dp *intel_dp)
+{
+ return psr2_block_count_lines(intel_dp) / 4;
+}
+
static void hsw_activate_psr2(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -536,11 +547,10 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
val |= intel_psr2_get_tp_time(intel_dp);
if (DISPLAY_VER(dev_priv) >= 12) {
- if (intel_dp->psr.io_wake_lines < 9 &&
- intel_dp->psr.fast_wake_lines < 9)
- val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
- else
+ if (psr2_block_count(intel_dp) > 2)
val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3;
+ else
+ val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
}
/* Wa_22012278275:adl-p */
--
2.34.1
next prev parent reply other threads:[~2023-03-22 10:34 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-22 10:34 [Intel-gfx] [PATCH v5 0/6] High refresh rate PSR fixes Jouni Högander
2023-03-22 10:34 ` [Intel-gfx] [PATCH v5 1/6] drm/i915/psr: Unify pre/post hooks Jouni Högander
2023-03-22 10:34 ` [Intel-gfx] [PATCH v5 2/6] drm/i915/psr: Modify/fix Wa_16013835468 and prepare for Wa_14015648006 Jouni Högander
2023-03-28 11:17 ` Ville Syrjälä
2023-03-28 11:31 ` Hogander, Jouni
2023-03-28 11:40 ` Ville Syrjälä
2023-03-22 10:34 ` [Intel-gfx] [PATCH v5 3/6] drm/i915/psr: Implement Wa_14015648006 Jouni Högander
2023-03-22 10:34 ` Jouni Högander [this message]
2023-03-28 11:19 ` [Intel-gfx] [PATCH v5 4/6] drm/i915/psr: Add helpers for block count number handling Ville Syrjälä
2023-03-22 10:34 ` [Intel-gfx] [PATCH v5 5/6] drm/i915/psr: Check that vblank is long enough for psr2 Jouni Högander
2023-03-28 11:24 ` Ville Syrjälä
2023-03-28 11:33 ` Hogander, Jouni
2023-03-22 10:34 ` [Intel-gfx] [PATCH v5 6/6] drm/i915/psr: Implement Display WA #1136 Jouni Högander
2023-03-28 11:26 ` Ville Syrjälä
2023-03-28 11:35 ` Hogander, Jouni
2023-03-22 13:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for High refresh rate PSR fixes (rev5) Patchwork
2023-03-22 13:43 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-03-22 13:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-22 18:29 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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