* [Intel-gfx] [PATCH 0/2] Add MTL Wa_14017066071, Wa_14017654203 and Wa_22015279794
@ 2023-03-29 20:24 Gustavo Sousa
2023-03-29 20:24 ` [Intel-gfx] [PATCH 1/2] drm/i915/mtl: Add workarounds Wa_14017066071 and Wa_14017654203 Gustavo Sousa
2023-03-29 20:24 ` [Intel-gfx] [PATCH 2/2] drm/i915/mtl: Add Wa_22015279794 Gustavo Sousa
0 siblings, 2 replies; 5+ messages in thread
From: Gustavo Sousa @ 2023-03-29 20:24 UTC (permalink / raw)
To: intel-gfx
Add some GT workarounds for MTL. Note that Wa_14017066071 and Wa_14017654203
require the same implementation and have the same platform and stepping bounds,
so there is a single patch for them.
Radhakrishna Sripada (2):
drm/i915/mtl: Add workarounds Wa_14017066071 and Wa_14017654203
drm/i915/mtl: Add Wa_22015279794
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 +++++++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 +++++++++++++++--
2 files changed, 22 insertions(+), 2 deletions(-)
--
2.40.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915/mtl: Add workarounds Wa_14017066071 and Wa_14017654203
2023-03-29 20:24 [Intel-gfx] [PATCH 0/2] Add MTL Wa_14017066071, Wa_14017654203 and Wa_22015279794 Gustavo Sousa
@ 2023-03-29 20:24 ` Gustavo Sousa
2023-03-29 21:03 ` Matt Roper
2023-03-29 20:24 ` [Intel-gfx] [PATCH 2/2] drm/i915/mtl: Add Wa_22015279794 Gustavo Sousa
1 sibling, 1 reply; 5+ messages in thread
From: Gustavo Sousa @ 2023-03-29 20:24 UTC (permalink / raw)
To: intel-gfx
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Both workarounds require the same implementation and apply to MTL P and
M from stepping A0 to B0 (exclusive).
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 ++++++++++--
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 4aecb5a7b631..1ec855813632 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1144,6 +1144,7 @@
#define ENABLE_SMALLPL REG_BIT(15)
#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
+#define MTL_DISABLE_SAMPLER_SC_OOO REG_BIT(3)
#define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
#define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e7ee24bcad89..cafdf66d9562 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2388,11 +2388,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
struct drm_i915_private *i915 = engine->i915;
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
/* Wa_22014600077 */
wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
ENABLE_EU_COUNT_FOR_TDL_FLUSH);
- }
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
@@ -2971,6 +2970,15 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
add_render_compute_tuning_settings(i915, wal);
+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ /*
+ * Wa_14017066071
+ * Wa_14017654203
+ */
+ wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
+ MTL_DISABLE_SAMPLER_SC_OOO);
+
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
--
2.40.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/mtl: Add Wa_22015279794
2023-03-29 20:24 [Intel-gfx] [PATCH 0/2] Add MTL Wa_14017066071, Wa_14017654203 and Wa_22015279794 Gustavo Sousa
2023-03-29 20:24 ` [Intel-gfx] [PATCH 1/2] drm/i915/mtl: Add workarounds Wa_14017066071 and Wa_14017654203 Gustavo Sousa
@ 2023-03-29 20:24 ` Gustavo Sousa
2023-03-29 21:12 ` Matt Roper
1 sibling, 1 reply; 5+ messages in thread
From: Gustavo Sousa @ 2023-03-29 20:24 UTC (permalink / raw)
To: intel-gfx
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Wa_22015279794 applies to MTL P from stepping A0 to B0 (exclusive).
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 6 ++++++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 1ec855813632..35a4cfac2d20 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1156,7 +1156,13 @@
#define ENABLE_EU_COUNT_FOR_TDL_FLUSH REG_BIT(10)
#define DISABLE_ECC REG_BIT(5)
#define FLOAT_BLEND_OPTIMIZATION_ENABLE REG_BIT(4)
+/*
+ * We have both ENABLE and DISABLE defines below using the same bit because the
+ * meaning depends on the target platform. There are no platform prefix for them
+ * because different steppings of DG2 pick one or the other semantics.
+ */
#define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
+#define DISABLE_PREFETCH_INTO_IC REG_BIT(3)
#define EU_PERF_CNTL0 PERF_REG(0xe458)
#define EU_PERF_CNTL4 PERF_REG(0xe45c)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index cafdf66d9562..29d09ddfc8a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2979,6 +2979,11 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
MTL_DISABLE_SAMPLER_SC_OOO);
+ if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ /* Wa_22015279794 */
+ wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
+ DISABLE_PREFETCH_INTO_IC);
+
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
--
2.40.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/mtl: Add workarounds Wa_14017066071 and Wa_14017654203
2023-03-29 20:24 ` [Intel-gfx] [PATCH 1/2] drm/i915/mtl: Add workarounds Wa_14017066071 and Wa_14017654203 Gustavo Sousa
@ 2023-03-29 21:03 ` Matt Roper
0 siblings, 0 replies; 5+ messages in thread
From: Matt Roper @ 2023-03-29 21:03 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-gfx
On Wed, Mar 29, 2023 at 05:24:50PM -0300, Gustavo Sousa wrote:
> From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>
> Both workarounds require the same implementation and apply to MTL P and
> M from stepping A0 to B0 (exclusive).
>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 ++++++++++--
> 2 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 4aecb5a7b631..1ec855813632 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1144,6 +1144,7 @@
> #define ENABLE_SMALLPL REG_BIT(15)
> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
> #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
> +#define MTL_DISABLE_SAMPLER_SC_OOO REG_BIT(3)
>
> #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
> #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index e7ee24bcad89..cafdf66d9562 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2388,11 +2388,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> struct drm_i915_private *i915 = engine->i915;
>
> if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> /* Wa_22014600077 */
> wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> ENABLE_EU_COUNT_FOR_TDL_FLUSH);
> - }
The brace removal here doesn't seem to be related to this patch.
Aside from that, the actual workaround addition below is
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
> if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> @@ -2971,6 +2970,15 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>
> add_render_compute_tuning_settings(i915, wal);
>
> + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> + /*
> + * Wa_14017066071
> + * Wa_14017654203
> + */
> + wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
> + MTL_DISABLE_SAMPLER_SC_OOO);
> +
> if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> --
> 2.40.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/mtl: Add Wa_22015279794
2023-03-29 20:24 ` [Intel-gfx] [PATCH 2/2] drm/i915/mtl: Add Wa_22015279794 Gustavo Sousa
@ 2023-03-29 21:12 ` Matt Roper
0 siblings, 0 replies; 5+ messages in thread
From: Matt Roper @ 2023-03-29 21:12 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-gfx
On Wed, Mar 29, 2023 at 05:24:51PM -0300, Gustavo Sousa wrote:
> From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>
> Wa_22015279794 applies to MTL P from stepping A0 to B0 (exclusive).
>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 6 ++++++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 1ec855813632..35a4cfac2d20 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1156,7 +1156,13 @@
> #define ENABLE_EU_COUNT_FOR_TDL_FLUSH REG_BIT(10)
> #define DISABLE_ECC REG_BIT(5)
> #define FLOAT_BLEND_OPTIMIZATION_ENABLE REG_BIT(4)
> +/*
> + * We have both ENABLE and DISABLE defines below using the same bit because the
> + * meaning depends on the target platform. There are no platform prefix for them
> + * because different steppings of DG2 pick one or the other semantics.
> + */
> #define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
> +#define DISABLE_PREFETCH_INTO_IC REG_BIT(3)
>
> #define EU_PERF_CNTL0 PERF_REG(0xe458)
> #define EU_PERF_CNTL4 PERF_REG(0xe45c)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index cafdf66d9562..29d09ddfc8a9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2979,6 +2979,11 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
> MTL_DISABLE_SAMPLER_SC_OOO);
>
> + if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> + /* Wa_22015279794 */
> + wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> + DISABLE_PREFETCH_INTO_IC);
> +
> if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> --
> 2.40.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-03-29 21:12 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2023-03-29 20:24 [Intel-gfx] [PATCH 0/2] Add MTL Wa_14017066071, Wa_14017654203 and Wa_22015279794 Gustavo Sousa
2023-03-29 20:24 ` [Intel-gfx] [PATCH 1/2] drm/i915/mtl: Add workarounds Wa_14017066071 and Wa_14017654203 Gustavo Sousa
2023-03-29 21:03 ` Matt Roper
2023-03-29 20:24 ` [Intel-gfx] [PATCH 2/2] drm/i915/mtl: Add Wa_22015279794 Gustavo Sousa
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