* [Intel-gfx] [PATCH] drm/i915: disable sampler indirect state in bindless heap
@ 2023-03-09 15:26 Lionel Landwerlin
2023-03-09 17:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (6 more replies)
0 siblings, 7 replies; 18+ messages in thread
From: Lionel Landwerlin @ 2023-03-09 15:26 UTC (permalink / raw)
To: intel-gfx; +Cc: stable
By default the indirect state sampler data (border colors) are stored
in the same heap as the SAMPLER_STATE structure. For userspace drivers
that can be 2 different heaps (dynamic state heap & bindless sampler
state heap). This means that border colors have to copied in 2
different places so that the same SAMPLER_STATE structure find the
right data.
This change is forcing the indirect state sampler data to only be in
the dynamic state pool (more convinient for userspace drivers, they
only have to have one copy of the border colors). This is reproducing
the behavior of the Windows drivers.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: stable@vger.kernel.org
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 +++++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 08d76aa06974c..1aaa471d08c56 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1141,6 +1141,7 @@
#define ENABLE_SMALLPL REG_BIT(15)
#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
+#define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
#define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
#define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 32aa1647721ae..734b64e714647 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2542,6 +2542,23 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
ENABLE_SMALLPL);
}
+ if (GRAPHICS_VER(i915) >= 11) {
+ /* This is not a Wa (although referred to as
+ * WaSetInidrectStateOverride in places), this allows
+ * applications that reference sampler states through
+ * the BindlessSamplerStateBaseAddress to have their
+ * border color relative to DynamicStateBaseAddress
+ * rather than BindlessSamplerStateBaseAddress.
+ *
+ * Otherwise SAMPLER_STATE border colors have to be
+ * copied in multiple heaps (DynamicStateBaseAddress &
+ * BindlessSamplerStateBaseAddress)
+ */
+ wa_mcr_masked_en(wal,
+ GEN10_SAMPLER_MODE,
+ GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
+ }
+
if (GRAPHICS_VER(i915) == 11) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
--
2.34.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: disable sampler indirect state in bindless heap
2023-03-09 15:26 [Intel-gfx] [PATCH] drm/i915: disable sampler indirect state in bindless heap Lionel Landwerlin
@ 2023-03-09 17:15 ` Patchwork
2023-03-09 17:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (5 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2023-03-09 17:15 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: disable sampler indirect state in bindless heap
URL : https://patchwork.freedesktop.org/series/114920/
State : warning
== Summary ==
Error: dim checkpatch failed
e4889ef6bb9b drm/i915: disable sampler indirect state in bindless heap
-:14: WARNING:TYPO_SPELLING: 'convinient' may be misspelled - perhaps 'convenient'?
#14:
the dynamic state pool (more convinient for userspace drivers, they
^^^^^^^^^^
total: 0 errors, 1 warnings, 0 checks, 30 lines checked
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: disable sampler indirect state in bindless heap
2023-03-09 15:26 [Intel-gfx] [PATCH] drm/i915: disable sampler indirect state in bindless heap Lionel Landwerlin
2023-03-09 17:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2023-03-09 17:38 ` Patchwork
2023-03-11 13:45 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
` (4 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2023-03-09 17:38 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6905 bytes --]
== Series Details ==
Series: drm/i915: disable sampler indirect state in bindless heap
URL : https://patchwork.freedesktop.org/series/114920/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12831 -> Patchwork_114920v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/index.html
Participating hosts (35 -> 36)
------------------------------
Additional (2): fi-kbl-soraka bat-atsm-1
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_114920v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@fbdev@eof:
- bat-atsm-1: NOTRUN -> [SKIP][1] ([i915#2582]) +4 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/bat-atsm-1/igt@fbdev@eof.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@gem_mmap@basic:
- bat-atsm-1: NOTRUN -> [SKIP][4] ([i915#4083])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/bat-atsm-1/igt@gem_mmap@basic.html
* igt@gem_sync@basic-each:
- bat-atsm-1: NOTRUN -> [FAIL][5] ([i915#8062]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/bat-atsm-1/igt@gem_sync@basic-each.html
* igt@gem_tiled_fence_blits@basic:
- bat-atsm-1: NOTRUN -> [SKIP][6] ([i915#4077]) +2 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/bat-atsm-1/igt@gem_tiled_fence_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-atsm-1: NOTRUN -> [SKIP][7] ([i915#4079]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/bat-atsm-1/igt@gem_tiled_pread_basic.html
* igt@i915_hangman@error-state-basic:
- bat-atsm-1: NOTRUN -> [ABORT][8] ([i915#8060])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/bat-atsm-1/igt@i915_hangman@error-state-basic.html
* igt@i915_selftest@live@gem_contexts:
- fi-kbl-soraka: NOTRUN -> [INCOMPLETE][9] ([i915#7913])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/fi-kbl-soraka/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][10] ([i915#1886])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: NOTRUN -> [ABORT][11] ([i915#4983] / [i915#7913])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/bat-rpls-2/igt@i915_selftest@live@reset.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271]) +16 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/fi-kbl-soraka/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- fi-glk-j4005: NOTRUN -> [SKIP][13] ([fdo#109271])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/fi-glk-j4005/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
- fi-bsw-nick: NOTRUN -> [SKIP][14] ([fdo#109271]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/fi-bsw-nick/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][15] ([i915#5354]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-bsw-nick: [ABORT][16] ([i915#7911] / [i915#7913]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/fi-bsw-nick/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@late_gt_pm:
- fi-glk-j4005: [ABORT][18] ([i915#6217]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/fi-glk-j4005/igt@i915_selftest@live@late_gt_pm.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/fi-glk-j4005/igt@i915_selftest@live@late_gt_pm.html
* igt@i915_selftest@live@requests:
- bat-rpls-2: [ABORT][20] ([i915#7694] / [i915#7913]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/bat-rpls-2/igt@i915_selftest@live@requests.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/bat-rpls-2/igt@i915_selftest@live@requests.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6217]: https://gitlab.freedesktop.org/drm/intel/issues/6217
[i915#7694]: https://gitlab.freedesktop.org/drm/intel/issues/7694
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#8060]: https://gitlab.freedesktop.org/drm/intel/issues/8060
[i915#8062]: https://gitlab.freedesktop.org/drm/intel/issues/8062
Build changes
-------------
* Linux: CI_DRM_12831 -> Patchwork_114920v1
CI-20190529: 20190529
CI_DRM_12831: 4910ebea52abc05f63bfc43bc91baebd8af93d45 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7188: b35bfa32fe672d67ced8555557e3e707ace211ad @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_114920v1: 4910ebea52abc05f63bfc43bc91baebd8af93d45 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
42dd40dce869 drm/i915: disable sampler indirect state in bindless heap
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/index.html
[-- Attachment #2: Type: text/html, Size: 8425 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: disable sampler indirect state in bindless heap
2023-03-09 15:26 [Intel-gfx] [PATCH] drm/i915: disable sampler indirect state in bindless heap Lionel Landwerlin
2023-03-09 17:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2023-03-09 17:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-03-11 13:45 ` Patchwork
2023-03-28 10:44 ` [Intel-gfx] [PATCH] " Kalvala, Haridhar
` (3 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2023-03-11 13:45 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 32901 bytes --]
== Series Details ==
Series: drm/i915: disable sampler indirect state in bindless heap
URL : https://patchwork.freedesktop.org/series/114920/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12831_full -> Patchwork_114920v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-rkl0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_114920v1_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_softpin@evict-single-offset:
- {shard-tglu}: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-tglu-8/igt@gem_softpin@evict-single-offset.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-2/igt@gem_softpin@evict-single-offset.html
* {igt@xe/xe_exec_basic@once-rebind}:
- {shard-dg1}: NOTRUN -> [SKIP][3] +124 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-dg1-14/igt@xe/xe_exec_basic@once-rebind.html
Known issues
------------
Here are the changes found in Patchwork_114920v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- shard-tglu-10: NOTRUN -> [SKIP][4] ([i915#7456])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@debugfs_test@basic-hwmon.html
* igt@feature_discovery@display-4x:
- shard-tglu-10: NOTRUN -> [SKIP][5] ([i915#1839])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@feature_discovery@display-4x.html
* igt@gem_close_race@multigpu-basic-process:
- shard-tglu-10: NOTRUN -> [SKIP][6] ([i915#7697])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-tglu-10: NOTRUN -> [SKIP][7] ([i915#280])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-tglu-10: NOTRUN -> [FAIL][8] ([i915#6117])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#2842]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-glk7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-glk4/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-apl: [PASS][11] -> [SKIP][12] ([fdo#109271])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-apl3/igt@gem_exec_fair@basic-none-share@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-apl1/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-tglu-10: NOTRUN -> [FAIL][13] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_gttfill@all-engines:
- shard-glk: [PASS][14] -> [DMESG-WARN][15] ([i915#118])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-glk6/igt@gem_exec_gttfill@all-engines.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-glk3/igt@gem_exec_gttfill@all-engines.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-tglu-10: NOTRUN -> [SKIP][16] ([i915#4613]) +2 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_pxp@reject-modify-context-protection-off-1:
- shard-tglu-10: NOTRUN -> [SKIP][17] ([i915#4270])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@gem_pxp@reject-modify-context-protection-off-1.html
* igt@gem_userptr_blits@vma-merge:
- shard-tglu-10: NOTRUN -> [FAIL][18] ([i915#3318])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@gem_userptr_blits@vma-merge.html
* igt@gen7_exec_parse@basic-allocation:
- shard-tglu-10: NOTRUN -> [SKIP][19] ([fdo#109289]) +5 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@gen7_exec_parse@basic-allocation.html
* igt@gen9_exec_parse@bb-chained:
- shard-tglu-10: NOTRUN -> [SKIP][20] ([i915#2527] / [i915#2856]) +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@gen9_exec_parse@bb-chained.html
* igt@i915_pm_dc@dc6-dpms:
- shard-tglu-10: NOTRUN -> [FAIL][21] ([i915#3989] / [i915#454])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
- shard-tglu-10: NOTRUN -> [SKIP][22] ([i915#3826])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-tglu-10: NOTRUN -> [SKIP][23] ([i915#5286]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@linear-16bpp-rotate-270:
- shard-tglu-10: NOTRUN -> [SKIP][24] ([fdo#111614]) +2 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_big_fb@linear-16bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-tglu-10: NOTRUN -> [SKIP][25] ([fdo#111615]) +3 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_joiner@invalid-modeset:
- shard-tglu-10: NOTRUN -> [SKIP][26] ([i915#2705])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_ccs@pipe-a-bad-rotation-90-yf_tiled_ccs:
- shard-tglu-10: NOTRUN -> [SKIP][27] ([fdo#111615] / [i915#3689]) +4 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_ccs@pipe-a-bad-rotation-90-yf_tiled_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-tglu-10: NOTRUN -> [SKIP][28] ([i915#3689] / [i915#3886]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-4_tiled_dg2_rc_ccs:
- shard-tglu-10: NOTRUN -> [SKIP][29] ([i915#3689] / [i915#6095]) +4 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_ccs@pipe-b-random-ccs-data-4_tiled_dg2_rc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_ccs:
- shard-tglu-10: NOTRUN -> [SKIP][30] ([i915#3689]) +7 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_ccs.html
* igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_dg2_mc_ccs:
- shard-tglu-10: NOTRUN -> [SKIP][31] ([i915#6095]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_dg2_mc_ccs.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-tglu-10: NOTRUN -> [SKIP][32] ([i915#3742])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode:
- shard-tglu-10: NOTRUN -> [SKIP][33] ([i915#7828]) +6 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-tglu-10: NOTRUN -> [SKIP][34] ([i915#3116] / [i915#3299])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@uevent:
- shard-tglu-10: NOTRUN -> [SKIP][35] ([i915#6944] / [i915#7116] / [i915#7118]) +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-tglu-10: NOTRUN -> [SKIP][36] ([i915#3359]) +2 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_crc@cursor-sliding-max-size:
- shard-tglu-10: NOTRUN -> [SKIP][37] ([i915#3555]) +3 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_cursor_crc@cursor-sliding-max-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
- shard-tglu-10: NOTRUN -> [SKIP][38] ([fdo#109274]) +2 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
- shard-tglu-10: NOTRUN -> [SKIP][39] ([i915#4103])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-tglu-10: NOTRUN -> [SKIP][40] ([i915#3469]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@2x-nonexisting-fb-interruptible:
- shard-tglu-10: NOTRUN -> [SKIP][41] ([fdo#109274] / [i915#3637]) +6 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_flip@2x-nonexisting-fb-interruptible.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode:
- shard-tglu-10: NOTRUN -> [SKIP][42] ([i915#2587] / [i915#2672]) +5 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-tglu-10: NOTRUN -> [SKIP][43] ([fdo#109285])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-tglu-10: NOTRUN -> [SKIP][44] ([fdo#110189]) +19 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-pwrite:
- shard-glk: NOTRUN -> [SKIP][45] ([fdo#109271]) +4 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-glk7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-tglu-10: NOTRUN -> [SKIP][46] ([i915#5439])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-pwrite:
- shard-tglu-10: NOTRUN -> [SKIP][47] ([fdo#109280]) +26 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-pwrite.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a-hdmi-a-1:
- shard-tglu-10: NOTRUN -> [SKIP][48] ([i915#5235]) +7 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a-hdmi-a-1.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-tglu-10: NOTRUN -> [SKIP][49] ([i915#658]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_writeback@writeback-fb-id:
- shard-tglu-10: NOTRUN -> [SKIP][50] ([i915#2437])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@kms_writeback@writeback-fb-id.html
* igt@prime_vgem@coherency-gtt:
- shard-tglu-10: NOTRUN -> [SKIP][51] ([fdo#109295] / [fdo#111656])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@prime_vgem@coherency-gtt.html
* igt@v3d/v3d_mmap@mmap-bo:
- shard-tglu-10: NOTRUN -> [SKIP][52] ([fdo#109315] / [i915#2575]) +2 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@v3d/v3d_mmap@mmap-bo.html
* igt@vc4/vc4_lookup_fail@bad-color-write:
- shard-tglu-10: NOTRUN -> [SKIP][53] ([i915#2575]) +7 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-10/igt@vc4/vc4_lookup_fail@bad-color-write.html
#### Possible fixes ####
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-tglu}: [FAIL][54] ([i915#6268]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-tglu-3/igt@gem_ctx_exec@basic-nohangcheck.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-8/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_eio@in-flight-suspend:
- {shard-rkl}: [FAIL][56] ([fdo#103375]) -> [PASS][57] +2 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-rkl-4/igt@gem_eio@in-flight-suspend.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-rkl-2/igt@gem_eio@in-flight-suspend.html
* igt@gem_eio@unwedge-stress:
- {shard-dg1}: [FAIL][58] ([i915#5784]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-dg1-18/igt@gem_eio@unwedge-stress.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-dg1-17/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-glk: [FAIL][60] ([i915#2842]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-glk1/igt@gem_exec_fair@basic-none-solo@rcs0.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-glk5/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- {shard-rkl}: [SKIP][62] ([fdo#109313]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-rkl-2/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-rkl-5/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_reloc@basic-wc:
- {shard-rkl}: [SKIP][64] ([i915#3281]) -> [PASS][65] +4 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-rkl-2/igt@gem_exec_reloc@basic-wc.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-rkl-5/igt@gem_exec_reloc@basic-wc.html
* igt@gem_pwrite@basic-self:
- {shard-rkl}: [SKIP][66] ([i915#3282]) -> [PASS][67] +5 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-rkl-1/igt@gem_pwrite@basic-self.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-rkl-5/igt@gem_pwrite@basic-self.html
* igt@gen9_exec_parse@bb-chained:
- {shard-rkl}: [SKIP][68] ([i915#2527]) -> [PASS][69] +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-rkl-1/igt@gen9_exec_parse@bb-chained.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-rkl-5/igt@gen9_exec_parse@bb-chained.html
* igt@i915_pm_dc@dc6-dpms:
- {shard-rkl}: [FAIL][70] ([i915#3989]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-rkl-4/igt@i915_pm_dc@dc6-dpms.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-rkl-2/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-rkl}: [WARN][72] ([i915#2681]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-rkl-4/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
* igt@i915_pm_rpm@fences:
- {shard-rkl}: [SKIP][74] ([i915#1849]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-rkl-5/igt@i915_pm_rpm@fences.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-rkl-6/igt@i915_pm_rpm@fences.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- {shard-tglu}: [SKIP][76] ([i915#1397]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-tglu-6/igt@i915_pm_rpm@modeset-lpsp-stress.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-2/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- {shard-dg1}: [SKIP][78] ([i915#1397]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-dg1-14/igt@i915_pm_rpm@modeset-non-lpsp.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-dg1-17/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_rc_ccs:
- {shard-tglu}: [SKIP][80] ([i915#1845] / [i915#7651]) -> [PASS][81] +21 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-tglu-6/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_rc_ccs.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-1/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_rc_ccs.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- {shard-rkl}: [SKIP][82] ([i915#1845] / [i915#4098]) -> [PASS][83] +9 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-rkl-5/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-rkl-6/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
- {shard-tglu}: [SKIP][84] ([i915#1845]) -> [PASS][85] +5 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-tglu-6/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-1/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [FAIL][86] ([i915#2346]) -> [PASS][87] +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt:
- {shard-tglu}: [SKIP][88] ([i915#1849]) -> [PASS][89] +4 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-tglu-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-tglu-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-gtt:
- {shard-rkl}: [SKIP][90] ([i915#1849] / [i915#4098]) -> [PASS][91] +4 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-gtt.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-gtt.html
* igt@perf_pmu@idle@rcs0:
- {shard-rkl}: [FAIL][92] ([i915#4349]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-rkl-4/igt@perf_pmu@idle@rcs0.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-rkl-2/igt@perf_pmu@idle@rcs0.html
* igt@prime_vgem@basic-write:
- {shard-rkl}: [SKIP][94] ([fdo#109295] / [i915#3291] / [i915#3708]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12831/shard-rkl-1/igt@prime_vgem@basic-write.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/shard-rkl-5/igt@prime_vgem@basic-write.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2532]: https://gitlab.freedesktop.org/drm/intel/issues/2532
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
[i915#7276]: https://gitlab.freedesktop.org/drm/intel/issues/7276
[i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
[i915#7330]: https://gitlab.freedesktop.org/drm/intel/issues/7330
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7949]: https://gitlab.freedesktop.org/drm/intel/issues/7949
[i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
[i915#8152]: https://gitlab.freedesktop.org/drm/intel/issues/8152
[i915#8154]: https://gitlab.freedesktop.org/drm/intel/issues/8154
[i915#8273]: https://gitlab.freedesktop.org/drm/intel/issues/8273
[i915#8275]: https://gitlab.freedesktop.org/drm/intel/issues/8275
Build changes
-------------
* Linux: CI_DRM_12831 -> Patchwork_114920v1
CI-20190529: 20190529
CI_DRM_12831: 4910ebea52abc05f63bfc43bc91baebd8af93d45 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7188: b35bfa32fe672d67ced8555557e3e707ace211ad @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_114920v1: 4910ebea52abc05f63bfc43bc91baebd8af93d45 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114920v1/index.html
[-- Attachment #2: Type: text/html, Size: 30620 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: disable sampler indirect state in bindless heap
2023-03-09 15:26 [Intel-gfx] [PATCH] drm/i915: disable sampler indirect state in bindless heap Lionel Landwerlin
` (2 preceding siblings ...)
2023-03-11 13:45 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2023-03-28 10:44 ` Kalvala, Haridhar
2023-03-28 22:49 ` Matt Atwood
2023-03-30 17:47 ` [Intel-gfx] [v2] " Lionel Landwerlin
` (2 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Kalvala, Haridhar @ 2023-03-28 10:44 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx; +Cc: stable
On 3/9/2023 8:56 PM, Lionel Landwerlin wrote:
> By default the indirect state sampler data (border colors) are stored
> in the same heap as the SAMPLER_STATE structure. For userspace drivers
> that can be 2 different heaps (dynamic state heap & bindless sampler
> state heap). This means that border colors have to copied in 2
> different places so that the same SAMPLER_STATE structure find the
> right data.
>
> This change is forcing the indirect state sampler data to only be in
> the dynamic state pool (more convinient for userspace drivers, they
> only have to have one copy of the border colors). This is reproducing
> the behavior of the Windows drivers.
>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Cc: stable@vger.kernel.org
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 +++++++++++++++++
> 2 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 08d76aa06974c..1aaa471d08c56 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1141,6 +1141,7 @@
> #define ENABLE_SMALLPL REG_BIT(15)
> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
> #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
> +#define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
>
> #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
> #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 32aa1647721ae..734b64e714647 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2542,6 +2542,23 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> ENABLE_SMALLPL);
> }
>
> + if (GRAPHICS_VER(i915) >= 11) {
Hi Lionel,
Not sure should this implementation be part of "rcs_engine_wa_init" or
"general_render_compute_wa_init".
> + /* This is not a Wa (although referred to as
> + * WaSetInidrectStateOverride in places), this allows
> + * applications that reference sampler states through
> + * the BindlessSamplerStateBaseAddress to have their
> + * border color relative to DynamicStateBaseAddress
> + * rather than BindlessSamplerStateBaseAddress.
> + *
> + * Otherwise SAMPLER_STATE border colors have to be
> + * copied in multiple heaps (DynamicStateBaseAddress &
> + * BindlessSamplerStateBaseAddress)
> + */
> + wa_mcr_masked_en(wal,
> + GEN10_SAMPLER_MODE,
since we checking the condition for GEN11 or above, can this register
be defined as GEN11_SAMPLER_MODE
> + GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> + }
> +
> if (GRAPHICS_VER(i915) == 11) {
> /* This is not an Wa. Enable for better image quality */
> wa_masked_en(wal,
--
Regards,
Haridhar Kalvala
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: disable sampler indirect state in bindless heap
2023-03-28 10:44 ` [Intel-gfx] [PATCH] " Kalvala, Haridhar
@ 2023-03-28 22:49 ` Matt Atwood
2023-03-30 17:19 ` Lionel Landwerlin
0 siblings, 1 reply; 18+ messages in thread
From: Matt Atwood @ 2023-03-28 22:49 UTC (permalink / raw)
To: Kalvala, Haridhar, lionel.g.landwerlin, intel-gfx; +Cc: intel-gfx, stable
On Tue, Mar 28, 2023 at 04:14:33PM +0530, Kalvala, Haridhar wrote:
>
> On 3/9/2023 8:56 PM, Lionel Landwerlin wrote:
> > By default the indirect state sampler data (border colors) are stored
> > in the same heap as the SAMPLER_STATE structure. For userspace drivers
> > that can be 2 different heaps (dynamic state heap & bindless sampler
> > state heap). This means that border colors have to copied in 2
> > different places so that the same SAMPLER_STATE structure find the
> > right data.
> >
> > This change is forcing the indirect state sampler data to only be in
> > the dynamic state pool (more convinient for userspace drivers, they
> > only have to have one copy of the border colors). This is reproducing
> > the behavior of the Windows drivers.
> >
Bspec:46052
> > Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> > Cc: stable@vger.kernel.org
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 +++++++++++++++++
> > 2 files changed, 18 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index 08d76aa06974c..1aaa471d08c56 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -1141,6 +1141,7 @@
> > #define ENABLE_SMALLPL REG_BIT(15)
> > #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
> > #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
> > +#define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
> > #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
> > #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 32aa1647721ae..734b64e714647 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -2542,6 +2542,23 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > ENABLE_SMALLPL);
> > }
> > + if (GRAPHICS_VER(i915) >= 11) {
>
> Hi Lionel,
>
> Not sure should this implementation be part of "rcs_engine_wa_init" or
> "general_render_compute_wa_init".
>
> > + /* This is not a Wa (although referred to as
> > + * WaSetInidrectStateOverride in places), this allows
> > + * applications that reference sampler states through
> > + * the BindlessSamplerStateBaseAddress to have their
> > + * border color relative to DynamicStateBaseAddress
> > + * rather than BindlessSamplerStateBaseAddress.
> > + *
> > + * Otherwise SAMPLER_STATE border colors have to be
> > + * copied in multiple heaps (DynamicStateBaseAddress &
> > + * BindlessSamplerStateBaseAddress)
> > + */
> > + wa_mcr_masked_en(wal,
> > + GEN10_SAMPLER_MODE,
>
> since we checking the condition for GEN11 or above, can this register be
> defined as GEN11_SAMPLER_MODE
We use the name of the first time the register was introduced, gen 10 is
fine here.
> > + GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> > + }
> > +
> > if (GRAPHICS_VER(i915) == 11) {
> > /* This is not an Wa. Enable for better image quality */
> > wa_masked_en(wal,
>
> --
> Regards,
> Haridhar Kalvala
>
Regards,
MattA
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: disable sampler indirect state in bindless heap
2023-03-28 22:49 ` Matt Atwood
@ 2023-03-30 17:19 ` Lionel Landwerlin
2023-03-31 7:05 ` Kalvala, Haridhar
0 siblings, 1 reply; 18+ messages in thread
From: Lionel Landwerlin @ 2023-03-30 17:19 UTC (permalink / raw)
To: Matt Atwood, Kalvala, Haridhar, intel-gfx; +Cc: stable
On 29/03/2023 01:49, Matt Atwood wrote:
> On Tue, Mar 28, 2023 at 04:14:33PM +0530, Kalvala, Haridhar wrote:
>> On 3/9/2023 8:56 PM, Lionel Landwerlin wrote:
>>> By default the indirect state sampler data (border colors) are stored
>>> in the same heap as the SAMPLER_STATE structure. For userspace drivers
>>> that can be 2 different heaps (dynamic state heap & bindless sampler
>>> state heap). This means that border colors have to copied in 2
>>> different places so that the same SAMPLER_STATE structure find the
>>> right data.
>>>
>>> This change is forcing the indirect state sampler data to only be in
>>> the dynamic state pool (more convinient for userspace drivers, they
>>> only have to have one copy of the border colors). This is reproducing
>>> the behavior of the Windows drivers.
>>>
> Bspec:46052
Sorry, missed your answer.
Should I just add the Bspec number to the commit message ?
Thanks,
-Lionel
>>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>>> Cc: stable@vger.kernel.org
>>> ---
>>> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
>>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 +++++++++++++++++
>>> 2 files changed, 18 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>> index 08d76aa06974c..1aaa471d08c56 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>> @@ -1141,6 +1141,7 @@
>>> #define ENABLE_SMALLPL REG_BIT(15)
>>> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
>>> #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
>>> +#define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
>>> #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
>>> #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> index 32aa1647721ae..734b64e714647 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> @@ -2542,6 +2542,23 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>> ENABLE_SMALLPL);
>>> }
>>> + if (GRAPHICS_VER(i915) >= 11) {
>> Hi Lionel,
>>
>> Not sure should this implementation be part of "rcs_engine_wa_init" or
>> "general_render_compute_wa_init".
>>
>>> + /* This is not a Wa (although referred to as
>>> + * WaSetInidrectStateOverride in places), this allows
>>> + * applications that reference sampler states through
>>> + * the BindlessSamplerStateBaseAddress to have their
>>> + * border color relative to DynamicStateBaseAddress
>>> + * rather than BindlessSamplerStateBaseAddress.
>>> + *
>>> + * Otherwise SAMPLER_STATE border colors have to be
>>> + * copied in multiple heaps (DynamicStateBaseAddress &
>>> + * BindlessSamplerStateBaseAddress)
>>> + */
>>> + wa_mcr_masked_en(wal,
>>> + GEN10_SAMPLER_MODE,
>> since we checking the condition for GEN11 or above, can this register be
>> defined as GEN11_SAMPLER_MODE
> We use the name of the first time the register was introduced, gen 10 is
> fine here.
>>> + GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>>> + }
>>> +
>>> if (GRAPHICS_VER(i915) == 11) {
>>> /* This is not an Wa. Enable for better image quality */
>>> wa_masked_en(wal,
>> --
>> Regards,
>> Haridhar Kalvala
>>
> Regards,
> MattA
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] [v2] drm/i915: disable sampler indirect state in bindless heap
2023-03-09 15:26 [Intel-gfx] [PATCH] drm/i915: disable sampler indirect state in bindless heap Lionel Landwerlin
` (3 preceding siblings ...)
2023-03-28 10:44 ` [Intel-gfx] [PATCH] " Kalvala, Haridhar
@ 2023-03-30 17:47 ` Lionel Landwerlin
2023-03-30 19:27 ` Matt Atwood
2023-03-30 20:42 ` [Intel-gfx] [v3] " Lionel Landwerlin
2023-03-31 0:06 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: disable sampler indirect state in bindless heap (rev3) Patchwork
6 siblings, 1 reply; 18+ messages in thread
From: Lionel Landwerlin @ 2023-03-30 17:47 UTC (permalink / raw)
To: intel-gfx; +Cc: stable
By default the indirect state sampler data (border colors) are stored
in the same heap as the SAMPLER_STATE structure. For userspace drivers
that can be 2 different heaps (dynamic state heap & bindless sampler
state heap). This means that border colors have to copied in 2
different places so that the same SAMPLER_STATE structure find the
right data.
This change is forcing the indirect state sampler data to only be in
the dynamic state pool (more convinient for userspace drivers, they
only have to have one copy of the border colors). This is reproducing
the behavior of the Windows drivers.
BSpec: 46052
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: stable@vger.kernel.org
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 19 +++++++++++++++++++
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 4aecb5a7b6318..f298dc461a72f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1144,6 +1144,7 @@
#define ENABLE_SMALLPL REG_BIT(15)
#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
+#define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
#define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
#define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e7ee24bcad893..0ce1c8c23c631 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2535,6 +2535,25 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
ENABLE_SMALLPL);
}
+ if (GRAPHICS_VER(i915) >= 11) {
+ /* This is not a Wa (although referred to as
+ * WaSetInidrectStateOverride in places), this allows
+ * applications that reference sampler states through
+ * the BindlessSamplerStateBaseAddress to have their
+ * border color relative to DynamicStateBaseAddress
+ * rather than BindlessSamplerStateBaseAddress.
+ *
+ * Otherwise SAMPLER_STATE border colors have to be
+ * copied in multiple heaps (DynamicStateBaseAddress &
+ * BindlessSamplerStateBaseAddress)
+ *
+ * BSpec: 46052
+ */
+ wa_mcr_masked_en(wal,
+ GEN10_SAMPLER_MODE,
+ GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
+ }
+
if (GRAPHICS_VER(i915) == 11) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
--
2.34.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [v2] drm/i915: disable sampler indirect state in bindless heap
2023-03-30 17:47 ` [Intel-gfx] [v2] " Lionel Landwerlin
@ 2023-03-30 19:27 ` Matt Atwood
2023-03-30 19:38 ` Matt Atwood
0 siblings, 1 reply; 18+ messages in thread
From: Matt Atwood @ 2023-03-30 19:27 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx; +Cc: intel-gfx, stable
On Thu, Mar 30, 2023 at 08:47:40PM +0300, Lionel Landwerlin wrote:
> By default the indirect state sampler data (border colors) are stored
> in the same heap as the SAMPLER_STATE structure. For userspace drivers
> that can be 2 different heaps (dynamic state heap & bindless sampler
> state heap). This means that border colors have to copied in 2
> different places so that the same SAMPLER_STATE structure find the
> right data.
>
> This change is forcing the indirect state sampler data to only be in
> the dynamic state pool (more convinient for userspace drivers, they
convenient
> only have to have one copy of the border colors). This is reproducing
> the behavior of the Windows drivers.
>
> BSpec: 46052
>
Assuming still good CI results..
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Cc: stable@vger.kernel.org
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 19 +++++++++++++++++++
> 2 files changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 4aecb5a7b6318..f298dc461a72f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1144,6 +1144,7 @@
> #define ENABLE_SMALLPL REG_BIT(15)
> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
> #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
> +#define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
>
> #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
> #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index e7ee24bcad893..0ce1c8c23c631 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2535,6 +2535,25 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> ENABLE_SMALLPL);
> }
>
> + if (GRAPHICS_VER(i915) >= 11) {
> + /* This is not a Wa (although referred to as
> + * WaSetInidrectStateOverride in places), this allows
> + * applications that reference sampler states through
> + * the BindlessSamplerStateBaseAddress to have their
> + * border color relative to DynamicStateBaseAddress
> + * rather than BindlessSamplerStateBaseAddress.
> + *
> + * Otherwise SAMPLER_STATE border colors have to be
> + * copied in multiple heaps (DynamicStateBaseAddress &
> + * BindlessSamplerStateBaseAddress)
> + *
> + * BSpec: 46052
> + */
> + wa_mcr_masked_en(wal,
> + GEN10_SAMPLER_MODE,
> + GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> + }
> +
> if (GRAPHICS_VER(i915) == 11) {
> /* This is not an Wa. Enable for better image quality */
> wa_masked_en(wal,
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [v2] drm/i915: disable sampler indirect state in bindless heap
2023-03-30 19:27 ` Matt Atwood
@ 2023-03-30 19:38 ` Matt Atwood
2023-03-30 20:43 ` Lionel Landwerlin
0 siblings, 1 reply; 18+ messages in thread
From: Matt Atwood @ 2023-03-30 19:38 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx; +Cc: stable
On Thu, Mar 30, 2023 at 12:27:33PM -0700, Matt Atwood wrote:
> On Thu, Mar 30, 2023 at 08:47:40PM +0300, Lionel Landwerlin wrote:
> > By default the indirect state sampler data (border colors) are stored
> > in the same heap as the SAMPLER_STATE structure. For userspace drivers
> > that can be 2 different heaps (dynamic state heap & bindless sampler
> > state heap). This means that border colors have to copied in 2
> > different places so that the same SAMPLER_STATE structure find the
> > right data.
> >
> > This change is forcing the indirect state sampler data to only be in
> > the dynamic state pool (more convinient for userspace drivers, they
> convenient
> > only have to have one copy of the border colors). This is reproducing
> > the behavior of the Windows drivers.
> >
> > BSpec: 46052
> >
> Assuming still good CI results..
> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
My mistake version 3 required. comments inline.
> > Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> > Cc: stable@vger.kernel.org
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 19 +++++++++++++++++++
> > 2 files changed, 20 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index 4aecb5a7b6318..f298dc461a72f 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -1144,6 +1144,7 @@
> > #define ENABLE_SMALLPL REG_BIT(15)
> > #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
> > #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
> > +#define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
> >
> > #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
> > #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index e7ee24bcad893..0ce1c8c23c631 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -2535,6 +2535,25 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > ENABLE_SMALLPL);
> > }
> >
This workaround belongs in general render workarounds not rcs, as per
the address space in i915_regs.h 0x2xxx.
#define RENDER_RING_BASE 0x02000
> > + if (GRAPHICS_VER(i915) >= 11) {
> > + /* This is not a Wa (although referred to as
> > + * WaSetInidrectStateOverride in places), this allows
> > + * applications that reference sampler states through
> > + * the BindlessSamplerStateBaseAddress to have their
> > + * border color relative to DynamicStateBaseAddress
> > + * rather than BindlessSamplerStateBaseAddress.
> > + *
> > + * Otherwise SAMPLER_STATE border colors have to be
> > + * copied in multiple heaps (DynamicStateBaseAddress &
> > + * BindlessSamplerStateBaseAddress)
> > + *
> > + * BSpec: 46052
> > + */
> > + wa_mcr_masked_en(wal,
> > + GEN10_SAMPLER_MODE,
> > + GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> > + }
> > +
> > if (GRAPHICS_VER(i915) == 11) {
> > /* This is not an Wa. Enable for better image quality */
> > wa_masked_en(wal,
> > --
> > 2.34.1
> >
MattA
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] [v3] drm/i915: disable sampler indirect state in bindless heap
2023-03-09 15:26 [Intel-gfx] [PATCH] drm/i915: disable sampler indirect state in bindless heap Lionel Landwerlin
` (4 preceding siblings ...)
2023-03-30 17:47 ` [Intel-gfx] [v2] " Lionel Landwerlin
@ 2023-03-30 20:42 ` Lionel Landwerlin
2023-04-04 5:48 ` Kalvala, Haridhar
2023-04-06 21:22 ` Matt Atwood
2023-03-31 0:06 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: disable sampler indirect state in bindless heap (rev3) Patchwork
6 siblings, 2 replies; 18+ messages in thread
From: Lionel Landwerlin @ 2023-03-30 20:42 UTC (permalink / raw)
To: intel-gfx; +Cc: stable
By default the indirect state sampler data (border colors) are stored
in the same heap as the SAMPLER_STATE structure. For userspace drivers
that can be 2 different heaps (dynamic state heap & bindless sampler
state heap). This means that border colors have to copied in 2
different places so that the same SAMPLER_STATE structure find the
right data.
This change is forcing the indirect state sampler data to only be in
the dynamic state pool (more convinient for userspace drivers, they
only have to have one copy of the border colors). This is reproducing
the behavior of the Windows drivers.
BSpec: 46052
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: stable@vger.kernel.org
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 19 +++++++++++++++++++
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 4aecb5a7b6318..f298dc461a72f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1144,6 +1144,7 @@
#define ENABLE_SMALLPL REG_BIT(15)
#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
+#define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
#define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
#define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e7ee24bcad893..5bfc864d5fcc0 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2971,6 +2971,25 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
add_render_compute_tuning_settings(i915, wal);
+ if (GRAPHICS_VER(i915) >= 11) {
+ /* This is not a Wa (although referred to as
+ * WaSetInidrectStateOverride in places), this allows
+ * applications that reference sampler states through
+ * the BindlessSamplerStateBaseAddress to have their
+ * border color relative to DynamicStateBaseAddress
+ * rather than BindlessSamplerStateBaseAddress.
+ *
+ * Otherwise SAMPLER_STATE border colors have to be
+ * copied in multiple heaps (DynamicStateBaseAddress &
+ * BindlessSamplerStateBaseAddress)
+ *
+ * BSpec: 46052
+ */
+ wa_mcr_masked_en(wal,
+ GEN10_SAMPLER_MODE,
+ GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
+ }
+
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
--
2.34.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [v2] drm/i915: disable sampler indirect state in bindless heap
2023-03-30 19:38 ` Matt Atwood
@ 2023-03-30 20:43 ` Lionel Landwerlin
0 siblings, 0 replies; 18+ messages in thread
From: Lionel Landwerlin @ 2023-03-30 20:43 UTC (permalink / raw)
To: Matt Atwood, intel-gfx; +Cc: stable
On 30/03/2023 22:38, Matt Atwood wrote:
> On Thu, Mar 30, 2023 at 12:27:33PM -0700, Matt Atwood wrote:
>> On Thu, Mar 30, 2023 at 08:47:40PM +0300, Lionel Landwerlin wrote:
>>> By default the indirect state sampler data (border colors) are stored
>>> in the same heap as the SAMPLER_STATE structure. For userspace drivers
>>> that can be 2 different heaps (dynamic state heap & bindless sampler
>>> state heap). This means that border colors have to copied in 2
>>> different places so that the same SAMPLER_STATE structure find the
>>> right data.
>>>
>>> This change is forcing the indirect state sampler data to only be in
>>> the dynamic state pool (more convinient for userspace drivers, they
>> convenient
>>> only have to have one copy of the border colors). This is reproducing
>>> the behavior of the Windows drivers.
>>>
>>> BSpec: 46052
>>>
>> Assuming still good CI results..
>> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> My mistake version 3 required. comments inline.
>>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>>> Cc: stable@vger.kernel.org
>>> ---
>>> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
>>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 19 +++++++++++++++++++
>>> 2 files changed, 20 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>> index 4aecb5a7b6318..f298dc461a72f 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>> @@ -1144,6 +1144,7 @@
>>> #define ENABLE_SMALLPL REG_BIT(15)
>>> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
>>> #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
>>> +#define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
>>>
>>> #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
>>> #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> index e7ee24bcad893..0ce1c8c23c631 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> @@ -2535,6 +2535,25 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>> ENABLE_SMALLPL);
>>> }
>>>
> This workaround belongs in general render workarounds not rcs, as per
> the address space in i915_regs.h 0x2xxx.
>
> #define RENDER_RING_BASE 0x02000
Thanks makes sense.
-Lionel
>
>
>>> + if (GRAPHICS_VER(i915) >= 11) {
>>> + /* This is not a Wa (although referred to as
>>> + * WaSetInidrectStateOverride in places), this allows
>>> + * applications that reference sampler states through
>>> + * the BindlessSamplerStateBaseAddress to have their
>>> + * border color relative to DynamicStateBaseAddress
>>> + * rather than BindlessSamplerStateBaseAddress.
>>> + *
>>> + * Otherwise SAMPLER_STATE border colors have to be
>>> + * copied in multiple heaps (DynamicStateBaseAddress &
>>> + * BindlessSamplerStateBaseAddress)
>>> + *
>>> + * BSpec: 46052
>>> + */
>>> + wa_mcr_masked_en(wal,
>>> + GEN10_SAMPLER_MODE,
>>> + GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>>> + }
>>> +
>>> if (GRAPHICS_VER(i915) == 11) {
>>> /* This is not an Wa. Enable for better image quality */
>>> wa_masked_en(wal,
>>> --
>>> 2.34.1
>>>
> MattA
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: disable sampler indirect state in bindless heap (rev3)
2023-03-09 15:26 [Intel-gfx] [PATCH] drm/i915: disable sampler indirect state in bindless heap Lionel Landwerlin
` (5 preceding siblings ...)
2023-03-30 20:42 ` [Intel-gfx] [v3] " Lionel Landwerlin
@ 2023-03-31 0:06 ` Patchwork
6 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2023-03-31 0:06 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: disable sampler indirect state in bindless heap (rev3)
URL : https://patchwork.freedesktop.org/series/114920/
State : failure
== Summary ==
Error: patch https://patchwork.freedesktop.org/api/1.0/series/114920/revisions/3/mbox/ not applied
Applying: drm/i915: disable sampler indirect state in bindless heap
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/gt/intel_gt_regs.h
M drivers/gpu/drm/i915/gt/intel_workarounds.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/gt/intel_workarounds.c
Auto-merging drivers/gpu/drm/i915/gt/intel_gt_regs.h
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_gt_regs.h
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 drm/i915: disable sampler indirect state in bindless heap
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Build failed, no error log produced
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: disable sampler indirect state in bindless heap
2023-03-30 17:19 ` Lionel Landwerlin
@ 2023-03-31 7:05 ` Kalvala, Haridhar
2023-04-03 18:22 ` Kalvala, Haridhar
0 siblings, 1 reply; 18+ messages in thread
From: Kalvala, Haridhar @ 2023-03-31 7:05 UTC (permalink / raw)
To: Lionel Landwerlin, Matt Atwood, intel-gfx; +Cc: stable
On 3/30/2023 10:49 PM, Lionel Landwerlin wrote:
> On 29/03/2023 01:49, Matt Atwood wrote:
>> On Tue, Mar 28, 2023 at 04:14:33PM +0530, Kalvala, Haridhar wrote:
>>> On 3/9/2023 8:56 PM, Lionel Landwerlin wrote:
>>>> By default the indirect state sampler data (border colors) are stored
>>>> in the same heap as the SAMPLER_STATE structure. For userspace drivers
>>>> that can be 2 different heaps (dynamic state heap & bindless sampler
>>>> state heap). This means that border colors have to copied in 2
>>>> different places so that the same SAMPLER_STATE structure find the
>>>> right data.
>>>>
>>>> This change is forcing the indirect state sampler data to only be in
>>>> the dynamic state pool (more convinient for userspace drivers, they
>>>> only have to have one copy of the border colors). This is reproducing
>>>> the behavior of the Windows drivers.
>>>>
>> Bspec:46052
>
>
> Sorry, missed your answer.
>
>
> Should I just add the Bspec number to the commit message ?
>
>
> Thanks,
>
>
> -Lionel
>
>
>>>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>>>> Cc: stable@vger.kernel.org
>>>> ---
>>>> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
>>>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 +++++++++++++++++
>>>> 2 files changed, 18 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>>> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>>> index 08d76aa06974c..1aaa471d08c56 100644
>>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>>> @@ -1141,6 +1141,7 @@
>>>> #define ENABLE_SMALLPL REG_BIT(15)
>>>> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
>>>> #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
>>>> +#define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
>>>> #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
>>>> #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>> index 32aa1647721ae..734b64e714647 100644
>>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>> @@ -2542,6 +2542,23 @@ rcs_engine_wa_init(struct intel_engine_cs
>>>> *engine, struct i915_wa_list *wal)
>>>> ENABLE_SMALLPL);
>>>> }
>>>> + if (GRAPHICS_VER(i915) >= 11) {
>>> Hi Lionel,
>>>
>>> Not sure should this implementation be part of "rcs_engine_wa_init" or
>>> "general_render_compute_wa_init" ?
>>>> + /* This is not a Wa (although referred to as
>>>> + * WaSetInidrectStateOverride in places), this allows
>>>> + * applications that reference sampler states through
>>>> + * the BindlessSamplerStateBaseAddress to have their
>>>> + * border color relative to DynamicStateBaseAddress
>>>> + * rather than BindlessSamplerStateBaseAddress.
>>>> + *
>>>> + * Otherwise SAMPLER_STATE border colors have to be
>>>> + * copied in multiple heaps (DynamicStateBaseAddress &
>>>> + * BindlessSamplerStateBaseAddress)
>>>> + */
>>>> + wa_mcr_masked_en(wal,
>>>> + GEN10_SAMPLER_MODE,
>>> since we checking the condition for GEN11 or above, can this
>>> register be
>>> defined as GEN11_SAMPLER_MODE
>> We use the name of the first time the register was introduced, gen 10 is
>> fine here.
ok
>>>> + GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>>>> + }
>>>> +
>>>> if (GRAPHICS_VER(i915) == 11) {
>>>> /* This is not an Wa. Enable for better image quality */
>>>> wa_masked_en(wal,
>>> --
>>> Regards,
>>> Haridhar Kalvala
>>>
>> Regards,
>> MattA
>
>
--
Regards,
Haridhar Kalvala
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: disable sampler indirect state in bindless heap
2023-03-31 7:05 ` Kalvala, Haridhar
@ 2023-04-03 18:22 ` Kalvala, Haridhar
2023-04-03 21:59 ` Lionel Landwerlin
0 siblings, 1 reply; 18+ messages in thread
From: Kalvala, Haridhar @ 2023-04-03 18:22 UTC (permalink / raw)
To: Lionel Landwerlin, Matt Atwood, intel-gfx; +Cc: stable
On 3/31/2023 12:35 PM, Kalvala, Haridhar wrote:
>
> On 3/30/2023 10:49 PM, Lionel Landwerlin wrote:
>> On 29/03/2023 01:49, Matt Atwood wrote:
>>> On Tue, Mar 28, 2023 at 04:14:33PM +0530, Kalvala, Haridhar wrote:
>>>> On 3/9/2023 8:56 PM, Lionel Landwerlin wrote:
>>>>> By default the indirect state sampler data (border colors) are stored
>>>>> in the same heap as the SAMPLER_STATE structure. For userspace
>>>>> drivers
>>>>> that can be 2 different heaps (dynamic state heap & bindless sampler
>>>>> state heap). This means that border colors have to copied in 2
>>>>> different places so that the same SAMPLER_STATE structure find the
>>>>> right data.
>>>>>
>>>>> This change is forcing the indirect state sampler data to only be in
>>>>> the dynamic state pool (more convinient for userspace drivers, they
>>>>> only have to have one copy of the border colors). This is reproducing
>>>>> the behavior of the Windows drivers.
>>>>>
>>> Bspec:46052
>>
>>
>> Sorry, missed your answer.
>>
>>
>> Should I just add the Bspec number to the commit message ?
>>
>>
>> Thanks,
>>
>>
>> -Lionel
>>
>>
>>>>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>>>>> Cc: stable@vger.kernel.org
>>>>> ---
>>>>> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
>>>>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 +++++++++++++++++
>>>>> 2 files changed, 18 insertions(+)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>>>> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>>>> index 08d76aa06974c..1aaa471d08c56 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>>>> @@ -1141,6 +1141,7 @@
>>>>> #define ENABLE_SMALLPL REG_BIT(15)
>>>>> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
>>>>> #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
>>>>> +#define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
>>>>> #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
>>>>> #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>> index 32aa1647721ae..734b64e714647 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>> @@ -2542,6 +2542,23 @@ rcs_engine_wa_init(struct intel_engine_cs
>>>>> *engine, struct i915_wa_list *wal)
>>>>> ENABLE_SMALLPL);
>>>>> }
>>>>> + if (GRAPHICS_VER(i915) >= 11) {
>>>> Hi Lionel,
>>>>
>>>> Not sure should this implementation be part of "rcs_engine_wa_init" or
>>>> "general_render_compute_wa_init" ?
I checked with Matt Ropper as well, looks like this implementation
should be part of "general_render_compute_wa_init".
>
>>>>> + /* This is not a Wa (although referred to as
>>>>> + * WaSetInidrectStateOverride in places), this allows
>>>>> + * applications that reference sampler states through
>>>>> + * the BindlessSamplerStateBaseAddress to have their
>>>>> + * border color relative to DynamicStateBaseAddress
>>>>> + * rather than BindlessSamplerStateBaseAddress.
>>>>> + *
>>>>> + * Otherwise SAMPLER_STATE border colors have to be
>>>>> + * copied in multiple heaps (DynamicStateBaseAddress &
>>>>> + * BindlessSamplerStateBaseAddress)
>>>>> + */
>>>>> + wa_mcr_masked_en(wal,
>>>>> + GEN10_SAMPLER_MODE,
>>>> since we checking the condition for GEN11 or above, can this
>>>> register be
>>>> defined as GEN11_SAMPLER_MODE
>>> We use the name of the first time the register was introduced, gen
>>> 10 is
>>> fine here.
> ok
>>>>> + GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>>>>> + }
>>>>> +
>>>>> if (GRAPHICS_VER(i915) == 11) {
>>>>> /* This is not an Wa. Enable for better image quality */
>>>>> wa_masked_en(wal,
>>>> --
>>>> Regards,
>>>> Haridhar Kalvala
>>>>
>>> Regards,
>>> MattA
>>
>>
--
Regards,
Haridhar Kalvala
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: disable sampler indirect state in bindless heap
2023-04-03 18:22 ` Kalvala, Haridhar
@ 2023-04-03 21:59 ` Lionel Landwerlin
0 siblings, 0 replies; 18+ messages in thread
From: Lionel Landwerlin @ 2023-04-03 21:59 UTC (permalink / raw)
To: Kalvala, Haridhar, Matt Atwood, intel-gfx; +Cc: stable
On 03/04/2023 21:22, Kalvala, Haridhar wrote:
>
> On 3/31/2023 12:35 PM, Kalvala, Haridhar wrote:
>>
>> On 3/30/2023 10:49 PM, Lionel Landwerlin wrote:
>>> On 29/03/2023 01:49, Matt Atwood wrote:
>>>> On Tue, Mar 28, 2023 at 04:14:33PM +0530, Kalvala, Haridhar wrote:
>>>>> On 3/9/2023 8:56 PM, Lionel Landwerlin wrote:
>>>>>> By default the indirect state sampler data (border colors) are
>>>>>> stored
>>>>>> in the same heap as the SAMPLER_STATE structure. For userspace
>>>>>> drivers
>>>>>> that can be 2 different heaps (dynamic state heap & bindless sampler
>>>>>> state heap). This means that border colors have to copied in 2
>>>>>> different places so that the same SAMPLER_STATE structure find the
>>>>>> right data.
>>>>>>
>>>>>> This change is forcing the indirect state sampler data to only be in
>>>>>> the dynamic state pool (more convinient for userspace drivers, they
>>>>>> only have to have one copy of the border colors). This is
>>>>>> reproducing
>>>>>> the behavior of the Windows drivers.
>>>>>>
>>>> Bspec:46052
>>>
>>>
>>> Sorry, missed your answer.
>>>
>>>
>>> Should I just add the Bspec number to the commit message ?
>>>
>>>
>>> Thanks,
>>>
>>>
>>> -Lionel
>>>
>>>
>>>>>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>>>>>> Cc: stable@vger.kernel.org
>>>>>> ---
>>>>>> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
>>>>>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 17
>>>>>> +++++++++++++++++
>>>>>> 2 files changed, 18 insertions(+)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>>>>> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>>>>> index 08d76aa06974c..1aaa471d08c56 100644
>>>>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>>>>> @@ -1141,6 +1141,7 @@
>>>>>> #define ENABLE_SMALLPL REG_BIT(15)
>>>>>> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
>>>>>> #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
>>>>>> +#define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
>>>>>> #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
>>>>>> #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
>>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>>> index 32aa1647721ae..734b64e714647 100644
>>>>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>>> @@ -2542,6 +2542,23 @@ rcs_engine_wa_init(struct intel_engine_cs
>>>>>> *engine, struct i915_wa_list *wal)
>>>>>> ENABLE_SMALLPL);
>>>>>> }
>>>>>> + if (GRAPHICS_VER(i915) >= 11) {
>>>>> Hi Lionel,
>>>>>
>>>>> Not sure should this implementation be part of
>>>>> "rcs_engine_wa_init" or
>>>>> "general_render_compute_wa_init" ?
>
>
> I checked with Matt Ropper as well, looks like this implementation
> should be part of "general_render_compute_wa_init".
I did send a v3 of the patch last Thursday to address this.
Let me know if that's good.
Thanks,
-Lionel
>
>>
>>>>>> + /* This is not a Wa (although referred to as
>>>>>> + * WaSetInidrectStateOverride in places), this allows
>>>>>> + * applications that reference sampler states through
>>>>>> + * the BindlessSamplerStateBaseAddress to have their
>>>>>> + * border color relative to DynamicStateBaseAddress
>>>>>> + * rather than BindlessSamplerStateBaseAddress.
>>>>>> + *
>>>>>> + * Otherwise SAMPLER_STATE border colors have to be
>>>>>> + * copied in multiple heaps (DynamicStateBaseAddress &
>>>>>> + * BindlessSamplerStateBaseAddress)
>>>>>> + */
>>>>>> + wa_mcr_masked_en(wal,
>>>>>> + GEN10_SAMPLER_MODE,
>>>>> since we checking the condition for GEN11 or above, can this
>>>>> register be
>>>>> defined as GEN11_SAMPLER_MODE
>>>> We use the name of the first time the register was introduced, gen
>>>> 10 is
>>>> fine here.
>> ok
>>>>>> + GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>>>>>> + }
>>>>>> +
>>>>>> if (GRAPHICS_VER(i915) == 11) {
>>>>>> /* This is not an Wa. Enable for better image quality */
>>>>>> wa_masked_en(wal,
>>>>> --
>>>>> Regards,
>>>>> Haridhar Kalvala
>>>>>
>>>> Regards,
>>>> MattA
>>>
>>>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [v3] drm/i915: disable sampler indirect state in bindless heap
2023-03-30 20:42 ` [Intel-gfx] [v3] " Lionel Landwerlin
@ 2023-04-04 5:48 ` Kalvala, Haridhar
2023-04-06 21:22 ` Matt Atwood
1 sibling, 0 replies; 18+ messages in thread
From: Kalvala, Haridhar @ 2023-04-04 5:48 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx; +Cc: stable
[-- Attachment #1: Type: text/plain, Size: 2974 bytes --]
On 3/31/2023 2:12 AM, Lionel Landwerlin wrote:
> By default the indirect state sampler data (border colors) are stored
> in the same heap as the SAMPLER_STATE structure. For userspace drivers
> that can be 2 different heaps (dynamic state heap & bindless sampler
> state heap). This means that border colors have to copied in 2
> different places so that the same SAMPLER_STATE structure find the
> right data.
>
> This change is forcing the indirect state sampler data to only be in
> the dynamic state pool (more convinient for userspace drivers, they
> only have to have one copy of the border colors). This is reproducing
> the behavior of the Windows drivers.
>
> BSpec: 46052
>
> Signed-off-by: Lionel Landwerlin<lionel.g.landwerlin@intel.com>
> Cc:stable@vger.kernel.org
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 19 +++++++++++++++++++
> 2 files changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 4aecb5a7b6318..f298dc461a72f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1144,6 +1144,7 @@
> #define ENABLE_SMALLPL REG_BIT(15)
> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
> #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
> +#define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
>
> #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
> #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index e7ee24bcad893..5bfc864d5fcc0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2971,6 +2971,25 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>
> add_render_compute_tuning_settings(i915, wal);
>
> + if (GRAPHICS_VER(i915) >= 11) {
> + /* This is not a Wa (although referred to as
> + * WaSetInidrectStateOverride in places), this allows
> + * applications that reference sampler states through
> + * the BindlessSamplerStateBaseAddress to have their
> + * border color relative to DynamicStateBaseAddress
> + * rather than BindlessSamplerStateBaseAddress.
> + *
> + * Otherwise SAMPLER_STATE border colors have to be
> + * copied in multiple heaps (DynamicStateBaseAddress &
> + * BindlessSamplerStateBaseAddress)
> + *
> + * BSpec: 46052
> + */
> + wa_mcr_masked_en(wal,
> + GEN10_SAMPLER_MODE,
> + GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> + }
> +
Looks Good to me.
Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
> if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
--
Regards,
Haridhar Kalvala
[-- Attachment #2: Type: text/html, Size: 4045 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [v3] drm/i915: disable sampler indirect state in bindless heap
2023-03-30 20:42 ` [Intel-gfx] [v3] " Lionel Landwerlin
2023-04-04 5:48 ` Kalvala, Haridhar
@ 2023-04-06 21:22 ` Matt Atwood
1 sibling, 0 replies; 18+ messages in thread
From: Matt Atwood @ 2023-04-06 21:22 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx; +Cc: intel-gfx, stable
On Thu, Mar 30, 2023 at 11:42:28PM +0300, Lionel Landwerlin wrote:
> By default the indirect state sampler data (border colors) are stored
> in the same heap as the SAMPLER_STATE structure. For userspace drivers
> that can be 2 different heaps (dynamic state heap & bindless sampler
> state heap). This means that border colors have to copied in 2
> different places so that the same SAMPLER_STATE structure find the
> right data.
>
> This change is forcing the indirect state sampler data to only be in
> the dynamic state pool (more convinient for userspace drivers, they
> only have to have one copy of the border colors). This is reproducing
> the behavior of the Windows drivers.
>
> BSpec: 46052
>
ci failed to build, respin and submit
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Cc: stable@vger.kernel.org
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 19 +++++++++++++++++++
> 2 files changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 4aecb5a7b6318..f298dc461a72f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1144,6 +1144,7 @@
> #define ENABLE_SMALLPL REG_BIT(15)
> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
> #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
> +#define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
>
> #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
> #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index e7ee24bcad893..5bfc864d5fcc0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2971,6 +2971,25 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>
> add_render_compute_tuning_settings(i915, wal);
>
> + if (GRAPHICS_VER(i915) >= 11) {
> + /* This is not a Wa (although referred to as
> + * WaSetInidrectStateOverride in places), this allows
> + * applications that reference sampler states through
> + * the BindlessSamplerStateBaseAddress to have their
> + * border color relative to DynamicStateBaseAddress
> + * rather than BindlessSamplerStateBaseAddress.
> + *
> + * Otherwise SAMPLER_STATE border colors have to be
> + * copied in multiple heaps (DynamicStateBaseAddress &
> + * BindlessSamplerStateBaseAddress)
> + *
> + * BSpec: 46052
> + */
> + wa_mcr_masked_en(wal,
> + GEN10_SAMPLER_MODE,
> + GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> + }
> +
> if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2023-04-06 21:22 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-09 15:26 [Intel-gfx] [PATCH] drm/i915: disable sampler indirect state in bindless heap Lionel Landwerlin
2023-03-09 17:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2023-03-09 17:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-11 13:45 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-03-28 10:44 ` [Intel-gfx] [PATCH] " Kalvala, Haridhar
2023-03-28 22:49 ` Matt Atwood
2023-03-30 17:19 ` Lionel Landwerlin
2023-03-31 7:05 ` Kalvala, Haridhar
2023-04-03 18:22 ` Kalvala, Haridhar
2023-04-03 21:59 ` Lionel Landwerlin
2023-03-30 17:47 ` [Intel-gfx] [v2] " Lionel Landwerlin
2023-03-30 19:27 ` Matt Atwood
2023-03-30 19:38 ` Matt Atwood
2023-03-30 20:43 ` Lionel Landwerlin
2023-03-30 20:42 ` [Intel-gfx] [v3] " Lionel Landwerlin
2023-04-04 5:48 ` Kalvala, Haridhar
2023-04-06 21:22 ` Matt Atwood
2023-03-31 0:06 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: disable sampler indirect state in bindless heap (rev3) Patchwork
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