* [Intel-gfx] [PATCH] drm/i915/guc: Don't capture Gen8 regs on Gen12 devices
@ 2023-04-03 21:33 John.C.Harrison
2023-04-03 22:36 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: John.C.Harrison @ 2023-04-03 21:33 UTC (permalink / raw)
To: Intel-GFX
Cc: Balasubramani Vivekanandan, Alan Previn, Jani Nikula, Matt Roper,
Lucas De Marchi, DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
A pair of pre-Gen12 registers were being included in the Gen12 capture
list. GuC was rejecting those as being invalid and logging errors
about them. So, stop doing it.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Fixes: dce2bd542337 ("drm/i915/guc: Add Gen9 registers for GuC error state capture.")
Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index cf49188db6a6e..e0e793167d61b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -31,12 +31,14 @@
{ FORCEWAKE_MT, 0, 0, "FORCEWAKE" }
#define COMMON_GEN9BASE_GLOBAL \
- { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \
- { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" }, \
{ ERROR_GEN6, 0, 0, "ERROR_GEN6" }, \
{ DONE_REG, 0, 0, "DONE_REG" }, \
{ HSW_GTT_CACHE_EN, 0, 0, "HSW_GTT_CACHE_EN" }
+#define GEN9_GLOBAL \
+ { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \
+ { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" }
+
#define COMMON_GEN12BASE_GLOBAL \
{ GEN12_FAULT_TLB_DATA0, 0, 0, "GEN12_FAULT_TLB_DATA0" }, \
{ GEN12_FAULT_TLB_DATA1, 0, 0, "GEN12_FAULT_TLB_DATA1" }, \
@@ -142,6 +144,7 @@ static const struct __guc_mmio_reg_descr xe_lpd_gsc_inst_regs[] = {
static const struct __guc_mmio_reg_descr default_global_regs[] = {
COMMON_BASE_GLOBAL,
COMMON_GEN9BASE_GLOBAL,
+ GEN9_GLOBAL,
};
static const struct __guc_mmio_reg_descr default_rc_class_regs[] = {
--
2.39.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/guc: Don't capture Gen8 regs on Gen12 devices
2023-04-03 21:33 [Intel-gfx] [PATCH] drm/i915/guc: Don't capture Gen8 regs on Gen12 devices John.C.Harrison
@ 2023-04-03 22:36 ` Patchwork
2023-04-03 22:57 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-04-04 0:34 ` [Intel-gfx] [PATCH] " Matt Roper
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2023-04-03 22:36 UTC (permalink / raw)
To: john.c.harrison; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/guc: Don't capture Gen8 regs on Gen12 devices
URL : https://patchwork.freedesktop.org/series/116051/
State : warning
== Summary ==
Error: dim checkpatch failed
c238f339fd40 drm/i915/guc: Don't capture Gen8 regs on Gen12 devices
-:35: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#35: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:38:
+#define GEN9_GLOBAL \
+ { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \
+ { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" }
total: 1 errors, 0 warnings, 0 checks, 23 lines checked
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/guc: Don't capture Gen8 regs on Gen12 devices
2023-04-03 21:33 [Intel-gfx] [PATCH] drm/i915/guc: Don't capture Gen8 regs on Gen12 devices John.C.Harrison
2023-04-03 22:36 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2023-04-03 22:57 ` Patchwork
2023-04-04 0:34 ` [Intel-gfx] [PATCH] " Matt Roper
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2023-04-03 22:57 UTC (permalink / raw)
To: john.c.harrison; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5516 bytes --]
== Series Details ==
Series: drm/i915/guc: Don't capture Gen8 regs on Gen12 devices
URL : https://patchwork.freedesktop.org/series/116051/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12961 -> Patchwork_116051v1
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_116051v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_116051v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116051v1/index.html
Participating hosts (36 -> 36)
------------------------------
Additional (1): fi-pnv-d510
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_116051v1:
### IGT changes ###
#### Possible regressions ####
* igt@dmabuf@all-tests@dma_fence:
- fi-glk-j4005: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12961/fi-glk-j4005/igt@dmabuf@all-tests@dma_fence.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116051v1/fi-glk-j4005/igt@dmabuf@all-tests@dma_fence.html
Known issues
------------
Here are the changes found in Patchwork_116051v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@dmabuf@all-tests@sanitycheck:
- fi-glk-j4005: [PASS][3] -> [ABORT][4] ([i915#8143])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12961/fi-glk-j4005/igt@dmabuf@all-tests@sanitycheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116051v1/fi-glk-j4005/igt@dmabuf@all-tests@sanitycheck.html
* igt@i915_selftest@live@requests:
- bat-rpls-2: [PASS][5] -> [ABORT][6] ([i915#7913] / [i915#7982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12961/bat-rpls-2/igt@i915_selftest@live@requests.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116051v1/bat-rpls-2/igt@i915_selftest@live@requests.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: [PASS][7] -> [ABORT][8] ([i915#6687] / [i915#7978])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12961/bat-rpls-1/igt@i915_suspend@basic-s3-without-i915.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116051v1/bat-rpls-1/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [PASS][9] -> [FAIL][10] ([i915#7932])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12961/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116051v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
* igt@kms_psr@primary_page_flip:
- fi-pnv-d510: NOTRUN -> [SKIP][11] ([fdo#109271]) +38 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116051v1/fi-pnv-d510/igt@kms_psr@primary_page_flip.html
#### Possible fixes ####
* igt@i915_pm_rps@basic-api:
- bat-dg2-11: [FAIL][12] ([i915#8308]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12961/bat-dg2-11/igt@i915_pm_rps@basic-api.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116051v1/bat-dg2-11/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@gt_pm:
- bat-rpls-2: [DMESG-FAIL][14] ([i915#4258]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12961/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116051v1/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [DMESG-FAIL][16] ([i915#6367]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12961/bat-rpls-1/igt@i915_selftest@live@slpc.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116051v1/bat-rpls-1/igt@i915_selftest@live@slpc.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982
[i915#8143]: https://gitlab.freedesktop.org/drm/intel/issues/8143
[i915#8308]: https://gitlab.freedesktop.org/drm/intel/issues/8308
Build changes
-------------
* Linux: CI_DRM_12961 -> Patchwork_116051v1
CI-20190529: 20190529
CI_DRM_12961: 82f1e99798a184af2c21c9c8748f3fba4bdc4556 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7233: 716520b469a2745e1882780f2aabbc88eb19332c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116051v1: 82f1e99798a184af2c21c9c8748f3fba4bdc4556 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
89f2ba64d435 drm/i915/guc: Don't capture Gen8 regs on Gen12 devices
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116051v1/index.html
[-- Attachment #2: Type: text/html, Size: 6356 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/guc: Don't capture Gen8 regs on Gen12 devices
2023-04-03 21:33 [Intel-gfx] [PATCH] drm/i915/guc: Don't capture Gen8 regs on Gen12 devices John.C.Harrison
2023-04-03 22:36 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2023-04-03 22:57 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2023-04-04 0:34 ` Matt Roper
2023-04-05 21:13 ` John Harrison
2 siblings, 1 reply; 6+ messages in thread
From: Matt Roper @ 2023-04-04 0:34 UTC (permalink / raw)
To: John.C.Harrison
Cc: Balasubramani Vivekanandan, Alan Previn, Jani Nikula, Intel-GFX,
Lucas De Marchi, DRI-Devel
On Mon, Apr 03, 2023 at 02:33:34PM -0700, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> A pair of pre-Gen12 registers were being included in the Gen12 capture
> list. GuC was rejecting those as being invalid and logging errors
> about them. So, stop doing it.
Looks like these registers existed from gen8-gen11. With this change,
it looks like they also won't be included in the GuC error capture for
gen11 (ICL and EHL/JSL) since those platforms return xe_lpd_lists [1]
rather than default_lists; do we care about that? I assume not (since
those platforms don't use GuC submission unless you force it with the
enable_guc modparam and taint your kernel), but I figured I should point
it out.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
[1] Why is the main list we use called xe_lpd (i.e., the name of ADL-P's
display IP)? It doesn't seem like we're doing anything with display
registers here so using display IP naming seems really confusing.
Matt
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> Fixes: dce2bd542337 ("drm/i915/guc: Add Gen9 registers for GuC error state capture.")
> Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: John Harrison <John.C.Harrison@Intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> index cf49188db6a6e..e0e793167d61b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> @@ -31,12 +31,14 @@
> { FORCEWAKE_MT, 0, 0, "FORCEWAKE" }
>
> #define COMMON_GEN9BASE_GLOBAL \
> - { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \
> - { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" }, \
> { ERROR_GEN6, 0, 0, "ERROR_GEN6" }, \
> { DONE_REG, 0, 0, "DONE_REG" }, \
> { HSW_GTT_CACHE_EN, 0, 0, "HSW_GTT_CACHE_EN" }
>
> +#define GEN9_GLOBAL \
> + { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \
> + { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" }
> +
> #define COMMON_GEN12BASE_GLOBAL \
> { GEN12_FAULT_TLB_DATA0, 0, 0, "GEN12_FAULT_TLB_DATA0" }, \
> { GEN12_FAULT_TLB_DATA1, 0, 0, "GEN12_FAULT_TLB_DATA1" }, \
> @@ -142,6 +144,7 @@ static const struct __guc_mmio_reg_descr xe_lpd_gsc_inst_regs[] = {
> static const struct __guc_mmio_reg_descr default_global_regs[] = {
> COMMON_BASE_GLOBAL,
> COMMON_GEN9BASE_GLOBAL,
> + GEN9_GLOBAL,
> };
>
> static const struct __guc_mmio_reg_descr default_rc_class_regs[] = {
> --
> 2.39.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/guc: Don't capture Gen8 regs on Gen12 devices
2023-04-04 0:34 ` [Intel-gfx] [PATCH] " Matt Roper
@ 2023-04-05 21:13 ` John Harrison
2023-04-05 21:45 ` Matt Roper
0 siblings, 1 reply; 6+ messages in thread
From: John Harrison @ 2023-04-05 21:13 UTC (permalink / raw)
To: Matt Roper
Cc: Balasubramani Vivekanandan, Alan Previn, Jani Nikula, Intel-GFX,
Lucas De Marchi, DRI-Devel
On 4/3/2023 17:34, Matt Roper wrote:
> On Mon, Apr 03, 2023 at 02:33:34PM -0700, John.C.Harrison@Intel.com wrote:
>> From: John Harrison <John.C.Harrison@Intel.com>
>>
>> A pair of pre-Gen12 registers were being included in the Gen12 capture
>> list. GuC was rejecting those as being invalid and logging errors
>> about them. So, stop doing it.
> Looks like these registers existed from gen8-gen11. With this change,
> it looks like they also won't be included in the GuC error capture for
> gen11 (ICL and EHL/JSL) since those platforms return xe_lpd_lists [1]
> rather than default_lists; do we care about that? I assume not (since
> those platforms don't use GuC submission unless you force it with the
> enable_guc modparam and taint your kernel), but I figured I should point
> it out.
Yeah, I think the code is treating Gen11 as Gen12 rather than Gen9 or
it's own thing. I hadn't spotted that before. It certainly seems incorrect.
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
>
> [1] Why is the main list we use called xe_lpd (i.e., the name of ADL-P's
> display IP)? It doesn't seem like we're doing anything with display
> registers here so using display IP naming seems really confusing.
I think because no-one has a clue what name refers to what hardware any
more :(.
What are the official names for IP_VER 9, 11, 12.00, 12.50 and 12.55?
John.
>
>
> Matt
>
>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>> Fixes: dce2bd542337 ("drm/i915/guc: Add Gen9 registers for GuC error state capture.")
>> Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
>> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> Cc: John Harrison <John.C.Harrison@Intel.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 7 +++++--
>> 1 file changed, 5 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
>> index cf49188db6a6e..e0e793167d61b 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
>> @@ -31,12 +31,14 @@
>> { FORCEWAKE_MT, 0, 0, "FORCEWAKE" }
>>
>> #define COMMON_GEN9BASE_GLOBAL \
>> - { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \
>> - { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" }, \
>> { ERROR_GEN6, 0, 0, "ERROR_GEN6" }, \
>> { DONE_REG, 0, 0, "DONE_REG" }, \
>> { HSW_GTT_CACHE_EN, 0, 0, "HSW_GTT_CACHE_EN" }
>>
>> +#define GEN9_GLOBAL \
>> + { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \
>> + { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" }
>> +
>> #define COMMON_GEN12BASE_GLOBAL \
>> { GEN12_FAULT_TLB_DATA0, 0, 0, "GEN12_FAULT_TLB_DATA0" }, \
>> { GEN12_FAULT_TLB_DATA1, 0, 0, "GEN12_FAULT_TLB_DATA1" }, \
>> @@ -142,6 +144,7 @@ static const struct __guc_mmio_reg_descr xe_lpd_gsc_inst_regs[] = {
>> static const struct __guc_mmio_reg_descr default_global_regs[] = {
>> COMMON_BASE_GLOBAL,
>> COMMON_GEN9BASE_GLOBAL,
>> + GEN9_GLOBAL,
>> };
>>
>> static const struct __guc_mmio_reg_descr default_rc_class_regs[] = {
>> --
>> 2.39.1
>>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/guc: Don't capture Gen8 regs on Gen12 devices
2023-04-05 21:13 ` John Harrison
@ 2023-04-05 21:45 ` Matt Roper
0 siblings, 0 replies; 6+ messages in thread
From: Matt Roper @ 2023-04-05 21:45 UTC (permalink / raw)
To: John Harrison
Cc: Balasubramani Vivekanandan, Alan Previn, Jani Nikula, Intel-GFX,
Lucas De Marchi, DRI-Devel
On Wed, Apr 05, 2023 at 02:13:31PM -0700, John Harrison wrote:
> On 4/3/2023 17:34, Matt Roper wrote:
> > On Mon, Apr 03, 2023 at 02:33:34PM -0700, John.C.Harrison@Intel.com wrote:
> > > From: John Harrison <John.C.Harrison@Intel.com>
> > >
> > > A pair of pre-Gen12 registers were being included in the Gen12 capture
> > > list. GuC was rejecting those as being invalid and logging errors
> > > about them. So, stop doing it.
> > Looks like these registers existed from gen8-gen11. With this change,
> > it looks like they also won't be included in the GuC error capture for
> > gen11 (ICL and EHL/JSL) since those platforms return xe_lpd_lists [1]
> > rather than default_lists; do we care about that? I assume not (since
> > those platforms don't use GuC submission unless you force it with the
> > enable_guc modparam and taint your kernel), but I figured I should point
> > it out.
> Yeah, I think the code is treating Gen11 as Gen12 rather than Gen9 or it's
> own thing. I hadn't spotted that before. It certainly seems incorrect.
>
> >
> > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> >
> >
> > [1] Why is the main list we use called xe_lpd (i.e., the name of ADL-P's
> > display IP)? It doesn't seem like we're doing anything with display
> > registers here so using display IP naming seems really confusing.
> I think because no-one has a clue what name refers to what hardware any more
> :(.
>
> What are the official names for IP_VER 9, 11, 12.00, 12.50 and 12.55?
Yeah, the naming is a real mess. :-( For graphics IP, the official
terms are supposed to be:
12.00 = Xe_LP
12.10 = Xe_LP+ (basically the same as Xe_LP except for interrupts)
12.50 = Xe_HP
12.55 = Xe_HPG (it's nearly identical to Xe_HP)
12.7x = Xe_LPG
There are separate names for media, although we didn't really start
using them anywhere in the i915 until the separation of IPs started
becoming more important with MTL:
12.00 = Xe_M (or Xe_M+ for DG1, but we treat it the same in the KMD)
12.50 = Xe_XPM
12.55 = Xe_HPM
12.60 = Xe_XPM+
13.00 = Xe_LPM+
and display:
12.00 = Xe_D
13.00 = Xe_LPD (ADL-P) or Xe_HPD (DG2)
14.00 = Xe_LPD+
The pre-12 stuff predates the fancy new marketing-mandated names. Even
though we're not using "gen" terminology going forward, those old ones
are grandfathered in, so it's still okay to refer to them as gen9,
gen11, etc.
Matt
>
> John.
>
> >
> >
> > Matt
> >
> > > Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> > > Fixes: dce2bd542337 ("drm/i915/guc: Add Gen9 registers for GuC error state capture.")
> > > Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> > > Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> > > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > > Cc: John Harrison <John.C.Harrison@Intel.com>
> > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> > > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 7 +++++--
> > > 1 file changed, 5 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> > > index cf49188db6a6e..e0e793167d61b 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> > > @@ -31,12 +31,14 @@
> > > { FORCEWAKE_MT, 0, 0, "FORCEWAKE" }
> > > #define COMMON_GEN9BASE_GLOBAL \
> > > - { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \
> > > - { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" }, \
> > > { ERROR_GEN6, 0, 0, "ERROR_GEN6" }, \
> > > { DONE_REG, 0, 0, "DONE_REG" }, \
> > > { HSW_GTT_CACHE_EN, 0, 0, "HSW_GTT_CACHE_EN" }
> > > +#define GEN9_GLOBAL \
> > > + { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \
> > > + { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" }
> > > +
> > > #define COMMON_GEN12BASE_GLOBAL \
> > > { GEN12_FAULT_TLB_DATA0, 0, 0, "GEN12_FAULT_TLB_DATA0" }, \
> > > { GEN12_FAULT_TLB_DATA1, 0, 0, "GEN12_FAULT_TLB_DATA1" }, \
> > > @@ -142,6 +144,7 @@ static const struct __guc_mmio_reg_descr xe_lpd_gsc_inst_regs[] = {
> > > static const struct __guc_mmio_reg_descr default_global_regs[] = {
> > > COMMON_BASE_GLOBAL,
> > > COMMON_GEN9BASE_GLOBAL,
> > > + GEN9_GLOBAL,
> > > };
> > > static const struct __guc_mmio_reg_descr default_rc_class_regs[] = {
> > > --
> > > 2.39.1
> > >
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-04-05 21:46 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-04-03 21:33 [Intel-gfx] [PATCH] drm/i915/guc: Don't capture Gen8 regs on Gen12 devices John.C.Harrison
2023-04-03 22:36 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2023-04-03 22:57 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-04-04 0:34 ` [Intel-gfx] [PATCH] " Matt Roper
2023-04-05 21:13 ` John Harrison
2023-04-05 21:45 ` Matt Roper
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