* [Intel-gfx] [PATCH V3] drm/i915/gt: Add workaround 14016712196
@ 2023-05-31 14:32 Tejas Upadhyay
2023-05-31 16:34 ` Andi Shyti
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Tejas Upadhyay @ 2023-05-31 14:32 UTC (permalink / raw)
To: intel-gfx
Wa_14016712196 implementation for mtl
Bspec: 72197
V3:
- Wrap dummy pipe control stuff in API - Andi
V2:
- Fix kernel test robot warnings
Closes: https://lore.kernel.org/oe-kbuild-all/202305121525.3EWdGoBY-lkp@intel.com/
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 39 ++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index e1c76e5bfa82..206947f1fc7c 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -177,6 +177,30 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
return cs;
}
+static u32 *mtl_dummy_pipe_control(struct i915_request *rq)
+{
+ u32 *cs;
+
+ /* Wa_14016712196 */
+ if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
+ int ret;
+
+ /* dummy PIPE_CONTROL + depth flush */
+ cs = intel_ring_begin(rq, 6);
+ ret = IS_ERR(cs);
+ if (ret)
+ return ERR_PTR(ret);
+ cs = gen12_emit_pipe_control(cs,
+ 0,
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH,
+ LRC_PPHWSP_SCRATCH_ADDR);
+ intel_ring_advance(rq, cs);
+ }
+
+ return cs;
+}
+
int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
{
struct intel_engine_cs *engine = rq->engine;
@@ -185,6 +209,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
u32 flags = 0;
u32 *cs;
+ cs = mtl_dummy_pipe_control(rq);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
flags |= PIPE_CONTROL_FLUSH_L3;
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
@@ -218,6 +246,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
u32 flags = 0;
u32 *cs, count;
+ cs = mtl_dummy_pipe_control(rq);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
flags |= PIPE_CONTROL_TLB_INVALIDATE;
flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
@@ -733,6 +765,13 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
PIPE_CONTROL_DC_FLUSH_ENABLE |
PIPE_CONTROL_FLUSH_ENABLE);
+ /* Wa_14016712196 */
+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ /* dummy PIPE_CONTROL + depth flush */
+ cs = gen12_emit_pipe_control(cs, 0,
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
+
if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
/* Wa_1409600907 */
flags |= PIPE_CONTROL_DEPTH_STALL;
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [Intel-gfx] [PATCH V3] drm/i915/gt: Add workaround 14016712196
2023-05-31 14:32 [Intel-gfx] [PATCH V3] drm/i915/gt: Add workaround 14016712196 Tejas Upadhyay
@ 2023-05-31 16:34 ` Andi Shyti
2023-05-31 23:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Add workaround 14016712196 (rev3) Patchwork
2023-06-01 0:16 ` [Intel-gfx] [PATCH V3] drm/i915/gt: Add workaround 14016712196 Matt Roper
2 siblings, 0 replies; 4+ messages in thread
From: Andi Shyti @ 2023-05-31 16:34 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: intel-gfx
Hi Tejas,
On Wed, May 31, 2023 at 08:02:14PM +0530, Tejas Upadhyay wrote:
> Wa_14016712196 implementation for mtl
>
> Bspec: 72197
>
> V3:
> - Wrap dummy pipe control stuff in API - Andi
> V2:
> - Fix kernel test robot warnings
>
> Closes: https://lore.kernel.org/oe-kbuild-all/202305121525.3EWdGoBY-lkp@intel.com/
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> ---
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 39 ++++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index e1c76e5bfa82..206947f1fc7c 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -177,6 +177,30 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
> return cs;
> }
>
> +static u32 *mtl_dummy_pipe_control(struct i915_request *rq)
> +{
> + u32 *cs;
> +
> + /* Wa_14016712196 */
> + if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
> + int ret;
> +
> + /* dummy PIPE_CONTROL + depth flush */
> + cs = intel_ring_begin(rq, 6);
> + ret = IS_ERR(cs);
> + if (ret)
> + return ERR_PTR(ret);
> + cs = gen12_emit_pipe_control(cs,
> + 0,
> + PIPE_CONTROL_DEPTH_CACHE_FLUSH,
> + LRC_PPHWSP_SCRATCH_ADDR);
> + intel_ring_advance(rq, cs);
> + }
> +
> + return cs;
mmmhhh... the value of cs at the end is not used, unless it's an
error. Isn't it better to just have this function as a "static
int" that returns '0' or -errno?
This might also confuse some static analyzers, I guess.
Andi
> +}
> +
> int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> {
> struct intel_engine_cs *engine = rq->engine;
> @@ -185,6 +209,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> u32 flags = 0;
> u32 *cs;
>
> + cs = mtl_dummy_pipe_control(rq);
> + if (IS_ERR(cs))
> + return PTR_ERR(cs);
> +
> flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
> flags |= PIPE_CONTROL_FLUSH_L3;
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> @@ -218,6 +246,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> u32 flags = 0;
> u32 *cs, count;
>
> + cs = mtl_dummy_pipe_control(rq);
> + if (IS_ERR(cs))
> + return PTR_ERR(cs);
> +
> flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
> flags |= PIPE_CONTROL_TLB_INVALIDATE;
> flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
> @@ -733,6 +765,13 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> PIPE_CONTROL_DC_FLUSH_ENABLE |
> PIPE_CONTROL_FLUSH_ENABLE);
>
> + /* Wa_14016712196 */
> + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> + /* dummy PIPE_CONTROL + depth flush */
> + cs = gen12_emit_pipe_control(cs, 0,
> + PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
> +
> if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> /* Wa_1409600907 */
> flags |= PIPE_CONTROL_DEPTH_STALL;
> --
> 2.25.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Add workaround 14016712196 (rev3)
2023-05-31 14:32 [Intel-gfx] [PATCH V3] drm/i915/gt: Add workaround 14016712196 Tejas Upadhyay
2023-05-31 16:34 ` Andi Shyti
@ 2023-05-31 23:59 ` Patchwork
2023-06-01 0:16 ` [Intel-gfx] [PATCH V3] drm/i915/gt: Add workaround 14016712196 Matt Roper
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2023-05-31 23:59 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6922 bytes --]
== Series Details ==
Series: drm/i915/gt: Add workaround 14016712196 (rev3)
URL : https://patchwork.freedesktop.org/series/117661/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13210 -> Patchwork_117661v3
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v3/index.html
Participating hosts (37 -> 35)
------------------------------
Missing (2): bat-jsl-1 bat-jsl-3
Known issues
------------
Here are the changes found in Patchwork_117661v3 that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- fi-kbl-8809g: [FAIL][1] ([i915#8293] / [i915#8298]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/fi-kbl-8809g/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v3/fi-kbl-8809g/boot.html
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@unbind-rebind:
- fi-kbl-8809g: NOTRUN -> [ABORT][3] ([i915#8298] / [i915#8299] / [i915#8397])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v3/fi-kbl-8809g/igt@core_hotunplug@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v3/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-hsw-4770: [PASS][5] -> [SKIP][6] ([fdo#109271])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/fi-hsw-4770/igt@i915_pm_rpm@basic-pci-d3-state.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v3/fi-hsw-4770/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- fi-hsw-4770: [PASS][7] -> [FAIL][8] ([i915#7364])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/fi-hsw-4770/igt@i915_pm_rpm@basic-rte.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v3/fi-hsw-4770/igt@i915_pm_rpm@basic-rte.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [PASS][9] -> [ABORT][10] ([i915#4983] / [i915#7911] / [i915#7920])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/bat-rpls-1/igt@i915_selftest@live@requests.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v3/bat-rpls-1/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][11] ([i915#6367])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v3/bat-rpls-2/igt@i915_selftest@live@slpc.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][12] ([i915#6687])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v3/bat-rpls-2/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@kms_addfb_basic@too-high:
- fi-kbl-8809g: NOTRUN -> [FAIL][13] ([i915#8296]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v3/fi-kbl-8809g/igt@kms_addfb_basic@too-high.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-8809g: NOTRUN -> [DMESG-FAIL][14] ([i915#8299])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v3/fi-kbl-8809g/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-8809g: NOTRUN -> [CRASH][15] ([i915#8299])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v3/fi-kbl-8809g/igt@kms_force_connector_basic@force-edid.html
* igt@kms_psr@cursor_plane_move:
- fi-kbl-8809g: NOTRUN -> [SKIP][16] ([fdo#109271]) +59 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v3/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-kbl-8809g: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4579])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v3/fi-kbl-8809g/igt@kms_setmode@basic-clone-single-crtc.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_mocs:
- {bat-mtlp-8}: [DMESG-FAIL][18] ([i915#7059]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v3/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][20] ([i915#4983] / [i915#7461] / [i915#7913] / [i915#7981] / [i915#8347]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13210/bat-rpls-2/igt@i915_selftest@live@reset.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v3/bat-rpls-2/igt@i915_selftest@live@reset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7364]: https://gitlab.freedesktop.org/drm/intel/issues/7364
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8296]: https://gitlab.freedesktop.org/drm/intel/issues/8296
[i915#8298]: https://gitlab.freedesktop.org/drm/intel/issues/8298
[i915#8299]: https://gitlab.freedesktop.org/drm/intel/issues/8299
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
[i915#8397]: https://gitlab.freedesktop.org/drm/intel/issues/8397
Build changes
-------------
* Linux: CI_DRM_13210 -> Patchwork_117661v3
CI-20190529: 20190529
CI_DRM_13210: a66da4c33d8ede541aea9ba6d0d73b556a072d54 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7314: ab70dfcdecf93a17fcaddb774855f726325fa0dd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_117661v3: a66da4c33d8ede541aea9ba6d0d73b556a072d54 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
ab39167f8e58 drm/i915/gt: Add workaround 14016712196
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v3/index.html
[-- Attachment #2: Type: text/html, Size: 8350 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Intel-gfx] [PATCH V3] drm/i915/gt: Add workaround 14016712196
2023-05-31 14:32 [Intel-gfx] [PATCH V3] drm/i915/gt: Add workaround 14016712196 Tejas Upadhyay
2023-05-31 16:34 ` Andi Shyti
2023-05-31 23:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Add workaround 14016712196 (rev3) Patchwork
@ 2023-06-01 0:16 ` Matt Roper
2 siblings, 0 replies; 4+ messages in thread
From: Matt Roper @ 2023-06-01 0:16 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: intel-gfx
On Wed, May 31, 2023 at 08:02:14PM +0530, Tejas Upadhyay wrote:
> Wa_14016712196 implementation for mtl
Since this isn't one of the trivial "write XXX to register YYY"
workarounds, you might want to give a brief description of what we're
being directed to do. E.g.,
"Wa_14016712196 asks us to submit a "dummy" PIPE_CONTROL when XYZ"
That way it will be more obvious to reviewers if you truly got all the
spots in the driver (e.g., it makes it easier for someone to point out
mistakes like "XYZ is also true in function foo() too").
Matt
>
> Bspec: 72197
>
> V3:
> - Wrap dummy pipe control stuff in API - Andi
> V2:
> - Fix kernel test robot warnings
>
> Closes: https://lore.kernel.org/oe-kbuild-all/202305121525.3EWdGoBY-lkp@intel.com/
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> ---
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 39 ++++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index e1c76e5bfa82..206947f1fc7c 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -177,6 +177,30 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
> return cs;
> }
>
> +static u32 *mtl_dummy_pipe_control(struct i915_request *rq)
> +{
> + u32 *cs;
> +
> + /* Wa_14016712196 */
> + if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
> + int ret;
> +
> + /* dummy PIPE_CONTROL + depth flush */
> + cs = intel_ring_begin(rq, 6);
> + ret = IS_ERR(cs);
> + if (ret)
> + return ERR_PTR(ret);
> + cs = gen12_emit_pipe_control(cs,
> + 0,
> + PIPE_CONTROL_DEPTH_CACHE_FLUSH,
> + LRC_PPHWSP_SCRATCH_ADDR);
> + intel_ring_advance(rq, cs);
> + }
> +
> + return cs;
> +}
> +
> int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> {
> struct intel_engine_cs *engine = rq->engine;
> @@ -185,6 +209,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> u32 flags = 0;
> u32 *cs;
>
> + cs = mtl_dummy_pipe_control(rq);
> + if (IS_ERR(cs))
> + return PTR_ERR(cs);
> +
> flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
> flags |= PIPE_CONTROL_FLUSH_L3;
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> @@ -218,6 +246,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> u32 flags = 0;
> u32 *cs, count;
>
> + cs = mtl_dummy_pipe_control(rq);
> + if (IS_ERR(cs))
> + return PTR_ERR(cs);
> +
> flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
> flags |= PIPE_CONTROL_TLB_INVALIDATE;
> flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
> @@ -733,6 +765,13 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> PIPE_CONTROL_DC_FLUSH_ENABLE |
> PIPE_CONTROL_FLUSH_ENABLE);
>
> + /* Wa_14016712196 */
> + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> + /* dummy PIPE_CONTROL + depth flush */
> + cs = gen12_emit_pipe_control(cs, 0,
> + PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
> +
> if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> /* Wa_1409600907 */
> flags |= PIPE_CONTROL_DEPTH_STALL;
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 4+ messages in thread
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2023-05-31 14:32 [Intel-gfx] [PATCH V3] drm/i915/gt: Add workaround 14016712196 Tejas Upadhyay
2023-05-31 16:34 ` Andi Shyti
2023-05-31 23:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Add workaround 14016712196 (rev3) Patchwork
2023-06-01 0:16 ` [Intel-gfx] [PATCH V3] drm/i915/gt: Add workaround 14016712196 Matt Roper
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