* [Intel-gfx] [PATCH 1/5] drm/i915/psr: Include some basic PSR information in the state dump
@ 2023-11-24 8:27 Ville Syrjala
2023-11-24 8:27 ` [Intel-gfx] [PATCH 2/5] drm/i915: Replace a memset() with zero initialization Ville Syrjala
` (9 more replies)
0 siblings, 10 replies; 18+ messages in thread
From: Ville Syrjala @ 2023-11-24 8:27 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Currently no one can figure out what the PSR code is doing since
we're including any of it in the basic state dump. Add at least the
bare minimum there.
v2: Also dump has_panel_replay (Jouni)
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index fbe89b6f038a..49fd100ec98a 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -265,6 +265,12 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
drm_dbg_kms(&i915->drm, "sdp split: %s\n",
str_enabled_disabled(pipe_config->sdp_split_enable));
+
+ drm_dbg_kms(&i915->drm, "psr: %s, psr2: %s, panel replay: %s, selective fetch: %s\n",
+ str_enabled_disabled(pipe_config->has_psr),
+ str_enabled_disabled(pipe_config->has_psr2),
+ str_enabled_disabled(pipe_config->has_panel_replay),
+ str_enabled_disabled(pipe_config->enable_psr2_sel_fetch));
}
drm_dbg_kms(&i915->drm, "framestart delay: %d, MSA timing delay: %d\n",
--
2.41.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 2/5] drm/i915: Replace a memset() with zero initialization
2023-11-24 8:27 [Intel-gfx] [PATCH 1/5] drm/i915/psr: Include some basic PSR information in the state dump Ville Syrjala
@ 2023-11-24 8:27 ` Ville Syrjala
2023-11-29 14:50 ` Kahola, Mika
2023-11-24 8:27 ` [Intel-gfx] [PATCH 3/5] drm/i915: Include the PLL name in the debug messages Ville Syrjala
` (8 subsequent siblings)
9 siblings, 1 reply; 18+ messages in thread
From: Ville Syrjala @ 2023-11-24 8:27 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Declaring a struct and immediately zeroing it with memset()
seems a bit silly to me. Just zero initialize the struct
when declaring it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index ef57dad1a9cb..0376adc36780 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4465,12 +4465,10 @@ verify_single_dpll_state(struct drm_i915_private *i915,
struct intel_crtc *crtc,
const struct intel_crtc_state *new_crtc_state)
{
- struct intel_dpll_hw_state dpll_hw_state;
+ struct intel_dpll_hw_state dpll_hw_state = {};
u8 pipe_mask;
bool active;
- memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
-
drm_dbg_kms(&i915->drm, "%s\n", pll->info->name);
active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state);
--
2.41.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 3/5] drm/i915: Include the PLL name in the debug messages
2023-11-24 8:27 [Intel-gfx] [PATCH 1/5] drm/i915/psr: Include some basic PSR information in the state dump Ville Syrjala
2023-11-24 8:27 ` [Intel-gfx] [PATCH 2/5] drm/i915: Replace a memset() with zero initialization Ville Syrjala
@ 2023-11-24 8:27 ` Ville Syrjala
2023-11-24 8:27 ` [Intel-gfx] [PATCH 4/5] drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLs Ville Syrjala
` (7 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjala @ 2023-11-24 8:27 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make the log easier to parse by including the name of the PLL
in the debug prints regarding said PLL.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 39 ++++++++++---------
1 file changed, 20 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 0376adc36780..d86b02de2923 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4469,25 +4469,25 @@ verify_single_dpll_state(struct drm_i915_private *i915,
u8 pipe_mask;
bool active;
- drm_dbg_kms(&i915->drm, "%s\n", pll->info->name);
-
active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state);
if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
I915_STATE_WARN(i915, !pll->on && pll->active_mask,
- "pll in active use but not on in sw tracking\n");
+ "%s: pll in active use but not on in sw tracking\n",
+ pll->info->name);
I915_STATE_WARN(i915, pll->on && !pll->active_mask,
- "pll is on but not used by any active pipe\n");
+ "%s: pll is on but not used by any active pipe\n",
+ pll->info->name);
I915_STATE_WARN(i915, pll->on != active,
- "pll on state mismatch (expected %i, found %i)\n",
- pll->on, active);
+ "%s: pll on state mismatch (expected %i, found %i)\n",
+ pll->info->name, pll->on, active);
}
if (!crtc) {
I915_STATE_WARN(i915,
pll->active_mask & ~pll->state.pipe_mask,
- "more active pll users than references: 0x%x vs 0x%x\n",
- pll->active_mask, pll->state.pipe_mask);
+ "%s: more active pll users than references: 0x%x vs 0x%x\n",
+ pll->info->name, pll->active_mask, pll->state.pipe_mask);
return;
}
@@ -4496,21 +4496,22 @@ verify_single_dpll_state(struct drm_i915_private *i915,
if (new_crtc_state->hw.active)
I915_STATE_WARN(i915, !(pll->active_mask & pipe_mask),
- "pll active mismatch (expected pipe %c in active mask 0x%x)\n",
- pipe_name(crtc->pipe), pll->active_mask);
+ "%s: pll active mismatch (expected pipe %c in active mask 0x%x)\n",
+ pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
else
I915_STATE_WARN(i915, pll->active_mask & pipe_mask,
- "pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n",
- pipe_name(crtc->pipe), pll->active_mask);
+ "%s: pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n",
+ pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
I915_STATE_WARN(i915, !(pll->state.pipe_mask & pipe_mask),
- "pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
- pipe_mask, pll->state.pipe_mask);
+ "%s: pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
+ pll->info->name, pipe_mask, pll->state.pipe_mask);
I915_STATE_WARN(i915,
pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state,
sizeof(dpll_hw_state)),
- "pll hw state mismatch\n");
+ "%s: pll hw state mismatch\n",
+ pll->info->name);
}
void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
@@ -4532,11 +4533,11 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
I915_STATE_WARN(i915, pll->active_mask & pipe_mask,
- "pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
- pipe_name(crtc->pipe), pll->active_mask);
+ "%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
+ pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
I915_STATE_WARN(i915, pll->state.pipe_mask & pipe_mask,
- "pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
- pipe_name(crtc->pipe), pll->state.pipe_mask);
+ "%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
+ pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
}
}
--
2.41.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 4/5] drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLs
2023-11-24 8:27 [Intel-gfx] [PATCH 1/5] drm/i915/psr: Include some basic PSR information in the state dump Ville Syrjala
2023-11-24 8:27 ` [Intel-gfx] [PATCH 2/5] drm/i915: Replace a memset() with zero initialization Ville Syrjala
2023-11-24 8:27 ` [Intel-gfx] [PATCH 3/5] drm/i915: Include the PLL name in the debug messages Ville Syrjala
@ 2023-11-24 8:27 ` Ville Syrjala
2023-12-07 14:05 ` Ville Syrjälä
2023-12-07 14:55 ` [Intel-gfx] " Imre Deak
2023-11-24 8:27 ` [Intel-gfx] [PATCH 5/5] drm/i915: Convert PLL flags to booleans Ville Syrjala
` (6 subsequent siblings)
9 siblings, 2 replies; 18+ messages in thread
From: Ville Syrjala @ 2023-11-24 8:27 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
TC ports have both the MG/TC and TBT PLLs selected simultanously (so
that we can switch from MG/TC to TBT as a fallback). This doesn't play
well with the state checker that assumes that the old PLL shouldn't
have the pipe in its pipe_mask anymore. Suppress that check for these
PLLs to avoid spurious WARNs when you disconnect a TC port and a
non-disabling modeset happens before actually disabling the port.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 56 +++++++++++++------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++
2 files changed, 42 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index d86b02de2923..5c6c4fc50b1d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4023,11 +4023,16 @@ static const struct intel_shared_dpll_funcs mg_pll_funcs = {
static const struct dpll_info icl_plls[] = {
{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
- { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
- { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
- { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
- { .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
- { .name = "MG PLL 4", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
+ { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
+ .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
+ .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
+ .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ { .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
+ .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ { .name = "MG PLL 4", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
+ .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
{}
};
@@ -4068,13 +4073,20 @@ static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
static const struct dpll_info tgl_plls[] = {
{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
- { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
- { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
- { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
- { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
- { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
- { .name = "TC PLL 5", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL5, },
- { .name = "TC PLL 6", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL6, },
+ { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
+ .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
+ .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
+ .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
+ .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
+ .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ { .name = "TC PLL 5", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL5,
+ .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ { .name = "TC PLL 6", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL6,
+ .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
{}
};
@@ -4141,11 +4153,16 @@ static const struct intel_dpll_mgr adls_pll_mgr = {
static const struct dpll_info adlp_plls[] = {
{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
- { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
- { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
- { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
- { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
- { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
+ { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
+ .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
+ .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
+ .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
+ .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
+ .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
{}
};
@@ -4535,7 +4552,10 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
I915_STATE_WARN(i915, pll->active_mask & pipe_mask,
"%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
- I915_STATE_WARN(i915, pll->state.pipe_mask & pipe_mask,
+
+ /* TC ports have both MG/TC and TBT PLL referenced simultaneously */
+ I915_STATE_WARN(i915, !(pll->info->flags & INTEL_DPLL_HAS_ALT_PORT_DPLL) &&
+ pll->state.pipe_mask & pipe_mask,
"%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 2e7ea0d8d3ff..594658087b4a 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -277,12 +277,16 @@ struct dpll_info {
enum intel_display_power_domain power_domain;
#define INTEL_DPLL_ALWAYS_ON (1 << 0)
+#define INTEL_DPLL_HAS_ALT_PORT_DPLL (1 << 1)
/**
* @flags:
*
* INTEL_DPLL_ALWAYS_ON
* Inform the state checker that the DPLL is kept enabled even if
* not in use by any CRTC.
+ * INTEL_DPLL_HAS_ALT_PORT_DPLL
+ * Inform the state checker that the CRTC will have two port DPLLs
+ * referenced simultanously (for TC->TBT fallback).
*/
u32 flags;
};
--
2.41.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 5/5] drm/i915: Convert PLL flags to booleans
2023-11-24 8:27 [Intel-gfx] [PATCH 1/5] drm/i915/psr: Include some basic PSR information in the state dump Ville Syrjala
` (2 preceding siblings ...)
2023-11-24 8:27 ` [Intel-gfx] [PATCH 4/5] drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLs Ville Syrjala
@ 2023-11-24 8:27 ` Ville Syrjala
2023-11-24 8:35 ` [Intel-gfx] [PATCH 1/5] drm/i915/psr: Include some basic PSR information in the state dump Hogander, Jouni
` (5 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjala @ 2023-11-24 8:27 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
No real reason why the PLL flags need to be a bitmask. Switch
to booleans to make the code simpler.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 46 +++++++++----------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 22 +++++----
2 files changed, 35 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 5c6c4fc50b1d..45a39a545453 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1263,11 +1263,11 @@ static const struct dpll_info hsw_plls[] = {
{ .name = "WRPLL 2", .funcs = &hsw_ddi_wrpll_funcs, .id = DPLL_ID_WRPLL2, },
{ .name = "SPLL", .funcs = &hsw_ddi_spll_funcs, .id = DPLL_ID_SPLL, },
{ .name = "LCPLL 810", .funcs = &hsw_ddi_lcpll_funcs, .id = DPLL_ID_LCPLL_810,
- .flags = INTEL_DPLL_ALWAYS_ON, },
+ .always_on = true, },
{ .name = "LCPLL 1350", .funcs = &hsw_ddi_lcpll_funcs, .id = DPLL_ID_LCPLL_1350,
- .flags = INTEL_DPLL_ALWAYS_ON, },
+ .always_on = true, },
{ .name = "LCPLL 2700", .funcs = &hsw_ddi_lcpll_funcs, .id = DPLL_ID_LCPLL_2700,
- .flags = INTEL_DPLL_ALWAYS_ON, },
+ .always_on = true, },
{}
};
@@ -1945,7 +1945,7 @@ static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
static const struct dpll_info skl_plls[] = {
{ .name = "DPLL 0", .funcs = &skl_ddi_dpll0_funcs, .id = DPLL_ID_SKL_DPLL0,
- .flags = INTEL_DPLL_ALWAYS_ON, },
+ .always_on = true, },
{ .name = "DPLL 1", .funcs = &skl_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL1, },
{ .name = "DPLL 2", .funcs = &skl_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL2, },
{ .name = "DPLL 3", .funcs = &skl_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL3, },
@@ -4024,15 +4024,15 @@ static const struct dpll_info icl_plls[] = {
{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
{ .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
- .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ .has_alt_port_dpll = true, },
{ .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
- .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ .has_alt_port_dpll = true, },
{ .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
- .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ .has_alt_port_dpll = true, },
{ .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
- .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ .has_alt_port_dpll = true, },
{ .name = "MG PLL 4", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
- .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ .has_alt_port_dpll = true, },
{}
};
@@ -4074,19 +4074,19 @@ static const struct dpll_info tgl_plls[] = {
{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
{ .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
- .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ .has_alt_port_dpll = true, },
{ .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
- .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ .has_alt_port_dpll = true, },
{ .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
- .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ .has_alt_port_dpll = true, },
{ .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
- .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ .has_alt_port_dpll = true, },
{ .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
- .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ .has_alt_port_dpll = true, },
{ .name = "TC PLL 5", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL5,
- .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ .has_alt_port_dpll = true, },
{ .name = "TC PLL 6", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL6,
- .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ .has_alt_port_dpll = true, },
{}
};
@@ -4154,15 +4154,15 @@ static const struct dpll_info adlp_plls[] = {
{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
{ .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
- .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ .has_alt_port_dpll = true, },
{ .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
- .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ .has_alt_port_dpll = true, },
{ .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
- .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ .has_alt_port_dpll = true, },
{ .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
- .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ .has_alt_port_dpll = true, },
{ .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
- .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
+ .has_alt_port_dpll = true, },
{}
};
@@ -4488,7 +4488,7 @@ verify_single_dpll_state(struct drm_i915_private *i915,
active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state);
- if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
+ if (!pll->info->always_on) {
I915_STATE_WARN(i915, !pll->on && pll->active_mask,
"%s: pll in active use but not on in sw tracking\n",
pll->info->name);
@@ -4554,7 +4554,7 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
/* TC ports have both MG/TC and TBT PLL referenced simultaneously */
- I915_STATE_WARN(i915, !(pll->info->flags & INTEL_DPLL_HAS_ALT_PORT_DPLL) &&
+ I915_STATE_WARN(i915, !pll->info->has_alt_port_dpll &&
pll->state.pipe_mask & pipe_mask,
"%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 594658087b4a..37cdc0b4ee18 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -276,19 +276,21 @@ struct dpll_info {
*/
enum intel_display_power_domain power_domain;
-#define INTEL_DPLL_ALWAYS_ON (1 << 0)
-#define INTEL_DPLL_HAS_ALT_PORT_DPLL (1 << 1)
/**
- * @flags:
+ * @always_on:
*
- * INTEL_DPLL_ALWAYS_ON
- * Inform the state checker that the DPLL is kept enabled even if
- * not in use by any CRTC.
- * INTEL_DPLL_HAS_ALT_PORT_DPLL
- * Inform the state checker that the CRTC will have two port DPLLs
- * referenced simultanously (for TC->TBT fallback).
+ * Inform the state checker that the DPLL is kept enabled even if
+ * not in use by any CRTC.
*/
- u32 flags;
+ bool always_on;
+
+ /**
+ * @has_alt_port_dpll:
+ *
+ * Inform the state checker that the CRTC will have two port DPLLs
+ * referenced simultanously (for TC->TBT fallback).
+ */
+ bool has_alt_port_dpll;
};
/**
--
2.41.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 1/5] drm/i915/psr: Include some basic PSR information in the state dump
2023-11-24 8:27 [Intel-gfx] [PATCH 1/5] drm/i915/psr: Include some basic PSR information in the state dump Ville Syrjala
` (3 preceding siblings ...)
2023-11-24 8:27 ` [Intel-gfx] [PATCH 5/5] drm/i915: Convert PLL flags to booleans Ville Syrjala
@ 2023-11-24 8:35 ` Hogander, Jouni
2023-11-24 16:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] " Patchwork
` (4 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Hogander, Jouni @ 2023-11-24 8:35 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Fri, 2023-11-24 at 10:27 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currently no one can figure out what the PSR code is doing since
> we're including any of it in the basic state dump. Add at least the
> bare minimum there.
>
> v2: Also dump has_panel_replay (Jouni)
>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index fbe89b6f038a..49fd100ec98a 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -265,6 +265,12 @@ void intel_crtc_state_dump(const struct
> intel_crtc_state *pipe_config,
>
> drm_dbg_kms(&i915->drm, "sdp split: %s\n",
> str_enabled_disabled(pipe_config-
> >sdp_split_enable));
> +
> + drm_dbg_kms(&i915->drm, "psr: %s, psr2: %s, panel
> replay: %s, selective fetch: %s\n",
> + str_enabled_disabled(pipe_config-
> >has_psr),
> + str_enabled_disabled(pipe_config-
> >has_psr2),
> + str_enabled_disabled(pipe_config-
> >has_panel_replay),
> + str_enabled_disabled(pipe_config-
> >enable_psr2_sel_fetch));
> }
>
> drm_dbg_kms(&i915->drm, "framestart delay: %d, MSA timing
> delay: %d\n",
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915/psr: Include some basic PSR information in the state dump
2023-11-24 8:27 [Intel-gfx] [PATCH 1/5] drm/i915/psr: Include some basic PSR information in the state dump Ville Syrjala
` (4 preceding siblings ...)
2023-11-24 8:35 ` [Intel-gfx] [PATCH 1/5] drm/i915/psr: Include some basic PSR information in the state dump Hogander, Jouni
@ 2023-11-24 16:28 ` Patchwork
2023-11-24 16:46 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (3 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2023-11-24 16:28 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/5] drm/i915/psr: Include some basic PSR information in the state dump
URL : https://patchwork.freedesktop.org/series/126859/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/i915/psr: Include some basic PSR information in the state dump
2023-11-24 8:27 [Intel-gfx] [PATCH 1/5] drm/i915/psr: Include some basic PSR information in the state dump Ville Syrjala
` (5 preceding siblings ...)
2023-11-24 16:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] " Patchwork
@ 2023-11-24 16:46 ` Patchwork
2023-11-28 22:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915/psr: Include some basic PSR information in the state dump (rev2) Patchwork
` (2 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2023-11-24 16:46 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 16414 bytes --]
== Series Details ==
Series: series starting with [1/5] drm/i915/psr: Include some basic PSR information in the state dump
URL : https://patchwork.freedesktop.org/series/126859/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13921 -> Patchwork_126859v1
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_126859v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_126859v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/index.html
Participating hosts (37 -> 39)
------------------------------
Additional (3): bat-dg2-9 bat-mtlp-8 bat-dg1-5
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_126859v1:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@gt_timelines:
- bat-rpls-1: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/bat-rpls-1/igt@i915_selftest@live@gt_timelines.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-rpls-1/igt@i915_selftest@live@gt_timelines.html
Known issues
------------
Here are the changes found in Patchwork_126859v1 that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- fi-bsw-n3050: [FAIL][3] ([i915#8293]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/fi-bsw-n3050/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/fi-bsw-n3050/boot.html
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-mtlp-8: NOTRUN -> [SKIP][5] ([i915#9318])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-mtlp-8/igt@debugfs_test@basic-hwmon.html
* igt@gem_lmem_swapping@random-engines:
- fi-bsw-n3050: NOTRUN -> [SKIP][6] ([fdo#109271]) +14 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/fi-bsw-n3050/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify-random:
- bat-mtlp-8: NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-mtlp-8/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap@basic:
- bat-dg1-5: NOTRUN -> [SKIP][8] ([i915#4083])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg1-5/igt@gem_mmap@basic.html
- bat-dg2-9: NOTRUN -> [SKIP][9] ([i915#4083])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg2-9/igt@gem_mmap@basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][10] ([i915#4083])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-mtlp-8/igt@gem_mmap@basic.html
* igt@gem_mmap_gtt@basic:
- bat-dg2-9: NOTRUN -> [SKIP][11] ([i915#4077]) +2 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg2-9/igt@gem_mmap_gtt@basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#4077]) +2 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-mtlp-8/igt@gem_mmap_gtt@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-dg2-9: NOTRUN -> [SKIP][13] ([i915#4079]) +1 other test skip
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg2-9/igt@gem_render_tiled_blits@basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#4079]) +1 other test skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-mtlp-8/igt@gem_render_tiled_blits@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg1-5: NOTRUN -> [SKIP][15] ([i915#4077]) +2 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg1-5/igt@gem_tiled_fence_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg1-5: NOTRUN -> [SKIP][16] ([i915#4079]) +1 other test skip
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg1-5/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-5: NOTRUN -> [SKIP][17] ([i915#6621])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg1-5/igt@i915_pm_rps@basic-api.html
- bat-dg2-9: NOTRUN -> [SKIP][18] ([i915#6621])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg2-9/igt@i915_pm_rps@basic-api.html
- bat-mtlp-8: NOTRUN -> [SKIP][19] ([i915#6621])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-mtlp-8/igt@i915_pm_rps@basic-api.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-mtlp-8: NOTRUN -> [SKIP][20] ([i915#6645])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-mtlp-8/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9: NOTRUN -> [SKIP][21] ([i915#5190])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg2-9/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
- bat-mtlp-8: NOTRUN -> [SKIP][22] ([i915#5190])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-mtlp-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- bat-dg1-5: NOTRUN -> [SKIP][23] ([i915#4212]) +7 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg1-5/igt@kms_addfb_basic@basic-x-tiled-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9: NOTRUN -> [SKIP][24] ([i915#4215] / [i915#5190])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg2-9/igt@kms_addfb_basic@basic-y-tiled-legacy.html
- bat-mtlp-8: NOTRUN -> [SKIP][25] ([i915#4212]) +8 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-mtlp-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
- bat-dg1-5: NOTRUN -> [SKIP][26] ([i915#4215])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg1-5/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9: NOTRUN -> [SKIP][27] ([i915#4212]) +6 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg2-9/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-9: NOTRUN -> [SKIP][28] ([i915#4212] / [i915#5608])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg2-9/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-9: NOTRUN -> [SKIP][29] ([i915#4103] / [i915#4213] / [i915#5608]) +1 other test skip
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg2-9/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-mtlp-8: NOTRUN -> [SKIP][30] ([i915#4213]) +1 other test skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-mtlp-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-dg1-5: NOTRUN -> [SKIP][31] ([i915#4103] / [i915#4213]) +1 other test skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg1-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-mtlp-8: NOTRUN -> [SKIP][32] ([i915#3555] / [i915#3840] / [i915#4098] / [i915#9159])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-mtlp-8/igt@kms_dsc@dsc-basic.html
- bat-dg1-5: NOTRUN -> [SKIP][33] ([i915#3555] / [i915#3840])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg1-5/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-9: NOTRUN -> [SKIP][34] ([fdo#109285])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg2-9/igt@kms_force_connector_basic@force-load-detect.html
- bat-mtlp-8: NOTRUN -> [SKIP][35] ([fdo#109285])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-mtlp-8/igt@kms_force_connector_basic@force-load-detect.html
- bat-dg1-5: NOTRUN -> [SKIP][36] ([fdo#109285])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg1-5/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-9: NOTRUN -> [SKIP][37] ([i915#5274])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg2-9/igt@kms_force_connector_basic@prune-stale-modes.html
- bat-mtlp-8: NOTRUN -> [SKIP][38] ([i915#5274])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-mtlp-8/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_hdmi_inject@inject-audio:
- bat-dg1-5: NOTRUN -> [SKIP][39] ([i915#433])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg1-5/igt@kms_hdmi_inject@inject-audio.html
- fi-kbl-guc: [PASS][40] -> [FAIL][41] ([IGT#3])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
- fi-bsw-n3050: NOTRUN -> [FAIL][42] ([IGT#152])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/fi-bsw-n3050/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg1-5: NOTRUN -> [SKIP][43] ([i915#3555])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg1-5/igt@kms_setmode@basic-clone-single-crtc.html
- bat-dg2-9: NOTRUN -> [SKIP][44] ([i915#3555] / [i915#4098])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg2-9/igt@kms_setmode@basic-clone-single-crtc.html
- bat-mtlp-8: NOTRUN -> [SKIP][45] ([i915#3555] / [i915#8809])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-mtlp-8/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-dg2-9: NOTRUN -> [SKIP][46] ([i915#3708])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg2-9/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-dg2-9: NOTRUN -> [SKIP][47] ([i915#3708] / [i915#4077]) +1 other test skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg2-9/igt@prime_vgem@basic-fence-mmap.html
- bat-mtlp-8: NOTRUN -> [SKIP][48] ([i915#3708] / [i915#4077]) +1 other test skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-mtlp-8/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- bat-mtlp-8: NOTRUN -> [SKIP][49] ([i915#3708]) +2 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-mtlp-8/igt@prime_vgem@basic-fence-read.html
- bat-dg1-5: NOTRUN -> [SKIP][50] ([i915#3708]) +3 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg1-5/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-gtt:
- bat-dg1-5: NOTRUN -> [SKIP][51] ([i915#3708] / [i915#4077]) +1 other test skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg1-5/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@basic-write:
- bat-dg2-9: NOTRUN -> [SKIP][52] ([i915#3291] / [i915#3708]) +2 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-dg2-9/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@gem_exec_fence@basic-await@bcs0:
- bat-rpls-1: [FAIL][53] -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/bat-rpls-1/igt@gem_exec_fence@basic-await@bcs0.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/bat-rpls-1/igt@gem_exec_fence@basic-await@bcs0.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-7567u: [DMESG-FAIL][55] ([i915#5334] / [i915#7872]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/fi-kbl-7567u/igt@i915_selftest@live@gt_heartbeat.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/fi-kbl-7567u/igt@i915_selftest@live@gt_heartbeat.html
- fi-apl-guc: [DMESG-FAIL][57] ([i915#5334]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#152]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/152
[IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
[i915#9159]: https://gitlab.freedesktop.org/drm/intel/issues/9159
[i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
[i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
Build changes
-------------
* Linux: CI_DRM_13921 -> Patchwork_126859v1
CI-20190529: 20190529
CI_DRM_13921: 002e96d8067fa253ee53af2fa191717f4f5b782b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7603: 2ddd8cac90d4333943cd017319514949b047821b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_126859v1: 002e96d8067fa253ee53af2fa191717f4f5b782b @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
c3e42500230b drm/i915: Convert PLL flags to booleans
73e78c7895d3 drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLs
4017bfd5084f drm/i915: Include the PLL name in the debug messages
4fd906a14958 drm/i915: Replace a memset() with zero initialization
85f9bc12314d drm/i915/psr: Include some basic PSR information in the state dump
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v1/index.html
[-- Attachment #2: Type: text/html, Size: 20550 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915/psr: Include some basic PSR information in the state dump (rev2)
2023-11-24 8:27 [Intel-gfx] [PATCH 1/5] drm/i915/psr: Include some basic PSR information in the state dump Ville Syrjala
` (6 preceding siblings ...)
2023-11-24 16:46 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2023-11-28 22:23 ` Patchwork
2023-11-28 22:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-11-29 4:34 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
9 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2023-11-28 22:23 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/5] drm/i915/psr: Include some basic PSR information in the state dump (rev2)
URL : https://patchwork.freedesktop.org/series/126859/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/psr: Include some basic PSR information in the state dump (rev2)
2023-11-24 8:27 [Intel-gfx] [PATCH 1/5] drm/i915/psr: Include some basic PSR information in the state dump Ville Syrjala
` (7 preceding siblings ...)
2023-11-28 22:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915/psr: Include some basic PSR information in the state dump (rev2) Patchwork
@ 2023-11-28 22:37 ` Patchwork
2023-11-29 4:34 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
9 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2023-11-28 22:37 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 9946 bytes --]
== Series Details ==
Series: series starting with [1/5] drm/i915/psr: Include some basic PSR information in the state dump (rev2)
URL : https://patchwork.freedesktop.org/series/126859/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13939 -> Patchwork_126859v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/index.html
Participating hosts (37 -> 37)
------------------------------
Additional (2): bat-mtlp-8 fi-pnv-d510
Missing (2): bat-dg2-9 fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_126859v2 that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- bat-adlp-11: [PASS][1] -> [FAIL][2] ([i915#8293])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/bat-adlp-11/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-adlp-11/boot.html
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-mtlp-8: NOTRUN -> [SKIP][3] ([i915#9318])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-mtlp-8/igt@debugfs_test@basic-hwmon.html
* igt@gem_lmem_swapping@basic:
- fi-pnv-d510: NOTRUN -> [SKIP][4] ([fdo#109271]) +25 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/fi-pnv-d510/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@verify-random:
- bat-mtlp-8: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-mtlp-8/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][6] ([i915#4083])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-mtlp-8/igt@gem_mmap@basic.html
* igt@gem_mmap_gtt@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][7] ([i915#4077]) +2 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-mtlp-8/igt@gem_mmap_gtt@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][8] ([i915#4079]) +1 other test skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-mtlp-8/igt@gem_render_tiled_blits@basic.html
* igt@i915_pm_rps@basic-api:
- bat-mtlp-8: NOTRUN -> [SKIP][9] ([i915#6621])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-mtlp-8/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@execlists:
- bat-mtlp-8: NOTRUN -> [INCOMPLETE][10] ([i915#9527])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-mtlp-8/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: NOTRUN -> [ABORT][11] ([i915#9413])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][12] ([i915#7978] / [i915#9631])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-rpls-1/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][13] ([i915#5190])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-mtlp-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#4212]) +8 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-mtlp-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][15] ([i915#4213]) +1 other test skip
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-mtlp-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#3555] / [i915#3840] / [i915#4098] / [i915#9159])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-mtlp-8/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-mtlp-8: NOTRUN -> [SKIP][17] ([fdo#109285])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-mtlp-8/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-mtlp-8: NOTRUN -> [SKIP][18] ([i915#5274])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-mtlp-8/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [PASS][19] -> [ABORT][20] ([i915#8668])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-mtlp-8: NOTRUN -> [SKIP][21] ([i915#3555] / [i915#8809])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-mtlp-8/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-mmap:
- bat-mtlp-8: NOTRUN -> [SKIP][22] ([i915#3708] / [i915#4077]) +1 other test skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-mtlp-8/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- bat-mtlp-8: NOTRUN -> [SKIP][23] ([i915#3708]) +2 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-mtlp-8/igt@prime_vgem@basic-fence-read.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_contexts:
- bat-rpls-1: [INCOMPLETE][24] ([i915#9756]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/bat-rpls-1/igt@i915_selftest@live@gt_contexts.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-rpls-1/igt@i915_selftest@live@gt_contexts.html
* igt@i915_selftest@live@workarounds:
- bat-dg1-5: [ABORT][26] ([i915#9413]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/bat-dg1-5/igt@i915_selftest@live@workarounds.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/bat-dg1-5/igt@i915_selftest@live@workarounds.html
* igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [FAIL][28] ([IGT#3]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#7359]: https://gitlab.freedesktop.org/drm/intel/issues/7359
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
[i915#8981]: https://gitlab.freedesktop.org/drm/intel/issues/8981
[i915#9159]: https://gitlab.freedesktop.org/drm/intel/issues/9159
[i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
[i915#9413]: https://gitlab.freedesktop.org/drm/intel/issues/9413
[i915#9527]: https://gitlab.freedesktop.org/drm/intel/issues/9527
[i915#9631]: https://gitlab.freedesktop.org/drm/intel/issues/9631
[i915#9756]: https://gitlab.freedesktop.org/drm/intel/issues/9756
Build changes
-------------
* Linux: CI_DRM_13939 -> Patchwork_126859v2
CI-20190529: 20190529
CI_DRM_13939: 444a2d69536b9fb289e86b48f53b6f212a4d6fac @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7608: 3e52de09140ec5ddf8919fcb11a858cfcc137359 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_126859v2: 444a2d69536b9fb289e86b48f53b6f212a4d6fac @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
86253af971dc drm/i915: Convert PLL flags to booleans
63c3240ac743 drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLs
52b945e4efba drm/i915: Include the PLL name in the debug messages
89e02eab07cb drm/i915: Replace a memset() with zero initialization
67dd283688f7 drm/i915/psr: Include some basic PSR information in the state dump
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/index.html
[-- Attachment #2: Type: text/html, Size: 11320 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/5] drm/i915/psr: Include some basic PSR information in the state dump (rev2)
2023-11-24 8:27 [Intel-gfx] [PATCH 1/5] drm/i915/psr: Include some basic PSR information in the state dump Ville Syrjala
` (8 preceding siblings ...)
2023-11-28 22:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-11-29 4:34 ` Patchwork
9 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2023-11-29 4:34 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
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== Series Details ==
Series: series starting with [1/5] drm/i915/psr: Include some basic PSR information in the state dump (rev2)
URL : https://patchwork.freedesktop.org/series/126859/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13939_full -> Patchwork_126859v2_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_126859v2_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_126859v2_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_126859v2_full:
### IGT changes ###
#### Possible regressions ####
* igt@perf@non-zero-reason@0-rcs0:
- shard-glk: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-glk8/igt@perf@non-zero-reason@0-rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-glk7/igt@perf@non-zero-reason@0-rcs0.html
Known issues
------------
Here are the changes found in Patchwork_126859v2_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-keep-cache:
- shard-dg2: NOTRUN -> [SKIP][3] ([i915#8411]) +2 other tests skip
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@api_intel_bb@blit-reloc-keep-cache.html
* igt@api_intel_bb@object-reloc-purge-cache:
- shard-rkl: NOTRUN -> [SKIP][4] ([i915#8411])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@api_intel_bb@object-reloc-purge-cache.html
* igt@device_reset@cold-reset-bound:
- shard-rkl: NOTRUN -> [SKIP][5] ([i915#7701])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@device_reset@cold-reset-bound.html
* igt@drm_fdinfo@busy-idle@bcs0:
- shard-dg2: NOTRUN -> [SKIP][6] ([i915#8414]) +20 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-1/igt@drm_fdinfo@busy-idle@bcs0.html
* igt@drm_fdinfo@isolation@bcs0:
- shard-dg1: NOTRUN -> [SKIP][7] ([i915#8414]) +4 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@drm_fdinfo@isolation@bcs0.html
* igt@fbdev@nullptr:
- shard-rkl: [PASS][8] -> [SKIP][9] ([i915#2582])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-6/igt@fbdev@nullptr.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@fbdev@nullptr.html
* igt@gem_ccs@suspend-resume:
- shard-rkl: NOTRUN -> [SKIP][10] ([i915#9323])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@gem_ccs@suspend-resume.html
* igt@gem_create@create-ext-set-pat:
- shard-dg2: NOTRUN -> [SKIP][11] ([i915#8562])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-1/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglu: [PASS][12] -> [FAIL][13] ([i915#6268])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-tglu-3/igt@gem_ctx_exec@basic-nohangcheck.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-tglu-6/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_persistence@heartbeat-hang:
- shard-dg2: NOTRUN -> [SKIP][14] ([i915#8555]) +1 other test skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@gem_ctx_persistence@heartbeat-hang.html
* igt@gem_exec_balancer@invalid-bonds:
- shard-dg2: NOTRUN -> [SKIP][15] ([i915#4036])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-2/igt@gem_exec_balancer@invalid-bonds.html
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-rkl: NOTRUN -> [SKIP][16] ([i915#4525]) +1 other test skip
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@gem_exec_balancer@parallel-keep-submit-fence.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk: NOTRUN -> [FAIL][17] ([i915#2842])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-glk5/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-rkl: [PASS][18] -> [FAIL][19] ([i915#2842])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-sync:
- shard-dg1: NOTRUN -> [SKIP][20] ([i915#3539]) +1 other test skip
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@gem_exec_fair@basic-sync.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-rkl: NOTRUN -> [FAIL][21] ([i915#2842]) +1 other test fail
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_fence@concurrent:
- shard-dg2: NOTRUN -> [SKIP][22] ([i915#4812])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-5/igt@gem_exec_fence@concurrent.html
* igt@gem_exec_flush@basic-uc-ro-default:
- shard-dg2: NOTRUN -> [SKIP][23] ([i915#3539] / [i915#4852]) +5 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@gem_exec_flush@basic-uc-ro-default.html
* igt@gem_exec_reloc@basic-gtt-cpu:
- shard-rkl: NOTRUN -> [SKIP][24] ([i915#3281]) +5 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-4/igt@gem_exec_reloc@basic-gtt-cpu.html
* igt@gem_exec_reloc@basic-range:
- shard-mtlp: NOTRUN -> [SKIP][25] ([i915#3281])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@gem_exec_reloc@basic-range.html
* igt@gem_exec_reloc@basic-softpin:
- shard-dg1: NOTRUN -> [SKIP][26] ([i915#3281]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@gem_exec_reloc@basic-softpin.html
* igt@gem_exec_reloc@basic-write-read-active:
- shard-dg2: NOTRUN -> [SKIP][27] ([i915#3281]) +10 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-1/igt@gem_exec_reloc@basic-write-read-active.html
* igt@gem_exec_schedule@preempt-queue-chain:
- shard-mtlp: NOTRUN -> [SKIP][28] ([i915#4537] / [i915#4812])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@gem_exec_schedule@preempt-queue-chain.html
* igt@gem_exec_schedule@semaphore-power:
- shard-dg1: NOTRUN -> [SKIP][29] ([i915#4812])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_exec_suspend@basic-s4-devices@smem:
- shard-rkl: NOTRUN -> [ABORT][30] ([i915#7975] / [i915#8213])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-4/igt@gem_exec_suspend@basic-s4-devices@smem.html
* igt@gem_fenced_exec_thrash@too-many-fences:
- shard-dg2: NOTRUN -> [SKIP][31] ([i915#4860]) +1 other test skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@gem_fenced_exec_thrash@too-many-fences.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs:
- shard-glk: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#4613]) +1 other test skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-glk5/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
* igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0:
- shard-dg1: NOTRUN -> [SKIP][33] ([i915#4565])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-mtlp: NOTRUN -> [SKIP][34] ([i915#4613])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg1: [PASS][35] -> [DMESG-WARN][36] ([i915#4936] / [i915#5493])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-dg1-13/igt@gem_lmem_swapping@smem-oom@lmem0.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-15/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-rkl: NOTRUN -> [SKIP][37] ([i915#4613]) +2 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@gem_lmem_swapping@verify-ccs.html
* igt@gem_madvise@dontneed-before-pwrite:
- shard-dg2: NOTRUN -> [SKIP][38] ([i915#3282]) +4 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-2/igt@gem_madvise@dontneed-before-pwrite.html
* igt@gem_mmap_gtt@cpuset-big-copy-xy:
- shard-dg1: NOTRUN -> [SKIP][39] ([i915#4077]) +1 other test skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@gem_mmap_gtt@cpuset-big-copy-xy.html
* igt@gem_mmap_gtt@medium-copy-xy:
- shard-dg2: NOTRUN -> [SKIP][40] ([i915#4077]) +14 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@gem_mmap_gtt@medium-copy-xy.html
* igt@gem_mmap_wc@close:
- shard-dg1: NOTRUN -> [SKIP][41] ([i915#4083]) +2 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@gem_mmap_wc@close.html
* igt@gem_mmap_wc@write-gtt-read-wc:
- shard-dg2: NOTRUN -> [SKIP][42] ([i915#4083]) +2 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-5/igt@gem_mmap_wc@write-gtt-read-wc.html
* igt@gem_partial_pwrite_pread@reads:
- shard-mtlp: NOTRUN -> [SKIP][43] ([i915#3282])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@gem_partial_pwrite_pread@reads.html
* igt@gem_pread@display:
- shard-dg1: NOTRUN -> [SKIP][44] ([i915#3282]) +2 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@gem_pread@display.html
* igt@gem_pread@snoop:
- shard-rkl: NOTRUN -> [SKIP][45] ([i915#3282]) +7 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@gem_pread@snoop.html
* igt@gem_pxp@create-valid-protected-context:
- shard-mtlp: NOTRUN -> [SKIP][46] ([i915#4270]) +1 other test skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@gem_pxp@create-valid-protected-context.html
* igt@gem_pxp@display-protected-crc:
- shard-dg2: NOTRUN -> [SKIP][47] ([i915#4270]) +4 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-1/igt@gem_pxp@display-protected-crc.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-rkl: NOTRUN -> [SKIP][48] ([i915#4270]) +1 other test skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_set_tiling_vs_blt@untiled-to-tiled:
- shard-dg1: NOTRUN -> [SKIP][49] ([i915#4079])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
* igt@gem_set_tiling_vs_gtt:
- shard-mtlp: NOTRUN -> [SKIP][50] ([i915#4079])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@gem_set_tiling_vs_gtt.html
* igt@gem_tiled_pread_basic:
- shard-dg2: NOTRUN -> [SKIP][51] ([i915#4079])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-2/igt@gem_tiled_pread_basic.html
* igt@gem_userptr_blits@coherency-unsync:
- shard-dg1: NOTRUN -> [SKIP][52] ([i915#3297])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@gem_userptr_blits@coherency-unsync.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-glk: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#3323])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-glk8/igt@gem_userptr_blits@dmabuf-sync.html
- shard-rkl: NOTRUN -> [SKIP][54] ([i915#3323])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-dg2: NOTRUN -> [SKIP][55] ([i915#3297] / [i915#4880])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@readonly-pwrite-unsync:
- shard-rkl: NOTRUN -> [SKIP][56] ([i915#3297]) +2 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-4/igt@gem_userptr_blits@readonly-pwrite-unsync.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-mtlp: NOTRUN -> [SKIP][57] ([i915#3297])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gen7_exec_parse@basic-rejected:
- shard-mtlp: NOTRUN -> [SKIP][58] ([fdo#109289]) +1 other test skip
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@gen7_exec_parse@basic-rejected.html
* igt@gen7_exec_parse@batch-without-end:
- shard-rkl: NOTRUN -> [SKIP][59] ([fdo#109289])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@gen7_exec_parse@batch-without-end.html
* igt@gen9_exec_parse@bb-start-far:
- shard-rkl: NOTRUN -> [SKIP][60] ([i915#2527]) +3 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@gen9_exec_parse@bb-start-far.html
* igt@gen9_exec_parse@valid-registers:
- shard-dg2: NOTRUN -> [SKIP][61] ([i915#2856]) +4 other tests skip
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-5/igt@gen9_exec_parse@valid-registers.html
* igt@i915_fb_tiling:
- shard-dg2: NOTRUN -> [SKIP][62] ([i915#4881])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@i915_fb_tiling.html
* igt@i915_module_load@resize-bar:
- shard-dg2: [PASS][63] -> [INCOMPLETE][64] ([i915#1982])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-dg2-11/igt@i915_module_load@resize-bar.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-7/igt@i915_module_load@resize-bar.html
* igt@i915_pm_freq_api@freq-reset-multiple:
- shard-rkl: NOTRUN -> [SKIP][65] ([i915#8399])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@i915_pm_freq_api@freq-reset-multiple.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-dg2: NOTRUN -> [SKIP][66] ([fdo#109293] / [fdo#109506])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@i915_pm_rps@basic-api:
- shard-dg1: NOTRUN -> [SKIP][67] ([i915#6621])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@i915_pm_rps@basic-api.html
* igt@i915_pm_rps@min-max-config-loaded:
- shard-dg2: NOTRUN -> [SKIP][68] ([i915#6621])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-2/igt@i915_pm_rps@min-max-config-loaded.html
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][69] -> [INCOMPLETE][70] ([i915#7790])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-snb5/igt@i915_pm_rps@reset.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-snb4/igt@i915_pm_rps@reset.html
* igt@i915_pm_rps@thresholds@gt0:
- shard-dg2: NOTRUN -> [SKIP][71] ([i915#8925])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@i915_pm_rps@thresholds@gt0.html
* igt@i915_query@query-topology-unsupported:
- shard-rkl: NOTRUN -> [SKIP][72] ([fdo#109302])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@i915_query@query-topology-unsupported.html
* igt@i915_query@test-query-geometry-subslices:
- shard-rkl: NOTRUN -> [SKIP][73] ([i915#5723])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@i915_query@test-query-geometry-subslices.html
* igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
- shard-dg2: NOTRUN -> [SKIP][74] ([i915#4212]) +1 other test skip
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-5/igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- shard-dg2: NOTRUN -> [SKIP][75] ([i915#4215] / [i915#5190])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-2:
- shard-glk: [PASS][76] -> [FAIL][77] ([i915#2521]) +1 other test fail
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-glk9/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-2.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-glk7/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-2.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-0:
- shard-rkl: NOTRUN -> [SKIP][78] ([i915#5286]) +4 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-180:
- shard-dg1: NOTRUN -> [SKIP][79] ([i915#4538] / [i915#5286])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@kms_big_fb@4-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-mtlp: [PASS][80] -> [FAIL][81] ([i915#5138])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@linear-16bpp-rotate-270:
- shard-dg1: NOTRUN -> [SKIP][82] ([i915#3638])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@kms_big_fb@linear-16bpp-rotate-270.html
* igt@kms_big_fb@linear-16bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][83] ([fdo#111614]) +2 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@kms_big_fb@linear-16bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-90:
- shard-mtlp: NOTRUN -> [SKIP][84] ([fdo#111614]) +1 other test skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-0:
- shard-dg2: NOTRUN -> [SKIP][85] ([i915#5190]) +19 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-2/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][86] ([fdo#111614] / [i915#3638]) +2 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-tglu: [PASS][87] -> [FAIL][88] ([i915#3743]) +1 other test fail
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-tglu-7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-tglu-9/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
- shard-rkl: NOTRUN -> [SKIP][89] ([fdo#110723]) +1 other test skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
- shard-dg1: NOTRUN -> [SKIP][90] ([i915#4538]) +1 other test skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][91] ([i915#4538] / [i915#5190]) +6 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-5/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
- shard-mtlp: NOTRUN -> [SKIP][92] ([fdo#111615]) +2 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-addfb:
- shard-rkl: NOTRUN -> [SKIP][93] ([fdo#111615])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_big_fb@yf-tiled-addfb.html
* igt@kms_big_joiner@2x-modeset:
- shard-dg1: NOTRUN -> [SKIP][94] ([i915#2705])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@kms_big_joiner@2x-modeset.html
* igt@kms_big_joiner@invalid-modeset:
- shard-rkl: NOTRUN -> [SKIP][95] ([i915#2705])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_cdclk@mode-transition:
- shard-rkl: NOTRUN -> [SKIP][96] ([i915#3742])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_cdclk@mode-transition.html
* igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][97] ([i915#7213]) +3 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-2/igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-2.html
* igt@kms_chamelium_color@ctm-0-25:
- shard-mtlp: NOTRUN -> [SKIP][98] ([fdo#111827])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@kms_chamelium_color@ctm-0-25.html
* igt@kms_chamelium_color@ctm-negative:
- shard-rkl: NOTRUN -> [SKIP][99] ([fdo#111827]) +1 other test skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@kms_chamelium_color@ctm-negative.html
* igt@kms_chamelium_color@degamma:
- shard-dg2: NOTRUN -> [SKIP][100] ([fdo#111827]) +2 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-5/igt@kms_chamelium_color@degamma.html
* igt@kms_chamelium_color@gamma:
- shard-dg1: NOTRUN -> [SKIP][101] ([fdo#111827])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@kms_chamelium_color@gamma.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- shard-mtlp: NOTRUN -> [SKIP][102] ([i915#7828])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_chamelium_frames@hdmi-crc-multiple:
- shard-dg2: NOTRUN -> [SKIP][103] ([i915#7828]) +7 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@kms_chamelium_frames@hdmi-crc-multiple.html
* igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode:
- shard-rkl: NOTRUN -> [SKIP][104] ([i915#7828]) +8 other tests skip
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html
* igt@kms_chamelium_hpd@dp-hpd-fast:
- shard-dg1: NOTRUN -> [SKIP][105] ([i915#7828]) +1 other test skip
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@kms_chamelium_hpd@dp-hpd-fast.html
* igt@kms_color@legacy-gamma-reset@pipe-b:
- shard-rkl: [PASS][106] -> [SKIP][107] ([i915#4098]) +3 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-7/igt@kms_color@legacy-gamma-reset@pipe-b.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-4/igt@kms_color@legacy-gamma-reset@pipe-b.html
* igt@kms_content_protection@atomic:
- shard-rkl: NOTRUN -> [SKIP][108] ([i915#7118])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@atomic-dpms:
- shard-dg2: NOTRUN -> [SKIP][109] ([i915#7118]) +2 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-7/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-mtlp: NOTRUN -> [SKIP][110] ([i915#3299])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@legacy@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [TIMEOUT][111] ([i915#7173]) +1 other test timeout
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@kms_content_protection@legacy@pipe-a-dp-4.html
* igt@kms_cursor_crc@cursor-offscreen-32x10:
- shard-rkl: NOTRUN -> [SKIP][112] ([i915#3555]) +8 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_cursor_crc@cursor-offscreen-32x10.html
* igt@kms_cursor_crc@cursor-offscreen-512x512:
- shard-dg2: NOTRUN -> [SKIP][113] ([i915#3359]) +2 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@kms_cursor_crc@cursor-offscreen-512x512.html
* igt@kms_cursor_crc@cursor-onscreen-max-size:
- shard-dg2: NOTRUN -> [SKIP][114] ([i915#3555]) +4 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@kms_cursor_crc@cursor-onscreen-max-size.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-mtlp: NOTRUN -> [SKIP][115] ([i915#3359]) +1 other test skip
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_crc@cursor-sliding-256x256@pipe-a-hdmi-a-1:
- shard-glk: [PASS][116] -> [DMESG-FAIL][117] ([i915#118])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-glk5/igt@kms_cursor_crc@cursor-sliding-256x256@pipe-a-hdmi-a-1.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-glk6/igt@kms_cursor_crc@cursor-sliding-256x256@pipe-a-hdmi-a-1.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-dg1: NOTRUN -> [SKIP][118] ([i915#3359])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_edge_walk@256x256-right-edge:
- shard-rkl: NOTRUN -> [SKIP][119] ([i915#4098]) +9 other tests skip
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-4/igt@kms_cursor_edge_walk@256x256-right-edge.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
- shard-dg2: NOTRUN -> [SKIP][120] ([fdo#109274] / [i915#5354]) +5 other tests skip
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-2/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-rkl: [PASS][121] -> [SKIP][122] ([i915#1845] / [i915#4098]) +9 other tests skip
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-7/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-4/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
- shard-dg1: NOTRUN -> [SKIP][123] ([fdo#111825]) +8 other tests skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
- shard-mtlp: NOTRUN -> [SKIP][124] ([i915#3546]) +1 other test skip
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-dg1: NOTRUN -> [SKIP][125] ([i915#4103] / [i915#4213])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc:
- shard-dg1: NOTRUN -> [SKIP][126] ([i915#3555])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
* igt@kms_draw_crc@draw-method-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][127] ([i915#8812])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-2/igt@kms_draw_crc@draw-method-mmap-wc.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-dg2: NOTRUN -> [SKIP][128] ([i915#3840] / [i915#9688])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-mtlp: NOTRUN -> [SKIP][129] ([i915#3555] / [i915#3840] / [i915#4098])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_dsc@dsc-with-formats:
- shard-rkl: NOTRUN -> [SKIP][130] ([i915#3555] / [i915#3840])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_dsc@dsc-with-formats.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-glk: [PASS][131] -> [FAIL][132] ([i915#4767])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-glk3/igt@kms_fbcon_fbt@fbc-suspend.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-glk1/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-rkl: NOTRUN -> [SKIP][133] ([i915#3955])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_fbcon_fbt@psr-suspend.html
- shard-dg2: NOTRUN -> [SKIP][134] ([i915#3469])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-2/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@2x-dpms-vs-vblank-race:
- shard-dg2: NOTRUN -> [SKIP][135] ([fdo#109274]) +7 other tests skip
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@kms_flip@2x-dpms-vs-vblank-race.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
- shard-mtlp: NOTRUN -> [SKIP][136] ([i915#3637]) +1 other test skip
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html
* igt@kms_flip@2x-flip-vs-panning:
- shard-rkl: NOTRUN -> [SKIP][137] ([fdo#111825]) +6 other tests skip
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@kms_flip@2x-flip-vs-panning.html
* igt@kms_flip@2x-flip-vs-rmfb-interruptible:
- shard-dg2: NOTRUN -> [SKIP][138] ([fdo#109274] / [fdo#111767])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-5/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html
* igt@kms_flip@2x-nonexisting-fb:
- shard-snb: NOTRUN -> [SKIP][139] ([fdo#109271]) +7 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-snb4/igt@kms_flip@2x-nonexisting-fb.html
* igt@kms_flip@basic-flip-vs-wf_vblank:
- shard-rkl: NOTRUN -> [SKIP][140] ([i915#3637] / [i915#4098]) +3 other tests skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@kms_flip@basic-flip-vs-wf_vblank.html
* igt@kms_flip@flip-vs-fences:
- shard-dg1: NOTRUN -> [SKIP][141] ([i915#8381])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@kms_flip@flip-vs-fences.html
* igt@kms_flip@flip-vs-fences-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][142] ([i915#8381])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@kms_flip@flip-vs-fences-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][143] ([i915#2672]) +1 other test skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][144] ([i915#2672]) +4 other tests skip
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][145] ([i915#2672]) +4 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-rkl: NOTRUN -> [SKIP][146] ([fdo#109285] / [i915#4098])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-4/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
- shard-rkl: [PASS][147] -> [SKIP][148] ([i915#1849] / [i915#4098] / [i915#5354]) +6 other tests skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt:
- shard-dg2: NOTRUN -> [SKIP][149] ([i915#5354]) +31 other tests skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][150] ([i915#1849] / [i915#4098] / [i915#5354]) +30 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][151] ([i915#8708]) +14 other tests skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
- shard-rkl: NOTRUN -> [SKIP][152] ([i915#3023]) +16 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][153] ([i915#8708]) +3 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt:
- shard-dg1: NOTRUN -> [SKIP][154] ([i915#3458]) +4 other tests skip
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][155] ([i915#8708]) +2 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw:
- shard-glk: NOTRUN -> [SKIP][156] ([fdo#109271]) +108 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-glk6/igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
- shard-rkl: NOTRUN -> [SKIP][157] ([fdo#111825] / [i915#1825]) +22 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
- shard-mtlp: NOTRUN -> [SKIP][158] ([i915#1825]) +8 other tests skip
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
- shard-dg2: NOTRUN -> [SKIP][159] ([i915#3458]) +26 other tests skip
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html
* igt@kms_hdr@bpc-switch:
- shard-rkl: NOTRUN -> [SKIP][160] ([i915#3555] / [i915#8228])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-dg2: NOTRUN -> [SKIP][161] ([i915#3555] / [i915#8228])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-10/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_invalid_mode@int-max-clock:
- shard-rkl: NOTRUN -> [SKIP][162] ([i915#3555] / [i915#4098]) +1 other test skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@kms_invalid_mode@int-max-clock.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-dg1: NOTRUN -> [SKIP][163] ([i915#1839])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c:
- shard-dg2: NOTRUN -> [SKIP][164] ([fdo#109289]) +4 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-1/igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c.html
* igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes:
- shard-dg1: NOTRUN -> [SKIP][165] ([fdo#109289]) +2 other tests skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes.html
* igt@kms_plane@plane-position-hole-dpms:
- shard-rkl: NOTRUN -> [SKIP][166] ([i915#4098] / [i915#8825]) +1 other test skip
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@kms_plane@plane-position-hole-dpms.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-dg2: NOTRUN -> [SKIP][167] ([i915#6953])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-1/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@invalid-parameters:
- shard-rkl: NOTRUN -> [SKIP][168] ([i915#8152]) +1 other test skip
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@kms_plane_scaling@invalid-parameters.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25:
- shard-rkl: NOTRUN -> [SKIP][169] ([i915#4098] / [i915#6953] / [i915#8152])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@kms_plane_scaling@planes-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][170] ([i915#5235]) +7 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-12/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][171] ([i915#5235]) +3 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][172] ([i915#5235]) +11 other tests skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-hdmi-a-2.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25:
- shard-rkl: NOTRUN -> [SKIP][173] ([i915#3555] / [i915#4098] / [i915#6953] / [i915#8152]) +1 other test skip
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-4/igt@kms_plane_scaling@planes-upscale-factor-0-25.html
* igt@kms_prime@basic-modeset-hybrid:
- shard-dg2: NOTRUN -> [SKIP][174] ([i915#6524] / [i915#6805]) +1 other test skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-2/igt@kms_prime@basic-modeset-hybrid.html
- shard-rkl: NOTRUN -> [SKIP][175] ([i915#6524])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_prime@basic-modeset-hybrid.html
* igt@kms_properties@crtc-properties-atomic:
- shard-rkl: [PASS][176] -> [SKIP][177] ([i915#1849])
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-6/igt@kms_properties@crtc-properties-atomic.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@kms_properties@crtc-properties-atomic.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf:
- shard-rkl: NOTRUN -> [SKIP][178] ([i915#9683])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-dg1: NOTRUN -> [SKIP][179] ([i915#9683])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-dg2: NOTRUN -> [SKIP][180] ([i915#9683]) +3 other tests skip
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-p010:
- shard-rkl: NOTRUN -> [SKIP][181] ([fdo#111068] / [i915#9683]) +1 other test skip
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-rkl: NOTRUN -> [SKIP][182] ([i915#9673] / [i915#9732])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-dg2: NOTRUN -> [SKIP][183] ([i915#9673])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_psr@psr2_sprite_blt:
- shard-dg2: NOTRUN -> [SKIP][184] ([i915#9673] / [i915#9732]) +2 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-1/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-dg2: NOTRUN -> [SKIP][185] ([i915#9673] / [i915#9736]) +1 other test skip
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-dg2: NOTRUN -> [SKIP][186] ([i915#9685])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-1/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@bad-tiling:
- shard-dg2: NOTRUN -> [SKIP][187] ([i915#4235]) +1 other test skip
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-1/igt@kms_rotation_crc@bad-tiling.html
* igt@kms_rotation_crc@primary-rotation-90:
- shard-rkl: NOTRUN -> [SKIP][188] ([i915#1845] / [i915#4098]) +33 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-4/igt@kms_rotation_crc@primary-rotation-90.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
- shard-mtlp: NOTRUN -> [SKIP][189] ([i915#4235])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-rkl: NOTRUN -> [SKIP][190] ([fdo#111615] / [i915#5289])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1:
- shard-mtlp: [PASS][191] -> [FAIL][192] ([i915#9196])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-mtlp-7/igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-4/igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1.html
* igt@perf_pmu@busy-double-start@rcs0:
- shard-mtlp: [PASS][193] -> [FAIL][194] ([i915#4349])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-mtlp-5/igt@perf_pmu@busy-double-start@rcs0.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-2/igt@perf_pmu@busy-double-start@rcs0.html
* igt@perf_pmu@module-unload:
- shard-dg2: NOTRUN -> [FAIL][195] ([i915#5793])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@perf_pmu@module-unload.html
* igt@perf_pmu@rc6-all-gts:
- shard-dg2: NOTRUN -> [SKIP][196] ([i915#5608] / [i915#8516])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@perf_pmu@rc6-all-gts.html
* igt@perf_pmu@rc6@other-idle-gt0:
- shard-dg2: NOTRUN -> [SKIP][197] ([i915#8516])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-11/igt@perf_pmu@rc6@other-idle-gt0.html
* igt@prime_udl:
- shard-rkl: NOTRUN -> [SKIP][198] ([fdo#109291])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-4/igt@prime_udl.html
* igt@prime_vgem@basic-fence-read:
- shard-dg1: NOTRUN -> [SKIP][199] ([i915#3708])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-read:
- shard-rkl: NOTRUN -> [SKIP][200] ([fdo#109295] / [i915#3291] / [i915#3708])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@prime_vgem@basic-read.html
* igt@prime_vgem@fence-write-hang:
- shard-dg2: NOTRUN -> [SKIP][201] ([i915#3708])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-2/igt@prime_vgem@fence-write-hang.html
- shard-rkl: NOTRUN -> [SKIP][202] ([fdo#109295] / [i915#3708])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@prime_vgem@fence-write-hang.html
* igt@v3d/v3d_perfmon@get-values-invalid-pad:
- shard-mtlp: NOTRUN -> [SKIP][203] ([i915#2575]) +2 other tests skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@v3d/v3d_perfmon@get-values-invalid-pad.html
* igt@v3d/v3d_perfmon@get-values-valid-perfmon:
- shard-rkl: NOTRUN -> [SKIP][204] ([fdo#109315]) +11 other tests skip
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-4/igt@v3d/v3d_perfmon@get-values-valid-perfmon.html
* igt@v3d/v3d_submit_csd@bad-extension:
- shard-dg1: NOTRUN -> [SKIP][205] ([i915#2575]) +2 other tests skip
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@v3d/v3d_submit_csd@bad-extension.html
* igt@v3d/v3d_submit_csd@job-perfmon:
- shard-dg2: NOTRUN -> [SKIP][206] ([i915#2575]) +14 other tests skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-2/igt@v3d/v3d_submit_csd@job-perfmon.html
* igt@vc4/vc4_label_bo@set-bad-handle:
- shard-mtlp: NOTRUN -> [SKIP][207] ([i915#7711]) +1 other test skip
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-6/igt@vc4/vc4_label_bo@set-bad-handle.html
* igt@vc4/vc4_mmap@mmap-bo:
- shard-dg2: NOTRUN -> [SKIP][208] ([i915#7711]) +9 other tests skip
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-2/igt@vc4/vc4_mmap@mmap-bo.html
* igt@vc4/vc4_perfmon@get-values-invalid-pointer:
- shard-dg1: NOTRUN -> [SKIP][209] ([i915#7711])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-16/igt@vc4/vc4_perfmon@get-values-invalid-pointer.html
* igt@vc4/vc4_purgeable_bo@mark-purgeable:
- shard-rkl: NOTRUN -> [SKIP][210] ([i915#7711]) +9 other tests skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@vc4/vc4_purgeable_bo@mark-purgeable.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [FAIL][211] ([i915#7742]) -> [PASS][212]
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-7/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@fbdev@write:
- shard-rkl: [SKIP][213] ([i915#2582]) -> [PASS][214]
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-2/igt@fbdev@write.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@fbdev@write.html
* igt@gem_eio@in-flight-contexts-1us:
- shard-mtlp: [FAIL][215] ([i915#8898]) -> [PASS][216]
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-mtlp-8/igt@gem_eio@in-flight-contexts-1us.html
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-5/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_eio@reset-stress:
- shard-dg1: [FAIL][217] ([i915#5784]) -> [PASS][218]
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-dg1-15/igt@gem_eio@reset-stress.html
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-12/igt@gem_eio@reset-stress.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [INCOMPLETE][219] ([i915#5566]) -> [PASS][220]
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-glk3/igt@gen9_exec_parse@allowed-single.html
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-glk6/igt@gen9_exec_parse@allowed-single.html
* {igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0}:
- shard-dg1: [FAIL][221] ([i915#3591]) -> [PASS][222] +2 other tests pass
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-mtlp: [FAIL][223] ([i915#5138]) -> [PASS][224]
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- shard-rkl: [SKIP][225] ([i915#1845] / [i915#4098]) -> [PASS][226] +11 other tests pass
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-1/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
* {igt@kms_ccs@pipe-a-ccs-on-another-bo-y-tiled-gen12-rc-ccs}:
- shard-rkl: [SKIP][227] ([i915#4098]) -> [PASS][228] +3 other tests pass
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-2/igt@kms_ccs@pipe-a-ccs-on-another-bo-y-tiled-gen12-rc-ccs.html
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@kms_ccs@pipe-a-ccs-on-another-bo-y-tiled-gen12-rc-ccs.html
* {igt@kms_feature_discovery@display-1x}:
- shard-rkl: [SKIP][229] -> [PASS][230]
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-1/igt@kms_feature_discovery@display-1x.html
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_feature_discovery@display-1x.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt:
- shard-rkl: [SKIP][231] ([i915#1849] / [i915#4098] / [i915#5354]) -> [PASS][232] +5 other tests pass
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-dg2: [FAIL][233] ([i915#6880]) -> [PASS][234]
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
* {igt@kms_pm_dc@dc5-dpms-negative}:
- shard-rkl: [SKIP][235] ([i915#9293]) -> [PASS][236]
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-2/igt@kms_pm_dc@dc5-dpms-negative.html
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@kms_pm_dc@dc5-dpms-negative.html
* {igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait}:
- shard-dg2: [SKIP][237] ([i915#9519]) -> [PASS][238] +1 other test pass
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-dg2-10/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-2/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
- shard-tglu: [FAIL][239] ([i915#9196]) -> [PASS][240]
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-tglu-5/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-tglu-5/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-edp-1:
- shard-mtlp: [FAIL][241] ([i915#9196]) -> [PASS][242]
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-mtlp-7/igt@kms_universal_plane@cursor-fb-leak@pipe-b-edp-1.html
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-mtlp-4/igt@kms_universal_plane@cursor-fb-leak@pipe-b-edp-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-vga-1:
- shard-snb: [FAIL][243] ([i915#9196]) -> [PASS][244]
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-snb4/igt@kms_universal_plane@cursor-fb-leak@pipe-b-vga-1.html
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-snb2/igt@kms_universal_plane@cursor-fb-leak@pipe-b-vga-1.html
* {igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-4}:
- shard-dg1: [FAIL][245] ([i915#9196]) -> [PASS][246]
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-dg1-19/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-4.html
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg1-14/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-4.html
#### Warnings ####
* igt@i915_suspend@basic-s2idle-without-i915:
- shard-snb: [INCOMPLETE][247] ([i915#4817]) -> [INCOMPLETE][248] ([i915#4528] / [i915#4817])
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-snb5/igt@i915_suspend@basic-s2idle-without-i915.html
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-snb5/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-rkl: [SKIP][249] ([i915#1845] / [i915#4098]) -> [SKIP][250] ([i915#9531])
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-2/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-90:
- shard-rkl: [SKIP][251] ([i915#1845] / [i915#4098]) -> [SKIP][252] ([i915#5286]) +1 other test skip
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-2/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
- shard-rkl: [SKIP][253] ([i915#5286]) -> [SKIP][254] ([i915#1845] / [i915#4098]) +1 other test skip
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-6/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-90:
- shard-rkl: [SKIP][255] ([fdo#111614] / [i915#3638]) -> [SKIP][256] ([i915#1845] / [i915#4098]) +2 other tests skip
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-6/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
- shard-rkl: [SKIP][257] ([i915#1845] / [i915#4098]) -> [SKIP][258] ([fdo#110723])
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-2/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-rkl: [SKIP][259] ([fdo#111615]) -> [SKIP][260] ([i915#1845] / [i915#4098])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-6/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-addfb-size-overflow:
- shard-rkl: [SKIP][261] ([i915#1845] / [i915#4098]) -> [SKIP][262] ([fdo#111615])
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-1/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-rkl: [SKIP][263] ([fdo#110723]) -> [SKIP][264] ([i915#1845] / [i915#4098]) +1 other test skip
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-6/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_color@deep-color:
- shard-rkl: [SKIP][265] ([i915#3546] / [i915#4098]) -> [SKIP][266] ([i915#3555])
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-1/igt@kms_color@deep-color.html
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_color@deep-color.html
* igt@kms_cursor_crc@cursor-sliding-32x10:
- shard-rkl: [SKIP][267] ([i915#1845] / [i915#4098]) -> [SKIP][268] ([i915#3555]) +2 other tests skip
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-2/igt@kms_cursor_crc@cursor-sliding-32x10.html
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@kms_cursor_crc@cursor-sliding-32x10.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-rkl: [SKIP][269] ([i915#3359]) -> [SKIP][270] ([i915#1845] / [i915#4098])
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-6/igt@kms_cursor_crc@cursor-sliding-512x170.html
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
- shard-rkl: [SKIP][271] ([fdo#111767] / [fdo#111825]) -> [SKIP][272] ([i915#1845] / [i915#4098]) +1 other test skip
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-7/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-4/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
- shard-rkl: [SKIP][273] ([fdo#111825]) -> [SKIP][274] ([i915#1845] / [i915#4098]) +3 other tests skip
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-7/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-4/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- shard-rkl: [SKIP][275] ([i915#1845] / [i915#4098]) -> [SKIP][276] ([i915#4103])
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
- shard-rkl: [SKIP][277] ([i915#1845] / [i915#4098]) -> [SKIP][278] ([fdo#111825]) +1 other test skip
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-2/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
* igt@kms_display_modes@mst-extended-mode-negative:
- shard-rkl: [SKIP][279] ([i915#8588]) -> [SKIP][280] ([i915#4098])
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-7/igt@kms_display_modes@mst-extended-mode-negative.html
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-4/igt@kms_display_modes@mst-extended-mode-negative.html
* igt@kms_dsc@dsc-basic:
- shard-rkl: [SKIP][281] ([i915#3555] / [i915#3840]) -> [SKIP][282] ([i915#4098])
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-6/igt@kms_dsc@dsc-basic.html
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@kms_dsc@dsc-basic.html
* igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt:
- shard-rkl: [SKIP][283] ([fdo#111825]) -> [SKIP][284] ([i915#1849] / [i915#4098] / [i915#5354])
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt.html
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-rkl: [SKIP][285] ([fdo#111825] / [i915#1825]) -> [SKIP][286] ([i915#1849] / [i915#4098] / [i915#5354]) +13 other tests skip
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-rkl: [SKIP][287] ([i915#1849] / [i915#4098] / [i915#5354]) -> [SKIP][288] ([i915#5439])
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- shard-rkl: [SKIP][289] ([i915#1849] / [i915#4098] / [i915#5354]) -> [SKIP][290] ([i915#3023]) +12 other tests skip
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-rkl: [SKIP][291] ([i915#3023]) -> [SKIP][292] ([i915#1849] / [i915#4098] / [i915#5354]) +10 other tests skip
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-rkl: [SKIP][293] ([i915#1849] / [i915#4098] / [i915#5354]) -> [SKIP][294] ([fdo#111825] / [i915#1825]) +14 other tests skip
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc.html
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-rkl: [SKIP][295] ([i915#3555] / [i915#8228]) -> [SKIP][296] ([i915#1845] / [i915#4098])
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-7/igt@kms_hdr@bpc-switch-dpms.html
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-4/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_hdr@static-swap:
- shard-rkl: [SKIP][297] ([i915#1845] / [i915#4098]) -> [SKIP][298] ([i915#3555] / [i915#8228])
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-2/igt@kms_hdr@static-swap.html
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@kms_hdr@static-swap.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][299] ([i915#4070] / [i915#4816]) -> [SKIP][300] ([i915#4816])
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-2/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_panel_fitting@atomic-fastset:
- shard-rkl: [SKIP][301] ([i915#1845] / [i915#4098]) -> [SKIP][302] ([i915#6301])
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-2/igt@kms_panel_fitting@atomic-fastset.html
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@kms_panel_fitting@atomic-fastset.html
* igt@kms_plane_lowres@tiling-4:
- shard-rkl: [SKIP][303] ([i915#3555]) -> [SKIP][304] ([i915#1845] / [i915#4098]) +2 other tests skip
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-7/igt@kms_plane_lowres@tiling-4.html
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-4/igt@kms_plane_lowres@tiling-4.html
* igt@kms_properties@plane-properties-atomic:
- shard-rkl: [SKIP][305] ([i915#1849] / [i915#4098]) -> [SKIP][306] ([i915#1849])
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-4/igt@kms_properties@plane-properties-atomic.html
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-2/igt@kms_properties@plane-properties-atomic.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-rkl: [SKIP][307] ([i915#9673] / [i915#9732]) -> [SKIP][308] ([i915#9673]) +1 other test skip
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-6/igt@kms_psr@psr2_cursor_mmap_cpu.html
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-1/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_psr@psr2_primary_render:
- shard-rkl: [SKIP][309] ([i915#9673]) -> [SKIP][310] ([i915#9673] / [i915#9732]) +1 other test skip
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-1/igt@kms_psr@psr2_primary_render.html
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-7/igt@kms_psr@psr2_primary_render.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-dg2: [SKIP][311] ([i915#9673] / [i915#9736]) -> [SKIP][312] ([i915#9673])
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-dg2-11/igt@kms_psr@psr2_sprite_mmap_cpu.html
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-10/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@kms_psr@psr2_suspend:
- shard-dg2: [SKIP][313] ([i915#9673] / [i915#9736]) -> [SKIP][314] ([i915#9673] / [i915#9732]) +1 other test skip
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-dg2-11/igt@kms_psr@psr2_suspend.html
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-dg2-10/igt@kms_psr@psr2_suspend.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
- shard-rkl: [SKIP][315] ([i915#1845] / [i915#4098]) -> [SKIP][316] ([i915#5289])
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13939/shard-rkl-2/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/shard-rkl-6/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5793]: https://gitlab.freedesktop.org/drm/intel/issues/5793
[i915#5978]: https://gitlab.freedesktop.org/drm/intel/issues/5978
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
[i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7790]: https://gitlab.freedesktop.org/drm/intel/issues/7790
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8152]: https://gitlab.freedesktop.org/drm/intel/issues/8152
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
[i915#8399]: https://gitlab.freedesktop.org/drm/intel/issues/8399
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8516]: https://gitlab.freedesktop.org/drm/intel/issues/8516
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
[i915#8562]: https://gitlab.freedesktop.org/drm/intel/issues/8562
[i915#8588]: https://gitlab.freedesktop.org/drm/intel/issues/8588
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
[i915#8812]: https://gitlab.freedesktop.org/drm/intel/issues/8812
[i915#8825]: https://gitlab.freedesktop.org/drm/intel/issues/8825
[i915#8898]: https://gitlab.freedesktop.org/drm/intel/issues/8898
[i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
[i915#9067]: https://gitlab.freedesktop.org/drm/intel/issues/9067
[i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
[i915#9293]: https://gitlab.freedesktop.org/drm/intel/issues/9293
[i915#9323]: https://gitlab.freedesktop.org/drm/intel/issues/9323
[i915#9337]: https://gitlab.freedesktop.org/drm/intel/issues/9337
[i915#9412]: https://gitlab.freedesktop.org/drm/intel/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/intel/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/intel/issues/9424
[i915#9519]: https://gitlab.freedesktop.org/drm/intel/issues/9519
[i915#9531]: https://gitlab.freedesktop.org/drm/intel/issues/9531
[i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
[i915#9683]: https://gitlab.freedesktop.org/drm/intel/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/intel/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688
[i915#9723]: https://gitlab.freedesktop.org/drm/intel/issues/9723
[i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
[i915#9736]: https://gitlab.freedesktop.org/drm/intel/issues/9736
Build changes
-------------
* Linux: CI_DRM_13939 -> Patchwork_126859v2
CI-20190529: 20190529
CI_DRM_13939: 444a2d69536b9fb289e86b48f53b6f212a4d6fac @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7608: 3e52de09140ec5ddf8919fcb11a858cfcc137359 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_126859v2: 444a2d69536b9fb289e86b48f53b6f212a4d6fac @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126859v2/index.html
[-- Attachment #2: Type: text/html, Size: 105403 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 2/5] drm/i915: Replace a memset() with zero initialization
2023-11-24 8:27 ` [Intel-gfx] [PATCH 2/5] drm/i915: Replace a memset() with zero initialization Ville Syrjala
@ 2023-11-29 14:50 ` Kahola, Mika
0 siblings, 0 replies; 18+ messages in thread
From: Kahola, Mika @ 2023-11-29 14:50 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Friday, November 24, 2023 10:28 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 2/5] drm/i915: Replace a memset() with zero initialization
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Declaring a struct and immediately zeroing it with memset() seems a bit silly to me. Just zero initialize the struct when declaring it.
>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index ef57dad1a9cb..0376adc36780 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4465,12 +4465,10 @@ verify_single_dpll_state(struct drm_i915_private *i915,
> struct intel_crtc *crtc,
> const struct intel_crtc_state *new_crtc_state) {
> - struct intel_dpll_hw_state dpll_hw_state;
> + struct intel_dpll_hw_state dpll_hw_state = {};
> u8 pipe_mask;
> bool active;
>
> - memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
> -
> drm_dbg_kms(&i915->drm, "%s\n", pll->info->name);
>
> active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state);
> --
> 2.41.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 4/5] drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLs
2023-11-24 8:27 ` [Intel-gfx] [PATCH 4/5] drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLs Ville Syrjala
@ 2023-12-07 14:05 ` Ville Syrjälä
2023-12-07 14:55 ` [Intel-gfx] " Imre Deak
1 sibling, 0 replies; 18+ messages in thread
From: Ville Syrjälä @ 2023-12-07 14:05 UTC (permalink / raw)
To: intel-gfx
On Fri, Nov 24, 2023 at 10:27:34AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> TC ports have both the MG/TC and TBT PLLs selected simultanously (so
> that we can switch from MG/TC to TBT as a fallback). This doesn't play
> well with the state checker that assumes that the old PLL shouldn't
> have the pipe in its pipe_mask anymore. Suppress that check for these
> PLLs to avoid spurious WARNs when you disconnect a TC port and a
> non-disabling modeset happens before actually disabling the port.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Presumably
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9816
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 56 +++++++++++++------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++
> 2 files changed, 42 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index d86b02de2923..5c6c4fc50b1d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4023,11 +4023,16 @@ static const struct intel_shared_dpll_funcs mg_pll_funcs = {
> static const struct dpll_info icl_plls[] = {
> { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
> - { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> - { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> - { .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> - { .name = "MG PLL 4", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
> + { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "MG PLL 4", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> {}
> };
>
> @@ -4068,13 +4073,20 @@ static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
> static const struct dpll_info tgl_plls[] = {
> { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
> - { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> - { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> - { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> - { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
> - { .name = "TC PLL 5", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL5, },
> - { .name = "TC PLL 6", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL6, },
> + { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "TC PLL 5", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL5,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "TC PLL 6", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL6,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> {}
> };
>
> @@ -4141,11 +4153,16 @@ static const struct intel_dpll_mgr adls_pll_mgr = {
> static const struct dpll_info adlp_plls[] = {
> { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
> - { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> - { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> - { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> - { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
> + { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> {}
> };
>
> @@ -4535,7 +4552,10 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> I915_STATE_WARN(i915, pll->active_mask & pipe_mask,
> "%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
> pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
> - I915_STATE_WARN(i915, pll->state.pipe_mask & pipe_mask,
> +
> + /* TC ports have both MG/TC and TBT PLL referenced simultaneously */
> + I915_STATE_WARN(i915, !(pll->info->flags & INTEL_DPLL_HAS_ALT_PORT_DPLL) &&
> + pll->state.pipe_mask & pipe_mask,
> "%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
> pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 2e7ea0d8d3ff..594658087b4a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -277,12 +277,16 @@ struct dpll_info {
> enum intel_display_power_domain power_domain;
>
> #define INTEL_DPLL_ALWAYS_ON (1 << 0)
> +#define INTEL_DPLL_HAS_ALT_PORT_DPLL (1 << 1)
> /**
> * @flags:
> *
> * INTEL_DPLL_ALWAYS_ON
> * Inform the state checker that the DPLL is kept enabled even if
> * not in use by any CRTC.
> + * INTEL_DPLL_HAS_ALT_PORT_DPLL
> + * Inform the state checker that the CRTC will have two port DPLLs
> + * referenced simultanously (for TC->TBT fallback).
> */
> u32 flags;
> };
> --
> 2.41.0
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 4/5] drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLs
2023-11-24 8:27 ` [Intel-gfx] [PATCH 4/5] drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLs Ville Syrjala
2023-12-07 14:05 ` Ville Syrjälä
@ 2023-12-07 14:55 ` Imre Deak
2023-12-07 15:24 ` Ville Syrjälä
1 sibling, 1 reply; 18+ messages in thread
From: Imre Deak @ 2023-12-07 14:55 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Fri, Nov 24, 2023 at 10:27:34AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> TC ports have both the MG/TC and TBT PLLs selected simultanously (so
> that we can switch from MG/TC to TBT as a fallback). This doesn't play
> well with the state checker that assumes that the old PLL shouldn't
> have the pipe in its pipe_mask anymore. Suppress that check for these
> PLLs to avoid spurious WARNs when you disconnect a TC port and a
> non-disabling modeset happens before actually disabling the port.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Looks ok to me:
Reviewed-by: Imre Deak <imre.deak@intel.com>
I suppose the check would be still valid for MG PLLs, but the port
PLL stuff makes doing that cumbersome.
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 56 +++++++++++++------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++
> 2 files changed, 42 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index d86b02de2923..5c6c4fc50b1d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4023,11 +4023,16 @@ static const struct intel_shared_dpll_funcs mg_pll_funcs = {
> static const struct dpll_info icl_plls[] = {
> { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
> - { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> - { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> - { .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> - { .name = "MG PLL 4", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
> + { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "MG PLL 4", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> {}
> };
>
> @@ -4068,13 +4073,20 @@ static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
> static const struct dpll_info tgl_plls[] = {
> { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
> - { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> - { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> - { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> - { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
> - { .name = "TC PLL 5", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL5, },
> - { .name = "TC PLL 6", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL6, },
> + { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "TC PLL 5", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL5,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "TC PLL 6", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL6,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> {}
> };
>
> @@ -4141,11 +4153,16 @@ static const struct intel_dpll_mgr adls_pll_mgr = {
> static const struct dpll_info adlp_plls[] = {
> { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
> - { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> - { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> - { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> - { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
> + { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> + { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
> + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> {}
> };
>
> @@ -4535,7 +4552,10 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> I915_STATE_WARN(i915, pll->active_mask & pipe_mask,
> "%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
> pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
> - I915_STATE_WARN(i915, pll->state.pipe_mask & pipe_mask,
> +
> + /* TC ports have both MG/TC and TBT PLL referenced simultaneously */
> + I915_STATE_WARN(i915, !(pll->info->flags & INTEL_DPLL_HAS_ALT_PORT_DPLL) &&
> + pll->state.pipe_mask & pipe_mask,
> "%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
> pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 2e7ea0d8d3ff..594658087b4a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -277,12 +277,16 @@ struct dpll_info {
> enum intel_display_power_domain power_domain;
>
> #define INTEL_DPLL_ALWAYS_ON (1 << 0)
> +#define INTEL_DPLL_HAS_ALT_PORT_DPLL (1 << 1)
> /**
> * @flags:
> *
> * INTEL_DPLL_ALWAYS_ON
> * Inform the state checker that the DPLL is kept enabled even if
> * not in use by any CRTC.
> + * INTEL_DPLL_HAS_ALT_PORT_DPLL
> + * Inform the state checker that the CRTC will have two port DPLLs
> + * referenced simultanously (for TC->TBT fallback).
> */
> u32 flags;
> };
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 4/5] drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLs
2023-12-07 14:55 ` [Intel-gfx] " Imre Deak
@ 2023-12-07 15:24 ` Ville Syrjälä
2023-12-07 15:47 ` Imre Deak
0 siblings, 1 reply; 18+ messages in thread
From: Ville Syrjälä @ 2023-12-07 15:24 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Dec 07, 2023 at 04:55:02PM +0200, Imre Deak wrote:
> On Fri, Nov 24, 2023 at 10:27:34AM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > TC ports have both the MG/TC and TBT PLLs selected simultanously (so
> > that we can switch from MG/TC to TBT as a fallback). This doesn't play
> > well with the state checker that assumes that the old PLL shouldn't
> > have the pipe in its pipe_mask anymore. Suppress that check for these
> > PLLs to avoid spurious WARNs when you disconnect a TC port and a
> > non-disabling modeset happens before actually disabling the port.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Looks ok to me:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
>
> I suppose the check would be still valid for MG PLLs, but the port
> PLL stuff makes doing that cumbersome.
You mean for legacy ports?
>
> > ---
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 56 +++++++++++++------
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++
> > 2 files changed, 42 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index d86b02de2923..5c6c4fc50b1d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -4023,11 +4023,16 @@ static const struct intel_shared_dpll_funcs mg_pll_funcs = {
> > static const struct dpll_info icl_plls[] = {
> > { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> > { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> > - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
> > - { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> > - { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> > - { .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> > - { .name = "MG PLL 4", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
> > + { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
> > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > + { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
> > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > + { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
> > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > + { .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
> > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > + { .name = "MG PLL 4", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
> > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > {}
> > };
> >
> > @@ -4068,13 +4073,20 @@ static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
> > static const struct dpll_info tgl_plls[] = {
> > { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> > { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> > - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
> > - { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> > - { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> > - { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> > - { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
> > - { .name = "TC PLL 5", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL5, },
> > - { .name = "TC PLL 6", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL6, },
> > + { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
> > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > + { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
> > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > + { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
> > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > + { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
> > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > + { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
> > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > + { .name = "TC PLL 5", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL5,
> > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > + { .name = "TC PLL 6", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL6,
> > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > {}
> > };
> >
> > @@ -4141,11 +4153,16 @@ static const struct intel_dpll_mgr adls_pll_mgr = {
> > static const struct dpll_info adlp_plls[] = {
> > { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> > { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> > - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
> > - { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> > - { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> > - { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> > - { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
> > + { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
> > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > + { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
> > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > + { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
> > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > + { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
> > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > + { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
> > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > {}
> > };
> >
> > @@ -4535,7 +4552,10 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> > I915_STATE_WARN(i915, pll->active_mask & pipe_mask,
> > "%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
> > pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
> > - I915_STATE_WARN(i915, pll->state.pipe_mask & pipe_mask,
> > +
> > + /* TC ports have both MG/TC and TBT PLL referenced simultaneously */
> > + I915_STATE_WARN(i915, !(pll->info->flags & INTEL_DPLL_HAS_ALT_PORT_DPLL) &&
> > + pll->state.pipe_mask & pipe_mask,
> > "%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
> > pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > index 2e7ea0d8d3ff..594658087b4a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > @@ -277,12 +277,16 @@ struct dpll_info {
> > enum intel_display_power_domain power_domain;
> >
> > #define INTEL_DPLL_ALWAYS_ON (1 << 0)
> > +#define INTEL_DPLL_HAS_ALT_PORT_DPLL (1 << 1)
> > /**
> > * @flags:
> > *
> > * INTEL_DPLL_ALWAYS_ON
> > * Inform the state checker that the DPLL is kept enabled even if
> > * not in use by any CRTC.
> > + * INTEL_DPLL_HAS_ALT_PORT_DPLL
> > + * Inform the state checker that the CRTC will have two port DPLLs
> > + * referenced simultanously (for TC->TBT fallback).
> > */
> > u32 flags;
> > };
> > --
> > 2.41.0
> >
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 4/5] drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLs
2023-12-07 15:24 ` Ville Syrjälä
@ 2023-12-07 15:47 ` Imre Deak
2023-12-07 16:06 ` Ville Syrjälä
0 siblings, 1 reply; 18+ messages in thread
From: Imre Deak @ 2023-12-07 15:47 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Dec 07, 2023 at 05:24:44PM +0200, Ville Syrjälä wrote:
> On Thu, Dec 07, 2023 at 04:55:02PM +0200, Imre Deak wrote:
> > On Fri, Nov 24, 2023 at 10:27:34AM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > TC ports have both the MG/TC and TBT PLLs selected simultanously (so
> > > that we can switch from MG/TC to TBT as a fallback). This doesn't play
> > > well with the state checker that assumes that the old PLL shouldn't
> > > have the pipe in its pipe_mask anymore. Suppress that check for these
> > > PLLs to avoid spurious WARNs when you disconnect a TC port and a
> > > non-disabling modeset happens before actually disabling the port.
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Looks ok to me:
> > Reviewed-by: Imre Deak <imre.deak@intel.com>
> >
> > I suppose the check would be still valid for MG PLLs, but the port
> > PLL stuff makes doing that cumbersome.
>
> You mean for legacy ports?
Yes, I suppose in that case too, but in general the state check doesn't
work only if the shared_dpll in either the the old or new crtc state is
the TBT PLL and in the other state it's MG PLL. If the PLL in both
states are MG PLL the state check would be still valid, if I didn't miss
something.
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 56 +++++++++++++------
> > > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++
> > > 2 files changed, 42 insertions(+), 18 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > index d86b02de2923..5c6c4fc50b1d 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > @@ -4023,11 +4023,16 @@ static const struct intel_shared_dpll_funcs mg_pll_funcs = {
> > > static const struct dpll_info icl_plls[] = {
> > > { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> > > { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> > > - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
> > > - { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> > > - { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> > > - { .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> > > - { .name = "MG PLL 4", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
> > > + { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
> > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > + { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
> > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > + { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
> > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > + { .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
> > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > + { .name = "MG PLL 4", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
> > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > {}
> > > };
> > >
> > > @@ -4068,13 +4073,20 @@ static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
> > > static const struct dpll_info tgl_plls[] = {
> > > { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> > > { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> > > - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
> > > - { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> > > - { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> > > - { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> > > - { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
> > > - { .name = "TC PLL 5", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL5, },
> > > - { .name = "TC PLL 6", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL6, },
> > > + { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
> > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > + { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
> > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > + { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
> > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > + { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
> > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > + { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
> > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > + { .name = "TC PLL 5", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL5,
> > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > + { .name = "TC PLL 6", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL6,
> > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > {}
> > > };
> > >
> > > @@ -4141,11 +4153,16 @@ static const struct intel_dpll_mgr adls_pll_mgr = {
> > > static const struct dpll_info adlp_plls[] = {
> > > { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> > > { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> > > - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
> > > - { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> > > - { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> > > - { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> > > - { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
> > > + { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
> > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > + { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
> > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > + { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
> > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > + { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
> > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > + { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
> > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > {}
> > > };
> > >
> > > @@ -4535,7 +4552,10 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> > > I915_STATE_WARN(i915, pll->active_mask & pipe_mask,
> > > "%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
> > > pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
> > > - I915_STATE_WARN(i915, pll->state.pipe_mask & pipe_mask,
> > > +
> > > + /* TC ports have both MG/TC and TBT PLL referenced simultaneously */
> > > + I915_STATE_WARN(i915, !(pll->info->flags & INTEL_DPLL_HAS_ALT_PORT_DPLL) &&
> > > + pll->state.pipe_mask & pipe_mask,
> > > "%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
> > > pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
> > > }
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > index 2e7ea0d8d3ff..594658087b4a 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > @@ -277,12 +277,16 @@ struct dpll_info {
> > > enum intel_display_power_domain power_domain;
> > >
> > > #define INTEL_DPLL_ALWAYS_ON (1 << 0)
> > > +#define INTEL_DPLL_HAS_ALT_PORT_DPLL (1 << 1)
> > > /**
> > > * @flags:
> > > *
> > > * INTEL_DPLL_ALWAYS_ON
> > > * Inform the state checker that the DPLL is kept enabled even if
> > > * not in use by any CRTC.
> > > + * INTEL_DPLL_HAS_ALT_PORT_DPLL
> > > + * Inform the state checker that the CRTC will have two port DPLLs
> > > + * referenced simultanously (for TC->TBT fallback).
> > > */
> > > u32 flags;
> > > };
> > > --
> > > 2.41.0
> > >
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 4/5] drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLs
2023-12-07 15:47 ` Imre Deak
@ 2023-12-07 16:06 ` Ville Syrjälä
2023-12-07 16:15 ` Imre Deak
0 siblings, 1 reply; 18+ messages in thread
From: Ville Syrjälä @ 2023-12-07 16:06 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Dec 07, 2023 at 05:47:02PM +0200, Imre Deak wrote:
> On Thu, Dec 07, 2023 at 05:24:44PM +0200, Ville Syrjälä wrote:
> > On Thu, Dec 07, 2023 at 04:55:02PM +0200, Imre Deak wrote:
> > > On Fri, Nov 24, 2023 at 10:27:34AM +0200, Ville Syrjala wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > >
> > > > TC ports have both the MG/TC and TBT PLLs selected simultanously (so
> > > > that we can switch from MG/TC to TBT as a fallback). This doesn't play
> > > > well with the state checker that assumes that the old PLL shouldn't
> > > > have the pipe in its pipe_mask anymore. Suppress that check for these
> > > > PLLs to avoid spurious WARNs when you disconnect a TC port and a
> > > > non-disabling modeset happens before actually disabling the port.
> > > >
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Looks ok to me:
> > > Reviewed-by: Imre Deak <imre.deak@intel.com>
> > >
> > > I suppose the check would be still valid for MG PLLs, but the port
> > > PLL stuff makes doing that cumbersome.
> >
> > You mean for legacy ports?
>
> Yes, I suppose in that case too, but in general the state check doesn't
> work only if the shared_dpll in either the the old or new crtc state is
> the TBT PLL and in the other state it's MG PLL. If the PLL in both
> states are MG PLL the state check would be still valid, if I didn't miss
> something.
Oh you mean switching from one MG PLL to another MG PLL?
Yeah, that in theory we'd still want to check.
Hmm. Maybe if we flag only the TBT PLL as special and
then skip the assert only when either the old or new PLL
is the TBT PLL?
>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 56 +++++++++++++------
> > > > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++
> > > > 2 files changed, 42 insertions(+), 18 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > > index d86b02de2923..5c6c4fc50b1d 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > > @@ -4023,11 +4023,16 @@ static const struct intel_shared_dpll_funcs mg_pll_funcs = {
> > > > static const struct dpll_info icl_plls[] = {
> > > > { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> > > > { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> > > > - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
> > > > - { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> > > > - { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> > > > - { .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> > > > - { .name = "MG PLL 4", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
> > > > + { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
> > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > + { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
> > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > + { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
> > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > + { .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
> > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > + { .name = "MG PLL 4", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
> > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > {}
> > > > };
> > > >
> > > > @@ -4068,13 +4073,20 @@ static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
> > > > static const struct dpll_info tgl_plls[] = {
> > > > { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> > > > { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> > > > - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
> > > > - { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> > > > - { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> > > > - { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> > > > - { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
> > > > - { .name = "TC PLL 5", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL5, },
> > > > - { .name = "TC PLL 6", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL6, },
> > > > + { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
> > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > + { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
> > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > + { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
> > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > + { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
> > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > + { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
> > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > + { .name = "TC PLL 5", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL5,
> > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > + { .name = "TC PLL 6", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL6,
> > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > {}
> > > > };
> > > >
> > > > @@ -4141,11 +4153,16 @@ static const struct intel_dpll_mgr adls_pll_mgr = {
> > > > static const struct dpll_info adlp_plls[] = {
> > > > { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> > > > { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> > > > - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
> > > > - { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> > > > - { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> > > > - { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> > > > - { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
> > > > + { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
> > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > + { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
> > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > + { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
> > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > + { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
> > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > + { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
> > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > {}
> > > > };
> > > >
> > > > @@ -4535,7 +4552,10 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> > > > I915_STATE_WARN(i915, pll->active_mask & pipe_mask,
> > > > "%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
> > > > pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
> > > > - I915_STATE_WARN(i915, pll->state.pipe_mask & pipe_mask,
> > > > +
> > > > + /* TC ports have both MG/TC and TBT PLL referenced simultaneously */
> > > > + I915_STATE_WARN(i915, !(pll->info->flags & INTEL_DPLL_HAS_ALT_PORT_DPLL) &&
> > > > + pll->state.pipe_mask & pipe_mask,
> > > > "%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
> > > > pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
> > > > }
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > index 2e7ea0d8d3ff..594658087b4a 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > @@ -277,12 +277,16 @@ struct dpll_info {
> > > > enum intel_display_power_domain power_domain;
> > > >
> > > > #define INTEL_DPLL_ALWAYS_ON (1 << 0)
> > > > +#define INTEL_DPLL_HAS_ALT_PORT_DPLL (1 << 1)
> > > > /**
> > > > * @flags:
> > > > *
> > > > * INTEL_DPLL_ALWAYS_ON
> > > > * Inform the state checker that the DPLL is kept enabled even if
> > > > * not in use by any CRTC.
> > > > + * INTEL_DPLL_HAS_ALT_PORT_DPLL
> > > > + * Inform the state checker that the CRTC will have two port DPLLs
> > > > + * referenced simultanously (for TC->TBT fallback).
> > > > */
> > > > u32 flags;
> > > > };
> > > > --
> > > > 2.41.0
> > > >
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 4/5] drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLs
2023-12-07 16:06 ` Ville Syrjälä
@ 2023-12-07 16:15 ` Imre Deak
0 siblings, 0 replies; 18+ messages in thread
From: Imre Deak @ 2023-12-07 16:15 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Dec 07, 2023 at 06:06:38PM +0200, Ville Syrjälä wrote:
> On Thu, Dec 07, 2023 at 05:47:02PM +0200, Imre Deak wrote:
> > On Thu, Dec 07, 2023 at 05:24:44PM +0200, Ville Syrjälä wrote:
> > > On Thu, Dec 07, 2023 at 04:55:02PM +0200, Imre Deak wrote:
> > > > On Fri, Nov 24, 2023 at 10:27:34AM +0200, Ville Syrjala wrote:
> > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > >
> > > > > TC ports have both the MG/TC and TBT PLLs selected simultanously (so
> > > > > that we can switch from MG/TC to TBT as a fallback). This doesn't play
> > > > > well with the state checker that assumes that the old PLL shouldn't
> > > > > have the pipe in its pipe_mask anymore. Suppress that check for these
> > > > > PLLs to avoid spurious WARNs when you disconnect a TC port and a
> > > > > non-disabling modeset happens before actually disabling the port.
> > > > >
> > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > >
> > > > Looks ok to me:
> > > > Reviewed-by: Imre Deak <imre.deak@intel.com>
> > > >
> > > > I suppose the check would be still valid for MG PLLs, but the port
> > > > PLL stuff makes doing that cumbersome.
> > >
> > > You mean for legacy ports?
> >
> > Yes, I suppose in that case too, but in general the state check doesn't
> > work only if the shared_dpll in either the the old or new crtc state is
> > the TBT PLL and in the other state it's MG PLL. If the PLL in both
> > states are MG PLL the state check would be still valid, if I didn't miss
> > something.
>
> Oh you mean switching from one MG PLL to another MG PLL?
> Yeah, that in theory we'd still want to check.
>
> Hmm. Maybe if we flag only the TBT PLL as special and
> then skip the assert only when either the old or new PLL
> is the TBT PLL?
Yes, I guess that would work.
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 56 +++++++++++++------
> > > > > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++
> > > > > 2 files changed, 42 insertions(+), 18 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > > > index d86b02de2923..5c6c4fc50b1d 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > > > @@ -4023,11 +4023,16 @@ static const struct intel_shared_dpll_funcs mg_pll_funcs = {
> > > > > static const struct dpll_info icl_plls[] = {
> > > > > { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> > > > > { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> > > > > - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
> > > > > - { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> > > > > - { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> > > > > - { .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> > > > > - { .name = "MG PLL 4", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
> > > > > + { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
> > > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > > + { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
> > > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > > + { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
> > > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > > + { .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
> > > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > > + { .name = "MG PLL 4", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
> > > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > > {}
> > > > > };
> > > > >
> > > > > @@ -4068,13 +4073,20 @@ static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
> > > > > static const struct dpll_info tgl_plls[] = {
> > > > > { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> > > > > { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> > > > > - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
> > > > > - { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> > > > > - { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> > > > > - { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> > > > > - { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
> > > > > - { .name = "TC PLL 5", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL5, },
> > > > > - { .name = "TC PLL 6", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL6, },
> > > > > + { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
> > > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > > + { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
> > > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > > + { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
> > > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > > + { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
> > > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > > + { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
> > > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > > + { .name = "TC PLL 5", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL5,
> > > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > > + { .name = "TC PLL 6", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL6,
> > > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > > {}
> > > > > };
> > > > >
> > > > > @@ -4141,11 +4153,16 @@ static const struct intel_dpll_mgr adls_pll_mgr = {
> > > > > static const struct dpll_info adlp_plls[] = {
> > > > > { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> > > > > { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> > > > > - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, },
> > > > > - { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> > > > > - { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> > > > > - { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> > > > > - { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
> > > > > + { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
> > > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > > + { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
> > > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > > + { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
> > > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > > + { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
> > > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > > + { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
> > > > > + .flags = INTEL_DPLL_HAS_ALT_PORT_DPLL, },
> > > > > {}
> > > > > };
> > > > >
> > > > > @@ -4535,7 +4552,10 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> > > > > I915_STATE_WARN(i915, pll->active_mask & pipe_mask,
> > > > > "%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
> > > > > pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
> > > > > - I915_STATE_WARN(i915, pll->state.pipe_mask & pipe_mask,
> > > > > +
> > > > > + /* TC ports have both MG/TC and TBT PLL referenced simultaneously */
> > > > > + I915_STATE_WARN(i915, !(pll->info->flags & INTEL_DPLL_HAS_ALT_PORT_DPLL) &&
> > > > > + pll->state.pipe_mask & pipe_mask,
> > > > > "%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
> > > > > pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
> > > > > }
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > index 2e7ea0d8d3ff..594658087b4a 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > @@ -277,12 +277,16 @@ struct dpll_info {
> > > > > enum intel_display_power_domain power_domain;
> > > > >
> > > > > #define INTEL_DPLL_ALWAYS_ON (1 << 0)
> > > > > +#define INTEL_DPLL_HAS_ALT_PORT_DPLL (1 << 1)
> > > > > /**
> > > > > * @flags:
> > > > > *
> > > > > * INTEL_DPLL_ALWAYS_ON
> > > > > * Inform the state checker that the DPLL is kept enabled even if
> > > > > * not in use by any CRTC.
> > > > > + * INTEL_DPLL_HAS_ALT_PORT_DPLL
> > > > > + * Inform the state checker that the CRTC will have two port DPLLs
> > > > > + * referenced simultanously (for TC->TBT fallback).
> > > > > */
> > > > > u32 flags;
> > > > > };
> > > > > --
> > > > > 2.41.0
> > > > >
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2023-12-07 16:15 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-11-24 8:27 [Intel-gfx] [PATCH 1/5] drm/i915/psr: Include some basic PSR information in the state dump Ville Syrjala
2023-11-24 8:27 ` [Intel-gfx] [PATCH 2/5] drm/i915: Replace a memset() with zero initialization Ville Syrjala
2023-11-29 14:50 ` Kahola, Mika
2023-11-24 8:27 ` [Intel-gfx] [PATCH 3/5] drm/i915: Include the PLL name in the debug messages Ville Syrjala
2023-11-24 8:27 ` [Intel-gfx] [PATCH 4/5] drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLs Ville Syrjala
2023-12-07 14:05 ` Ville Syrjälä
2023-12-07 14:55 ` [Intel-gfx] " Imre Deak
2023-12-07 15:24 ` Ville Syrjälä
2023-12-07 15:47 ` Imre Deak
2023-12-07 16:06 ` Ville Syrjälä
2023-12-07 16:15 ` Imre Deak
2023-11-24 8:27 ` [Intel-gfx] [PATCH 5/5] drm/i915: Convert PLL flags to booleans Ville Syrjala
2023-11-24 8:35 ` [Intel-gfx] [PATCH 1/5] drm/i915/psr: Include some basic PSR information in the state dump Hogander, Jouni
2023-11-24 16:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] " Patchwork
2023-11-24 16:46 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-11-28 22:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915/psr: Include some basic PSR information in the state dump (rev2) Patchwork
2023-11-28 22:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-11-29 4:34 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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