* [Intel-gfx] [PATCH] drm/i915/display: Use unions per platform in intel_dpll_hw_state
@ 2022-02-22 14:20 José Roberto de Souza
2022-02-22 23:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: José Roberto de Souza @ 2022-02-22 14:20 UTC (permalink / raw)
To: intel-gfx
This will save us a few bytes in intel_dpll_hw_state struct now
and guarantee that it will not keep growing with each new platform.
Cc: Imre Deak <imre.deak@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 71 ++++++-----
.../drm/i915/display/intel_display_debugfs.c | 63 +++++-----
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 77 ++++++------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 114 +++++++++++-------
4 files changed, 180 insertions(+), 145 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e2ca70696c058..4cea1fc14bd44 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6303,38 +6303,45 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
if (dev_priv->dpll.mgr) {
PIPE_CONF_CHECK_P(shared_dpll);
- PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
- PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
- PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
- PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
- PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
- PIPE_CONF_CHECK_X(dpll_hw_state.spll);
- PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
- PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
- PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
- PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
- PIPE_CONF_CHECK_X(dpll_hw_state.div0);
- PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
- PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
- PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
+ if (DISPLAY_VER(dev_priv) >= 11) {
+ PIPE_CONF_CHECK_X(dpll_hw_state.icl_cfgcr0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.icl_cfgcr1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.icl_div0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
+ } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
+ PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
+ } else if (DISPLAY_VER(dev_priv) == 9) {
+ PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
+ } else if (HAS_DDI(dev_priv)) {
+ PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
+ PIPE_CONF_CHECK_X(dpll_hw_state.spll);
+ } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
+ PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
+ PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
+ PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
+ }
}
PIPE_CONF_CHECK_X(dsi_pll.ctrl);
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 695aa6efe8c1b..d5d68b8901c4b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1006,35 +1006,40 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
seq_printf(m, " pipe_mask: 0x%x, active: 0x%x, on: %s\n",
pll->state.pipe_mask, pll->active_mask, yesno(pll->on));
seq_printf(m, " tracked hardware state:\n");
- seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll);
- seq_printf(m, " dpll_md: 0x%08x\n",
- pll->state.hw_state.dpll_md);
- seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0);
- seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1);
- seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll);
- seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0);
- seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1);
- seq_printf(m, " div0: 0x%08x\n", pll->state.hw_state.div0);
- seq_printf(m, " mg_refclkin_ctl: 0x%08x\n",
- pll->state.hw_state.mg_refclkin_ctl);
- seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n",
- pll->state.hw_state.mg_clktop2_coreclkctl1);
- seq_printf(m, " mg_clktop2_hsclkctl: 0x%08x\n",
- pll->state.hw_state.mg_clktop2_hsclkctl);
- seq_printf(m, " mg_pll_div0: 0x%08x\n",
- pll->state.hw_state.mg_pll_div0);
- seq_printf(m, " mg_pll_div1: 0x%08x\n",
- pll->state.hw_state.mg_pll_div1);
- seq_printf(m, " mg_pll_lf: 0x%08x\n",
- pll->state.hw_state.mg_pll_lf);
- seq_printf(m, " mg_pll_frac_lock: 0x%08x\n",
- pll->state.hw_state.mg_pll_frac_lock);
- seq_printf(m, " mg_pll_ssc: 0x%08x\n",
- pll->state.hw_state.mg_pll_ssc);
- seq_printf(m, " mg_pll_bias: 0x%08x\n",
- pll->state.hw_state.mg_pll_bias);
- seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n",
- pll->state.hw_state.mg_pll_tdc_coldst_bias);
+
+ if (DISPLAY_VER(dev_priv) >= 11) {
+ seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.icl_cfgcr0);
+ seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.icl_cfgcr1);
+ seq_printf(m, " div0: 0x%08x\n", pll->state.hw_state.icl_div0);
+ seq_printf(m, " mg_refclkin_ctl: 0x%08x\n",
+ pll->state.hw_state.mg_refclkin_ctl);
+ seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n",
+ pll->state.hw_state.mg_clktop2_coreclkctl1);
+ seq_printf(m, " mg_clktop2_hsclkctl: 0x%08x\n",
+ pll->state.hw_state.mg_clktop2_hsclkctl);
+ seq_printf(m, " mg_pll_div0: 0x%08x\n",
+ pll->state.hw_state.mg_pll_div0);
+ seq_printf(m, " mg_pll_div1: 0x%08x\n",
+ pll->state.hw_state.mg_pll_div1);
+ seq_printf(m, " mg_pll_lf: 0x%08x\n",
+ pll->state.hw_state.mg_pll_lf);
+ seq_printf(m, " mg_pll_frac_lock: 0x%08x\n",
+ pll->state.hw_state.mg_pll_frac_lock);
+ seq_printf(m, " mg_pll_ssc: 0x%08x\n",
+ pll->state.hw_state.mg_pll_ssc);
+ seq_printf(m, " mg_pll_bias: 0x%08x\n",
+ pll->state.hw_state.mg_pll_bias);
+ seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n",
+ pll->state.hw_state.mg_pll_tdc_coldst_bias);
+ } else if (HAS_DDI(dev_priv)) {
+ seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll);
+ seq_printf(m, " spll: 0x%08x\n", pll->state.hw_state.spll);
+ } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
+ seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll);
+ seq_printf(m, " dpll_md: 0x%08x\n", pll->state.hw_state.dpll_md);
+ seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0);
+ seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1);
+ }
}
drm_modeset_unlock_all(dev);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 569903d47aea5..8c38ebedb75f7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2708,10 +2708,10 @@ static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
break;
}
- dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
+ dco_freq = (pll_state->icl_cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
ref_clock;
- dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
+ dco_fraction = (pll_state->icl_cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
DPLL_CFGCR0_DCO_FRACTION_SHIFT;
if (ehl_combo_pll_div_frac_wa_needed(i915))
@@ -2736,21 +2736,22 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
if (ehl_combo_pll_div_frac_wa_needed(i915))
dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
- pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
- pll_params->dco_integer;
+ pll_state->icl_cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
+ pll_params->dco_integer;
- pll_state->cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio) |
- DPLL_CFGCR1_QDIV_MODE(pll_params->qdiv_mode) |
- DPLL_CFGCR1_KDIV(pll_params->kdiv) |
- DPLL_CFGCR1_PDIV(pll_params->pdiv);
+ pll_state->icl_cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio) |
+ DPLL_CFGCR1_QDIV_MODE(pll_params->qdiv_mode) |
+ DPLL_CFGCR1_KDIV(pll_params->kdiv) |
+ DPLL_CFGCR1_PDIV(pll_params->pdiv);
if (DISPLAY_VER(i915) >= 12)
- pll_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
+ pll_state->icl_cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
else
- pll_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
+ pll_state->icl_cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
if (i915->vbt.override_afc_startup)
- pll_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->vbt.override_afc_startup_val);
+ pll_state->icl_div0 =
+ TGL_DPLL0_DIV0_AFC_STARTUP(i915->vbt.override_afc_startup_val);
}
static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
@@ -3506,36 +3507,36 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
goto out;
if (IS_ALDERLAKE_S(dev_priv)) {
- hw_state->cfgcr0 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR0(id));
- hw_state->cfgcr1 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR1(id));
+ hw_state->icl_cfgcr0 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR0(id));
+ hw_state->icl_cfgcr1 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR1(id));
} else if (IS_DG1(dev_priv)) {
- hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id));
- hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id));
+ hw_state->icl_cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id));
+ hw_state->icl_cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id));
} else if (IS_ROCKETLAKE(dev_priv)) {
- hw_state->cfgcr0 = intel_de_read(dev_priv,
- RKL_DPLL_CFGCR0(id));
- hw_state->cfgcr1 = intel_de_read(dev_priv,
- RKL_DPLL_CFGCR1(id));
+ hw_state->icl_cfgcr0 = intel_de_read(dev_priv,
+ RKL_DPLL_CFGCR0(id));
+ hw_state->icl_cfgcr1 = intel_de_read(dev_priv,
+ RKL_DPLL_CFGCR1(id));
} else if (DISPLAY_VER(dev_priv) >= 12) {
- hw_state->cfgcr0 = intel_de_read(dev_priv,
- TGL_DPLL_CFGCR0(id));
- hw_state->cfgcr1 = intel_de_read(dev_priv,
- TGL_DPLL_CFGCR1(id));
+ hw_state->icl_cfgcr0 = intel_de_read(dev_priv,
+ TGL_DPLL_CFGCR0(id));
+ hw_state->icl_cfgcr1 = intel_de_read(dev_priv,
+ TGL_DPLL_CFGCR1(id));
if (dev_priv->vbt.override_afc_startup) {
- hw_state->div0 = intel_de_read(dev_priv, TGL_DPLL0_DIV0(id));
- hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK;
+ hw_state->icl_div0 = intel_de_read(dev_priv, TGL_DPLL0_DIV0(id));
+ hw_state->icl_div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK;
}
} else {
if (IS_JSL_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
- hw_state->cfgcr0 = intel_de_read(dev_priv,
- ICL_DPLL_CFGCR0(4));
- hw_state->cfgcr1 = intel_de_read(dev_priv,
- ICL_DPLL_CFGCR1(4));
+ hw_state->icl_cfgcr0 = intel_de_read(dev_priv,
+ ICL_DPLL_CFGCR0(4));
+ hw_state->icl_cfgcr1 = intel_de_read(dev_priv,
+ ICL_DPLL_CFGCR1(4));
} else {
- hw_state->cfgcr0 = intel_de_read(dev_priv,
- ICL_DPLL_CFGCR0(id));
- hw_state->cfgcr1 = intel_de_read(dev_priv,
- ICL_DPLL_CFGCR1(id));
+ hw_state->icl_cfgcr0 = intel_de_read(dev_priv,
+ ICL_DPLL_CFGCR0(id));
+ hw_state->icl_cfgcr1 = intel_de_read(dev_priv,
+ ICL_DPLL_CFGCR1(id));
}
}
@@ -3591,14 +3592,14 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
}
}
- intel_de_write(dev_priv, cfgcr0_reg, hw_state->cfgcr0);
- intel_de_write(dev_priv, cfgcr1_reg, hw_state->cfgcr1);
+ intel_de_write(dev_priv, cfgcr0_reg, hw_state->icl_cfgcr0);
+ intel_de_write(dev_priv, cfgcr1_reg, hw_state->icl_cfgcr1);
drm_WARN_ON_ONCE(&dev_priv->drm, dev_priv->vbt.override_afc_startup &&
!i915_mmio_reg_valid(div0_reg));
if (dev_priv->vbt.override_afc_startup &&
i915_mmio_reg_valid(div0_reg))
intel_de_rmw(dev_priv, div0_reg, TGL_DPLL0_DIV0_AFC_STARTUP_MASK,
- hw_state->div0);
+ hw_state->icl_div0);
intel_de_posting_read(dev_priv, cfgcr1_reg);
}
@@ -3935,8 +3936,8 @@ static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
"mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, "
"mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
"mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n",
- hw_state->cfgcr0, hw_state->cfgcr1,
- hw_state->div0,
+ hw_state->icl_cfgcr0, hw_state->cfgcr1,
+ hw_state->icl_div0,
hw_state->mg_refclkin_ctl,
hw_state->mg_clktop2_coreclkctl1,
hw_state->mg_clktop2_hsclkctl,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index ba2fdfce15792..4360e1c9266d8 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -184,52 +184,74 @@ enum icl_port_dpll_id {
};
struct intel_dpll_hw_state {
- /* i9xx, pch plls */
- u32 dpll;
- u32 dpll_md;
- u32 fp0;
- u32 fp1;
-
- /* hsw, bdw */
- u32 wrpll;
- u32 spll;
-
- /* skl */
- /*
- * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
- * lower part of ctrl1 and they get shifted into position when writing
- * the register. This allows us to easily compare the state to share
- * the DPLL.
- */
- u32 ctrl1;
- /* HDMI only, 0 when used for DP */
- u32 cfgcr1, cfgcr2;
-
- /* icl */
- u32 cfgcr0;
-
- /* tgl */
- u32 div0;
-
- /* bxt */
- u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;
-
- /*
- * ICL uses the following, already defined:
- * u32 cfgcr0, cfgcr1;
- */
- u32 mg_refclkin_ctl;
- u32 mg_clktop2_coreclkctl1;
- u32 mg_clktop2_hsclkctl;
- u32 mg_pll_div0;
- u32 mg_pll_div1;
- u32 mg_pll_lf;
- u32 mg_pll_frac_lock;
- u32 mg_pll_ssc;
- u32 mg_pll_bias;
- u32 mg_pll_tdc_coldst_bias;
- u32 mg_pll_bias_mask;
- u32 mg_pll_tdc_coldst_bias_mask;
+ union {
+ /* icl+ combo */
+ struct {
+ u32 icl_cfgcr0;
+ u32 icl_cfgcr1;
+ u32 icl_div0;
+ };
+
+ /* icl+ TC */
+ struct {
+ u32 mg_refclkin_ctl;
+ u32 mg_clktop2_coreclkctl1;
+ u32 mg_clktop2_hsclkctl;
+ u32 mg_pll_div0;
+ u32 mg_pll_div1;
+ u32 mg_pll_lf;
+ u32 mg_pll_frac_lock;
+ u32 mg_pll_ssc;
+ u32 mg_pll_bias;
+ u32 mg_pll_tdc_coldst_bias;
+ u32 mg_pll_bias_mask;
+ u32 mg_pll_tdc_coldst_bias_mask;
+ };
+
+ /* bxt */
+ struct {
+ /* bxt */
+ u32 ebb0;
+ u32 ebb4;
+ u32 pll0;
+ u32 pll1;
+ u32 pll2;
+ u32 pll3;
+ u32 pll6;
+ u32 pll8;
+ u32 pll9;
+ u32 pll10;
+ u32 pcsdw12;
+ };
+
+ /* skl */
+ struct {
+ /*
+ * DPLL_CTRL1 has 6 bits for each this DPLL. We store those in
+ * lower part of ctrl1 and they get shifted into position when writing
+ * the register. This allows us to easily compare the state to share
+ * the DPLL.
+ */
+ u32 ctrl1;
+ u32 cfgcr1;
+ /* HDMI only, 0 when used for DP */
+ u32 cfgcr2;
+ };
+
+ /* hsw, bdw */
+ struct {
+ u32 wrpll;
+ u32 spll;
+ };
+
+ /* i9xx, pch plls */
+ struct {
+ u32 dpll;
+ u32 dpll_md;
+ u32 fp0;
+ u32 fp1;
+ };
+ };
};
/**
--
2.35.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: Use unions per platform in intel_dpll_hw_state
2022-02-22 14:20 [Intel-gfx] [PATCH] drm/i915/display: Use unions per platform in intel_dpll_hw_state José Roberto de Souza
@ 2022-02-22 23:08 ` Patchwork
2022-02-22 23:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2022-02-22 23:08 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/display: Use unions per platform in intel_dpll_hw_state
URL : https://patchwork.freedesktop.org/series/100577/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Use unions per platform in intel_dpll_hw_state
2022-02-22 14:20 [Intel-gfx] [PATCH] drm/i915/display: Use unions per platform in intel_dpll_hw_state José Roberto de Souza
2022-02-22 23:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
@ 2022-02-22 23:37 ` Patchwork
2022-02-23 12:23 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-02-23 19:58 ` [Intel-gfx] [PATCH] " Imre Deak
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2022-02-22 23:37 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 2160 bytes --]
== Series Details ==
Series: drm/i915/display: Use unions per platform in intel_dpll_hw_state
URL : https://patchwork.freedesktop.org/series/100577/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11268 -> Patchwork_22355
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/index.html
Participating hosts (18 -> 17)
------------------------------
Additional (1): fi-pnv-d510
Missing (2): fi-icl-u2 shard-tglu
Known issues
------------
Here are the changes found in Patchwork_22355 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510: NOTRUN -> [SKIP][1] ([fdo#109271]) +57 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/fi-pnv-d510/igt@prime_vgem@basic-userptr.html
#### Warnings ####
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][2] ([i915#4957]) -> [DMESG-FAIL][3] ([i915#4494] / [i915#4957])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
Build changes
-------------
* Linux: CI_DRM_11268 -> Patchwork_22355
CI-20190529: 20190529
CI_DRM_11268: 26326bf05392ab3da8cba36642a0efec97f00da9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6352: 11b4d227d8f0efad522519c8fd9525774247c8d8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22355: 8464317cead47363a0995d4314a885bb007f99e8 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8464317cead4 drm/i915/display: Use unions per platform in intel_dpll_hw_state
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/index.html
[-- Attachment #2: Type: text/html, Size: 2846 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Use unions per platform in intel_dpll_hw_state
2022-02-22 14:20 [Intel-gfx] [PATCH] drm/i915/display: Use unions per platform in intel_dpll_hw_state José Roberto de Souza
2022-02-22 23:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
2022-02-22 23:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-02-23 12:23 ` Patchwork
2022-02-23 19:58 ` [Intel-gfx] [PATCH] " Imre Deak
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2022-02-23 12:23 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30288 bytes --]
== Series Details ==
Series: drm/i915/display: Use unions per platform in intel_dpll_hw_state
URL : https://patchwork.freedesktop.org/series/100577/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11268_full -> Patchwork_22355_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22355_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22355_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22355_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@system-suspend:
- {shard-tglu}: [PASS][1] -> [SKIP][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-tglu-8/igt@i915_pm_rpm@system-suspend.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglu-5/igt@i915_pm_rpm@system-suspend.html
* igt@perf_pmu@semaphore-busy:
- {shard-tglu}: NOTRUN -> [SKIP][3] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglu-5/igt@perf_pmu@semaphore-busy.html
### Piglit changes ###
#### Possible regressions ####
* spec@glsl-4.20@execution@vs_in@vs-input-position-float_mat3-double_dmat2_array2:
- pig-skl-6260u: NOTRUN -> [INCOMPLETE][4] +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/pig-skl-6260u/spec@glsl-4.20@execution@vs_in@vs-input-position-float_mat3-double_dmat2_array2.html
Known issues
------------
Here are the changes found in Patchwork_22355_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-iclb: [PASS][7] -> [FAIL][8] ([i915#2842])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-iclb7/igt@gem_exec_fair@basic-pace@bcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb4/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][9] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_params@no-blt:
- shard-tglb: NOTRUN -> [SKIP][10] ([fdo#109283])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglb6/igt@gem_exec_params@no-blt.html
- shard-iclb: NOTRUN -> [SKIP][11] ([fdo#109283])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb2/igt@gem_exec_params@no-blt.html
* igt@gem_lmem_swapping@basic:
- shard-iclb: NOTRUN -> [SKIP][12] ([i915#4613])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb2/igt@gem_lmem_swapping@basic.html
- shard-tglb: NOTRUN -> [SKIP][13] ([i915#4613])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglb6/igt@gem_lmem_swapping@basic.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-tglb: NOTRUN -> [SKIP][14] ([i915#4270])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglb6/igt@gem_pxp@regular-baseline-src-copy-readible.html
- shard-iclb: NOTRUN -> [SKIP][15] ([i915#4270])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb2/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_render_copy@linear-to-vebox-yf-tiled:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#768]) +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb1/igt@gem_render_copy@linear-to-vebox-yf-tiled.html
* igt@gem_userptr_blits@unsync-unmap:
- shard-iclb: NOTRUN -> [SKIP][17] ([i915#3297])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb2/igt@gem_userptr_blits@unsync-unmap.html
- shard-tglb: NOTRUN -> [SKIP][18] ([i915#3297])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglb6/igt@gem_userptr_blits@unsync-unmap.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [PASS][19] -> [DMESG-WARN][20] ([i915#1436] / [i915#716])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-glk8/igt@gen9_exec_parse@allowed-all.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-glk7/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@valid-registers:
- shard-iclb: NOTRUN -> [SKIP][21] ([i915#2856])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb2/igt@gen9_exec_parse@valid-registers.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-tglb: [PASS][22] -> [DMESG-WARN][23] ([i915#2867])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-tglb3/igt@i915_module_load@reload-with-fault-injection.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglb6/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_lpsp@screens-disabled:
- shard-tglb: NOTRUN -> [SKIP][24] ([i915#1902])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglb2/igt@i915_pm_lpsp@screens-disabled.html
* igt@kms_big_fb@linear-32bpp-rotate-0:
- shard-glk: [PASS][25] -> [DMESG-WARN][26] ([i915#118]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-glk5/igt@kms_big_fb@linear-32bpp-rotate-0.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-glk1/igt@kms_big_fb@linear-32bpp-rotate-0.html
* igt@kms_big_fb@linear-64bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][27] ([fdo#111614])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglb2/igt@kms_big_fb@linear-64bpp-rotate-90.html
* igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][28] ([i915#3689]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglb6/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][29] ([fdo#109278] / [i915#3886]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb1/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][30] ([i915#3689] / [i915#3886]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglb2/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_color_chamelium@pipe-c-gamma:
- shard-iclb: NOTRUN -> [SKIP][31] ([fdo#109284] / [fdo#111827])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb2/igt@kms_color_chamelium@pipe-c-gamma.html
* igt@kms_color_chamelium@pipe-d-degamma:
- shard-tglb: NOTRUN -> [SKIP][32] ([fdo#109284] / [fdo#111827]) +2 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglb2/igt@kms_color_chamelium@pipe-d-degamma.html
- shard-iclb: NOTRUN -> [SKIP][33] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb1/igt@kms_color_chamelium@pipe-d-degamma.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen:
- shard-glk: [PASS][34] -> [FAIL][35] ([i915#3444])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-glk5/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-glk1/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-512x170-onscreen:
- shard-tglb: NOTRUN -> [SKIP][36] ([fdo#109279] / [i915#3359])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglb2/igt@kms_cursor_crc@pipe-c-cursor-512x170-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-256x85-rapid-movement:
- shard-iclb: NOTRUN -> [SKIP][37] ([fdo#109278]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb2/igt@kms_cursor_crc@pipe-d-cursor-256x85-rapid-movement.html
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-tglb: NOTRUN -> [SKIP][38] ([fdo#109274] / [fdo#111825]) +2 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglb2/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_flip@2x-absolute-wf_vblank-interruptible:
- shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109274])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb2/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1:
- shard-glk: [PASS][40] -> [FAIL][41] ([i915#79])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-glk6/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-glk3/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
- shard-tglb: NOTRUN -> [SKIP][42] ([i915#2587])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglb6/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
- shard-iclb: NOTRUN -> [SKIP][43] ([i915#3701])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt:
- shard-tglb: NOTRUN -> [SKIP][44] ([fdo#109280] / [fdo#111825]) +2 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt:
- shard-iclb: NOTRUN -> [SKIP][45] ([fdo#109280]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt.html
* igt@kms_hdr@static-toggle-suspend:
- shard-tglb: NOTRUN -> [SKIP][46] ([i915#1187])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglb6/igt@kms_hdr@static-toggle-suspend.html
- shard-iclb: NOTRUN -> [SKIP][47] ([i915#1187])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb2/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c:
- shard-tglb: NOTRUN -> [SKIP][48] ([fdo#109289])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglb2/igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c.html
- shard-iclb: NOTRUN -> [SKIP][49] ([fdo#109289])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb1/igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c.html
* igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][50] ([fdo#111615])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglb6/igt@kms_plane_multiple@atomic-pipe-a-tiling-yf.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-iclb: [PASS][51] -> [SKIP][52] ([fdo#109642] / [fdo#111068] / [i915#658])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-iclb2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb1/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_primary_render:
- shard-iclb: [PASS][53] -> [SKIP][54] ([fdo#109441])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-iclb2/igt@kms_psr@psr2_primary_render.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb1/igt@kms_psr@psr2_primary_render.html
* igt@kms_vrr@flip-suspend:
- shard-iclb: NOTRUN -> [SKIP][55] ([fdo#109502])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb2/igt@kms_vrr@flip-suspend.html
* igt@nouveau_crc@pipe-b-source-outp-inactive:
- shard-iclb: NOTRUN -> [SKIP][56] ([i915#2530])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb1/igt@nouveau_crc@pipe-b-source-outp-inactive.html
- shard-tglb: NOTRUN -> [SKIP][57] ([i915#2530])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglb2/igt@nouveau_crc@pipe-b-source-outp-inactive.html
* igt@prime_nv_pcopy@test_semaphore:
- shard-tglb: NOTRUN -> [SKIP][58] ([fdo#109291])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglb6/igt@prime_nv_pcopy@test_semaphore.html
- shard-iclb: NOTRUN -> [SKIP][59] ([fdo#109291])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb2/igt@prime_nv_pcopy@test_semaphore.html
#### Possible fixes ####
* igt@fbdev@info:
- {shard-rkl}: [SKIP][60] ([i915#2582]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@fbdev@info.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@fbdev@info.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [FAIL][62] ([i915#232]) -> [PASS][63] +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-tglb3/igt@gem_eio@unwedge-stress.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][64] ([i915#2846]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-glk6/igt@gem_exec_fair@basic-deadline.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-glk2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][66] ([i915#2842]) -> [PASS][67] +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_reloc@basic-scanout@vecs0:
- {shard-rkl}: ([PASS][68], [SKIP][69]) ([i915#3639]) -> [PASS][70] +3 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-6/igt@gem_exec_reloc@basic-scanout@vecs0.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@gem_exec_reloc@basic-scanout@vecs0.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@gem_exec_reloc@basic-scanout@vecs0.html
* igt@i915_pm_rpm@dpms-lpsp:
- {shard-rkl}: [SKIP][71] ([i915#1397]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@i915_pm_rpm@dpms-lpsp.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@i915_pm_rpm@dpms-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- {shard-rkl}: ([SKIP][73], [SKIP][74]) ([i915#1397]) -> [PASS][75]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-1/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@i915_pm_rpm@pm-tiling:
- {shard-rkl}: [SKIP][76] ([fdo#109308]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@i915_pm_rpm@pm-tiling.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@i915_pm_rpm@pm-tiling.html
* igt@i915_pm_rps@reset:
- {shard-rkl}: [FAIL][78] ([i915#4016]) -> [PASS][79] +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@i915_pm_rps@reset.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-1/igt@i915_pm_rps@reset.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- {shard-rkl}: [SKIP][80] ([i915#1845]) -> [PASS][81] +16 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-1/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
- shard-glk: [DMESG-WARN][82] ([i915#118]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-glk9/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-glk9/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
* igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- {shard-rkl}: [SKIP][84] ([i915#1845] / [i915#4098]) -> [PASS][85] +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-1/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_color@pipe-b-ctm-0-5:
- {shard-rkl}: ([SKIP][86], [SKIP][87]) ([i915#1149] / [i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][88]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@kms_color@pipe-b-ctm-0-5.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@kms_color@pipe-b-ctm-0-5.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@kms_color@pipe-b-ctm-0-5.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-random:
- {shard-rkl}: [SKIP][89] ([fdo#112022] / [i915#4070]) -> [PASS][90] +3 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-1/igt@kms_cursor_crc@pipe-b-cursor-256x256-random.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-256x256-random.html
* igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding:
- shard-glk: [FAIL][91] ([i915#1888] / [i915#3444]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-glk8/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-glk7/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html
* igt@kms_cursor_edge_walk@pipe-a-128x128-right-edge:
- {shard-rkl}: [SKIP][93] ([i915#1849] / [i915#4070]) -> [PASS][94] +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-1/igt@kms_cursor_edge_walk@pipe-a-128x128-right-edge.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-a-128x128-right-edge.html
* igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge:
- {shard-rkl}: ([SKIP][95], [SKIP][96]) ([i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][97]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- {shard-rkl}: [SKIP][98] ([fdo#111825] / [i915#4070]) -> [PASS][99] +1 similar issue
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-1/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-iclb: [FAIL][100] ([i915#2346]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb4/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled:
- {shard-rkl}: [SKIP][102] ([fdo#111314]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled.html
* igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled:
- {shard-rkl}: ([SKIP][104], [SKIP][105]) ([fdo#111314] / [i915#4098]) -> [PASS][106]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-1/igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled.html
* igt@kms_draw_crc@draw-method-xrgb2101010-render-ytiled:
- {shard-rkl}: ([PASS][107], [SKIP][108]) ([i915#4098]) -> [PASS][109]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-render-ytiled.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@kms_draw_crc@draw-method-xrgb2101010-render-ytiled.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-render-ytiled.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
- shard-iclb: [SKIP][110] ([i915#3701]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen:
- {shard-rkl}: ([SKIP][112], [SKIP][113]) ([i915#1849] / [i915#4098]) -> [PASS][114] +4 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc:
- {shard-rkl}: [SKIP][115] ([i915#1849]) -> [PASS][116] +10 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
* igt@kms_invalid_mode@bad-htotal:
- {shard-rkl}: ([SKIP][117], [SKIP][118]) ([i915#4278]) -> [PASS][119]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@kms_invalid_mode@bad-htotal.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@kms_invalid_mode@bad-htotal.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@kms_invalid_mode@bad-htotal.html
* igt@kms_plane@plane-position-hole@pipe-b-planes:
- {shard-rkl}: ([SKIP][120], [SKIP][121]) ([i915#1849] / [i915#3558]) -> [PASS][122] +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@kms_plane@plane-position-hole@pipe-b-planes.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@kms_plane@plane-position-hole@pipe-b-planes.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@kms_plane@plane-position-hole@pipe-b-planes.html
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- {shard-rkl}: [SKIP][123] ([i915#1849] / [i915#3558] / [i915#4070]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html
* igt@kms_prime@basic-crc@second-to-first:
- {shard-tglu}: [FAIL][125] ([i915#402]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-tglu-1/igt@kms_prime@basic-crc@second-to-first.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-tglu-8/igt@kms_prime@basic-crc@second-to-first.html
* igt@kms_psr@cursor_plane_onoff:
- {shard-rkl}: [SKIP][127] ([i915#1072]) -> [PASS][128] +2 similar issues
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-1/igt@kms_psr@cursor_plane_onoff.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@kms_psr@cursor_plane_onoff.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: [SKIP][129] ([fdo#109441]) -> [PASS][130] +1 similar issue
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-iclb5/igt@kms_psr@psr2_cursor_plane_onoff.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@kms_universal_plane@cursor-fb-leak-pipe-b:
- {shard-rkl}: ([SKIP][131], [SKIP][132]) ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][133]
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-2/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html
* igt@kms_universal_plane@universal-plane-gen9-features-pipe-b:
- {shard-rkl}: [SKIP][134] ([i915#1845] / [i915#4070]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-1/igt@kms_universal_plane@universal-plane-gen9-features-pipe-b.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@kms_universal_plane@universal-plane-gen9-features-pipe-b.html
* igt@kms_vblank@pipe-a-wait-forked-busy-hang:
- {shard-rkl}: ([PASS][136], [SKIP][137]) ([i915#1845]) -> [PASS][138] +1 similar issue
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-6/igt@kms_vblank@pipe-a-wait-forked-busy-hang.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-rkl-4/igt@kms_vblank@pipe-a-wait-forked-busy-hang.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-rkl-6/igt@kms_vblank@pipe-a-wait-forked-busy-hang.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][139] ([i915#4525]) -> [DMESG-WARN][140] ([i915#5076])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-iclb5/igt@gem_exec_balancer@parallel-out-fence.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb2/igt@gem_exec_balancer@parallel-out-fence.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][141] ([fdo#111068] / [i915#658]) -> [SKIP][142] ([i915#2920])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-iclb1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-iclb: [SKIP][143] ([i915#2920]) -> [SKIP][144] ([fdo#111068] / [i915#658])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11268/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/shard-iclb1/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
### Piglit changes ###
#### Issues hit ####
* spec@glsl-4.20@execution@vs_in@vs-input-float_mat4x2-double_dvec3_array2-position:
- pig-skl-6260u: NOTRUN -> [FAIL][145] ([i915#5167]) +399 similar issues
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/pig-skl-6260u/spec@glsl-4.20@execution@vs_in@vs-input-float_mat4x2-doubl
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22355/index.html
[-- Attachment #2: Type: text/html, Size: 33177 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display: Use unions per platform in intel_dpll_hw_state
2022-02-22 14:20 [Intel-gfx] [PATCH] drm/i915/display: Use unions per platform in intel_dpll_hw_state José Roberto de Souza
` (2 preceding siblings ...)
2022-02-23 12:23 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2022-02-23 19:58 ` Imre Deak
2022-02-23 20:01 ` Souza, Jose
3 siblings, 1 reply; 6+ messages in thread
From: Imre Deak @ 2022-02-23 19:58 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Tue, Feb 22, 2022 at 06:20:45AM -0800, José Roberto de Souza wrote:
[...]
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index ba2fdfce15792..4360e1c9266d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -184,52 +184,74 @@ enum icl_port_dpll_id {
> };
>
> struct intel_dpll_hw_state {
> - /* i9xx, pch plls */
> - u32 dpll;
> - u32 dpll_md;
> - u32 fp0;
> - u32 fp1;
> -
> - /* hsw, bdw */
> - u32 wrpll;
> - u32 spll;
> -
> - /* skl */
> - /*
> - * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
> - * lower part of ctrl1 and they get shifted into position when writing
> - * the register. This allows us to easily compare the state to share
> - * the DPLL.
> - */
> - u32 ctrl1;
> - /* HDMI only, 0 when used for DP */
> - u32 cfgcr1, cfgcr2;
> -
> - /* icl */
> - u32 cfgcr0;
> -
> - /* tgl */
> - u32 div0;
> -
> - /* bxt */
> - u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;
> -
> - /*
> - * ICL uses the following, already defined:
> - * u32 cfgcr0, cfgcr1;
> - */
> - u32 mg_refclkin_ctl;
> - u32 mg_clktop2_coreclkctl1;
> - u32 mg_clktop2_hsclkctl;
> - u32 mg_pll_div0;
> - u32 mg_pll_div1;
> - u32 mg_pll_lf;
> - u32 mg_pll_frac_lock;
> - u32 mg_pll_ssc;
> - u32 mg_pll_bias;
> - u32 mg_pll_tdc_coldst_bias;
> - u32 mg_pll_bias_mask;
> - u32 mg_pll_tdc_coldst_bias_mask;
> + union {
> + /* icl+ combo */
> + struct {
> + u32 icl_cfgcr0;
> + u32 icl_cfgcr1;
> + u32 icl_div0;
At least icl_ddi_combo_pll_get_freq() and icl_dump_hw_state() missed
converting cfgcr1 to icl_cfgcr1. Would it be less error-prone/simpler to
store here all the skl+ combo state? That would also reduce the diff
size.
> + };
> +
> + /* icl+ TC */
> + struct {
> + u32 mg_refclkin_ctl;
> + u32 mg_clktop2_coreclkctl1;
> + u32 mg_clktop2_hsclkctl;
> + u32 mg_pll_div0;
> + u32 mg_pll_div1;
> + u32 mg_pll_lf;
> + u32 mg_pll_frac_lock;
> + u32 mg_pll_ssc;
> + u32 mg_pll_bias;
> + u32 mg_pll_tdc_coldst_bias;
> + u32 mg_pll_bias_mask;
> + u32 mg_pll_tdc_coldst_bias_mask;
> + };
> +
> + /* bxt */
> + struct {
> + /* bxt */
> + u32 ebb0;
> + u32 ebb4;
> + u32 pll0;
> + u32 pll1;
> + u32 pll2;
> + u32 pll3;
> + u32 pll6;
> + u32 pll8;
> + u32 pll9;
> + u32 pll10;
> + u32 pcsdw12;
> + };
> +
> + /* skl */
> + struct {
> + /*
> + * DPLL_CTRL1 has 6 bits for each this DPLL. We store those in
> + * lower part of ctrl1 and they get shifted into position when writing
> + * the register. This allows us to easily compare the state to share
> + * the DPLL.
> + */
> + u32 ctrl1;
> + u32 cfgcr1;
> + /* HDMI only, 0 when used for DP */
> + u32 cfgcr2;
> + };
> +
> + /* hsw, bdw */
> + struct {
> + u32 wrpll;
> + u32 spll;
> + };
> +
> + /* i9xx, pch plls */
> + struct {
> + u32 dpll;
> + u32 dpll_md;
> + u32 fp0;
> + u32 fp1;
> + };
> + };
> };
>
> /**
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display: Use unions per platform in intel_dpll_hw_state
2022-02-23 19:58 ` [Intel-gfx] [PATCH] " Imre Deak
@ 2022-02-23 20:01 ` Souza, Jose
0 siblings, 0 replies; 6+ messages in thread
From: Souza, Jose @ 2022-02-23 20:01 UTC (permalink / raw)
To: Deak, Imre; +Cc: intel-gfx
On Wed, 2022-02-23 at 21:58 +0200, Imre Deak wrote:
> On Tue, Feb 22, 2022 at 06:20:45AM -0800, José Roberto de Souza wrote:
> [...]
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > index ba2fdfce15792..4360e1c9266d8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > @@ -184,52 +184,74 @@ enum icl_port_dpll_id {
> > };
> >
> > struct intel_dpll_hw_state {
> > - /* i9xx, pch plls */
> > - u32 dpll;
> > - u32 dpll_md;
> > - u32 fp0;
> > - u32 fp1;
> > -
> > - /* hsw, bdw */
> > - u32 wrpll;
> > - u32 spll;
> > -
> > - /* skl */
> > - /*
> > - * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
> > - * lower part of ctrl1 and they get shifted into position when writing
> > - * the register. This allows us to easily compare the state to share
> > - * the DPLL.
> > - */
> > - u32 ctrl1;
> > - /* HDMI only, 0 when used for DP */
> > - u32 cfgcr1, cfgcr2;
> > -
> > - /* icl */
> > - u32 cfgcr0;
> > -
> > - /* tgl */
> > - u32 div0;
> > -
> > - /* bxt */
> > - u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;
> > -
> > - /*
> > - * ICL uses the following, already defined:
> > - * u32 cfgcr0, cfgcr1;
> > - */
> > - u32 mg_refclkin_ctl;
> > - u32 mg_clktop2_coreclkctl1;
> > - u32 mg_clktop2_hsclkctl;
> > - u32 mg_pll_div0;
> > - u32 mg_pll_div1;
> > - u32 mg_pll_lf;
> > - u32 mg_pll_frac_lock;
> > - u32 mg_pll_ssc;
> > - u32 mg_pll_bias;
> > - u32 mg_pll_tdc_coldst_bias;
> > - u32 mg_pll_bias_mask;
> > - u32 mg_pll_tdc_coldst_bias_mask;
> > + union {
> > + /* icl+ combo */
> > + struct {
> > + u32 icl_cfgcr0;
> > + u32 icl_cfgcr1;
> > + u32 icl_div0;
>
> At least icl_ddi_combo_pll_get_freq() and icl_dump_hw_state() missed
> converting cfgcr1 to icl_cfgcr1. Would it be less error-prone/simpler to
Damn, yep missed that.
> store here all the skl+ combo state? That would also reduce the diff
> size.
Looks a good idea and will not make intel_dpll_hw_state increase in size.
Will send v2, thanks for the review.
>
> > + };
> > +
> > + /* icl+ TC */
> > + struct {
> > + u32 mg_refclkin_ctl;
> > + u32 mg_clktop2_coreclkctl1;
> > + u32 mg_clktop2_hsclkctl;
> > + u32 mg_pll_div0;
> > + u32 mg_pll_div1;
> > + u32 mg_pll_lf;
> > + u32 mg_pll_frac_lock;
> > + u32 mg_pll_ssc;
> > + u32 mg_pll_bias;
> > + u32 mg_pll_tdc_coldst_bias;
> > + u32 mg_pll_bias_mask;
> > + u32 mg_pll_tdc_coldst_bias_mask;
> > + };
> > +
> > + /* bxt */
> > + struct {
> > + /* bxt */
> > + u32 ebb0;
> > + u32 ebb4;
> > + u32 pll0;
> > + u32 pll1;
> > + u32 pll2;
> > + u32 pll3;
> > + u32 pll6;
> > + u32 pll8;
> > + u32 pll9;
> > + u32 pll10;
> > + u32 pcsdw12;
> > + };
> > +
> > + /* skl */
> > + struct {
> > + /*
> > + * DPLL_CTRL1 has 6 bits for each this DPLL. We store those in
> > + * lower part of ctrl1 and they get shifted into position when writing
> > + * the register. This allows us to easily compare the state to share
> > + * the DPLL.
> > + */
> > + u32 ctrl1;
> > + u32 cfgcr1;
> > + /* HDMI only, 0 when used for DP */
> > + u32 cfgcr2;
> > + };
> > +
> > + /* hsw, bdw */
> > + struct {
> > + u32 wrpll;
> > + u32 spll;
> > + };
> > +
> > + /* i9xx, pch plls */
> > + struct {
> > + u32 dpll;
> > + u32 dpll_md;
> > + u32 fp0;
> > + u32 fp1;
> > + };
> > + };
> > };
> >
> > /**
> > --
> > 2.35.1
> >
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-02-23 20:02 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-22 14:20 [Intel-gfx] [PATCH] drm/i915/display: Use unions per platform in intel_dpll_hw_state José Roberto de Souza
2022-02-22 23:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
2022-02-22 23:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-02-23 12:23 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-02-23 19:58 ` [Intel-gfx] [PATCH] " Imre Deak
2022-02-23 20:01 ` Souza, Jose
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