* [PATCH 1/2] drm/i915: Add ERR_INT to gen7 error state
@ 2012-08-20 23:15 Ben Widawsky
2012-08-20 23:15 ` [PATCH 2/2] drm/i915: Find unclaimed MMIO writes Ben Widawsky
2012-08-22 12:54 ` [PATCH 1/2] drm/i915: Add ERR_INT to gen7 error state Antti Koskipää
0 siblings, 2 replies; 6+ messages in thread
From: Ben Widawsky @ 2012-08-20 23:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Ben Widawsky
ERR_INT can generate interrupts. However since most of the conditions seem
quite fatal the patch opts to simply report it in error state instead of
adding more complexity to the interrupt handler for little gain (the
bits are sticky anyway).
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 1 +
4 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 0e8f14d..02405c7 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -702,6 +702,9 @@ static int i915_error_state(struct seq_file *m, void *unused)
seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
}
+ if (INTEL_INFO(dev)->gen == 7)
+ seq_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
+
for_each_ring(ring, dev_priv, i)
i915_ring_error_state(m, dev, error, i);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 33f19eb..c61fc48 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -196,6 +196,7 @@ struct drm_i915_error_state {
u32 cpu_ring_head[I915_NUM_RINGS];
u32 cpu_ring_tail[I915_NUM_RINGS];
u32 error; /* gen6+ */
+ u32 err_int; /* gen7 */
u32 instpm[I915_NUM_RINGS];
u32 instps[I915_NUM_RINGS];
u32 instdone1;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0c37101..021207c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1211,6 +1211,9 @@ static void i915_capture_error_state(struct drm_device *dev)
error->done_reg = I915_READ(DONE_REG);
}
+ if (INTEL_INFO(dev)->gen == 7)
+ error->err_int = I915_READ(GEN7_ERR_INT);
+
i915_gem_record_fences(dev, error);
i915_gem_record_rings(dev, error);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2f7b688..d4a7d73 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -507,6 +507,7 @@
#define DMA_FADD_I8XX 0x020d0
#define ERROR_GEN6 0x040a0
+#define GEN7_ERR_INT 0x44040
/* GM45+ chicken bits -- debug workaround bits that may be required
* for various sorts of correct behavior. The top 16 bits of each are
--
1.7.11.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/i915: Find unclaimed MMIO writes.
2012-08-20 23:15 [PATCH 1/2] drm/i915: Add ERR_INT to gen7 error state Ben Widawsky
@ 2012-08-20 23:15 ` Ben Widawsky
2012-08-22 13:15 ` Paulo Zanoni
2012-08-22 16:06 ` Daniel Vetter
2012-08-22 12:54 ` [PATCH 1/2] drm/i915: Add ERR_INT to gen7 error state Antti Koskipää
1 sibling, 2 replies; 6+ messages in thread
From: Ben Widawsky @ 2012-08-20 23:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Ben Widawsky
ERR_INT on HSW will display unclaimed MMIO accesses. This can be either
the result of a driver bug writing to an invalid addresses, or the
result of RC6.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_drv.c | 4 ++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 845e390..255087f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1182,6 +1182,10 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
if (unlikely(__fifo_ret)) { \
gen6_gt_check_fifodbg(dev_priv); \
} \
+ if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
+ DRM_ERROR("Unclaimed write to %x\n", reg); \
+ writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT); \
+ } \
}
__i915_write(8, b)
__i915_write(16, w)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d4a7d73..bab4762 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -508,6 +508,7 @@
#define ERROR_GEN6 0x040a0
#define GEN7_ERR_INT 0x44040
+#define ERR_INT_MMIO_UNCLAIMED (1<<13)
/* GM45+ chicken bits -- debug workaround bits that may be required
* for various sorts of correct behavior. The top 16 bits of each are
--
1.7.11.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/i915: Add ERR_INT to gen7 error state
2012-08-20 23:15 [PATCH 1/2] drm/i915: Add ERR_INT to gen7 error state Ben Widawsky
2012-08-20 23:15 ` [PATCH 2/2] drm/i915: Find unclaimed MMIO writes Ben Widawsky
@ 2012-08-22 12:54 ` Antti Koskipää
1 sibling, 0 replies; 6+ messages in thread
From: Antti Koskipää @ 2012-08-22 12:54 UTC (permalink / raw)
To: intel-gfx
Both patches look ok.
Reviewed-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
On 08/21/12 02:15, Ben Widawsky wrote:
> ERR_INT can generate interrupts. However since most of the conditions seem
> quite fatal the patch opts to simply report it in error state instead of
> adding more complexity to the interrupt handler for little gain (the
> bits are sticky anyway).
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 3 +++
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_irq.c | 3 +++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 4 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 0e8f14d..02405c7 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -702,6 +702,9 @@ static int i915_error_state(struct seq_file *m, void *unused)
> seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
> }
>
> + if (INTEL_INFO(dev)->gen == 7)
> + seq_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
> +
> for_each_ring(ring, dev_priv, i)
> i915_ring_error_state(m, dev, error, i);
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 33f19eb..c61fc48 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -196,6 +196,7 @@ struct drm_i915_error_state {
> u32 cpu_ring_head[I915_NUM_RINGS];
> u32 cpu_ring_tail[I915_NUM_RINGS];
> u32 error; /* gen6+ */
> + u32 err_int; /* gen7 */
> u32 instpm[I915_NUM_RINGS];
> u32 instps[I915_NUM_RINGS];
> u32 instdone1;
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 0c37101..021207c 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1211,6 +1211,9 @@ static void i915_capture_error_state(struct drm_device *dev)
> error->done_reg = I915_READ(DONE_REG);
> }
>
> + if (INTEL_INFO(dev)->gen == 7)
> + error->err_int = I915_READ(GEN7_ERR_INT);
> +
> i915_gem_record_fences(dev, error);
> i915_gem_record_rings(dev, error);
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2f7b688..d4a7d73 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -507,6 +507,7 @@
> #define DMA_FADD_I8XX 0x020d0
>
> #define ERROR_GEN6 0x040a0
> +#define GEN7_ERR_INT 0x44040
>
> /* GM45+ chicken bits -- debug workaround bits that may be required
> * for various sorts of correct behavior. The top 16 bits of each are
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915: Find unclaimed MMIO writes.
2012-08-20 23:15 ` [PATCH 2/2] drm/i915: Find unclaimed MMIO writes Ben Widawsky
@ 2012-08-22 13:15 ` Paulo Zanoni
2012-08-22 15:42 ` Ben Widawsky
2012-08-22 16:06 ` Daniel Vetter
1 sibling, 1 reply; 6+ messages in thread
From: Paulo Zanoni @ 2012-08-22 13:15 UTC (permalink / raw)
To: Ben Widawsky; +Cc: intel-gfx
2012/8/20 Ben Widawsky <ben@bwidawsk.net>:
> ERR_INT on HSW will display unclaimed MMIO accesses. This can be either
> the result of a driver bug writing to an invalid addresses, or the
> result of RC6.
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
For both patches:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
This is a pretty awesome change! It will really help the new hardware
enablement/debugging efforts.
We should volunteer someone to look at the other ERR_INT bits.
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 845e390..255087f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1182,6 +1182,10 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
> if (unlikely(__fifo_ret)) { \
> gen6_gt_check_fifodbg(dev_priv); \
> } \
> + if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
> + DRM_ERROR("Unclaimed write to %x\n", reg); \
> + writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT); \
> + } \
> }
> __i915_write(8, b)
> __i915_write(16, w)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d4a7d73..bab4762 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -508,6 +508,7 @@
>
> #define ERROR_GEN6 0x040a0
> #define GEN7_ERR_INT 0x44040
> +#define ERR_INT_MMIO_UNCLAIMED (1<<13)
>
> /* GM45+ chicken bits -- debug workaround bits that may be required
> * for various sorts of correct behavior. The top 16 bits of each are
> --
> 1.7.11.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915: Find unclaimed MMIO writes.
2012-08-22 13:15 ` Paulo Zanoni
@ 2012-08-22 15:42 ` Ben Widawsky
0 siblings, 0 replies; 6+ messages in thread
From: Ben Widawsky @ 2012-08-22 15:42 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On 2012-08-22 06:15, Paulo Zanoni wrote:
> 2012/8/20 Ben Widawsky <ben@bwidawsk.net>:
>> ERR_INT on HSW will display unclaimed MMIO accesses. This can be
>> either
>> the result of a driver bug writing to an invalid addresses, or the
>> result of RC6.
>>
>> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
>
> For both patches:
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> This is a pretty awesome change! It will really help the new hardware
> enablement/debugging efforts.
>
> We should volunteer someone to look at the other ERR_INT bits.
Consider yourself volunteered :-)
In all seriousness, I did look at the others. Nothing was as useful as
this one, IMO. There were a bunch of display related ones which I'm
fortunate enough to not have to fully understand. Having it in the error
state though over time might prove otherwise.
>
>> ---
>> drivers/gpu/drm/i915/i915_drv.c | 4 ++++
>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>> 2 files changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
>> b/drivers/gpu/drm/i915/i915_drv.c
>> index 845e390..255087f 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -1182,6 +1182,10 @@ void i915_write##x(struct drm_i915_private
>> *dev_priv, u32 reg, u##x val) { \
>> if (unlikely(__fifo_ret)) { \
>> gen6_gt_check_fifodbg(dev_priv); \
>> } \
>> + if (IS_HASWELL(dev_priv->dev) &&
>> (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
>> + DRM_ERROR("Unclaimed write to %x\n", reg); \
>> + writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs +
>> GEN7_ERR_INT); \
>> + } \
>> }
>> __i915_write(8, b)
>> __i915_write(16, w)
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index d4a7d73..bab4762 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -508,6 +508,7 @@
>>
>> #define ERROR_GEN6 0x040a0
>> #define GEN7_ERR_INT 0x44040
>> +#define ERR_INT_MMIO_UNCLAIMED (1<<13)
>>
>> /* GM45+ chicken bits -- debug workaround bits that may be required
>> * for various sorts of correct behavior. The top 16 bits of each
>> are
>> --
>> 1.7.11.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ben Widawsky, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915: Find unclaimed MMIO writes.
2012-08-20 23:15 ` [PATCH 2/2] drm/i915: Find unclaimed MMIO writes Ben Widawsky
2012-08-22 13:15 ` Paulo Zanoni
@ 2012-08-22 16:06 ` Daniel Vetter
1 sibling, 0 replies; 6+ messages in thread
From: Daniel Vetter @ 2012-08-22 16:06 UTC (permalink / raw)
To: Ben Widawsky; +Cc: intel-gfx
On Mon, Aug 20, 2012 at 04:15:14PM -0700, Ben Widawsky wrote:
> ERR_INT on HSW will display unclaimed MMIO accesses. This can be either
> the result of a driver bug writing to an invalid addresses, or the
> result of RC6.
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Both patches queued for -next, thanks.
-Daniel
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2012-08-22 16:06 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2012-08-20 23:15 [PATCH 1/2] drm/i915: Add ERR_INT to gen7 error state Ben Widawsky
2012-08-20 23:15 ` [PATCH 2/2] drm/i915: Find unclaimed MMIO writes Ben Widawsky
2012-08-22 13:15 ` Paulo Zanoni
2012-08-22 15:42 ` Ben Widawsky
2012-08-22 16:06 ` Daniel Vetter
2012-08-22 12:54 ` [PATCH 1/2] drm/i915: Add ERR_INT to gen7 error state Antti Koskipää
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