* [Intel-gfx] [PATCH 0/2] GuC submission / DRM scheduler integration plan + new uAPI
@ 2021-06-29 19:35 Matthew Brost
2021-06-29 19:35 ` [Intel-gfx] [PATCH 1/2] drm/doc/rfc: i915 GuC submission / DRM scheduler Matthew Brost
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: Matthew Brost @ 2021-06-29 19:35 UTC (permalink / raw)
To: intel-gfx, dri-devel
Subject and patches say it all.
v2: Address comments, patches have details of changes
v3: Address comments, patches have details of changes
v4: Address comments, patches have details of changes
v5: Fix checkpatch and docs warnings
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Matthew Brost (2):
drm/doc/rfc: i915 GuC submission / DRM scheduler
drm/doc/rfc: i915 new parallel submission uAPI plan
Documentation/gpu/rfc/i915_parallel_execbuf.h | 122 +++++++++++++++
Documentation/gpu/rfc/i915_scheduler.rst | 148 ++++++++++++++++++
Documentation/gpu/rfc/index.rst | 4 +
3 files changed, 274 insertions(+)
create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
create mode 100644 Documentation/gpu/rfc/i915_scheduler.rst
--
2.28.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread* [Intel-gfx] [PATCH 1/2] drm/doc/rfc: i915 GuC submission / DRM scheduler 2021-06-29 19:35 [Intel-gfx] [PATCH 0/2] GuC submission / DRM scheduler integration plan + new uAPI Matthew Brost @ 2021-06-29 19:35 ` Matthew Brost 2021-06-30 8:11 ` Martin Peres 2021-06-29 19:35 ` [Intel-gfx] [PATCH 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan Matthew Brost ` (4 subsequent siblings) 5 siblings, 1 reply; 11+ messages in thread From: Matthew Brost @ 2021-06-29 19:35 UTC (permalink / raw) To: intel-gfx, dri-devel Add entry for i915 GuC submission / DRM scheduler integration plan. Follow up patch with details of new parallel submission uAPI to come. v2: (Daniel Vetter) - Expand explaination of why bonding isn't supported for GuC submission - CC some of the DRM scheduler maintainers - Add priority inheritance / boosting use case - Add reasoning for removing in order assumptions (Daniel Stone) - Add links to priority spec v4: (Tvrtko) - Add TODOs section (Daniel Vetter) - Pull in 1 line from following patch v5: (Checkpatch) - Fix typos Cc: Christian König <christian.koenig@amd.com> Cc: Luben Tuikov <luben.tuikov@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Steven Price <steven.price@arm.com> Cc: Jon Bloomfield <jon.bloomfield@intel.com> Cc: Dave Airlie <airlied@gmail.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: dri-devel@lists.freedesktop.org Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Dave Airlie <airlied@redhat.com> --- Documentation/gpu/rfc/i915_scheduler.rst | 91 ++++++++++++++++++++++++ Documentation/gpu/rfc/index.rst | 4 ++ 2 files changed, 95 insertions(+) create mode 100644 Documentation/gpu/rfc/i915_scheduler.rst diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst new file mode 100644 index 000000000000..7acd386a6b49 --- /dev/null +++ b/Documentation/gpu/rfc/i915_scheduler.rst @@ -0,0 +1,91 @@ +========================================= +I915 GuC Submission/DRM Scheduler Section +========================================= + +Upstream plan +============= +For upstream the overall plan for landing GuC submission and integrating the +i915 with the DRM scheduler is: + +* Merge basic GuC submission + * Basic submission support for all gen11+ platforms + * Not enabled by default on any current platforms but can be enabled via + modparam enable_guc + * Lots of rework will need to be done to integrate with DRM scheduler so + no need to nit pick everything in the code, it just should be + functional, no major coding style / layering errors, and not regress + execlists + * Update IGTs / selftests as needed to work with GuC submission + * Enable CI on supported platforms for a baseline + * Rework / get CI heathly for GuC submission in place as needed +* Merge new parallel submission uAPI + * Bonding uAPI completely incompatible with GuC submission, plus it has + severe design issues in general, which is why we want to retire it no + matter what + * New uAPI adds I915_CONTEXT_ENGINES_EXT_PARALLEL context setup step + which configures a slot with N contexts + * After I915_CONTEXT_ENGINES_EXT_PARALLEL a user can submit N batches to + a slot in a single execbuf IOCTL and the batches run on the GPU in + paralllel + * Initially only for GuC submission but execlists can be supported if + needed +* Convert the i915 to use the DRM scheduler + * GuC submission backend fully integrated with DRM scheduler + * All request queues removed from backend (e.g. all backpressure + handled in DRM scheduler) + * Resets / cancels hook in DRM scheduler + * Watchdog hooks into DRM scheduler + * Lots of complexity of the GuC backend can be pulled out once + integrated with DRM scheduler (e.g. state machine gets + simplier, locking gets simplier, etc...) + * Execlists backend will minimum required to hook in the DRM scheduler + * Legacy interface + * Features like timeslicing / preemption / virtual engines would + be difficult to integrate with the DRM scheduler and these + features are not required for GuC submission as the GuC does + these things for us + * ROI low on fully integrating into DRM scheduler + * Fully integrating would add lots of complexity to DRM + scheduler + * Port i915 priority inheritance / boosting feature in DRM scheduler + * Used for i915 page flip, may be useful to other DRM drivers as + well + * Will be an optional feature in the DRM scheduler + * Remove in-order completion assumptions from DRM scheduler + * Even when using the DRM scheduler the backends will handle + preemption, timeslicing, etc... so it is possible for jobs to + finish out of order + * Pull out i915 priority levels and use DRM priority levels + * Optimize DRM scheduler as needed + +TODOs for GuC submission upstream +================================= + +* Need an update to GuC firmware / i915 to enable error state capture +* Open source tool to decode GuC logs +* Public GuC spec + +New uAPI for basic GuC submission +================================= +No major changes are required to the uAPI for basic GuC submission. The only +change is a new scheduler attribute: I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP. +This attribute indicates the 2k i915 user priority levels are statically mapped +into 3 levels as follows: + +* -1k to -1 Low priority +* 0 Medium priority +* 1 to 1k High priority + +This is needed because the GuC only has 4 priority bands. The highest priority +band is reserved with the kernel. This aligns with the DRM scheduler priority +levels too. + +Spec references: +---------------- +* https://www.khronos.org/registry/EGL/extensions/IMG/EGL_IMG_context_priority.txt +* https://www.khronos.org/registry/vulkan/specs/1.2-extensions/html/chap5.html#devsandqueues-priority +* https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priority-t + +New parallel submission uAPI +============================ +Details to come in a following patch. diff --git a/Documentation/gpu/rfc/index.rst b/Documentation/gpu/rfc/index.rst index 05670442ca1b..91e93a705230 100644 --- a/Documentation/gpu/rfc/index.rst +++ b/Documentation/gpu/rfc/index.rst @@ -19,3 +19,7 @@ host such documentation: .. toctree:: i915_gem_lmem.rst + +.. toctree:: + + i915_scheduler.rst -- 2.28.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/doc/rfc: i915 GuC submission / DRM scheduler 2021-06-29 19:35 ` [Intel-gfx] [PATCH 1/2] drm/doc/rfc: i915 GuC submission / DRM scheduler Matthew Brost @ 2021-06-30 8:11 ` Martin Peres 0 siblings, 0 replies; 11+ messages in thread From: Martin Peres @ 2021-06-30 8:11 UTC (permalink / raw) To: Matthew Brost, intel-gfx, dri-devel On 29/06/2021 22:35, Matthew Brost wrote: > Add entry for i915 GuC submission / DRM scheduler integration plan. > Follow up patch with details of new parallel submission uAPI to come. > > v2: > (Daniel Vetter) > - Expand explaination of why bonding isn't supported for GuC > submission > - CC some of the DRM scheduler maintainers > - Add priority inheritance / boosting use case > - Add reasoning for removing in order assumptions > (Daniel Stone) > - Add links to priority spec > v4: > (Tvrtko) > - Add TODOs section > (Daniel Vetter) > - Pull in 1 line from following patch > v5: > (Checkpatch) > - Fix typos > > Cc: Christian König <christian.koenig@amd.com> > Cc: Luben Tuikov <luben.tuikov@amd.com> > Cc: Alex Deucher <alexander.deucher@amd.com> > Cc: Steven Price <steven.price@arm.com> > Cc: Jon Bloomfield <jon.bloomfield@intel.com> > Cc: Dave Airlie <airlied@gmail.com> > Cc: Daniel Vetter <daniel.vetter@intel.com> > Cc: Jason Ekstrand <jason@jlekstrand.net> > Cc: dri-devel@lists.freedesktop.org > Signed-off-by: Matthew Brost <matthew.brost@intel.com> > Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> > Acked-by: Dave Airlie <airlied@redhat.com> > --- > Documentation/gpu/rfc/i915_scheduler.rst | 91 ++++++++++++++++++++++++ > Documentation/gpu/rfc/index.rst | 4 ++ > 2 files changed, 95 insertions(+) > create mode 100644 Documentation/gpu/rfc/i915_scheduler.rst > > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst > new file mode 100644 > index 000000000000..7acd386a6b49 > --- /dev/null > +++ b/Documentation/gpu/rfc/i915_scheduler.rst > @@ -0,0 +1,91 @@ > +========================================= > +I915 GuC Submission/DRM Scheduler Section > +========================================= > + > +Upstream plan > +============= > +For upstream the overall plan for landing GuC submission and integrating the > +i915 with the DRM scheduler is: > + > +* Merge basic GuC submission > + * Basic submission support for all gen11+ platforms > + * Not enabled by default on any current platforms but can be enabled via > + modparam enable_guc Just a quick reminder that a lot of users have this parameter set in their grub command line because of the incorrect assumption that quick sync requires the HuC which requires the GuC command submission. Just bear that in mind and make sure there is a minimum of quality in the GuC backend before allowing users to use the GuC, even behind this kernel parameter. Maybe a warning in the kernel logs saying that this feature is experimental, and use "enable_guc=1" for the fullest quick sync support will improve the user satisfaction, and save you some time handling unwanted bugs. > + * Lots of rework will need to be done to integrate with DRM scheduler so > + no need to nit pick everything in the code, it just should be > + functional, no major coding style / layering errors, and not regress > + execlists > + * Update IGTs / selftests as needed to work with GuC submission > + * Enable CI on supported platforms for a baseline What's the plan to keep the comparison between GuC and execlists? The CI machines cannot just test the GuC as it would expose users to regressions in the default mode, and machines are hard to come by in the CI lab. > + * Rework / get CI heathly for GuC submission in place as needed > +* Merge new parallel submission uAPI > + * Bonding uAPI completely incompatible with GuC submission, plus it has > + severe design issues in general, which is why we want to retire it no > + matter what > + * New uAPI adds I915_CONTEXT_ENGINES_EXT_PARALLEL context setup step > + which configures a slot with N contexts > + * After I915_CONTEXT_ENGINES_EXT_PARALLEL a user can submit N batches to > + a slot in a single execbuf IOCTL and the batches run on the GPU in > + paralllel FYI, this is a typo > + * Initially only for GuC submission but execlists can be supported if > + needed > +* Convert the i915 to use the DRM scheduler > + * GuC submission backend fully integrated with DRM scheduler > + * All request queues removed from backend (e.g. all backpressure > + handled in DRM scheduler) > + * Resets / cancels hook in DRM scheduler > + * Watchdog hooks into DRM scheduler > + * Lots of complexity of the GuC backend can be pulled out once > + integrated with DRM scheduler (e.g. state machine gets > + simplier, locking gets simplier, etc...) As much as I would like more consistency in the English language, simplier is not a word in the dictionary. > + * Execlists backend will minimum required to hook in the DRM scheduler Can't parse this sentence. How about: "Minimum integration of the execlists backend in the DRM scheduler"? Other than these typographical nitpicks, I think the plan is sane provided that you can find enough CI machines and add the warning. > + * Legacy interface > + * Features like timeslicing / preemption / virtual engines would > + be difficult to integrate with the DRM scheduler and these > + features are not required for GuC submission as the GuC does > + these things for us > + * ROI low on fully integrating into DRM scheduler > + * Fully integrating would add lots of complexity to DRM > + scheduler > + * Port i915 priority inheritance / boosting feature in DRM scheduler > + * Used for i915 page flip, may be useful to other DRM drivers as > + well > + * Will be an optional feature in the DRM scheduler > + * Remove in-order completion assumptions from DRM scheduler > + * Even when using the DRM scheduler the backends will handle > + preemption, timeslicing, etc... so it is possible for jobs to > + finish out of order > + * Pull out i915 priority levels and use DRM priority levels > + * Optimize DRM scheduler as needed > + > +TODOs for GuC submission upstream > +================================= > + > +* Need an update to GuC firmware / i915 to enable error state capture > +* Open source tool to decode GuC logs > +* Public GuC spec > + > +New uAPI for basic GuC submission > +================================= > +No major changes are required to the uAPI for basic GuC submission. The only > +change is a new scheduler attribute: I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP. > +This attribute indicates the 2k i915 user priority levels are statically mapped > +into 3 levels as follows: > + > +* -1k to -1 Low priority > +* 0 Medium priority > +* 1 to 1k High priority > + > +This is needed because the GuC only has 4 priority bands. The highest priority > +band is reserved with the kernel. This aligns with the DRM scheduler priority > +levels too. > + > +Spec references: > +---------------- > +* https://www.khronos.org/registry/EGL/extensions/IMG/EGL_IMG_context_priority.txt > +* https://www.khronos.org/registry/vulkan/specs/1.2-extensions/html/chap5.html#devsandqueues-priority > +* https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priority-t > + > +New parallel submission uAPI > +============================ > +Details to come in a following patch. > diff --git a/Documentation/gpu/rfc/index.rst b/Documentation/gpu/rfc/index.rst > index 05670442ca1b..91e93a705230 100644 > --- a/Documentation/gpu/rfc/index.rst > +++ b/Documentation/gpu/rfc/index.rst > @@ -19,3 +19,7 @@ host such documentation: > .. toctree:: > > i915_gem_lmem.rst > + > +.. toctree:: > + > + i915_scheduler.rst > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan 2021-06-29 19:35 [Intel-gfx] [PATCH 0/2] GuC submission / DRM scheduler integration plan + new uAPI Matthew Brost 2021-06-29 19:35 ` [Intel-gfx] [PATCH 1/2] drm/doc/rfc: i915 GuC submission / DRM scheduler Matthew Brost @ 2021-06-29 19:35 ` Matthew Brost 2021-06-30 9:11 ` Martin Peres 2021-06-29 19:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GuC submission / DRM scheduler integration plan + new uAPI Patchwork ` (3 subsequent siblings) 5 siblings, 1 reply; 11+ messages in thread From: Matthew Brost @ 2021-06-29 19:35 UTC (permalink / raw) To: intel-gfx, dri-devel Add entry for i915 new parallel submission uAPI plan. v2: (Daniel Vetter): - Expand logical order explaination - Add dummy header - Only allow N BBs in execbuf IOCTL - Configure parallel submission per slot not per gem context v3: (Marcin Ślusarz): - Lot's of typos / bad english fixed (Tvrtko Ursulin): - Consistent pseudo code, clean up wording in descriptions v4: (Daniel Vetter) - Drop flags - Add kernel doc - Reword a few things / fix typos (Tvrtko) - Reword a few things / fix typos v5: (Checkpatch) - Fix typos (Docs) - Fix warning Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Tony Ye <tony.ye@intel.com> CC: Carl Zhang <carl.zhang@intel.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Tony Ye <tony.ye@intel.com> --- Documentation/gpu/rfc/i915_parallel_execbuf.h | 122 ++++++++++++++++++ Documentation/gpu/rfc/i915_scheduler.rst | 59 ++++++++- 2 files changed, 180 insertions(+), 1 deletion(-) create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h new file mode 100644 index 000000000000..8cbe2c4e0172 --- /dev/null +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2021 Intel Corporation + */ + +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */ + +/** + * struct drm_i915_context_engines_parallel_submit - Configure engine for + * parallel submission. + * + * Setup a slot in the context engine map to allow multiple BBs to be submitted + * in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU + * in parallel. Multiple hardware contexts are created internally in the i915 + * run these BBs. Once a slot is configured for N BBs only N BBs can be + * submitted in each execbuf IOCTL and this is implicit behavior e.g. The user + * doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how + * many BBs there are based on the slot's configuration. The N BBs are the last + * N buffer objects or first N if I915_EXEC_BATCH_FIRST is set. + * + * The default placement behavior is to create implicit bonds between each + * context if each context maps to more than 1 physical engine (e.g. context is + * a virtual engine). Also we only allow contexts of same engine class and these + * contexts must be in logically contiguous order. Examples of the placement + * behavior described below. Lastly, the default is to not allow BBs to + * preempted mid BB rather insert coordinated preemption on all hardware + * contexts between each set of BBs. Flags may be added in the future to change + * both of these default behaviors. + * + * Returns -EINVAL if hardware context placement configuration is invalid or if + * the placement configuration isn't supported on the platform / submission + * interface. + * Returns -ENODEV if extension isn't supported on the platform / submission + * interface. + * + * .. code-block:: none + * + * Example 1 pseudo code: + * CS[X] = generic engine of same class, logical instance X + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE + * set_engines(INVALID) + * set_parallel(engine_index=0, width=2, num_siblings=1, + * engines=CS[0],CS[1]) + * + * Results in the following valid placement: + * CS[0], CS[1] + * + * Example 2 pseudo code: + * CS[X] = generic engine of same class, logical instance X + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE + * set_engines(INVALID) + * set_parallel(engine_index=0, width=2, num_siblings=2, + * engines=CS[0],CS[2],CS[1],CS[3]) + * + * Results in the following valid placements: + * CS[0], CS[1] + * CS[2], CS[3] + * + * This can also be thought of as 2 virtual engines described by 2-D array + * in the engines the field with bonds placed between each index of the + * virtual engines. e.g. CS[0] is bonded to CS[1], CS[2] is bonded to + * CS[3]. + * VE[0] = CS[0], CS[2] + * VE[1] = CS[1], CS[3] + * + * Example 3 pseudo code: + * CS[X] = generic engine of same class, logical instance X + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE + * set_engines(INVALID) + * set_parallel(engine_index=0, width=2, num_siblings=2, + * engines=CS[0],CS[1],CS[1],CS[3]) + * + * Results in the following valid and invalid placements: + * CS[0], CS[1] + * CS[1], CS[3] - Not logical contiguous, return -EINVAL + */ +struct drm_i915_context_engines_parallel_submit { + /** + * @base: base user extension. + */ + struct i915_user_extension base; + + /** + * @engine_index: slot for parallel engine + */ + __u16 engine_index; + + /** + * @width: number of contexts per parallel engine + */ + __u16 width; + + /** + * @num_siblings: number of siblings per context + */ + __u16 num_siblings; + + /** + * @mbz16: reserved for future use; must be zero + */ + __u16 mbz16; + + /** + * @flags: all undefined flags must be zero, currently not defined flags + */ + __u64 flags; + + /** + * @mbz64: reserved for future use; must be zero + */ + __u64 mbz64[3]; + + /** + * @engines: 2-d array of engine instances to configure parallel engine + * + * length = width (i) * num_siblings (j) + * index = j + i * num_siblings + */ + struct i915_engine_class_instance engines[0]; + +} __packed; + diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst index 7acd386a6b49..cbda75065dad 100644 --- a/Documentation/gpu/rfc/i915_scheduler.rst +++ b/Documentation/gpu/rfc/i915_scheduler.rst @@ -88,4 +88,61 @@ Spec references: New parallel submission uAPI ============================ -Details to come in a following patch. +The existing bonding uAPI is completely broken with GuC submission because +whether a submission is a single context submit or parallel submit isn't known +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple +contexts in parallel with the GuC the context must be explicitly registered with +N contexts and all N contexts must be submitted in a single command to the GuC. +The GuC interfaces do not support dynamically changing between N contexts as the +bonding uAPI does. Hence the need for a new parallel submission interface. Also +the legacy bonding uAPI is quite confusing and not intuitive at all. Furthermore +I915_SUBMIT_FENCE is by design a future fence, so not really something we should +continue to support. + +The new parallel submission uAPI consists of 3 parts: + +* Export engines logical mapping +* A 'set_parallel' extension to configure contexts for parallel + submission +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL + +Export engines logical mapping +------------------------------ +Certain use cases require BBs to be placed on engine instances in logical order +(e.g. split-frame on gen11+). The logical mapping of engine instances can change +based on fusing. Rather than making UMDs be aware of fusing, simply expose the +logical mapping with the existing query engine info IOCTL. Also the GuC +submission interface currently only supports submitting multiple contexts to +engines in logical order which is a new requirement compared to execlists. +Lastly, all current platforms have at most 2 engine instances and the logical +order is the same as uAPI order. This will change on platforms with more than 2 +engine instances. + +A single bit will be added to drm_i915_engine_info.flags indicating that the +logical instance has been returned and a new field, +drm_i915_engine_info.logical_instance, returns the logical instance. + +A 'set_parallel' extension to configure contexts for parallel submission +------------------------------------------------------------------------ +The 'set_parallel' extension configures a slot for parallel submission of N BBs. +It is a setup step that must be called before using any of the contexts. See +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for +similar existing examples. Once a slot is configured for parallel submission the +execbuf2 IOCTL can be called submitting N BBs in a single IOCTL. Initially only +supports GuC submission. Execlists supports can be added later if needed. + +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and +drm_i915_context_engines_parallel_submit to the uAPI to implement this +extension. + +.. kernel-doc:: Documentation/gpu/rfc/i915_parallel_execbuf.h + :functions: drm_i915_context_engines_parallel_submit + +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL +------------------------------------------------------------------- +Contexts that have been configured with the 'set_parallel' extension can only +submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N objects +in the drm_i915_gem_exec_object2 list or the first N if I915_EXEC_BATCH_FIRST is +set. The number of BBs is implicit based on the slot submitted and how it has +been configured by 'set_parallel' or other extensions. No uAPI changes are +required to the execbuf2 IOCTL. -- 2.28.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan 2021-06-29 19:35 ` [Intel-gfx] [PATCH 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan Matthew Brost @ 2021-06-30 9:11 ` Martin Peres 0 siblings, 0 replies; 11+ messages in thread From: Martin Peres @ 2021-06-30 9:11 UTC (permalink / raw) To: Matthew Brost, intel-gfx, dri-devel On 29/06/2021 22:35, Matthew Brost wrote: > Add entry for i915 new parallel submission uAPI plan. > > v2: > (Daniel Vetter): > - Expand logical order explaination > - Add dummy header > - Only allow N BBs in execbuf IOCTL > - Configure parallel submission per slot not per gem context > v3: > (Marcin Ślusarz): > - Lot's of typos / bad english fixed > (Tvrtko Ursulin): > - Consistent pseudo code, clean up wording in descriptions > v4: > (Daniel Vetter) > - Drop flags > - Add kernel doc > - Reword a few things / fix typos > (Tvrtko) > - Reword a few things / fix typos > v5: > (Checkpatch) > - Fix typos > (Docs) > - Fix warning > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Tony Ye <tony.ye@intel.com> > CC: Carl Zhang <carl.zhang@intel.com> > Cc: Daniel Vetter <daniel.vetter@intel.com> > Cc: Jason Ekstrand <jason@jlekstrand.net> > Signed-off-by: Matthew Brost <matthew.brost@intel.com> > Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> > Acked-by: Tony Ye <tony.ye@intel.com> > --- > Documentation/gpu/rfc/i915_parallel_execbuf.h | 122 ++++++++++++++++++ > Documentation/gpu/rfc/i915_scheduler.rst | 59 ++++++++- > 2 files changed, 180 insertions(+), 1 deletion(-) > create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h > > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h > new file mode 100644 > index 000000000000..8cbe2c4e0172 > --- /dev/null > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h > @@ -0,0 +1,122 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2021 Intel Corporation > + */ > + > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */ > + > +/** > + * struct drm_i915_context_engines_parallel_submit - Configure engine for > + * parallel submission. > + * > + * Setup a slot in the context engine map to allow multiple BBs to be submitted > + * in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU > + * in parallel. Multiple hardware contexts are created internally in the i915 > + * run these BBs. The previous sentence makes little sense. > Once a slot is configured for N BBs only N BBs can be > + * submitted in each execbuf IOCTL and this is implicit behavior e.g. The user > + * doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how > + * many BBs there are based on the slot's configuration. The N BBs are the last > + * N buffer objects or first N if I915_EXEC_BATCH_FIRST is set. > + * > + * The default placement behavior is to create implicit bonds between each > + * context if each context maps to more than 1 physical engine (e.g. context is > + * a virtual engine). Also we only allow contexts of same engine class and these > + * contexts must be in logically contiguous order. Examples of the placement > + * behavior described below. Lastly, the default is to not allow BBs to > + * preempted mid BB rather insert coordinated preemption on all hardware > + * contexts between each set of BBs. Flags may be added in the future to change > + * both of these default behaviors. > + * > + * Returns -EINVAL if hardware context placement configuration is invalid or if > + * the placement configuration isn't supported on the platform / submission > + * interface. > + * Returns -ENODEV if extension isn't supported on the platform / submission > + * interface. > + * > + * .. code-block:: none > + * > + * Example 1 pseudo code: > + * CS[X] = generic engine of same class, logical instance X > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE > + * set_engines(INVALID) > + * set_parallel(engine_index=0, width=2, num_siblings=1, > + * engines=CS[0],CS[1]) > + * > + * Results in the following valid placement: > + * CS[0], CS[1] > + * > + * Example 2 pseudo code: > + * CS[X] = generic engine of same class, logical instance X > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE > + * set_engines(INVALID) > + * set_parallel(engine_index=0, width=2, num_siblings=2, > + * engines=CS[0],CS[2],CS[1],CS[3]) > + * > + * Results in the following valid placements: > + * CS[0], CS[1] > + * CS[2], CS[3] > + * > + * This can also be thought of as 2 virtual engines described by 2-D array > + * in the engines the field with bonds placed between each index of the > + * virtual engines. e.g. CS[0] is bonded to CS[1], CS[2] is bonded to > + * CS[3]. > + * VE[0] = CS[0], CS[2] > + * VE[1] = CS[1], CS[3] > + * > + * Example 3 pseudo code: > + * CS[X] = generic engine of same class, logical instance X > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE > + * set_engines(INVALID) > + * set_parallel(engine_index=0, width=2, num_siblings=2, > + * engines=CS[0],CS[1],CS[1],CS[3]) > + * > + * Results in the following valid and invalid placements: > + * CS[0], CS[1] > + * CS[1], CS[3] - Not logical contiguous, return -EINVAL > + */ > +struct drm_i915_context_engines_parallel_submit { > + /** > + * @base: base user extension. > + */ > + struct i915_user_extension base; > + > + /** > + * @engine_index: slot for parallel engine > + */ > + __u16 engine_index; > + > + /** > + * @width: number of contexts per parallel engine > + */ > + __u16 width; > + > + /** > + * @num_siblings: number of siblings per context > + */ > + __u16 num_siblings; > + > + /** > + * @mbz16: reserved for future use; must be zero > + */ > + __u16 mbz16; > + > + /** > + * @flags: all undefined flags must be zero, currently not defined flags > + */ > + __u64 flags; > + > + /** > + * @mbz64: reserved for future use; must be zero > + */ > + __u64 mbz64[3]; > + > + /** > + * @engines: 2-d array of engine instances to configure parallel engine > + * > + * length = width (i) * num_siblings (j) > + * index = j + i * num_siblings > + */ > + struct i915_engine_class_instance engines[0]; > + > +} __packed; > + > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst > index 7acd386a6b49..cbda75065dad 100644 > --- a/Documentation/gpu/rfc/i915_scheduler.rst > +++ b/Documentation/gpu/rfc/i915_scheduler.rst > @@ -88,4 +88,61 @@ Spec references: > > New parallel submission uAPI > ============================ > -Details to come in a following patch. > +The existing bonding uAPI is completely broken with GuC submission because > +whether a submission is a single context submit or parallel submit isn't known > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple > +contexts in parallel with the GuC the context must be explicitly registered with > +N contexts and all N contexts must be submitted in a single command to the GuC. > +The GuC interfaces do not support dynamically changing between N contexts as the > +bonding uAPI does. Hence the need for a new parallel submission interface. Also > +the legacy bonding uAPI is quite confusing and not intuitive at all. Furthermore > +I915_SUBMIT_FENCE is by design a future fence, so not really something we should > +continue to support. A proprietary firmware interface should not be considered a good reason to retire a Linux uAPI. It is messages like this that make me super uneasy about the entire ordeal with the GuC: we would have no say on its interface, and Linux would be an afterthought of the firmware developers. Anyway, I'm sure there are plenty of user-facing reasons to the original interface sucks, so please focus on that instead. > + > +The new parallel submission uAPI consists of 3 parts: > + > +* Export engines logical mapping > +* A 'set_parallel' extension to configure contexts for parallel > + submission > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL > + > +Export engines logical mapping > +------------------------------ > +Certain use cases require BBs to be placed on engine instances in logical order > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change > +based on fusing. This sentence can be quite confusing: How about "The logical mapping of engine instances can change from one GPU to another, as some engines can be fused-out at the factory for various reasons". The above makes it clear that this would be fixed on a per-GPU basis, and what type of fusing we are talking about, making it easier to google for. > Rather than making UMDs be aware of fusing, simply expose the > +logical mapping with the existing query engine info IOCTL. Also the GuC > +submission interface currently only supports submitting multiple contexts to > +engines in logical order which is a new requirement compared to execlists. > +Lastly, all current platforms have at most 2 engine instances and the logical > +order is the same as uAPI order. This will change on platforms with more than 2 > +engine instances. > + > +A single bit will be added to drm_i915_engine_info.flags indicating that the > +logical instance has been returned and a new field, > +drm_i915_engine_info.logical_instance, returns the logical instance. > + > +A 'set_parallel' extension to configure contexts for parallel submission > +------------------------------------------------------------------------ > +The 'set_parallel' extension configures a slot for parallel submission of N BBs. > +It is a setup step that must be called before using any of the contexts. See > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for > +similar existing examples. Once a slot is configured for parallel submission the > +execbuf2 IOCTL can be called submitting N BBs in a single IOCTL. Initially only > +supports GuC submission. Execlists supports can be added later if needed. > + > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and > +drm_i915_context_engines_parallel_submit to the uAPI to implement this > +extension. > + > +.. kernel-doc:: Documentation/gpu/rfc/i915_parallel_execbuf.h > + :functions: drm_i915_context_engines_parallel_submit > + > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL > +------------------------------------------------------------------- > +Contexts that have been configured with the 'set_parallel' extension can only > +submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N objects > +in the drm_i915_gem_exec_object2 list or the first N if I915_EXEC_BATCH_FIRST is > +set. The number of BBs is implicit based on the slot submitted and how it has > +been configured by 'set_parallel' or other extensions. No uAPI changes are > +required to the execbuf2 IOCTL. > Good job! The interface is pretty well described, and setting up ahead of time how many parallel contexts will be run should make it easier to reason with than the current interface. That being said, a uAPI is not designed just with a firmware and driver in mind. Would you mind adding a list of use cases where this interface would be needed, and a small analysis about the impact of such change? I mean, the userspace was designed with the old interface in mind, and forcing them to set up the number of parallel execution at context creation may lead them to submit empty command buffers when they would need a lower parallelism. Any recommendations there? Cheers, Martin _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GuC submission / DRM scheduler integration plan + new uAPI 2021-06-29 19:35 [Intel-gfx] [PATCH 0/2] GuC submission / DRM scheduler integration plan + new uAPI Matthew Brost 2021-06-29 19:35 ` [Intel-gfx] [PATCH 1/2] drm/doc/rfc: i915 GuC submission / DRM scheduler Matthew Brost 2021-06-29 19:35 ` [Intel-gfx] [PATCH 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan Matthew Brost @ 2021-06-29 19:47 ` Patchwork 2021-06-29 20:18 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork ` (2 subsequent siblings) 5 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2021-06-29 19:47 UTC (permalink / raw) To: Matthew Brost; +Cc: intel-gfx == Series Details == Series: GuC submission / DRM scheduler integration plan + new uAPI URL : https://patchwork.freedesktop.org/series/92028/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9534ae8c12da drm/doc/rfc: i915 GuC submission / DRM scheduler -:44: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #44: new file mode 100644 -:49: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #49: FILE: Documentation/gpu/rfc/i915_scheduler.rst:1: +========================================= total: 0 errors, 2 warnings, 0 checks, 98 lines checked 16b33a940e29 drm/doc/rfc: i915 new parallel submission uAPI plan -:45: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #45: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 184 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for GuC submission / DRM scheduler integration plan + new uAPI 2021-06-29 19:35 [Intel-gfx] [PATCH 0/2] GuC submission / DRM scheduler integration plan + new uAPI Matthew Brost ` (2 preceding siblings ...) 2021-06-29 19:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GuC submission / DRM scheduler integration plan + new uAPI Patchwork @ 2021-06-29 20:18 ` Patchwork 2021-06-30 0:57 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2021-06-30 7:52 ` [Intel-gfx] [PATCH 0/2] " Daniel Vetter 5 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2021-06-29 20:18 UTC (permalink / raw) To: Matthew Brost; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 3400 bytes --] == Series Details == Series: GuC submission / DRM scheduler integration plan + new uAPI URL : https://patchwork.freedesktop.org/series/92028/ State : success == Summary == CI Bug Log - changes from CI_DRM_10289 -> Patchwork_20489 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/index.html Known issues ------------ Here are the changes found in Patchwork_20489 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +23 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/fi-bdw-5557u/igt@amdgpu/amd_basic@semaphore.html * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-snb-2600: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html * igt@core_hotunplug@unbind-rebind: - fi-bdw-5557u: NOTRUN -> [WARN][3] ([i915#2283]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/fi-bdw-5557u/igt@core_hotunplug@unbind-rebind.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][4] -> [FAIL][5] ([i915#1372]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html #### Possible fixes #### * igt@i915_selftest@live@hugepages: - fi-snb-2600: [INCOMPLETE][6] -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/fi-snb-2600/igt@i915_selftest@live@hugepages.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/fi-snb-2600/igt@i915_selftest@live@hugepages.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7500u: [DMESG-FAIL][8] ([i915#165]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283 Participating hosts (42 -> 37) ------------------------------ Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes ------------- * Linux: CI_DRM_10289 -> Patchwork_20489 CI-20190529: 20190529 CI_DRM_10289: b9081c2437cee8e573eeafcd19c816cc7e10f19d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6121: a63ceb48e6c3e733d04156b32fba3b4f4d5ad794 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_20489: 16b33a940e2989e992e71b1812606efb1464ad2b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 16b33a940e29 drm/doc/rfc: i915 new parallel submission uAPI plan 9534ae8c12da drm/doc/rfc: i915 GuC submission / DRM scheduler == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/index.html [-- Attachment #1.2: Type: text/html, Size: 4225 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for GuC submission / DRM scheduler integration plan + new uAPI 2021-06-29 19:35 [Intel-gfx] [PATCH 0/2] GuC submission / DRM scheduler integration plan + new uAPI Matthew Brost ` (3 preceding siblings ...) 2021-06-29 20:18 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2021-06-30 0:57 ` Patchwork 2021-06-30 7:52 ` [Intel-gfx] [PATCH 0/2] " Daniel Vetter 5 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2021-06-30 0:57 UTC (permalink / raw) To: Matthew Brost; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 30281 bytes --] == Series Details == Series: GuC submission / DRM scheduler integration plan + new uAPI URL : https://patchwork.freedesktop.org/series/92028/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10289_full -> Patchwork_20489_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_20489_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20489_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_20489_full: ### IGT changes ### #### Possible regressions #### * igt@i915_pm_rps@waitboost: - shard-glk: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-glk1/igt@i915_pm_rps@waitboost.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-glk5/igt@i915_pm_rps@waitboost.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs}: - {shard-rkl}: [PASS][3] -> [FAIL][4] +5 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-rkl-6/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-rkl-5/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs.html * {igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_ccs}: - {shard-rkl}: [SKIP][5] -> [FAIL][6] +7 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-rkl-6/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_ccs.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-rkl-2/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_ccs.html * {igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs}: - {shard-rkl}: [FAIL][7] -> [SKIP][8] +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-rkl-1/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-rkl-6/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html * {igt@kms_ccs@pipe-d-ccs-on-another-bo-y_tiled_gen12_mc_ccs}: - {shard-rkl}: [SKIP][9] ([i915#533]) -> [FAIL][10] +6 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-rkl-6/igt@kms_ccs@pipe-d-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-rkl-2/igt@kms_ccs@pipe-d-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html * igt@kms_content_protection@dp-mst-type-0: - {shard-rkl}: [SKIP][11] ([i915#3116]) -> [SKIP][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-rkl-6/igt@kms_content_protection@dp-mst-type-0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-rkl-1/igt@kms_content_protection@dp-mst-type-0.html * igt@kms_cursor_crc@pipe-a-cursor-512x170-random: - {shard-rkl}: [SKIP][13] ([fdo#109279] / [i915#3359]) -> [SKIP][14] +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-512x170-random.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-rkl-1/igt@kms_cursor_crc@pipe-a-cursor-512x170-random.html * igt@kms_cursor_crc@pipe-c-cursor-32x10-onscreen: - {shard-rkl}: [SKIP][15] ([i915#3359]) -> [SKIP][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-rkl-6/igt@kms_cursor_crc@pipe-c-cursor-32x10-onscreen.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-rkl-5/igt@kms_cursor_crc@pipe-c-cursor-32x10-onscreen.html * igt@kms_cursor_crc@pipe-c-cursor-32x32-onscreen: - {shard-rkl}: [SKIP][17] ([i915#3319]) -> [SKIP][18] +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-rkl-6/igt@kms_cursor_crc@pipe-c-cursor-32x32-onscreen.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-rkl-2/igt@kms_cursor_crc@pipe-c-cursor-32x32-onscreen.html * igt@kms_cursor_crc@pipe-c-cursor-dpms: - {shard-rkl}: [SKIP][19] ([fdo#112022]) -> [SKIP][20] +6 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-rkl-5/igt@kms_cursor_crc@pipe-c-cursor-dpms.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-rkl-1/igt@kms_cursor_crc@pipe-c-cursor-dpms.html * igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled: - {shard-rkl}: [PASS][21] -> [SKIP][22] +36 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-rkl-5/igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled.html * igt@kms_flip@flip-vs-panning: - {shard-rkl}: NOTRUN -> [SKIP][23] +7 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-rkl-2/igt@kms_flip@flip-vs-panning.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs: - {shard-rkl}: [INCOMPLETE][24] -> [SKIP][25] +1 similar issue [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-rkl-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt: - {shard-rkl}: [SKIP][26] ([i915#1849]) -> [SKIP][27] +17 similar issues [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html * igt@kms_frontbuffer_tracking@fbc-2p-shrfb-fliptrack-mmap-gtt: - {shard-rkl}: [SKIP][28] ([fdo#111825]) -> [SKIP][29] +1 similar issue [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-shrfb-fliptrack-mmap-gtt.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-2p-shrfb-fliptrack-mmap-gtt.html * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt: - {shard-rkl}: [SKIP][30] ([fdo#111825] / [i915#1825]) -> [SKIP][31] +6 similar issues [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt.html * igt@kms_hdr@static-swap: - {shard-rkl}: [SKIP][32] ([i915#1845]) -> [DMESG-WARN][33] [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-rkl-1/igt@kms_hdr@static-swap.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-rkl-6/igt@kms_hdr@static-swap.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - {shard-rkl}: [FAIL][34] ([fdo#103375]) -> [SKIP][35] [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-rkl-6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-rkl-5/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3: - {shard-rkl}: [SKIP][36] ([i915#658]) -> [SKIP][37] +1 similar issue [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-rkl-1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-rkl-6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html * igt@kms_psr@psr2_sprite_mmap_cpu: - {shard-rkl}: [SKIP][38] ([i915#1072]) -> [SKIP][39] +1 similar issue [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-rkl-5/igt@kms_psr@psr2_sprite_mmap_cpu.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-rkl-1/igt@kms_psr@psr2_sprite_mmap_cpu.html Known issues ------------ Here are the changes found in Patchwork_20489_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@api_intel_bb@blit-noreloc-purge-cache-random: - shard-skl: [PASS][40] -> [DMESG-WARN][41] ([i915#1982]) +1 similar issue [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-skl7/igt@api_intel_bb@blit-noreloc-purge-cache-random.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-skl3/igt@api_intel_bb@blit-noreloc-purge-cache-random.html * igt@feature_discovery@display-4x: - shard-tglb: NOTRUN -> [SKIP][42] ([i915#1839]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-tglb7/igt@feature_discovery@display-4x.html * igt@gem_create@create-massive: - shard-kbl: NOTRUN -> [DMESG-WARN][43] ([i915#3002]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-kbl1/igt@gem_create@create-massive.html * igt@gem_ctx_persistence@legacy-engines-hostile-preempt: - shard-snb: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#1099]) +2 similar issues [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-snb5/igt@gem_ctx_persistence@legacy-engines-hostile-preempt.html * igt@gem_exec_fair@basic-deadline: - shard-apl: NOTRUN -> [FAIL][45] ([i915#2846]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-apl1/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-glk: [PASS][46] -> [FAIL][47] ([i915#2842]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-glk7/igt@gem_exec_fair@basic-none-rrul@rcs0.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-glk2/igt@gem_exec_fair@basic-none-rrul@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][48] -> [FAIL][49] ([i915#2842]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][50] ([i915#2842]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-iclb2/igt@gem_exec_fair@basic-none@vcs1.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-tglb: NOTRUN -> [FAIL][51] ([i915#2842]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-tglb7/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_exec_reloc@basic-wide-active@bcs0: - shard-apl: NOTRUN -> [FAIL][52] ([i915#3633]) +3 similar issues [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-apl8/igt@gem_exec_reloc@basic-wide-active@bcs0.html * igt@gem_exec_reloc@basic-wide-active@rcs0: - shard-kbl: NOTRUN -> [FAIL][53] ([i915#3633]) +4 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-kbl4/igt@gem_exec_reloc@basic-wide-active@rcs0.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#2190]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-apl1/igt@gem_huc_copy@huc-copy.html - shard-iclb: NOTRUN -> [SKIP][55] ([i915#2190]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-iclb3/igt@gem_huc_copy@huc-copy.html * igt@gem_mmap_gtt@big-copy-odd: - shard-skl: [PASS][56] -> [FAIL][57] ([i915#307]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-skl8/igt@gem_mmap_gtt@big-copy-odd.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-skl6/igt@gem_mmap_gtt@big-copy-odd.html * igt@gem_pread@exhaustion: - shard-snb: NOTRUN -> [WARN][58] ([i915#2658]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-snb5/igt@gem_pread@exhaustion.html * igt@gem_render_copy@y-tiled-ccs-to-linear: - shard-snb: NOTRUN -> [SKIP][59] ([fdo#109271]) +174 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-snb7/igt@gem_render_copy@y-tiled-ccs-to-linear.html * igt@gem_userptr_blits@dmabuf-sync: - shard-apl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#3323]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-apl2/igt@gem_userptr_blits@dmabuf-sync.html * igt@gem_userptr_blits@input-checking: - shard-snb: NOTRUN -> [DMESG-WARN][61] ([i915#3002]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-snb5/igt@gem_userptr_blits@input-checking.html * igt@gem_userptr_blits@vma-merge: - shard-apl: NOTRUN -> [FAIL][62] ([i915#3318]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-apl8/igt@gem_userptr_blits@vma-merge.html * igt@gem_vm_create@destroy-race: - shard-tglb: [PASS][63] -> [TIMEOUT][64] ([i915#2795]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-tglb3/igt@gem_vm_create@destroy-race.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-tglb7/igt@gem_vm_create@destroy-race.html * igt@gen3_render_mixed_blits: - shard-tglb: NOTRUN -> [SKIP][65] ([fdo#109289]) +1 similar issue [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-tglb7/igt@gen3_render_mixed_blits.html * igt@gen7_exec_parse@basic-offset: - shard-apl: NOTRUN -> [SKIP][66] ([fdo#109271]) +344 similar issues [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-apl7/igt@gen7_exec_parse@basic-offset.html * igt@gen9_exec_parse@batch-invalid-length: - shard-tglb: NOTRUN -> [SKIP][67] ([fdo#112306]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-tglb7/igt@gen9_exec_parse@batch-invalid-length.html * igt@gen9_exec_parse@unaligned-access: - shard-iclb: NOTRUN -> [SKIP][68] ([fdo#112306]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-iclb3/igt@gen9_exec_parse@unaligned-access.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: NOTRUN -> [INCOMPLETE][69] ([i915#1982] / [i915#3698]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-iclb6/igt@i915_pm_dc@dc6-psr.html * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp: - shard-apl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#1937]) [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-apl2/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html * igt@i915_pm_rpm@dpms-non-lpsp: - shard-iclb: NOTRUN -> [SKIP][71] ([fdo#110892]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-iclb3/igt@i915_pm_rpm@dpms-non-lpsp.html * igt@i915_pm_rpm@pc8-residency: - shard-tglb: NOTRUN -> [SKIP][72] ([fdo#109506] / [i915#2411]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-tglb7/igt@i915_pm_rpm@pc8-residency.html * igt@i915_pm_sseu@full-enable: - shard-tglb: NOTRUN -> [SKIP][73] ([fdo#109288]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-tglb7/igt@i915_pm_sseu@full-enable.html * igt@i915_suspend@forcewake: - shard-apl: NOTRUN -> [DMESG-WARN][74] ([i915#180]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-apl8/igt@i915_suspend@forcewake.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][75] -> [DMESG-WARN][76] ([i915#180]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-apl6/igt@i915_suspend@sysfs-reader.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-apl1/igt@i915_suspend@sysfs-reader.html * igt@kms_big_fb@linear-32bpp-rotate-270: - shard-tglb: NOTRUN -> [SKIP][77] ([fdo#111614]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-tglb7/igt@kms_big_fb@linear-32bpp-rotate-270.html * igt@kms_big_fb@yf-tiled-32bpp-rotate-90: - shard-tglb: NOTRUN -> [SKIP][78] ([fdo#111615]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-tglb7/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html * igt@kms_chamelium@hdmi-hpd-fast: - shard-snb: NOTRUN -> [SKIP][79] ([fdo#109271] / [fdo#111827]) +9 similar issues [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-snb7/igt@kms_chamelium@hdmi-hpd-fast.html * igt@kms_chamelium@vga-edid-read: - shard-iclb: NOTRUN -> [SKIP][80] ([fdo#109284] / [fdo#111827]) +1 similar issue [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-iclb6/igt@kms_chamelium@vga-edid-read.html * igt@kms_chamelium@vga-hpd: - shard-apl: NOTRUN -> [SKIP][81] ([fdo#109271] / [fdo#111827]) +32 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-apl3/igt@kms_chamelium@vga-hpd.html * igt@kms_chamelium@vga-hpd-for-each-pipe: - shard-skl: NOTRUN -> [SKIP][82] ([fdo#109271] / [fdo#111827]) +5 similar issues [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-skl3/igt@kms_chamelium@vga-hpd-for-each-pipe.html * igt@kms_color@pipe-a-ctm-0-75: - shard-skl: NOTRUN -> [DMESG-WARN][83] ([i915#1982]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-skl3/igt@kms_color@pipe-a-ctm-0-75.html * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red: - shard-kbl: NOTRUN -> [SKIP][84] ([fdo#109271] / [fdo#111827]) +8 similar issues [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-kbl4/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html * igt@kms_color_chamelium@pipe-d-ctm-green-to-red: - shard-tglb: NOTRUN -> [SKIP][85] ([fdo#109284] / [fdo#111827]) +3 similar issues [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-tglb7/igt@kms_color_chamelium@pipe-d-ctm-green-to-red.html * igt@kms_content_protection@atomic: - shard-kbl: NOTRUN -> [TIMEOUT][86] ([i915#1319]) [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-kbl6/igt@kms_content_protection@atomic.html * igt@kms_content_protection@atomic-dpms: - shard-apl: NOTRUN -> [TIMEOUT][87] ([i915#1319]) +2 similar issues [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-apl6/igt@kms_content_protection@atomic-dpms.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-kbl: NOTRUN -> [DMESG-WARN][88] ([i915#180]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-kbl2/igt@kms_cursor_crc@pipe-b-cursor-suspend.html * igt@kms_cursor_crc@pipe-c-cursor-512x512-rapid-movement: - shard-tglb: NOTRUN -> [SKIP][89] ([fdo#109279] / [i915#3359]) +3 similar issues [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-tglb7/igt@kms_cursor_crc@pipe-c-cursor-512x512-rapid-movement.html * igt@kms_cursor_crc@pipe-d-cursor-max-size-rapid-movement: - shard-tglb: NOTRUN -> [SKIP][90] ([i915#3359]) [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-max-size-rapid-movement.html * igt@kms_cursor_legacy@flip-vs-cursor-toggle: - shard-skl: [PASS][91] -> [FAIL][92] ([i915#2346]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html * igt@kms_cursor_legacy@pipe-d-torture-bo: - shard-skl: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#533]) +1 similar issue [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-skl10/igt@kms_cursor_legacy@pipe-d-torture-bo.html * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled: - shard-glk: [PASS][94] -> [DMESG-WARN][95] ([i915#118] / [i915#95]) [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-glk7/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-glk8/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled.html * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible: - shard-iclb: NOTRUN -> [SKIP][96] ([fdo#109274]) [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-iclb3/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1: - shard-glk: [PASS][97] -> [FAIL][98] ([i915#79]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1: - shard-skl: NOTRUN -> [FAIL][99] ([i915#2122]) [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html * igt@kms_flip@flip-vs-expired-vblank@b-edp1: - shard-skl: [PASS][100] -> [FAIL][101] ([i915#79]) [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-skl2/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: - shard-kbl: [PASS][102] -> [DMESG-WARN][103] ([i915#180]) +3 similar issues [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html * igt@kms_flip@flip-vs-suspend-interruptible@b-edp1: - shard-skl: [PASS][104] -> [INCOMPLETE][105] ([i915#146] / [i915#198]) [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-skl2/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs: - shard-kbl: NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#2672]) [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-kbl1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs: - shard-apl: NOTRUN -> [SKIP][107] ([fdo#109271] / [i915#2672]) [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-apl3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt: - shard-glk: [PASS][108] -> [FAIL][109] ([i915#2546] / [i915#49]) [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-glk2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt.html [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-glk3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt: - shard-skl: NOTRUN -> [SKIP][110] ([fdo#109271]) +42 similar issues [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-skl10/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][111] -> [FAIL][112] ([i915#2546] / [i915#49]) [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-pwrite: - shard-iclb: NOTRUN -> [SKIP][113] ([fdo#109280]) +2 similar issues [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt: - shard-tglb: NOTRUN -> [SKIP][114] ([fdo#111825]) +8 similar issues [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt: - shard-skl: [PASS][115] -> [FAIL][116] ([i915#49]) [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html * igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c: - shard-iclb: NOTRUN -> [SKIP][117] ([fdo#109289]) [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-iclb3/igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - shard-apl: NOTRUN -> [SKIP][118] ([fdo#109271] / [i915#533]) +2 similar issues [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-apl6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d: - shard-kbl: NOTRUN -> [SKIP][119] ([fdo#109271] / [i915#533]) [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html * igt@kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-apl: NOTRUN -> [FAIL][120] ([fdo#108145] / [i915#265]) +5 similar issues [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb: - shard-kbl: NOTRUN -> [FAIL][121] ([fdo#108145] / [i915#265]) [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-kbl1/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb: - shard-apl: NOTRUN -> [FAIL][122] ([i915#265]) +1 similar issue [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-apl2/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb: - shard-kbl: NOTRUN -> [FAIL][123] ([i915#265]) [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-kbl3/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][124] -> [FAIL][125] ([fdo#108145] / [i915#265]) +1 similar issue [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10289/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_plane_cursor@pipe-d-overlay-size-64: - shard-iclb: NOTRUN -> [SKIP][126] ([fdo#109278]) +2 similar issues [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-iclb3/igt@kms_plane_cursor@pipe-d-overlay-size-64.html * igt@kms_plane_lowres@pipe-a-tiling-none: - shard-iclb: NOTRUN -> [SKIP][127] ([i915#3536]) [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-iclb3/igt@kms_plane_lowres@pipe-a-tiling-none.html * igt@kms_plane_lowres@pipe-b-tiling-none: - shard-tglb: NOTRUN -> [SKIP][128] ([i915#3536]) [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-tglb7/igt@kms_plane_lowres@pipe-b-tiling-none.html * igt@kms_plane_multiple@atomic-pipe-d-tiling-yf: - shard-tglb: NOTRUN -> [SKIP][129] ([fdo#112054]) [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-tglb7/igt@kms_plane_multiple@atomic-pipe-d-tiling-yf.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1: - shard-tglb: NOTRUN -> [SKIP][130] ([i915#2920]) [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-tglb7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2: - shard-kbl: NOTRUN -> [SKIP][131] ([fdo#109271] / [i915#658]) +1 similar issue [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-kbl1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4: - shard-apl: NOTRUN -> [SKIP][132] ([fdo#109271] / [i915#658]) +7 similar issues [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/shard-apl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-2: - shard-iclb: NOT == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20489/index.html [-- Attachment #1.2: Type: text/html, Size: 33598 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 0/2] GuC submission / DRM scheduler integration plan + new uAPI 2021-06-29 19:35 [Intel-gfx] [PATCH 0/2] GuC submission / DRM scheduler integration plan + new uAPI Matthew Brost ` (4 preceding siblings ...) 2021-06-30 0:57 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork @ 2021-06-30 7:52 ` Daniel Vetter 5 siblings, 0 replies; 11+ messages in thread From: Daniel Vetter @ 2021-06-30 7:52 UTC (permalink / raw) To: Matthew Brost; +Cc: intel-gfx, dri-devel On Tue, Jun 29, 2021 at 12:35:09PM -0700, Matthew Brost wrote: > Subject and patches say it all. > > v2: Address comments, patches have details of changes > v3: Address comments, patches have details of changes > v4: Address comments, patches have details of changes > v5: Fix checkpatch and docs warnings > > Signed-off-by: Matthew Brost <matthew.brost@intel.com> Pushed to drm-intel-gt-next, thanks a lot! -Daniel > > Matthew Brost (2): > drm/doc/rfc: i915 GuC submission / DRM scheduler > drm/doc/rfc: i915 new parallel submission uAPI plan > > Documentation/gpu/rfc/i915_parallel_execbuf.h | 122 +++++++++++++++ > Documentation/gpu/rfc/i915_scheduler.rst | 148 ++++++++++++++++++ > Documentation/gpu/rfc/index.rst | 4 + > 3 files changed, 274 insertions(+) > create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h > create mode 100644 Documentation/gpu/rfc/i915_scheduler.rst > > -- > 2.28.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 0/2] GuC submission / DRM scheduler integration plan + new uAPI @ 2021-06-11 23:40 Matthew Brost 2021-06-11 23:40 ` [Intel-gfx] [PATCH 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan Matthew Brost 0 siblings, 1 reply; 11+ messages in thread From: Matthew Brost @ 2021-06-11 23:40 UTC (permalink / raw) To: intel-gfx, dri-devel Cc: carl.zhang, jason.ekstrand, mesa-dev, daniel.vetter, christian.koenig Subject and patches say it all. v2: Address comments, patches have details of changes v3: Address comments, patches have details of changes v4: Address comments, patches have details of changes Signed-off-by: Matthew Brost <matthew.brost@intel.com> Matthew Brost (2): drm/doc/rfc: i915 GuC submission / DRM scheduler drm/doc/rfc: i915 new parallel submission uAPI plan Documentation/gpu/rfc/i915_parallel_execbuf.h | 117 ++++++++++++++ Documentation/gpu/rfc/i915_scheduler.rst | 148 ++++++++++++++++++ Documentation/gpu/rfc/index.rst | 4 + 3 files changed, 269 insertions(+) create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h create mode 100644 Documentation/gpu/rfc/i915_scheduler.rst -- 2.28.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan 2021-06-11 23:40 Matthew Brost @ 2021-06-11 23:40 ` Matthew Brost 2021-06-18 17:58 ` Ye, Tony 0 siblings, 1 reply; 11+ messages in thread From: Matthew Brost @ 2021-06-11 23:40 UTC (permalink / raw) To: intel-gfx, dri-devel Cc: carl.zhang, jason.ekstrand, mesa-dev, daniel.vetter, christian.koenig Add entry for i915 new parallel submission uAPI plan. v2: (Daniel Vetter): - Expand logical order explaination - Add dummy header - Only allow N BBs in execbuf IOCTL - Configure parallel submission per slot not per gem context v3: (Marcin Ślusarz): - Lot's of typos / bad english fixed (Tvrtko Ursulin): - Consistent pseudo code, clean up wording in descriptions v4: (Daniel Vetter) - Drop flags - Add kernel doc - Reword a few things / fix typos (Tvrtko) - Reword a few things / fix typos Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Tony Ye <tony.ye@intel.com> CC: Carl Zhang <carl.zhang@intel.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> --- Documentation/gpu/rfc/i915_parallel_execbuf.h | 117 ++++++++++++++++++ Documentation/gpu/rfc/i915_scheduler.rst | 59 ++++++++- 2 files changed, 175 insertions(+), 1 deletion(-) create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h new file mode 100644 index 000000000000..c22af3a359e4 --- /dev/null +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h @@ -0,0 +1,117 @@ +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */ + +/** + * struct drm_i915_context_engines_parallel_submit - Configure engine for + * parallel submission. + * + * Setup a slot in the context engine map to allow multiple BBs to be submitted + * in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU + * in parallel. Multiple hardware contexts are created internally in the i915 + * run these BBs. Once a slot is configured for N BBs only N BBs can be + * submitted in each execbuf IOCTL and this is implicit behavior e.g. The user + * doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how + * many BBs there are based on the slot's configuration. The N BBs are the last + * N buffer objects or first N if I915_EXEC_BATCH_FIRST is set. + * + * The default placement behavior is to create implicit bonds between each + * context if each context maps to more than 1 physical engine (e.g. context is + * a virtual engine). Also we only allow contexts of same engine class and these + * contexts must be in logically contiguous order. Examples of the placement + * behavior described below. Lastly, the default is to not allow BBs to + * preempted mid BB rather insert coordinated preemption on all hardware + * contexts between each set of BBs. Flags may be added in the future to change + * bott of these default behaviors. + * + * Returns -EINVAL if hardware context placement configuration is invalid or if + * the placement configuration isn't supported on the platform / submission + * interface. + * Returns -ENODEV if extension isn't supported on the platform / submission + * inteface. + * + * .. code-block:: + * + * Example 1 pseudo code: + * CS[X] = generic engine of same class, logical instance X + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE + * set_engines(INVALID) + * set_parallel(engine_index=0, width=2, num_siblings=1, + * engines=CS[0],CS[1]) + * + * Results in the following valid placement: + * CS[0], CS[1] + * + * Example 2 pseudo code: + * CS[X] = generic engine of same class, logical instance X + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE + * set_engines(INVALID) + * set_parallel(engine_index=0, width=2, num_siblings=2, + * engines=CS[0],CS[2],CS[1],CS[3]) + * + * Results in the following valid placements: + * CS[0], CS[1] + * CS[2], CS[3] + * + * This can also be thought of as 2 virtual engines described by 2-D array + * in the engines the field with bonds placed between each index of the + * virtual engines. e.g. CS[0] is bonded to CS[1], CS[2] is bonded to + * CS[3]. + * VE[0] = CS[0], CS[2] + * VE[1] = CS[1], CS[3] + * + * Example 3 pseudo code: + * CS[X] = generic engine of same class, logical instance X + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE + * set_engines(INVALID) + * set_parallel(engine_index=0, width=2, num_siblings=2, + * engines=CS[0],CS[1],CS[1],CS[3]) + * + * Results in the following valid and invalid placements: + * CS[0], CS[1] + * CS[1], CS[3] - Not logical contiguous, return -EINVAL + */ +struct drm_i915_context_engines_parallel_submit { + /** + * @base: base user extension. + */ + struct i915_user_extension base; + + /** + * @engine_index: slot for parallel engine + */ + __u16 engine_index; + + /** + * @width: number of contexts per parallel engine + */ + __u16 width; + + /** + * @num_siblings: number of siblings per context + */ + __u16 num_siblings; + + /** + * @mbz16: reserved for future use; must be zero + */ + __u16 mbz16; + + /** + * @flags: all undefined flags must be zero, currently not defined flags + */ + __u64 flags; + + /** + * @mbz64: reserved for future use; must be zero + */ + __u64 mbz64[3]; + + /** + * @engines: 2-d array of engine instances to configure parallel engine + * + * length = width (i) * num_siblings (j) + * index = j + i * num_siblings + */ + struct i915_engine_class_instance engines[0]; + +} __attribute__ ((packed)); + diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst index 7acd386a6b49..63849b50e663 100644 --- a/Documentation/gpu/rfc/i915_scheduler.rst +++ b/Documentation/gpu/rfc/i915_scheduler.rst @@ -88,4 +88,61 @@ Spec references: New parallel submission uAPI ============================ -Details to come in a following patch. +The existing bonding uAPI is completely broken with GuC submission because +whether a submission is a single context submit or parallel submit isn't known +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple +contexts in parallel with the GuC the context must be explicitly registered with +N contexts and all N contexts must be submitted in a single command to the GuC. +The GuC interfaces do not support dynamically changing between N contexts as the +bonding uAPI does. Hence the need for a new parallel submission interface. Also +the legacy bonding uAPI is quite confusing and not intuitive at all. Furthermore +I915_SUBMIT_FENCE is by design a future fence, so not really something we should +continue to support. + +The new parallel submission uAPI consists of 3 parts: + +* Export engines logical mapping +* A 'set_parallel' extension to configure contexts for parallel + submission +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL + +Export engines logical mapping +------------------------------ +Certain use cases require BBs to be placed on engine instances in logical order +(e.g. split-frame on gen11+). The logical mapping of engine instances can change +based on fusing. Rather than making UMDs be aware of fusing, simply expose the +logical mapping with the existing query engine info IOCTL. Also the GuC +submission interface currently only supports submitting multiple contexts to +engines in logical order which is a new requirement compared to execlists. +Lastly, all current platforms have at most 2 engine instances and the logical +order is the same as uAPI order. This will change on platforms with more than 2 +engine instances. + +A single bit will be added to drm_i915_engine_info.flags indicating that the +logical instance has been returned and a new field, +drm_i915_engine_info.logical_instance, returns the logical instance. + +A 'set_parallel' extension to configure contexts for parallel submission +------------------------------------------------------------------------ +The 'set_parallel' extension configures a slot for parallel submission of N BBs. +It is a setup step that must be called before using any of the contexts. See +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for +similar existing examples. Once a slot is configured for parallel submission the +execbuf2 IOCTL can be called submitting N BBs in a single IOCTL. Initially only +supports GuC submission. Execlists supports can be added later if needed. + +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and +drm_i915_context_engines_parallel_submit to the uAPI to implement this +extension. + +.. kernel-doc:: Documentation/gpu/rfc/i915_parallel_execbuf.h + :functions: drm_i915_context_engines_parallel_submit + +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL +------------------------------------------------------------------- +Contexts that have been configured with the 'set_parallel' extension can only +submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N objects +in in the drm_i915_gem_exec_object2 list or the first N if I915_EXEC_BATCH_FIRST +is set. The number of BBs is implicit based on the slot submitted and how it has +been configured by 'set_parallel' or other extensions. No uAPI changes are +required to execbuf2 IOCTL. -- 2.28.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan 2021-06-11 23:40 ` [Intel-gfx] [PATCH 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan Matthew Brost @ 2021-06-18 17:58 ` Ye, Tony 0 siblings, 0 replies; 11+ messages in thread From: Ye, Tony @ 2021-06-18 17:58 UTC (permalink / raw) To: Brost, Matthew, intel-gfx, dri-devel Cc: Zhang, Carl, Ekstrand, Jason, mesa-dev, Vetter, Daniel, christian.koenig Acked-by: Tony Ye <tony.ye@intel.com> Regards, Tony On 6/11/2021 4:40 PM, Matthew Brost wrote: > Add entry for i915 new parallel submission uAPI plan. > > v2: > (Daniel Vetter): > - Expand logical order explaination > - Add dummy header > - Only allow N BBs in execbuf IOCTL > - Configure parallel submission per slot not per gem context > v3: > (Marcin Ślusarz): > - Lot's of typos / bad english fixed > (Tvrtko Ursulin): > - Consistent pseudo code, clean up wording in descriptions > v4: > (Daniel Vetter) > - Drop flags > - Add kernel doc > - Reword a few things / fix typos > (Tvrtko) > - Reword a few things / fix typos > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Tony Ye <tony.ye@intel.com> > CC: Carl Zhang <carl.zhang@intel.com> > Cc: Daniel Vetter <daniel.vetter@intel.com> > Cc: Jason Ekstrand <jason@jlekstrand.net> > Signed-off-by: Matthew Brost <matthew.brost@intel.com> > Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> > --- > Documentation/gpu/rfc/i915_parallel_execbuf.h | 117 ++++++++++++++++++ > Documentation/gpu/rfc/i915_scheduler.rst | 59 ++++++++- > 2 files changed, 175 insertions(+), 1 deletion(-) > create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h > > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h > new file mode 100644 > index 000000000000..c22af3a359e4 > --- /dev/null > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h > @@ -0,0 +1,117 @@ > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */ > + > +/** > + * struct drm_i915_context_engines_parallel_submit - Configure engine for > + * parallel submission. > + * > + * Setup a slot in the context engine map to allow multiple BBs to be submitted > + * in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU > + * in parallel. Multiple hardware contexts are created internally in the i915 > + * run these BBs. Once a slot is configured for N BBs only N BBs can be > + * submitted in each execbuf IOCTL and this is implicit behavior e.g. The user > + * doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how > + * many BBs there are based on the slot's configuration. The N BBs are the last > + * N buffer objects or first N if I915_EXEC_BATCH_FIRST is set. > + * > + * The default placement behavior is to create implicit bonds between each > + * context if each context maps to more than 1 physical engine (e.g. context is > + * a virtual engine). Also we only allow contexts of same engine class and these > + * contexts must be in logically contiguous order. Examples of the placement > + * behavior described below. Lastly, the default is to not allow BBs to > + * preempted mid BB rather insert coordinated preemption on all hardware > + * contexts between each set of BBs. Flags may be added in the future to change > + * bott of these default behaviors. > + * > + * Returns -EINVAL if hardware context placement configuration is invalid or if > + * the placement configuration isn't supported on the platform / submission > + * interface. > + * Returns -ENODEV if extension isn't supported on the platform / submission > + * inteface. > + * > + * .. code-block:: > + * > + * Example 1 pseudo code: > + * CS[X] = generic engine of same class, logical instance X > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE > + * set_engines(INVALID) > + * set_parallel(engine_index=0, width=2, num_siblings=1, > + * engines=CS[0],CS[1]) > + * > + * Results in the following valid placement: > + * CS[0], CS[1] > + * > + * Example 2 pseudo code: > + * CS[X] = generic engine of same class, logical instance X > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE > + * set_engines(INVALID) > + * set_parallel(engine_index=0, width=2, num_siblings=2, > + * engines=CS[0],CS[2],CS[1],CS[3]) > + * > + * Results in the following valid placements: > + * CS[0], CS[1] > + * CS[2], CS[3] > + * > + * This can also be thought of as 2 virtual engines described by 2-D array > + * in the engines the field with bonds placed between each index of the > + * virtual engines. e.g. CS[0] is bonded to CS[1], CS[2] is bonded to > + * CS[3]. > + * VE[0] = CS[0], CS[2] > + * VE[1] = CS[1], CS[3] > + * > + * Example 3 pseudo code: > + * CS[X] = generic engine of same class, logical instance X > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE > + * set_engines(INVALID) > + * set_parallel(engine_index=0, width=2, num_siblings=2, > + * engines=CS[0],CS[1],CS[1],CS[3]) > + * > + * Results in the following valid and invalid placements: > + * CS[0], CS[1] > + * CS[1], CS[3] - Not logical contiguous, return -EINVAL > + */ > +struct drm_i915_context_engines_parallel_submit { > + /** > + * @base: base user extension. > + */ > + struct i915_user_extension base; > + > + /** > + * @engine_index: slot for parallel engine > + */ > + __u16 engine_index; > + > + /** > + * @width: number of contexts per parallel engine > + */ > + __u16 width; > + > + /** > + * @num_siblings: number of siblings per context > + */ > + __u16 num_siblings; > + > + /** > + * @mbz16: reserved for future use; must be zero > + */ > + __u16 mbz16; > + > + /** > + * @flags: all undefined flags must be zero, currently not defined flags > + */ > + __u64 flags; > + > + /** > + * @mbz64: reserved for future use; must be zero > + */ > + __u64 mbz64[3]; > + > + /** > + * @engines: 2-d array of engine instances to configure parallel engine > + * > + * length = width (i) * num_siblings (j) > + * index = j + i * num_siblings > + */ > + struct i915_engine_class_instance engines[0]; > + > +} __attribute__ ((packed)); > + > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst > index 7acd386a6b49..63849b50e663 100644 > --- a/Documentation/gpu/rfc/i915_scheduler.rst > +++ b/Documentation/gpu/rfc/i915_scheduler.rst > @@ -88,4 +88,61 @@ Spec references: > > New parallel submission uAPI > ============================ > -Details to come in a following patch. > +The existing bonding uAPI is completely broken with GuC submission because > +whether a submission is a single context submit or parallel submit isn't known > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple > +contexts in parallel with the GuC the context must be explicitly registered with > +N contexts and all N contexts must be submitted in a single command to the GuC. > +The GuC interfaces do not support dynamically changing between N contexts as the > +bonding uAPI does. Hence the need for a new parallel submission interface. Also > +the legacy bonding uAPI is quite confusing and not intuitive at all. Furthermore > +I915_SUBMIT_FENCE is by design a future fence, so not really something we should > +continue to support. > + > +The new parallel submission uAPI consists of 3 parts: > + > +* Export engines logical mapping > +* A 'set_parallel' extension to configure contexts for parallel > + submission > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL > + > +Export engines logical mapping > +------------------------------ > +Certain use cases require BBs to be placed on engine instances in logical order > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change > +based on fusing. Rather than making UMDs be aware of fusing, simply expose the > +logical mapping with the existing query engine info IOCTL. Also the GuC > +submission interface currently only supports submitting multiple contexts to > +engines in logical order which is a new requirement compared to execlists. > +Lastly, all current platforms have at most 2 engine instances and the logical > +order is the same as uAPI order. This will change on platforms with more than 2 > +engine instances. > + > +A single bit will be added to drm_i915_engine_info.flags indicating that the > +logical instance has been returned and a new field, > +drm_i915_engine_info.logical_instance, returns the logical instance. > + > +A 'set_parallel' extension to configure contexts for parallel submission > +------------------------------------------------------------------------ > +The 'set_parallel' extension configures a slot for parallel submission of N BBs. > +It is a setup step that must be called before using any of the contexts. See > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for > +similar existing examples. Once a slot is configured for parallel submission the > +execbuf2 IOCTL can be called submitting N BBs in a single IOCTL. Initially only > +supports GuC submission. Execlists supports can be added later if needed. > + > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and > +drm_i915_context_engines_parallel_submit to the uAPI to implement this > +extension. > + > +.. kernel-doc:: Documentation/gpu/rfc/i915_parallel_execbuf.h > + :functions: drm_i915_context_engines_parallel_submit > + > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL > +------------------------------------------------------------------- > +Contexts that have been configured with the 'set_parallel' extension can only > +submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N objects > +in in the drm_i915_gem_exec_object2 list or the first N if I915_EXEC_BATCH_FIRST > +is set. The number of BBs is implicit based on the slot submitted and how it has > +been configured by 'set_parallel' or other extensions. No uAPI changes are > +required to execbuf2 IOCTL. > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2021-06-30 9:12 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-06-29 19:35 [Intel-gfx] [PATCH 0/2] GuC submission / DRM scheduler integration plan + new uAPI Matthew Brost 2021-06-29 19:35 ` [Intel-gfx] [PATCH 1/2] drm/doc/rfc: i915 GuC submission / DRM scheduler Matthew Brost 2021-06-30 8:11 ` Martin Peres 2021-06-29 19:35 ` [Intel-gfx] [PATCH 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan Matthew Brost 2021-06-30 9:11 ` Martin Peres 2021-06-29 19:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GuC submission / DRM scheduler integration plan + new uAPI Patchwork 2021-06-29 20:18 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-06-30 0:57 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2021-06-30 7:52 ` [Intel-gfx] [PATCH 0/2] " Daniel Vetter -- strict thread matches above, loose matches on Subject: below -- 2021-06-11 23:40 Matthew Brost 2021-06-11 23:40 ` [Intel-gfx] [PATCH 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan Matthew Brost 2021-06-18 17:58 ` Ye, Tony
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