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* [Intel-gfx] [PATCH 1/2] drm/i915/csr: use intel_de_*() functions for register access
@ 2020-02-14 14:09 Jani Nikula
  2020-02-14 14:09 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: " Jani Nikula
                   ` (2 more replies)
  0 siblings, 3 replies; 7+ messages in thread
From: Jani Nikula @ 2020-02-14 14:09 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().

Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().

No functional changes.

Generated using the following semantic patch:

@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)

@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_csr.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index 6a408e11a3de..57320c12839f 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -27,6 +27,7 @@
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "intel_csr.h"
+#include "intel_de.h"
 
 /**
  * DOC: csr support for dmc
@@ -276,11 +277,11 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 		mask |= DC_STATE_DEBUG_MASK_CORES;
 
 	/* The below bit doesn't need to be cleared ever afterwards */
-	val = I915_READ(DC_STATE_DEBUG);
+	val = intel_de_read(dev_priv, DC_STATE_DEBUG);
 	if ((val & mask) != mask) {
 		val |= mask;
-		I915_WRITE(DC_STATE_DEBUG, val);
-		POSTING_READ(DC_STATE_DEBUG);
+		intel_de_write(dev_priv, DC_STATE_DEBUG, val);
+		intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
 	}
 }
 
@@ -321,8 +322,8 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
 	preempt_enable();
 
 	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
-		I915_WRITE(dev_priv->csr.mmioaddr[i],
-			   dev_priv->csr.mmiodata[i]);
+		intel_de_write(dev_priv, dev_priv->csr.mmioaddr[i],
+			       dev_priv->csr.mmiodata[i]);
 	}
 
 	dev_priv->csr.dc_state = 0;
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [Intel-gfx] [PATCH 2/2] drm/i915/display: use intel_de_*() functions for register access
  2020-02-14 14:09 [Intel-gfx] [PATCH 1/2] drm/i915/csr: use intel_de_*() functions for register access Jani Nikula
@ 2020-02-14 14:09 ` " Jani Nikula
  2020-02-14 14:24   ` Ville Syrjälä
  2020-02-14 20:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/csr: " Patchwork
  2020-02-18  2:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  2 siblings, 1 reply; 7+ messages in thread
From: Jani Nikula @ 2020-02-14 14:09 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().

Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().

No functional changes.

Generated using the following semantic patch:

@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)

@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../drm/i915/display/intel_display_debugfs.c  | 65 +++++++++++--------
 1 file changed, 37 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 50baac726e70..287442bbcb46 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -57,15 +57,15 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
 		u32 mask;
 
 		if (INTEL_GEN(dev_priv) >= 8)
-			mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
+			mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
 		else if (INTEL_GEN(dev_priv) >= 7)
-			mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
+			mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
 		else if (INTEL_GEN(dev_priv) >= 5)
-			mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
+			mask = intel_de_read(dev_priv, ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
 		else if (IS_G4X(dev_priv))
-			mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK;
+			mask = intel_de_read(dev_priv, DPFC_STATUS) & DPFC_COMP_SEG_MASK;
 		else
-			mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING |
+			mask = intel_de_read(dev_priv, FBC_STATUS) & (FBC_STAT_COMPRESSING |
 							FBC_STAT_COMPRESSED);
 
 		seq_printf(m, "Compressing: %s\n", yesno(mask));
@@ -99,12 +99,11 @@ static int i915_fbc_false_color_set(void *data, u64 val)
 
 	mutex_lock(&dev_priv->fbc.lock);
 
-	reg = I915_READ(ILK_DPFC_CONTROL);
+	reg = intel_de_read(dev_priv, ILK_DPFC_CONTROL);
 	dev_priv->fbc.false_color = val;
 
-	I915_WRITE(ILK_DPFC_CONTROL, val ?
-		   (reg | FBC_CTL_FALSE_COLOR) :
-		   (reg & ~FBC_CTL_FALSE_COLOR));
+	intel_de_write(dev_priv, ILK_DPFC_CONTROL,
+		       val ? (reg | FBC_CTL_FALSE_COLOR) : (reg & ~FBC_CTL_FALSE_COLOR));
 
 	mutex_unlock(&dev_priv->fbc.lock);
 	return 0;
@@ -130,7 +129,7 @@ static int i915_ips_status(struct seq_file *m, void *unused)
 	if (INTEL_GEN(dev_priv) >= 8) {
 		seq_puts(m, "Currently: unknown\n");
 	} else {
-		if (I915_READ(IPS_CTL) & IPS_ENABLE)
+		if (intel_de_read(dev_priv, IPS_CTL) & IPS_ENABLE)
 			seq_puts(m, "Currently: enabled\n");
 		else
 			seq_puts(m, "Currently: disabled\n");
@@ -152,16 +151,16 @@ static int i915_sr_status(struct seq_file *m, void *unused)
 	if (INTEL_GEN(dev_priv) >= 9)
 		/* no global SR status; inspect per-plane WM */;
 	else if (HAS_PCH_SPLIT(dev_priv))
-		sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
+		sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM1_LP_SR_EN;
 	else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
 		 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
-		sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
+		sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN;
 	else if (IS_I915GM(dev_priv))
-		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
+		sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN;
 	else if (IS_PINEVIEW(dev_priv))
-		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
+		sr_enabled = intel_de_read(dev_priv, DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
+		sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 
 	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
 
@@ -298,7 +297,8 @@ psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
 			"BUF_ON",
 			"TG_ON"
 		};
-		val = I915_READ(EDP_PSR2_STATUS(dev_priv->psr.transcoder));
+		val = intel_de_read(dev_priv,
+				    EDP_PSR2_STATUS(dev_priv->psr.transcoder));
 		status_val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
 			      EDP_PSR2_STATUS_STATE_SHIFT;
 		if (status_val < ARRAY_SIZE(live_status))
@@ -314,7 +314,8 @@ psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
 			"SRDOFFACK",
 			"SRDENT_ON",
 		};
-		val = I915_READ(EDP_PSR_STATUS(dev_priv->psr.transcoder));
+		val = intel_de_read(dev_priv,
+				    EDP_PSR_STATUS(dev_priv->psr.transcoder));
 		status_val = (val & EDP_PSR_STATUS_STATE_MASK) >>
 			      EDP_PSR_STATUS_STATE_SHIFT;
 		if (status_val < ARRAY_SIZE(live_status))
@@ -361,10 +362,12 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 	}
 
 	if (psr->psr2_enabled) {
-		val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
+		val = intel_de_read(dev_priv,
+				    EDP_PSR2_CTL(dev_priv->psr.transcoder));
 		enabled = val & EDP_PSR2_ENABLE;
 	} else {
-		val = I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder));
+		val = intel_de_read(dev_priv,
+				    EDP_PSR_CTL(dev_priv->psr.transcoder));
 		enabled = val & EDP_PSR_ENABLE;
 	}
 	seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
@@ -377,7 +380,8 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 	 * SKL+ Perf counter is reset to 0 everytime DC state is entered
 	 */
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-		val = I915_READ(EDP_PSR_PERF_CNT(dev_priv->psr.transcoder));
+		val = intel_de_read(dev_priv,
+				    EDP_PSR_PERF_CNT(dev_priv->psr.transcoder));
 		val &= EDP_PSR_PERF_CNT_MASK;
 		seq_printf(m, "Performance counter: %u\n", val);
 	}
@@ -397,8 +401,8 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 		 * frame boundary between register reads
 		 */
 		for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) {
-			val = I915_READ(PSR2_SU_STATUS(dev_priv->psr.transcoder,
-						       frame));
+			val = intel_de_read(dev_priv,
+					    PSR2_SU_STATUS(dev_priv->psr.transcoder, frame));
 			su_frames_val[frame / 3] = val;
 		}
 
@@ -518,7 +522,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 		 * reg for DC3CO debugging and validation,
 		 * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
 		 */
-		seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
+		seq_printf(m, "DC3CO count: %d\n",
+			   intel_de_read(dev_priv, DMC_DEBUG3));
 	} else {
 		dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
 						 SKL_CSR_DC3_DC5_COUNT;
@@ -526,14 +531,18 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 			dc6_reg = SKL_CSR_DC5_DC6_COUNT;
 	}
 
-	seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(dc5_reg));
+	seq_printf(m, "DC3 -> DC5 count: %d\n",
+		   intel_de_read(dev_priv, dc5_reg));
 	if (dc6_reg.reg)
-		seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(dc6_reg));
+		seq_printf(m, "DC5 -> DC6 count: %d\n",
+			   intel_de_read(dev_priv, dc6_reg));
 
 out:
-	seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
-	seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
-	seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
+	seq_printf(m, "program base: 0x%08x\n",
+		   intel_de_read(dev_priv, CSR_PROGRAM(0)));
+	seq_printf(m, "ssp base: 0x%08x\n",
+		   intel_de_read(dev_priv, CSR_SSP_BASE));
+	seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, CSR_HTP_SKL));
 
 	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
 
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [Intel-gfx] [PATCH 2/2] drm/i915/display: use intel_de_*() functions for register access
  2020-02-14 14:09 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: " Jani Nikula
@ 2020-02-14 14:24   ` Ville Syrjälä
  2020-02-14 14:27     ` Jani Nikula
  2020-02-18  9:31     ` Jani Nikula
  0 siblings, 2 replies; 7+ messages in thread
From: Ville Syrjälä @ 2020-02-14 14:24 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

On Fri, Feb 14, 2020 at 04:09:10PM +0200, Jani Nikula wrote:
> The implicit "dev_priv" local variable use has been a long-standing pain
> point in the register access macros I915_READ(), I915_WRITE(),
> POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
> 
> Replace them with the corresponding new display engine register
> accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
> intel_de_read_fw(), and intel_de_write_fw().
> 
> No functional changes.
> 
> Generated using the following semantic patch:
> 
> @@
> expression REG, OFFSET;
> @@
> - I915_READ(REG)
> + intel_de_read(dev_priv, REG)
> 
> @@
> expression REG, OFFSET;
> @@
> - POSTING_READ(REG)
> + intel_de_posting_read(dev_priv, REG)
> 
> @@
> expression REG, OFFSET;
> @@
> - I915_WRITE(REG, OFFSET)
> + intel_de_write(dev_priv, REG, OFFSET)
> 
> @@
> expression REG;
> @@
> - I915_READ_FW(REG)
> + intel_de_read_fw(dev_priv, REG)
> 
> @@
> expression REG, OFFSET;
> @@
> - I915_WRITE_FW(REG, OFFSET)
> + intel_de_write_fw(dev_priv, REG, OFFSET)
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  .../drm/i915/display/intel_display_debugfs.c  | 65 +++++++++++--------
>  1 file changed, 37 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 50baac726e70..287442bbcb46 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -57,15 +57,15 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
>  		u32 mask;
>  
>  		if (INTEL_GEN(dev_priv) >= 8)
> -			mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
> +			mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
>  		else if (INTEL_GEN(dev_priv) >= 7)
> -			mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
> +			mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
>  		else if (INTEL_GEN(dev_priv) >= 5)
> -			mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
> +			mask = intel_de_read(dev_priv, ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
>  		else if (IS_G4X(dev_priv))
> -			mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK;
> +			mask = intel_de_read(dev_priv, DPFC_STATUS) & DPFC_COMP_SEG_MASK;
>  		else
> -			mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING |
> +			mask = intel_de_read(dev_priv, FBC_STATUS) & (FBC_STAT_COMPRESSING |
>  							FBC_STAT_COMPRESSED);

Seesm to want some manual work to fix the alignment afterwards.
Probably should wrap after & actually.

>  
>  		seq_printf(m, "Compressing: %s\n", yesno(mask));
> @@ -99,12 +99,11 @@ static int i915_fbc_false_color_set(void *data, u64 val)
>  
>  	mutex_lock(&dev_priv->fbc.lock);
>  
> -	reg = I915_READ(ILK_DPFC_CONTROL);
> +	reg = intel_de_read(dev_priv, ILK_DPFC_CONTROL);
>  	dev_priv->fbc.false_color = val;
>  
> -	I915_WRITE(ILK_DPFC_CONTROL, val ?
> -		   (reg | FBC_CTL_FALSE_COLOR) :
> -		   (reg & ~FBC_CTL_FALSE_COLOR));
> +	intel_de_write(dev_priv, ILK_DPFC_CONTROL,
> +		       val ? (reg | FBC_CTL_FALSE_COLOR) : (reg & ~FBC_CTL_FALSE_COLOR));

Did we introduce some kind of rmw() variant? Could use it here to get
rid of this rather ugly construct.

For the series
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  
>  	mutex_unlock(&dev_priv->fbc.lock);
>  	return 0;
> @@ -130,7 +129,7 @@ static int i915_ips_status(struct seq_file *m, void *unused)
>  	if (INTEL_GEN(dev_priv) >= 8) {
>  		seq_puts(m, "Currently: unknown\n");
>  	} else {
> -		if (I915_READ(IPS_CTL) & IPS_ENABLE)
> +		if (intel_de_read(dev_priv, IPS_CTL) & IPS_ENABLE)
>  			seq_puts(m, "Currently: enabled\n");
>  		else
>  			seq_puts(m, "Currently: disabled\n");
> @@ -152,16 +151,16 @@ static int i915_sr_status(struct seq_file *m, void *unused)
>  	if (INTEL_GEN(dev_priv) >= 9)
>  		/* no global SR status; inspect per-plane WM */;
>  	else if (HAS_PCH_SPLIT(dev_priv))
> -		sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
> +		sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM1_LP_SR_EN;
>  	else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
>  		 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
> -		sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
> +		sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN;
>  	else if (IS_I915GM(dev_priv))
> -		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
> +		sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN;
>  	else if (IS_PINEVIEW(dev_priv))
> -		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
> +		sr_enabled = intel_de_read(dev_priv, DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
>  	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> -		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
> +		sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>  
>  	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
>  
> @@ -298,7 +297,8 @@ psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
>  			"BUF_ON",
>  			"TG_ON"
>  		};
> -		val = I915_READ(EDP_PSR2_STATUS(dev_priv->psr.transcoder));
> +		val = intel_de_read(dev_priv,
> +				    EDP_PSR2_STATUS(dev_priv->psr.transcoder));
>  		status_val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
>  			      EDP_PSR2_STATUS_STATE_SHIFT;
>  		if (status_val < ARRAY_SIZE(live_status))
> @@ -314,7 +314,8 @@ psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
>  			"SRDOFFACK",
>  			"SRDENT_ON",
>  		};
> -		val = I915_READ(EDP_PSR_STATUS(dev_priv->psr.transcoder));
> +		val = intel_de_read(dev_priv,
> +				    EDP_PSR_STATUS(dev_priv->psr.transcoder));
>  		status_val = (val & EDP_PSR_STATUS_STATE_MASK) >>
>  			      EDP_PSR_STATUS_STATE_SHIFT;
>  		if (status_val < ARRAY_SIZE(live_status))
> @@ -361,10 +362,12 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>  	}
>  
>  	if (psr->psr2_enabled) {
> -		val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
> +		val = intel_de_read(dev_priv,
> +				    EDP_PSR2_CTL(dev_priv->psr.transcoder));
>  		enabled = val & EDP_PSR2_ENABLE;
>  	} else {
> -		val = I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder));
> +		val = intel_de_read(dev_priv,
> +				    EDP_PSR_CTL(dev_priv->psr.transcoder));
>  		enabled = val & EDP_PSR_ENABLE;
>  	}
>  	seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
> @@ -377,7 +380,8 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>  	 * SKL+ Perf counter is reset to 0 everytime DC state is entered
>  	 */
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> -		val = I915_READ(EDP_PSR_PERF_CNT(dev_priv->psr.transcoder));
> +		val = intel_de_read(dev_priv,
> +				    EDP_PSR_PERF_CNT(dev_priv->psr.transcoder));
>  		val &= EDP_PSR_PERF_CNT_MASK;
>  		seq_printf(m, "Performance counter: %u\n", val);
>  	}
> @@ -397,8 +401,8 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>  		 * frame boundary between register reads
>  		 */
>  		for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) {
> -			val = I915_READ(PSR2_SU_STATUS(dev_priv->psr.transcoder,
> -						       frame));
> +			val = intel_de_read(dev_priv,
> +					    PSR2_SU_STATUS(dev_priv->psr.transcoder, frame));
>  			su_frames_val[frame / 3] = val;
>  		}
>  
> @@ -518,7 +522,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>  		 * reg for DC3CO debugging and validation,
>  		 * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
>  		 */
> -		seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
> +		seq_printf(m, "DC3CO count: %d\n",
> +			   intel_de_read(dev_priv, DMC_DEBUG3));
>  	} else {
>  		dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
>  						 SKL_CSR_DC3_DC5_COUNT;
> @@ -526,14 +531,18 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>  			dc6_reg = SKL_CSR_DC5_DC6_COUNT;
>  	}
>  
> -	seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(dc5_reg));
> +	seq_printf(m, "DC3 -> DC5 count: %d\n",
> +		   intel_de_read(dev_priv, dc5_reg));
>  	if (dc6_reg.reg)
> -		seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(dc6_reg));
> +		seq_printf(m, "DC5 -> DC6 count: %d\n",
> +			   intel_de_read(dev_priv, dc6_reg));
>  
>  out:
> -	seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
> -	seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
> -	seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
> +	seq_printf(m, "program base: 0x%08x\n",
> +		   intel_de_read(dev_priv, CSR_PROGRAM(0)));
> +	seq_printf(m, "ssp base: 0x%08x\n",
> +		   intel_de_read(dev_priv, CSR_SSP_BASE));
> +	seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, CSR_HTP_SKL));
>  
>  	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
>  
> -- 
> 2.20.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [Intel-gfx] [PATCH 2/2] drm/i915/display: use intel_de_*() functions for register access
  2020-02-14 14:24   ` Ville Syrjälä
@ 2020-02-14 14:27     ` Jani Nikula
  2020-02-18  9:31     ` Jani Nikula
  1 sibling, 0 replies; 7+ messages in thread
From: Jani Nikula @ 2020-02-14 14:27 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

On Fri, 14 Feb 2020, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Fri, Feb 14, 2020 at 04:09:10PM +0200, Jani Nikula wrote:
>> The implicit "dev_priv" local variable use has been a long-standing pain
>> point in the register access macros I915_READ(), I915_WRITE(),
>> POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
>> 
>> Replace them with the corresponding new display engine register
>> accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
>> intel_de_read_fw(), and intel_de_write_fw().
>> 
>> No functional changes.
>> 
>> Generated using the following semantic patch:
>> 
>> @@
>> expression REG, OFFSET;
>> @@
>> - I915_READ(REG)
>> + intel_de_read(dev_priv, REG)
>> 
>> @@
>> expression REG, OFFSET;
>> @@
>> - POSTING_READ(REG)
>> + intel_de_posting_read(dev_priv, REG)
>> 
>> @@
>> expression REG, OFFSET;
>> @@
>> - I915_WRITE(REG, OFFSET)
>> + intel_de_write(dev_priv, REG, OFFSET)
>> 
>> @@
>> expression REG;
>> @@
>> - I915_READ_FW(REG)
>> + intel_de_read_fw(dev_priv, REG)
>> 
>> @@
>> expression REG, OFFSET;
>> @@
>> - I915_WRITE_FW(REG, OFFSET)
>> + intel_de_write_fw(dev_priv, REG, OFFSET)
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  .../drm/i915/display/intel_display_debugfs.c  | 65 +++++++++++--------
>>  1 file changed, 37 insertions(+), 28 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> index 50baac726e70..287442bbcb46 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> @@ -57,15 +57,15 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
>>  		u32 mask;
>>  
>>  		if (INTEL_GEN(dev_priv) >= 8)
>> -			mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
>> +			mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
>>  		else if (INTEL_GEN(dev_priv) >= 7)
>> -			mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
>> +			mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
>>  		else if (INTEL_GEN(dev_priv) >= 5)
>> -			mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
>> +			mask = intel_de_read(dev_priv, ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
>>  		else if (IS_G4X(dev_priv))
>> -			mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK;
>> +			mask = intel_de_read(dev_priv, DPFC_STATUS) & DPFC_COMP_SEG_MASK;
>>  		else
>> -			mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING |
>> +			mask = intel_de_read(dev_priv, FBC_STATUS) & (FBC_STAT_COMPRESSING |
>>  							FBC_STAT_COMPRESSED);
>
> Seesm to want some manual work to fix the alignment afterwards.
> Probably should wrap after & actually.

Hmmh, was too hasty glancing over the cocci generated patch.

>
>>  
>>  		seq_printf(m, "Compressing: %s\n", yesno(mask));
>> @@ -99,12 +99,11 @@ static int i915_fbc_false_color_set(void *data, u64 val)
>>  
>>  	mutex_lock(&dev_priv->fbc.lock);
>>  
>> -	reg = I915_READ(ILK_DPFC_CONTROL);
>> +	reg = intel_de_read(dev_priv, ILK_DPFC_CONTROL);
>>  	dev_priv->fbc.false_color = val;
>>  
>> -	I915_WRITE(ILK_DPFC_CONTROL, val ?
>> -		   (reg | FBC_CTL_FALSE_COLOR) :
>> -		   (reg & ~FBC_CTL_FALSE_COLOR));
>> +	intel_de_write(dev_priv, ILK_DPFC_CONTROL,
>> +		       val ? (reg | FBC_CTL_FALSE_COLOR) : (reg & ~FBC_CTL_FALSE_COLOR));
>
> Did we introduce some kind of rmw() variant? Could use it here to get
> rid of this rather ugly construct.

I wonder if it would be possible to come up with a magic cocci spell
to convert those.

>
> For the series
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Thanks.

BR,
Jani.

>
>>  
>>  	mutex_unlock(&dev_priv->fbc.lock);
>>  	return 0;
>> @@ -130,7 +129,7 @@ static int i915_ips_status(struct seq_file *m, void *unused)
>>  	if (INTEL_GEN(dev_priv) >= 8) {
>>  		seq_puts(m, "Currently: unknown\n");
>>  	} else {
>> -		if (I915_READ(IPS_CTL) & IPS_ENABLE)
>> +		if (intel_de_read(dev_priv, IPS_CTL) & IPS_ENABLE)
>>  			seq_puts(m, "Currently: enabled\n");
>>  		else
>>  			seq_puts(m, "Currently: disabled\n");
>> @@ -152,16 +151,16 @@ static int i915_sr_status(struct seq_file *m, void *unused)
>>  	if (INTEL_GEN(dev_priv) >= 9)
>>  		/* no global SR status; inspect per-plane WM */;
>>  	else if (HAS_PCH_SPLIT(dev_priv))
>> -		sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
>> +		sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM1_LP_SR_EN;
>>  	else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
>>  		 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
>> -		sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
>> +		sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN;
>>  	else if (IS_I915GM(dev_priv))
>> -		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
>> +		sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN;
>>  	else if (IS_PINEVIEW(dev_priv))
>> -		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
>> +		sr_enabled = intel_de_read(dev_priv, DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
>>  	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>> -		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>> +		sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>>  
>>  	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
>>  
>> @@ -298,7 +297,8 @@ psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
>>  			"BUF_ON",
>>  			"TG_ON"
>>  		};
>> -		val = I915_READ(EDP_PSR2_STATUS(dev_priv->psr.transcoder));
>> +		val = intel_de_read(dev_priv,
>> +				    EDP_PSR2_STATUS(dev_priv->psr.transcoder));
>>  		status_val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
>>  			      EDP_PSR2_STATUS_STATE_SHIFT;
>>  		if (status_val < ARRAY_SIZE(live_status))
>> @@ -314,7 +314,8 @@ psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
>>  			"SRDOFFACK",
>>  			"SRDENT_ON",
>>  		};
>> -		val = I915_READ(EDP_PSR_STATUS(dev_priv->psr.transcoder));
>> +		val = intel_de_read(dev_priv,
>> +				    EDP_PSR_STATUS(dev_priv->psr.transcoder));
>>  		status_val = (val & EDP_PSR_STATUS_STATE_MASK) >>
>>  			      EDP_PSR_STATUS_STATE_SHIFT;
>>  		if (status_val < ARRAY_SIZE(live_status))
>> @@ -361,10 +362,12 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>>  	}
>>  
>>  	if (psr->psr2_enabled) {
>> -		val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
>> +		val = intel_de_read(dev_priv,
>> +				    EDP_PSR2_CTL(dev_priv->psr.transcoder));
>>  		enabled = val & EDP_PSR2_ENABLE;
>>  	} else {
>> -		val = I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder));
>> +		val = intel_de_read(dev_priv,
>> +				    EDP_PSR_CTL(dev_priv->psr.transcoder));
>>  		enabled = val & EDP_PSR_ENABLE;
>>  	}
>>  	seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
>> @@ -377,7 +380,8 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>>  	 * SKL+ Perf counter is reset to 0 everytime DC state is entered
>>  	 */
>>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
>> -		val = I915_READ(EDP_PSR_PERF_CNT(dev_priv->psr.transcoder));
>> +		val = intel_de_read(dev_priv,
>> +				    EDP_PSR_PERF_CNT(dev_priv->psr.transcoder));
>>  		val &= EDP_PSR_PERF_CNT_MASK;
>>  		seq_printf(m, "Performance counter: %u\n", val);
>>  	}
>> @@ -397,8 +401,8 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>>  		 * frame boundary between register reads
>>  		 */
>>  		for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) {
>> -			val = I915_READ(PSR2_SU_STATUS(dev_priv->psr.transcoder,
>> -						       frame));
>> +			val = intel_de_read(dev_priv,
>> +					    PSR2_SU_STATUS(dev_priv->psr.transcoder, frame));
>>  			su_frames_val[frame / 3] = val;
>>  		}
>>  
>> @@ -518,7 +522,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>>  		 * reg for DC3CO debugging and validation,
>>  		 * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
>>  		 */
>> -		seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
>> +		seq_printf(m, "DC3CO count: %d\n",
>> +			   intel_de_read(dev_priv, DMC_DEBUG3));
>>  	} else {
>>  		dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
>>  						 SKL_CSR_DC3_DC5_COUNT;
>> @@ -526,14 +531,18 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>>  			dc6_reg = SKL_CSR_DC5_DC6_COUNT;
>>  	}
>>  
>> -	seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(dc5_reg));
>> +	seq_printf(m, "DC3 -> DC5 count: %d\n",
>> +		   intel_de_read(dev_priv, dc5_reg));
>>  	if (dc6_reg.reg)
>> -		seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(dc6_reg));
>> +		seq_printf(m, "DC5 -> DC6 count: %d\n",
>> +			   intel_de_read(dev_priv, dc6_reg));
>>  
>>  out:
>> -	seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
>> -	seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
>> -	seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
>> +	seq_printf(m, "program base: 0x%08x\n",
>> +		   intel_de_read(dev_priv, CSR_PROGRAM(0)));
>> +	seq_printf(m, "ssp base: 0x%08x\n",
>> +		   intel_de_read(dev_priv, CSR_SSP_BASE));
>> +	seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, CSR_HTP_SKL));
>>  
>>  	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
>>  
>> -- 
>> 2.20.1
>> 
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/csr: use intel_de_*() functions for register access
  2020-02-14 14:09 [Intel-gfx] [PATCH 1/2] drm/i915/csr: use intel_de_*() functions for register access Jani Nikula
  2020-02-14 14:09 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: " Jani Nikula
@ 2020-02-14 20:54 ` " Patchwork
  2020-02-18  2:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2020-02-14 20:54 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/2] drm/i915/csr: use intel_de_*() functions for register access
URL   : https://patchwork.freedesktop.org/series/73473/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7942 -> Patchwork_16575
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/index.html

Known issues
------------

  Here are the changes found in Patchwork_16575 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_close_race@basic-threads:
    - fi-byt-n2820:       [PASS][1] -> [INCOMPLETE][2] ([i915#45])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/fi-byt-n2820/igt@gem_close_race@basic-threads.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/fi-byt-n2820/igt@gem_close_race@basic-threads.html

  * igt@i915_selftest@live_execlists:
    - fi-icl-y:           [PASS][3] -> [DMESG-FAIL][4] ([fdo#108569])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/fi-icl-y/igt@i915_selftest@live_execlists.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/fi-icl-y/igt@i915_selftest@live_execlists.html

  * igt@i915_selftest@live_gtt:
    - fi-skl-6600u:       [PASS][5] -> [TIMEOUT][6] ([fdo#111732] / [fdo#112271])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/fi-skl-6600u/igt@i915_selftest@live_gtt.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/fi-skl-6600u/igt@i915_selftest@live_gtt.html
    - fi-glk-dsi:         [PASS][7] -> [TIMEOUT][8] ([fdo#112271] / [i915#690])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/fi-glk-dsi/igt@i915_selftest@live_gtt.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/fi-glk-dsi/igt@i915_selftest@live_gtt.html

  
#### Possible fixes ####

  * igt@i915_selftest@live_gem_contexts:
    - fi-cfl-8700k:       [INCOMPLETE][9] ([i915#424]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html

  
#### Warnings ####

  * igt@gem_close_race@basic-threads:
    - fi-byt-j1900:       [INCOMPLETE][11] ([i915#45]) -> [TIMEOUT][12] ([fdo#112271] / [i915#1084] / [i915#816])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/fi-byt-j1900/igt@gem_close_race@basic-threads.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/fi-byt-j1900/igt@gem_close_race@basic-threads.html

  
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#111732]: https://bugs.freedesktop.org/show_bug.cgi?id=111732
  [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
  [i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084
  [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
  [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
  [i915#690]: https://gitlab.freedesktop.org/drm/intel/issues/690
  [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816


Participating hosts (47 -> 43)
------------------------------

  Additional (4): fi-bsw-kefka fi-blb-e6850 fi-cfl-8109u fi-ilk-650 
  Missing    (8): fi-ilk-m540 fi-ehl-1 fi-hsw-4200u fi-bsw-n3050 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7942 -> Patchwork_16575

  CI-20190529: 20190529
  CI_DRM_7942: f4805f5a516d0a107438ff0f236c9f4187434819 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5442: 3f6080996885b997685f08ecb8b416b2dc485290 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16575: 728c79fc6b4b6c0ceb4e143a76852993a5983fbc @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

728c79fc6b4b drm/i915/display: use intel_de_*() functions for register access
5367ca72657d drm/i915/csr: use intel_de_*() functions for register access

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/csr: use intel_de_*() functions for register access
  2020-02-14 14:09 [Intel-gfx] [PATCH 1/2] drm/i915/csr: use intel_de_*() functions for register access Jani Nikula
  2020-02-14 14:09 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: " Jani Nikula
  2020-02-14 20:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/csr: " Patchwork
@ 2020-02-18  2:09 ` " Patchwork
  2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2020-02-18  2:09 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/2] drm/i915/csr: use intel_de_*() functions for register access
URL   : https://patchwork.freedesktop.org/series/73473/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7942_full -> Patchwork_16575_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_16575_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@gem_ctx_persistence@close-replace-race}:
    - shard-apl:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-apl7/igt@gem_ctx_persistence@close-replace-race.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-apl2/igt@gem_ctx_persistence@close-replace-race.html

  
Known issues
------------

  Here are the changes found in Patchwork_16575_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#112080]) +10 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-iclb1/igt@gem_busy@busy-vcs1.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-iclb3/igt@gem_busy@busy-vcs1.html

  * igt@gem_exec_balancer@hang:
    - shard-tglb:         [PASS][5] -> [TIMEOUT][6] ([fdo#112271])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-tglb8/igt@gem_exec_balancer@hang.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-tglb7/igt@gem_exec_balancer@hang.html

  * igt@gem_exec_parallel@rcs0-fds:
    - shard-hsw:          [PASS][7] -> [INCOMPLETE][8] ([i915#61])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-hsw4/igt@gem_exec_parallel@rcs0-fds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-hsw7/igt@gem_exec_parallel@rcs0-fds.html

  * igt@gem_exec_schedule@out-order-bsd2:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#109276]) +20 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-iclb1/igt@gem_exec_schedule@out-order-bsd2.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-iclb7/igt@gem_exec_schedule@out-order-bsd2.html

  * igt@gem_exec_schedule@wide-bsd:
    - shard-iclb:         [PASS][11] -> [SKIP][12] ([fdo#112146]) +5 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-iclb3/igt@gem_exec_schedule@wide-bsd.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-iclb4/igt@gem_exec_schedule@wide-bsd.html

  * igt@gem_partial_pwrite_pread@writes-after-reads:
    - shard-hsw:          [PASS][13] -> [FAIL][14] ([i915#694])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-hsw7/igt@gem_partial_pwrite_pread@writes-after-reads.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-hsw4/igt@gem_partial_pwrite_pread@writes-after-reads.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +5 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-apl6/igt@gem_workarounds@suspend-resume-context.html

  * igt@i915_pm_dc@dc5-dpms:
    - shard-iclb:         [PASS][17] -> [FAIL][18] ([i915#447])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-iclb1/igt@i915_pm_dc@dc5-dpms.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html

  * igt@i915_pm_rps@reset:
    - shard-iclb:         [PASS][19] -> [FAIL][20] ([i915#413])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-iclb4/igt@i915_pm_rps@reset.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-iclb8/igt@i915_pm_rps@reset.html

  * igt@i915_suspend@forcewake:
    - shard-kbl:          [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +4 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-kbl7/igt@i915_suspend@forcewake.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-kbl7/igt@i915_suspend@forcewake.html

  * igt@kms_cursor_crc@pipe-a-cursor-128x128-sliding:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([i915#54])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-skl7/igt@kms_cursor_crc@pipe-a-cursor-128x128-sliding.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-128x128-sliding.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-hsw:          [PASS][25] -> [FAIL][26] ([i915#46])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-hsw4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-hsw1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-apl:          [PASS][27] -> [FAIL][28] ([i915#79])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-apl8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-apl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
    - shard-snb:          [PASS][29] -> [SKIP][30] ([fdo#109271])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-snb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-snb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-tglb:         [PASS][31] -> [SKIP][32] ([i915#668]) +5 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-tglb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-tglb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-skl:          [PASS][33] -> [INCOMPLETE][34] ([i915#69]) +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-skl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-skl5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [PASS][35] -> [FAIL][36] ([fdo#108145])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][37] -> [FAIL][38] ([fdo#108145] / [i915#265]) +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-glk:          [PASS][39] -> [FAIL][40] ([i915#899])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-glk8/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-glk6/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@perf@oa-exponents:
    - shard-hsw:          [PASS][41] -> [FAIL][42] ([i915#84])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-hsw2/igt@perf@oa-exponents.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-hsw7/igt@perf@oa-exponents.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@vcs1-none:
    - shard-iclb:         [SKIP][43] ([fdo#112080]) -> [PASS][44] +11 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-iclb7/igt@gem_ctx_isolation@vcs1-none.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-iclb4/igt@gem_ctx_isolation@vcs1-none.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [SKIP][45] ([fdo#110841]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [SKIP][47] ([fdo#110854]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-iclb8/igt@gem_exec_balancer@smoke.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-iclb1/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_schedule@pi-common-bsd:
    - shard-iclb:         [SKIP][49] ([i915#677]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-iclb1/igt@gem_exec_schedule@pi-common-bsd.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-iclb7/igt@gem_exec_schedule@pi-common-bsd.html

  * igt@gem_exec_schedule@preempt-contexts-bsd2:
    - shard-iclb:         [SKIP][51] ([fdo#109276]) -> [PASS][52] +18 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-iclb7/igt@gem_exec_schedule@preempt-contexts-bsd2.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-iclb4/igt@gem_exec_schedule@preempt-contexts-bsd2.html

  * igt@gem_exec_schedule@reorder-wide-bsd:
    - shard-iclb:         [SKIP][53] ([fdo#112146]) -> [PASS][54] +1 similar issue
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-iclb1/igt@gem_exec_schedule@reorder-wide-bsd.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-iclb3/igt@gem_exec_schedule@reorder-wide-bsd.html

  * igt@gem_partial_pwrite_pread@write-display:
    - shard-hsw:          [FAIL][55] ([i915#694]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-hsw4/igt@gem_partial_pwrite_pread@write-display.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-hsw1/igt@gem_partial_pwrite_pread@write-display.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [FAIL][57] ([i915#79]) -> [PASS][58] +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-skl1/igt@kms_flip@flip-vs-expired-vblank.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html

  * {igt@kms_hdr@bpc-switch-suspend}:
    - shard-skl:          [FAIL][59] ([i915#1188]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-skl5/igt@kms_hdr@bpc-switch-suspend.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-skl4/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-apl:          [DMESG-WARN][61] ([i915#180]) -> [PASS][62] +3 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
    - shard-kbl:          [INCOMPLETE][63] ([fdo#103665]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
    - shard-kbl:          [DMESG-WARN][65] ([i915#180]) -> [PASS][66] +5 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html

  * igt@kms_plane_lowres@pipe-a-tiling-y:
    - shard-glk:          [FAIL][67] ([i915#899]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-glk7/igt@kms_plane_lowres@pipe-a-tiling-y.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-glk5/igt@kms_plane_lowres@pipe-a-tiling-y.html

  * igt@perf_pmu@cpu-hotplug:
    - shard-hsw:          [INCOMPLETE][69] ([i915#1176] / [i915#61]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-hsw5/igt@perf_pmu@cpu-hotplug.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-hsw8/igt@perf_pmu@cpu-hotplug.html

  * igt@prime_mmap_coherency@ioctl-errors:
    - shard-hsw:          [FAIL][71] ([i915#831]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-hsw7/igt@prime_mmap_coherency@ioctl-errors.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-hsw4/igt@prime_mmap_coherency@ioctl-errors.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [SKIP][73] ([fdo#112080]) -> [FAIL][74] ([IGT#28])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-iclb3/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@gem_tiled_blits@interruptible:
    - shard-hsw:          [FAIL][75] ([i915#818]) -> [FAIL][76] ([i915#694])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-hsw6/igt@gem_tiled_blits@interruptible.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-hsw2/igt@gem_tiled_blits@interruptible.html

  * igt@gem_tiled_blits@normal:
    - shard-hsw:          [FAIL][77] ([i915#694]) -> [FAIL][78] ([i915#818])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-hsw5/igt@gem_tiled_blits@normal.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-hsw8/igt@gem_tiled_blits@normal.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-tglb:         [FAIL][79] ([i915#454]) -> [SKIP][80] ([i915#468])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-tglb8/igt@i915_pm_dc@dc6-psr.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-tglb2/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rpm@gem-evict-pwrite:
    - shard-snb:          [INCOMPLETE][81] ([i915#82]) -> [SKIP][82] ([fdo#109271])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-snb5/igt@i915_pm_rpm@gem-evict-pwrite.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-snb4/igt@i915_pm_rpm@gem-evict-pwrite.html

  * igt@runner@aborted:
    - shard-hsw:          ([FAIL][83], [FAIL][84]) ([i915#1176] / [i915#974]) -> ([FAIL][85], [FAIL][86]) ([fdo#111012] / [i915#694] / [i915#974])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-hsw5/igt@runner@aborted.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7942/shard-hsw6/igt@runner@aborted.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-hsw7/igt@runner@aborted.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/shard-hsw7/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
  [fdo#111012]: https://bugs.freedesktop.org/show_bug.cgi?id=111012
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
  [i915#1176]: https://gitlab.freedesktop.org/drm/intel/issues/1176
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
  [i915#447]: https://gitlab.freedesktop.org/drm/intel/issues/447
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46
  [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
  [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
  [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
  [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
  [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#818]: https://gitlab.freedesktop.org/drm/intel/issues/818
  [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
  [i915#831]: https://gitlab.freedesktop.org/drm/intel/issues/831
  [i915#84]: https://gitlab.freedesktop.org/drm/intel/issues/84
  [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
  [i915#974]: https://gitlab.freedesktop.org/drm/intel/issues/974


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7942 -> Patchwork_16575

  CI-20190529: 20190529
  CI_DRM_7942: f4805f5a516d0a107438ff0f236c9f4187434819 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5442: 3f6080996885b997685f08ecb8b416b2dc485290 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16575: 728c79fc6b4b6c0ceb4e143a76852993a5983fbc @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16575/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [Intel-gfx] [PATCH 2/2] drm/i915/display: use intel_de_*() functions for register access
  2020-02-14 14:24   ` Ville Syrjälä
  2020-02-14 14:27     ` Jani Nikula
@ 2020-02-18  9:31     ` Jani Nikula
  1 sibling, 0 replies; 7+ messages in thread
From: Jani Nikula @ 2020-02-18  9:31 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

On Fri, 14 Feb 2020, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Fri, Feb 14, 2020 at 04:09:10PM +0200, Jani Nikula wrote:
>> The implicit "dev_priv" local variable use has been a long-standing pain
>> point in the register access macros I915_READ(), I915_WRITE(),
>> POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
>> 
>> Replace them with the corresponding new display engine register
>> accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
>> intel_de_read_fw(), and intel_de_write_fw().
>> 
>> No functional changes.
>> 
>> Generated using the following semantic patch:
>> 
>> @@
>> expression REG, OFFSET;
>> @@
>> - I915_READ(REG)
>> + intel_de_read(dev_priv, REG)
>> 
>> @@
>> expression REG, OFFSET;
>> @@
>> - POSTING_READ(REG)
>> + intel_de_posting_read(dev_priv, REG)
>> 
>> @@
>> expression REG, OFFSET;
>> @@
>> - I915_WRITE(REG, OFFSET)
>> + intel_de_write(dev_priv, REG, OFFSET)
>> 
>> @@
>> expression REG;
>> @@
>> - I915_READ_FW(REG)
>> + intel_de_read_fw(dev_priv, REG)
>> 
>> @@
>> expression REG, OFFSET;
>> @@
>> - I915_WRITE_FW(REG, OFFSET)
>> + intel_de_write_fw(dev_priv, REG, OFFSET)
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  .../drm/i915/display/intel_display_debugfs.c  | 65 +++++++++++--------
>>  1 file changed, 37 insertions(+), 28 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> index 50baac726e70..287442bbcb46 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> @@ -57,15 +57,15 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
>>  		u32 mask;
>>  
>>  		if (INTEL_GEN(dev_priv) >= 8)
>> -			mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
>> +			mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
>>  		else if (INTEL_GEN(dev_priv) >= 7)
>> -			mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
>> +			mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
>>  		else if (INTEL_GEN(dev_priv) >= 5)
>> -			mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
>> +			mask = intel_de_read(dev_priv, ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
>>  		else if (IS_G4X(dev_priv))
>> -			mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK;
>> +			mask = intel_de_read(dev_priv, DPFC_STATUS) & DPFC_COMP_SEG_MASK;
>>  		else
>> -			mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING |
>> +			mask = intel_de_read(dev_priv, FBC_STATUS) & (FBC_STAT_COMPRESSING |
>>  							FBC_STAT_COMPRESSED);
>
> Seesm to want some manual work to fix the alignment afterwards.
> Probably should wrap after & actually.

Thanks for the review, pushed with this whitespace change applied.

BR,
Jani.

>
>>  
>>  		seq_printf(m, "Compressing: %s\n", yesno(mask));
>> @@ -99,12 +99,11 @@ static int i915_fbc_false_color_set(void *data, u64 val)
>>  
>>  	mutex_lock(&dev_priv->fbc.lock);
>>  
>> -	reg = I915_READ(ILK_DPFC_CONTROL);
>> +	reg = intel_de_read(dev_priv, ILK_DPFC_CONTROL);
>>  	dev_priv->fbc.false_color = val;
>>  
>> -	I915_WRITE(ILK_DPFC_CONTROL, val ?
>> -		   (reg | FBC_CTL_FALSE_COLOR) :
>> -		   (reg & ~FBC_CTL_FALSE_COLOR));
>> +	intel_de_write(dev_priv, ILK_DPFC_CONTROL,
>> +		       val ? (reg | FBC_CTL_FALSE_COLOR) : (reg & ~FBC_CTL_FALSE_COLOR));
>
> Did we introduce some kind of rmw() variant? Could use it here to get
> rid of this rather ugly construct.
>
> For the series
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>>  
>>  	mutex_unlock(&dev_priv->fbc.lock);
>>  	return 0;
>> @@ -130,7 +129,7 @@ static int i915_ips_status(struct seq_file *m, void *unused)
>>  	if (INTEL_GEN(dev_priv) >= 8) {
>>  		seq_puts(m, "Currently: unknown\n");
>>  	} else {
>> -		if (I915_READ(IPS_CTL) & IPS_ENABLE)
>> +		if (intel_de_read(dev_priv, IPS_CTL) & IPS_ENABLE)
>>  			seq_puts(m, "Currently: enabled\n");
>>  		else
>>  			seq_puts(m, "Currently: disabled\n");
>> @@ -152,16 +151,16 @@ static int i915_sr_status(struct seq_file *m, void *unused)
>>  	if (INTEL_GEN(dev_priv) >= 9)
>>  		/* no global SR status; inspect per-plane WM */;
>>  	else if (HAS_PCH_SPLIT(dev_priv))
>> -		sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
>> +		sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM1_LP_SR_EN;
>>  	else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
>>  		 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
>> -		sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
>> +		sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN;
>>  	else if (IS_I915GM(dev_priv))
>> -		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
>> +		sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN;
>>  	else if (IS_PINEVIEW(dev_priv))
>> -		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
>> +		sr_enabled = intel_de_read(dev_priv, DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
>>  	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>> -		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>> +		sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>>  
>>  	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
>>  
>> @@ -298,7 +297,8 @@ psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
>>  			"BUF_ON",
>>  			"TG_ON"
>>  		};
>> -		val = I915_READ(EDP_PSR2_STATUS(dev_priv->psr.transcoder));
>> +		val = intel_de_read(dev_priv,
>> +				    EDP_PSR2_STATUS(dev_priv->psr.transcoder));
>>  		status_val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
>>  			      EDP_PSR2_STATUS_STATE_SHIFT;
>>  		if (status_val < ARRAY_SIZE(live_status))
>> @@ -314,7 +314,8 @@ psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
>>  			"SRDOFFACK",
>>  			"SRDENT_ON",
>>  		};
>> -		val = I915_READ(EDP_PSR_STATUS(dev_priv->psr.transcoder));
>> +		val = intel_de_read(dev_priv,
>> +				    EDP_PSR_STATUS(dev_priv->psr.transcoder));
>>  		status_val = (val & EDP_PSR_STATUS_STATE_MASK) >>
>>  			      EDP_PSR_STATUS_STATE_SHIFT;
>>  		if (status_val < ARRAY_SIZE(live_status))
>> @@ -361,10 +362,12 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>>  	}
>>  
>>  	if (psr->psr2_enabled) {
>> -		val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
>> +		val = intel_de_read(dev_priv,
>> +				    EDP_PSR2_CTL(dev_priv->psr.transcoder));
>>  		enabled = val & EDP_PSR2_ENABLE;
>>  	} else {
>> -		val = I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder));
>> +		val = intel_de_read(dev_priv,
>> +				    EDP_PSR_CTL(dev_priv->psr.transcoder));
>>  		enabled = val & EDP_PSR_ENABLE;
>>  	}
>>  	seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
>> @@ -377,7 +380,8 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>>  	 * SKL+ Perf counter is reset to 0 everytime DC state is entered
>>  	 */
>>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
>> -		val = I915_READ(EDP_PSR_PERF_CNT(dev_priv->psr.transcoder));
>> +		val = intel_de_read(dev_priv,
>> +				    EDP_PSR_PERF_CNT(dev_priv->psr.transcoder));
>>  		val &= EDP_PSR_PERF_CNT_MASK;
>>  		seq_printf(m, "Performance counter: %u\n", val);
>>  	}
>> @@ -397,8 +401,8 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>>  		 * frame boundary between register reads
>>  		 */
>>  		for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) {
>> -			val = I915_READ(PSR2_SU_STATUS(dev_priv->psr.transcoder,
>> -						       frame));
>> +			val = intel_de_read(dev_priv,
>> +					    PSR2_SU_STATUS(dev_priv->psr.transcoder, frame));
>>  			su_frames_val[frame / 3] = val;
>>  		}
>>  
>> @@ -518,7 +522,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>>  		 * reg for DC3CO debugging and validation,
>>  		 * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
>>  		 */
>> -		seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
>> +		seq_printf(m, "DC3CO count: %d\n",
>> +			   intel_de_read(dev_priv, DMC_DEBUG3));
>>  	} else {
>>  		dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
>>  						 SKL_CSR_DC3_DC5_COUNT;
>> @@ -526,14 +531,18 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>>  			dc6_reg = SKL_CSR_DC5_DC6_COUNT;
>>  	}
>>  
>> -	seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(dc5_reg));
>> +	seq_printf(m, "DC3 -> DC5 count: %d\n",
>> +		   intel_de_read(dev_priv, dc5_reg));
>>  	if (dc6_reg.reg)
>> -		seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(dc6_reg));
>> +		seq_printf(m, "DC5 -> DC6 count: %d\n",
>> +			   intel_de_read(dev_priv, dc6_reg));
>>  
>>  out:
>> -	seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
>> -	seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
>> -	seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
>> +	seq_printf(m, "program base: 0x%08x\n",
>> +		   intel_de_read(dev_priv, CSR_PROGRAM(0)));
>> +	seq_printf(m, "ssp base: 0x%08x\n",
>> +		   intel_de_read(dev_priv, CSR_SSP_BASE));
>> +	seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, CSR_HTP_SKL));
>>  
>>  	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
>>  
>> -- 
>> 2.20.1
>> 
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, back to index

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-14 14:09 [Intel-gfx] [PATCH 1/2] drm/i915/csr: use intel_de_*() functions for register access Jani Nikula
2020-02-14 14:09 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: " Jani Nikula
2020-02-14 14:24   ` Ville Syrjälä
2020-02-14 14:27     ` Jani Nikula
2020-02-18  9:31     ` Jani Nikula
2020-02-14 20:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/csr: " Patchwork
2020-02-18  2:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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