* [Intel-gfx] [PATCH 1/2] drm/i915: Split _MMIO() for _PORT3()/_PIPE3()
@ 2023-01-31 19:15 Lucas De Marchi
2023-01-31 19:15 ` [Intel-gfx] [PATCH 2/2] drm/i915: Move common mmio base out of private macros Lucas De Marchi
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Lucas De Marchi @ 2023-01-31 19:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
In some cases it might be preferred to use _MMIO() and _PORT3()/_PIPE3()
separately, so a common mmio base can be added to all cases. In order to
help removing the implicit dev_priv from some macros, this can be used
in future patches to pass for example DISPLAY_MMIO_BASE().
Declare _MMIO_PIPE3() and _MMIO_PORT3() like then non-3 variants.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_reg_defs.h | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
index 755c1ea8225c..477704eeea0f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
@@ -16,22 +16,23 @@
* Named helper wrappers around _PICK_EVEN() and _PICK_EVEN_2RANGES().
*/
#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
+#define _PIPE3(pipe, a, b, c) _PICK_EVEN_2RANGES(pipe, 1, a, a, b, c)
#define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
+#define _PORT3(port, a, b, c) _PICK_EVEN_2RANGES(port, 1, a, a, b, c)
#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
#define _PHY(phy, a, b) _PICK_EVEN(phy, a, b)
#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
+#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PIPE3(pipe, a, b, c))
#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
+#define _MMIO_PORT3(port, a, b, c) _MMIO(_PORT3(port, a, b, c))
#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
#define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b))
-#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK_EVEN_2RANGES(pipe, 1, a, a, b, c))
-#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK_EVEN_2RANGES(pipe, 1, a, a, b, c))
-
/*
* Device info offset array based helpers for groups of registers with unevenly
* spaced base offsets.
--
2.39.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915: Move common mmio base out of private macros
2023-01-31 19:15 [Intel-gfx] [PATCH 1/2] drm/i915: Split _MMIO() for _PORT3()/_PIPE3() Lucas De Marchi
@ 2023-01-31 19:15 ` Lucas De Marchi
2023-02-01 9:59 ` Jani Nikula
2023-01-31 20:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Split _MMIO() for _PORT3()/_PIPE3() Patchwork
2023-01-31 21:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2 siblings, 1 reply; 9+ messages in thread
From: Lucas De Marchi @ 2023-01-31 19:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
Instead of using the common DISPLAY_MMIO_BASE(dev_priv) in all single
macros, only use them in the macros that are to be used outside the
header. This reduces the use of the implicit dev_priv, making it easier
to remove it later.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 73 ++++++++++++++++++---------------
1 file changed, 39 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 943db8ec63f8..1cde3bcb9c88 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1182,9 +1182,9 @@
#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
-#define GT_PARITY_ERROR(dev_priv) \
+#define GT_PARITY_ERROR(__i915) \
(GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
- (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
+ (IS_HASWELL(__i915) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
/* These are all the "old" interrupts */
#define ILK_BSD_USER_INTERRUPT (1 << 5)
@@ -1403,10 +1403,11 @@
/*
* Clock control & power management
*/
-#define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
-#define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
-#define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
-#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
+#define _DPLL_A 0x6014
+#define _DPLL_B 0x6018
+#define _CHV_DPLL_C 0x6030
+#define DPLL(pipe) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
+ _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C))
#define VGA0 _MMIO(0x6000)
#define VGA1 _MMIO(0x6004)
@@ -1502,10 +1503,11 @@
#define SDVO_MULTIPLIER_SHIFT_HIRES 4
#define SDVO_MULTIPLIER_SHIFT_VGA 0
-#define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
-#define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
-#define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
-#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
+#define _DPLL_A_MD 0x601c
+#define _DPLL_B_MD 0x6020
+#define _CHV_DPLL_C_MD 0x603c
+#define DPLL_MD(pipe) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
+ _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD))
/*
* UDI pixel divider, controlling how many pixels are stuffed into a packet.
@@ -3323,42 +3325,45 @@
* is 20 bytes in each direction, hence the 5 fixed
* data registers
*/
-#define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
-#define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
-
-#define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
-#define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
-
-#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
-#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
+#define _DPA_AUX_CH_CTL 0x64010
+#define _DPA_AUX_CH_DATA1 0x64014
+#define _DPB_AUX_CH_CTL 0x64110
+#define _DPB_AUX_CH_DATA1 0x64114
+#define DP_AUX_CH_CTL(aux_ch) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
+ _PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL))
+#define DP_AUX_CH_DATA(aux_ch, i) \
+ _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
+ _PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
#define _XELPDP_USBC1_AUX_CH_CTL 0x16F210
#define _XELPDP_USBC2_AUX_CH_CTL 0x16F410
#define _XELPDP_USBC3_AUX_CH_CTL 0x16F610
#define _XELPDP_USBC4_AUX_CH_CTL 0x16F810
-#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
- _DPA_AUX_CH_CTL, \
- _DPB_AUX_CH_CTL, \
- 0, /* port/aux_ch C is non-existent */ \
- _XELPDP_USBC1_AUX_CH_CTL, \
- _XELPDP_USBC2_AUX_CH_CTL, \
- _XELPDP_USBC3_AUX_CH_CTL, \
- _XELPDP_USBC4_AUX_CH_CTL))
+#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
+ _PICK(aux_ch, \
+ _DPA_AUX_CH_CTL, \
+ _DPB_AUX_CH_CTL, \
+ 0, /* port/aux_ch C is non-existent */ \
+ _XELPDP_USBC1_AUX_CH_CTL, \
+ _XELPDP_USBC2_AUX_CH_CTL, \
+ _XELPDP_USBC3_AUX_CH_CTL, \
+ _XELPDP_USBC4_AUX_CH_CTL))
#define _XELPDP_USBC1_AUX_CH_DATA1 0x16F214
#define _XELPDP_USBC2_AUX_CH_DATA1 0x16F414
#define _XELPDP_USBC3_AUX_CH_DATA1 0x16F614
#define _XELPDP_USBC4_AUX_CH_DATA1 0x16F814
-#define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \
- _DPA_AUX_CH_DATA1, \
- _DPB_AUX_CH_DATA1, \
- 0, /* port/aux_ch C is non-existent */ \
- _XELPDP_USBC1_AUX_CH_DATA1, \
- _XELPDP_USBC2_AUX_CH_DATA1, \
- _XELPDP_USBC3_AUX_CH_DATA1, \
- _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
+#define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
+ _PICK(aux_ch, \
+ _DPA_AUX_CH_DATA1, \
+ _DPB_AUX_CH_DATA1, \
+ 0, /* port/aux_ch C is non-existent */ \
+ _XELPDP_USBC1_AUX_CH_DATA1, \
+ _XELPDP_USBC2_AUX_CH_DATA1, \
+ _XELPDP_USBC3_AUX_CH_DATA1, \
+ _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
#define DP_AUX_CH_CTL_DONE (1 << 30)
--
2.39.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Split _MMIO() for _PORT3()/_PIPE3()
2023-01-31 19:15 [Intel-gfx] [PATCH 1/2] drm/i915: Split _MMIO() for _PORT3()/_PIPE3() Lucas De Marchi
2023-01-31 19:15 ` [Intel-gfx] [PATCH 2/2] drm/i915: Move common mmio base out of private macros Lucas De Marchi
@ 2023-01-31 20:03 ` Patchwork
2023-01-31 21:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2023-01-31 20:03 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4868 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915: Split _MMIO() for _PORT3()/_PIPE3()
URL : https://patchwork.freedesktop.org/series/113532/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12674 -> Patchwork_113532v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/index.html
Participating hosts (27 -> 25)
------------------------------
Missing (2): bat-atsm-1 fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_113532v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@slpc:
- {bat-rpls-2}: [DMESG-FAIL][1] ([i915#6997]) -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/bat-rpls-2/igt@i915_selftest@live@slpc.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/bat-rpls-2/igt@i915_selftest@live@slpc.html
- {bat-rpls-1}: NOTRUN -> [DMESG-FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/bat-rpls-1/igt@i915_selftest@live@slpc.html
Known issues
------------
Here are the changes found in Patchwork_113532v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@fbdev@write:
- fi-blb-e6850: [PASS][4] -> [SKIP][5] ([fdo#109271]) +4 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/fi-blb-e6850/igt@fbdev@write.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/fi-blb-e6850/igt@fbdev@write.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][6] -> [DMESG-FAIL][7] ([i915#5334])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- {bat-dg2-11}: [ABORT][8] ([i915#7913]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/bat-dg2-11/igt@i915_selftest@live@hangcheck.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/bat-dg2-11/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- {bat-rpls-1}: [ABORT][10] ([i915#4983] / [i915#7981]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/bat-rpls-1/igt@i915_selftest@live@requests.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/bat-rpls-1/igt@i915_selftest@live@requests.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-n3050: [FAIL][12] ([i915#6298]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6311]: https://gitlab.freedesktop.org/drm/intel/issues/6311
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
Build changes
-------------
* Linux: CI_DRM_12674 -> Patchwork_113532v1
CI-20190529: 20190529
CI_DRM_12674: abcd161e6541aaf1e5c23e16019d02905c0e50fd @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7143: c7b12dcc460fc2348e1fa7f4dcb791bb82e29e44 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_113532v1: abcd161e6541aaf1e5c23e16019d02905c0e50fd @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
8f412e0acb50 drm/i915: Move common mmio base out of private macros
2f027a8d4688 drm/i915: Split _MMIO() for _PORT3()/_PIPE3()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/index.html
[-- Attachment #2: Type: text/html, Size: 5388 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Split _MMIO() for _PORT3()/_PIPE3()
2023-01-31 19:15 [Intel-gfx] [PATCH 1/2] drm/i915: Split _MMIO() for _PORT3()/_PIPE3() Lucas De Marchi
2023-01-31 19:15 ` [Intel-gfx] [PATCH 2/2] drm/i915: Move common mmio base out of private macros Lucas De Marchi
2023-01-31 20:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Split _MMIO() for _PORT3()/_PIPE3() Patchwork
@ 2023-01-31 21:55 ` Patchwork
2 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2023-01-31 21:55 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 23865 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915: Split _MMIO() for _PORT3()/_PIPE3()
URL : https://patchwork.freedesktop.org/series/113532/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12674_full -> Patchwork_113532v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_113532v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_113532v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/index.html
Participating hosts (11 -> 10)
------------------------------
Missing (1): shard-rkl0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_113532v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_capture@userptr:
- shard-glk: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-glk3/igt@gem_exec_capture@userptr.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-glk7/igt@gem_exec_capture@userptr.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
- shard-glk: [PASS][3] -> [TIMEOUT][4] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-glk4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-glk5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@resize-bar:
- {shard-dg1}: [SKIP][5] ([i915#7178]) -> [ABORT][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-dg1-12/igt@i915_module_load@resize-bar.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-dg1-14/igt@i915_module_load@resize-bar.html
Known issues
------------
Here are the changes found in Patchwork_113532v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [SKIP][7] ([fdo#109271])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-glk3/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@perf@enable-disable:
- shard-glk: [PASS][8] -> [TIMEOUT][9] ([i915#6943])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-glk4/igt@perf@enable-disable.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-glk5/igt@perf@enable-disable.html
#### Possible fixes ####
* igt@drm_fdinfo@virtual-idle:
- {shard-rkl}: [FAIL][10] ([i915#7742]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-rkl-2/igt@drm_fdinfo@virtual-idle.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-rkl-2/igt@drm_fdinfo@virtual-idle.html
* igt@drm_read@empty-block:
- {shard-rkl}: [SKIP][12] ([i915#4098]) -> [PASS][13] +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-rkl-3/igt@drm_read@empty-block.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-rkl-6/igt@drm_read@empty-block.html
* igt@drm_read@short-buffer-block:
- {shard-tglu}: [SKIP][14] ([i915#7651]) -> [PASS][15] +6 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-tglu-6/igt@drm_read@short-buffer-block.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-tglu-7/igt@drm_read@short-buffer-block.html
* igt@fbdev@write:
- {shard-tglu}: [SKIP][16] ([i915#2582]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-tglu-6/igt@fbdev@write.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-tglu-7/igt@fbdev@write.html
* igt@feature_discovery@psr1:
- {shard-rkl}: [SKIP][18] ([i915#658]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-rkl-4/igt@feature_discovery@psr1.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-rkl-6/igt@feature_discovery@psr1.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- {shard-rkl}: [FAIL][20] ([i915#2842]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-rkl-1/igt@gem_exec_fair@basic-none-share@rcs0.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-rkl-5/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][22] ([i915#2842]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_reloc@basic-gtt-wc-noreloc:
- {shard-rkl}: [SKIP][24] ([i915#3281]) -> [PASS][25] +3 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-rkl-1/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-rkl-5/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html
* igt@gem_exec_schedule@semaphore-power:
- {shard-rkl}: [SKIP][26] ([i915#7276]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-rkl-1/igt@gem_exec_schedule@semaphore-power.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-rkl-5/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_partial_pwrite_pread@reads:
- {shard-rkl}: [SKIP][28] ([i915#3282]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-rkl-1/igt@gem_partial_pwrite_pread@reads.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-rkl-5/igt@gem_partial_pwrite_pread@reads.html
* igt@gem_spin_batch@resubmit@rcs0:
- {shard-rkl}: [ABORT][30] -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-rkl-4/igt@gem_spin_batch@resubmit@rcs0.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-rkl-2/igt@gem_spin_batch@resubmit@rcs0.html
* igt@gem_spin_batch@resubmit@vecs0:
- {shard-rkl}: [DMESG-WARN][32] -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-rkl-4/igt@gem_spin_batch@resubmit@vecs0.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-rkl-2/igt@gem_spin_batch@resubmit@vecs0.html
* igt@gen9_exec_parse@secure-batches:
- {shard-rkl}: [SKIP][34] ([i915#2527]) -> [PASS][35] +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-rkl-3/igt@gen9_exec_parse@secure-batches.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-rkl-5/igt@gen9_exec_parse@secure-batches.html
* igt@i915_hangman@gt-engine-error@bcs0:
- {shard-rkl}: [SKIP][36] ([i915#6258]) -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-rkl-5/igt@i915_hangman@gt-engine-error@bcs0.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-rkl-3/igt@i915_hangman@gt-engine-error@bcs0.html
* igt@i915_pm_rpm@fences:
- {shard-rkl}: [SKIP][38] ([i915#1849]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-rkl-3/igt@i915_pm_rpm@fences.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-rkl-6/igt@i915_pm_rpm@fences.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- {shard-tglu}: [SKIP][40] ([i915#1397]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-tglu-6/igt@i915_pm_rpm@modeset-lpsp-stress.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-tglu-7/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_pm_rpm@system-suspend-modeset:
- {shard-rkl}: [SKIP][42] ([fdo#109308]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-rkl-3/igt@i915_pm_rpm@system-suspend-modeset.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-rkl-6/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-0:
- shard-glk: [FAIL][44] ([i915#5138]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-glk7/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-glk2/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-glk: [FAIL][46] ([i915#2346]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][48] ([i915#2122]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2:
- shard-glk: [FAIL][50] ([i915#79]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- {shard-tglu}: [SKIP][52] ([i915#1849]) -> [PASS][53] +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-tglu-6/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-tglu-7/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite:
- {shard-rkl}: [SKIP][54] ([i915#1849] / [i915#4098]) -> [PASS][55] +11 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html
* igt@kms_psr@sprite_plane_onoff:
- {shard-rkl}: [SKIP][56] ([i915#1072]) -> [PASS][57] +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-rkl-4/igt@kms_psr@sprite_plane_onoff.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-rkl-6/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_universal_plane@universal-plane-pipe-c-sanity:
- {shard-tglu}: [SKIP][58] ([fdo#109274]) -> [PASS][59] +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-tglu-6/igt@kms_universal_plane@universal-plane-pipe-c-sanity.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-tglu-7/igt@kms_universal_plane@universal-plane-pipe-c-sanity.html
* igt@kms_vblank@pipe-b-wait-idle-hang:
- {shard-rkl}: [SKIP][60] ([i915#1845] / [i915#4098]) -> [PASS][61] +15 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-rkl-4/igt@kms_vblank@pipe-b-wait-idle-hang.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-rkl-6/igt@kms_vblank@pipe-b-wait-idle-hang.html
* igt@kms_vblank@pipe-d-wait-forked-busy:
- {shard-tglu}: [SKIP][62] ([i915#1845] / [i915#7651]) -> [PASS][63] +2 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12674/shard-tglu-6/igt@kms_vblank@pipe-d-wait-forked-busy.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/shard-tglu-7/igt@kms_vblank@pipe-d-wait-forked-busy.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2232]: https://gitlab.freedesktop.org/drm/intel/issues/2232
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6943]: https://gitlab.freedesktop.org/drm/intel/issues/6943
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
[i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178
[i915#7276]: https://gitlab.freedesktop.org/drm/intel/issues/7276
[i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7949]: https://gitlab.freedesktop.org/drm/intel/issues/7949
Build changes
-------------
* Linux: CI_DRM_12674 -> Patchwork_113532v1
CI-20190529: 20190529
CI_DRM_12674: abcd161e6541aaf1e5c23e16019d02905c0e50fd @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7143: c7b12dcc460fc2348e1fa7f4dcb791bb82e29e44 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_113532v1: abcd161e6541aaf1e5c23e16019d02905c0e50fd @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113532v1/index.html
[-- Attachment #2: Type: text/html, Size: 16942 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915: Move common mmio base out of private macros
2023-01-31 19:15 ` [Intel-gfx] [PATCH 2/2] drm/i915: Move common mmio base out of private macros Lucas De Marchi
@ 2023-02-01 9:59 ` Jani Nikula
2023-02-01 12:09 ` Ville Syrjälä
0 siblings, 1 reply; 9+ messages in thread
From: Jani Nikula @ 2023-02-01 9:59 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx; +Cc: Lucas De Marchi, Rodrigo Vivi
On Tue, 31 Jan 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> Instead of using the common DISPLAY_MMIO_BASE(dev_priv) in all single
> macros, only use them in the macros that are to be used outside the
> header. This reduces the use of the implicit dev_priv, making it easier
> to remove it later.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 73 ++++++++++++++++++---------------
> 1 file changed, 39 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 943db8ec63f8..1cde3bcb9c88 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1182,9 +1182,9 @@
> #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
> #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
>
> -#define GT_PARITY_ERROR(dev_priv) \
> +#define GT_PARITY_ERROR(__i915) \
> (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
> - (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
> + (IS_HASWELL(__i915) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
Unrelated change.
>
> /* These are all the "old" interrupts */
> #define ILK_BSD_USER_INTERRUPT (1 << 5)
> @@ -1403,10 +1403,11 @@
> /*
> * Clock control & power management
> */
> -#define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
> -#define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
> -#define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
> -#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
> +#define _DPLL_A 0x6014
> +#define _DPLL_B 0x6018
> +#define _CHV_DPLL_C 0x6030
> +#define DPLL(pipe) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> + _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C))
>
> #define VGA0 _MMIO(0x6000)
> #define VGA1 _MMIO(0x6004)
> @@ -1502,10 +1503,11 @@
> #define SDVO_MULTIPLIER_SHIFT_HIRES 4
> #define SDVO_MULTIPLIER_SHIFT_VGA 0
>
> -#define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
> -#define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
> -#define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
> -#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
> +#define _DPLL_A_MD 0x601c
> +#define _DPLL_B_MD 0x6020
> +#define _CHV_DPLL_C_MD 0x603c
> +#define DPLL_MD(pipe) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> + _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD))
>
> /*
> * UDI pixel divider, controlling how many pixels are stuffed into a packet.
> @@ -3323,42 +3325,45 @@
> * is 20 bytes in each direction, hence the 5 fixed
> * data registers
> */
> -#define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
> -#define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
> -
> -#define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
> -#define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
> -
> -#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
> -#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
> +#define _DPA_AUX_CH_CTL 0x64010
> +#define _DPA_AUX_CH_DATA1 0x64014
> +#define _DPB_AUX_CH_CTL 0x64110
> +#define _DPB_AUX_CH_DATA1 0x64114
> +#define DP_AUX_CH_CTL(aux_ch) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> + _PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL))
> +#define DP_AUX_CH_DATA(aux_ch, i) \
> + _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> + _PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
>
> #define _XELPDP_USBC1_AUX_CH_CTL 0x16F210
> #define _XELPDP_USBC2_AUX_CH_CTL 0x16F410
> #define _XELPDP_USBC3_AUX_CH_CTL 0x16F610
> #define _XELPDP_USBC4_AUX_CH_CTL 0x16F810
>
> -#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
> - _DPA_AUX_CH_CTL, \
> - _DPB_AUX_CH_CTL, \
> - 0, /* port/aux_ch C is non-existent */ \
> - _XELPDP_USBC1_AUX_CH_CTL, \
> - _XELPDP_USBC2_AUX_CH_CTL, \
> - _XELPDP_USBC3_AUX_CH_CTL, \
> - _XELPDP_USBC4_AUX_CH_CTL))
> +#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
Note that only VLV and CHV have DISPLAY_MMIO_BASE() != 0.
This is an XELPDP specific macro. Just drop the DISPLAY_MMIO_BASE() part
altogether, and you've removed an implicit dev_priv. Yay.
This also makes me think we should probably add VLV/CHV specific
DP_AUX_CH_CTL and DP_AUX_CH_DATA macros that just add VLV_DISPLAY_BASE
directly, and use that to ditch the implicit dev_priv there too. This
approach doesn't work for everything, but the aux channel stuff is both
fairly limited use and already has if ladders to pick the
registers. Handling VLV/CHV separately is not a big deal.
(DPLL on the other hand seems much harder to deal that way.)
BR,
Jani.
> + _PICK(aux_ch, \
> + _DPA_AUX_CH_CTL, \
> + _DPB_AUX_CH_CTL, \
> + 0, /* port/aux_ch C is non-existent */ \
> + _XELPDP_USBC1_AUX_CH_CTL, \
> + _XELPDP_USBC2_AUX_CH_CTL, \
> + _XELPDP_USBC3_AUX_CH_CTL, \
> + _XELPDP_USBC4_AUX_CH_CTL))
>
> #define _XELPDP_USBC1_AUX_CH_DATA1 0x16F214
> #define _XELPDP_USBC2_AUX_CH_DATA1 0x16F414
> #define _XELPDP_USBC3_AUX_CH_DATA1 0x16F614
> #define _XELPDP_USBC4_AUX_CH_DATA1 0x16F814
>
> -#define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \
> - _DPA_AUX_CH_DATA1, \
> - _DPB_AUX_CH_DATA1, \
> - 0, /* port/aux_ch C is non-existent */ \
> - _XELPDP_USBC1_AUX_CH_DATA1, \
> - _XELPDP_USBC2_AUX_CH_DATA1, \
> - _XELPDP_USBC3_AUX_CH_DATA1, \
> - _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
> +#define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> + _PICK(aux_ch, \
> + _DPA_AUX_CH_DATA1, \
> + _DPB_AUX_CH_DATA1, \
> + 0, /* port/aux_ch C is non-existent */ \
> + _XELPDP_USBC1_AUX_CH_DATA1, \
> + _XELPDP_USBC2_AUX_CH_DATA1, \
> + _XELPDP_USBC3_AUX_CH_DATA1, \
> + _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
>
> #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
> #define DP_AUX_CH_CTL_DONE (1 << 30)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915: Move common mmio base out of private macros
2023-02-01 9:59 ` Jani Nikula
@ 2023-02-01 12:09 ` Ville Syrjälä
2023-02-01 17:26 ` Lucas De Marchi
0 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2023-02-01 12:09 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, Lucas De Marchi, Rodrigo Vivi
On Wed, Feb 01, 2023 at 11:59:19AM +0200, Jani Nikula wrote:
> On Tue, 31 Jan 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> > Instead of using the common DISPLAY_MMIO_BASE(dev_priv) in all single
> > macros, only use them in the macros that are to be used outside the
> > header. This reduces the use of the implicit dev_priv, making it easier
> > to remove it later.
> >
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 73 ++++++++++++++++++---------------
> > 1 file changed, 39 insertions(+), 34 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 943db8ec63f8..1cde3bcb9c88 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1182,9 +1182,9 @@
> > #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
> > #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
> >
> > -#define GT_PARITY_ERROR(dev_priv) \
> > +#define GT_PARITY_ERROR(__i915) \
> > (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
> > - (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
> > + (IS_HASWELL(__i915) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
>
> Unrelated change.
>
> >
> > /* These are all the "old" interrupts */
> > #define ILK_BSD_USER_INTERRUPT (1 << 5)
> > @@ -1403,10 +1403,11 @@
> > /*
> > * Clock control & power management
> > */
> > -#define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
> > -#define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
> > -#define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
> > -#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
> > +#define _DPLL_A 0x6014
> > +#define _DPLL_B 0x6018
> > +#define _CHV_DPLL_C 0x6030
> > +#define DPLL(pipe) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> > + _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C))
> >
> > #define VGA0 _MMIO(0x6000)
> > #define VGA1 _MMIO(0x6004)
> > @@ -1502,10 +1503,11 @@
> > #define SDVO_MULTIPLIER_SHIFT_HIRES 4
> > #define SDVO_MULTIPLIER_SHIFT_VGA 0
> >
> > -#define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
> > -#define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
> > -#define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
> > -#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
> > +#define _DPLL_A_MD 0x601c
> > +#define _DPLL_B_MD 0x6020
> > +#define _CHV_DPLL_C_MD 0x603c
> > +#define DPLL_MD(pipe) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> > + _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD))
> >
> > /*
> > * UDI pixel divider, controlling how many pixels are stuffed into a packet.
> > @@ -3323,42 +3325,45 @@
> > * is 20 bytes in each direction, hence the 5 fixed
> > * data registers
> > */
> > -#define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
> > -#define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
> > -
> > -#define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
> > -#define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
> > -
> > -#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
> > -#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
> > +#define _DPA_AUX_CH_CTL 0x64010
> > +#define _DPA_AUX_CH_DATA1 0x64014
> > +#define _DPB_AUX_CH_CTL 0x64110
> > +#define _DPB_AUX_CH_DATA1 0x64114
> > +#define DP_AUX_CH_CTL(aux_ch) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> > + _PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL))
> > +#define DP_AUX_CH_DATA(aux_ch, i) \
> > + _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> > + _PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
> >
> > #define _XELPDP_USBC1_AUX_CH_CTL 0x16F210
> > #define _XELPDP_USBC2_AUX_CH_CTL 0x16F410
> > #define _XELPDP_USBC3_AUX_CH_CTL 0x16F610
> > #define _XELPDP_USBC4_AUX_CH_CTL 0x16F810
> >
> > -#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
> > - _DPA_AUX_CH_CTL, \
> > - _DPB_AUX_CH_CTL, \
> > - 0, /* port/aux_ch C is non-existent */ \
> > - _XELPDP_USBC1_AUX_CH_CTL, \
> > - _XELPDP_USBC2_AUX_CH_CTL, \
> > - _XELPDP_USBC3_AUX_CH_CTL, \
> > - _XELPDP_USBC4_AUX_CH_CTL))
> > +#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
>
> Note that only VLV and CHV have DISPLAY_MMIO_BASE() != 0.
>
> This is an XELPDP specific macro. Just drop the DISPLAY_MMIO_BASE() part
> altogether, and you've removed an implicit dev_priv. Yay.
>
> This also makes me think we should probably add VLV/CHV specific
> DP_AUX_CH_CTL and DP_AUX_CH_DATA macros that just add VLV_DISPLAY_BASE
> directly, and use that to ditch the implicit dev_priv there too. This
> approach doesn't work for everything, but the aux channel stuff is both
> fairly limited use and already has if ladders to pick the
> registers. Handling VLV/CHV separately is not a big deal.
>
> (DPLL on the other hand seems much harder to deal that way.)
Most of the DPLL code should be have vlv/chv vs. rest specific
codepaths. A quick scan says readout is perhaps the only exception.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915: Move common mmio base out of private macros
2023-02-01 12:09 ` Ville Syrjälä
@ 2023-02-01 17:26 ` Lucas De Marchi
2023-02-01 17:39 ` Ville Syrjälä
0 siblings, 1 reply; 9+ messages in thread
From: Lucas De Marchi @ 2023-02-01 17:26 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Rodrigo Vivi
On Wed, Feb 01, 2023 at 02:09:54PM +0200, Ville Syrjälä wrote:
>On Wed, Feb 01, 2023 at 11:59:19AM +0200, Jani Nikula wrote:
>> On Tue, 31 Jan 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> > Instead of using the common DISPLAY_MMIO_BASE(dev_priv) in all single
>> > macros, only use them in the macros that are to be used outside the
>> > header. This reduces the use of the implicit dev_priv, making it easier
>> > to remove it later.
>> >
>> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/i915_reg.h | 73 ++++++++++++++++++---------------
>> > 1 file changed, 39 insertions(+), 34 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > index 943db8ec63f8..1cde3bcb9c88 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -1182,9 +1182,9 @@
>> > #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
>> > #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
>> >
>> > -#define GT_PARITY_ERROR(dev_priv) \
>> > +#define GT_PARITY_ERROR(__i915) \
>> > (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
>> > - (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
>> > + (IS_HASWELL(__i915) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
>>
>> Unrelated change.
>>
>> >
>> > /* These are all the "old" interrupts */
>> > #define ILK_BSD_USER_INTERRUPT (1 << 5)
>> > @@ -1403,10 +1403,11 @@
>> > /*
>> > * Clock control & power management
>> > */
>> > -#define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
>> > -#define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
>> > -#define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
>> > -#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
>> > +#define _DPLL_A 0x6014
>> > +#define _DPLL_B 0x6018
>> > +#define _CHV_DPLL_C 0x6030
>> > +#define DPLL(pipe) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
>> > + _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C))
>> >
>> > #define VGA0 _MMIO(0x6000)
>> > #define VGA1 _MMIO(0x6004)
>> > @@ -1502,10 +1503,11 @@
>> > #define SDVO_MULTIPLIER_SHIFT_HIRES 4
>> > #define SDVO_MULTIPLIER_SHIFT_VGA 0
>> >
>> > -#define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
>> > -#define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
>> > -#define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
>> > -#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
>> > +#define _DPLL_A_MD 0x601c
>> > +#define _DPLL_B_MD 0x6020
>> > +#define _CHV_DPLL_C_MD 0x603c
>> > +#define DPLL_MD(pipe) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
>> > + _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD))
>> >
>> > /*
>> > * UDI pixel divider, controlling how many pixels are stuffed into a packet.
>> > @@ -3323,42 +3325,45 @@
>> > * is 20 bytes in each direction, hence the 5 fixed
>> > * data registers
>> > */
>> > -#define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
>> > -#define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
>> > -
>> > -#define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
>> > -#define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
>> > -
>> > -#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
>> > -#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
>> > +#define _DPA_AUX_CH_CTL 0x64010
>> > +#define _DPA_AUX_CH_DATA1 0x64014
>> > +#define _DPB_AUX_CH_CTL 0x64110
>> > +#define _DPB_AUX_CH_DATA1 0x64114
>> > +#define DP_AUX_CH_CTL(aux_ch) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
>> > + _PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL))
>> > +#define DP_AUX_CH_DATA(aux_ch, i) \
>> > + _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
>> > + _PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
>> >
>> > #define _XELPDP_USBC1_AUX_CH_CTL 0x16F210
>> > #define _XELPDP_USBC2_AUX_CH_CTL 0x16F410
>> > #define _XELPDP_USBC3_AUX_CH_CTL 0x16F610
>> > #define _XELPDP_USBC4_AUX_CH_CTL 0x16F810
>> >
>> > -#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
>> > - _DPA_AUX_CH_CTL, \
>> > - _DPB_AUX_CH_CTL, \
>> > - 0, /* port/aux_ch C is non-existent */ \
>> > - _XELPDP_USBC1_AUX_CH_CTL, \
>> > - _XELPDP_USBC2_AUX_CH_CTL, \
>> > - _XELPDP_USBC3_AUX_CH_CTL, \
>> > - _XELPDP_USBC4_AUX_CH_CTL))
>> > +#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
>>
>> Note that only VLV and CHV have DISPLAY_MMIO_BASE() != 0.
>>
>> This is an XELPDP specific macro. Just drop the DISPLAY_MMIO_BASE() part
>> altogether, and you've removed an implicit dev_priv. Yay.
>>
>> This also makes me think we should probably add VLV/CHV specific
>> DP_AUX_CH_CTL and DP_AUX_CH_DATA macros that just add VLV_DISPLAY_BASE
>> directly, and use that to ditch the implicit dev_priv there too. This
>> approach doesn't work for everything, but the aux channel stuff is both
>> fairly limited use and already has if ladders to pick the
>> registers. Handling VLV/CHV separately is not a big deal.
>>
>> (DPLL on the other hand seems much harder to deal that way.)
>
>Most of the DPLL code should be have vlv/chv vs. rest specific
>codepaths. A quick scan says readout is perhaps the only exception.
and then remove display.mmio_offset since vlv/chv are the only ones
using it?
Lucas De Marchi
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915: Move common mmio base out of private macros
2023-02-01 17:26 ` Lucas De Marchi
@ 2023-02-01 17:39 ` Ville Syrjälä
2023-02-02 10:11 ` Jani Nikula
0 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2023-02-01 17:39 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Rodrigo Vivi
On Wed, Feb 01, 2023 at 09:26:29AM -0800, Lucas De Marchi wrote:
> On Wed, Feb 01, 2023 at 02:09:54PM +0200, Ville Syrjälä wrote:
> >On Wed, Feb 01, 2023 at 11:59:19AM +0200, Jani Nikula wrote:
> >> On Tue, 31 Jan 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> >> > Instead of using the common DISPLAY_MMIO_BASE(dev_priv) in all single
> >> > macros, only use them in the macros that are to be used outside the
> >> > header. This reduces the use of the implicit dev_priv, making it easier
> >> > to remove it later.
> >> >
> >> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >> > ---
> >> > drivers/gpu/drm/i915/i915_reg.h | 73 ++++++++++++++++++---------------
> >> > 1 file changed, 39 insertions(+), 34 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> > index 943db8ec63f8..1cde3bcb9c88 100644
> >> > --- a/drivers/gpu/drm/i915/i915_reg.h
> >> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> > @@ -1182,9 +1182,9 @@
> >> > #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
> >> > #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
> >> >
> >> > -#define GT_PARITY_ERROR(dev_priv) \
> >> > +#define GT_PARITY_ERROR(__i915) \
> >> > (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
> >> > - (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
> >> > + (IS_HASWELL(__i915) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
> >>
> >> Unrelated change.
> >>
> >> >
> >> > /* These are all the "old" interrupts */
> >> > #define ILK_BSD_USER_INTERRUPT (1 << 5)
> >> > @@ -1403,10 +1403,11 @@
> >> > /*
> >> > * Clock control & power management
> >> > */
> >> > -#define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
> >> > -#define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
> >> > -#define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
> >> > -#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
> >> > +#define _DPLL_A 0x6014
> >> > +#define _DPLL_B 0x6018
> >> > +#define _CHV_DPLL_C 0x6030
> >> > +#define DPLL(pipe) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> >> > + _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C))
> >> >
> >> > #define VGA0 _MMIO(0x6000)
> >> > #define VGA1 _MMIO(0x6004)
> >> > @@ -1502,10 +1503,11 @@
> >> > #define SDVO_MULTIPLIER_SHIFT_HIRES 4
> >> > #define SDVO_MULTIPLIER_SHIFT_VGA 0
> >> >
> >> > -#define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
> >> > -#define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
> >> > -#define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
> >> > -#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
> >> > +#define _DPLL_A_MD 0x601c
> >> > +#define _DPLL_B_MD 0x6020
> >> > +#define _CHV_DPLL_C_MD 0x603c
> >> > +#define DPLL_MD(pipe) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> >> > + _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD))
> >> >
> >> > /*
> >> > * UDI pixel divider, controlling how many pixels are stuffed into a packet.
> >> > @@ -3323,42 +3325,45 @@
> >> > * is 20 bytes in each direction, hence the 5 fixed
> >> > * data registers
> >> > */
> >> > -#define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
> >> > -#define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
> >> > -
> >> > -#define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
> >> > -#define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
> >> > -
> >> > -#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
> >> > -#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
> >> > +#define _DPA_AUX_CH_CTL 0x64010
> >> > +#define _DPA_AUX_CH_DATA1 0x64014
> >> > +#define _DPB_AUX_CH_CTL 0x64110
> >> > +#define _DPB_AUX_CH_DATA1 0x64114
> >> > +#define DP_AUX_CH_CTL(aux_ch) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> >> > + _PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL))
> >> > +#define DP_AUX_CH_DATA(aux_ch, i) \
> >> > + _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> >> > + _PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
> >> >
> >> > #define _XELPDP_USBC1_AUX_CH_CTL 0x16F210
> >> > #define _XELPDP_USBC2_AUX_CH_CTL 0x16F410
> >> > #define _XELPDP_USBC3_AUX_CH_CTL 0x16F610
> >> > #define _XELPDP_USBC4_AUX_CH_CTL 0x16F810
> >> >
> >> > -#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
> >> > - _DPA_AUX_CH_CTL, \
> >> > - _DPB_AUX_CH_CTL, \
> >> > - 0, /* port/aux_ch C is non-existent */ \
> >> > - _XELPDP_USBC1_AUX_CH_CTL, \
> >> > - _XELPDP_USBC2_AUX_CH_CTL, \
> >> > - _XELPDP_USBC3_AUX_CH_CTL, \
> >> > - _XELPDP_USBC4_AUX_CH_CTL))
> >> > +#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> >>
> >> Note that only VLV and CHV have DISPLAY_MMIO_BASE() != 0.
> >>
> >> This is an XELPDP specific macro. Just drop the DISPLAY_MMIO_BASE() part
> >> altogether, and you've removed an implicit dev_priv. Yay.
> >>
> >> This also makes me think we should probably add VLV/CHV specific
> >> DP_AUX_CH_CTL and DP_AUX_CH_DATA macros that just add VLV_DISPLAY_BASE
> >> directly, and use that to ditch the implicit dev_priv there too. This
> >> approach doesn't work for everything, but the aux channel stuff is both
> >> fairly limited use and already has if ladders to pick the
> >> registers. Handling VLV/CHV separately is not a big deal.
> >>
> >> (DPLL on the other hand seems much harder to deal that way.)
> >
> >Most of the DPLL code should be have vlv/chv vs. rest specific
> >codepaths. A quick scan says readout is perhaps the only exception.
>
> and then remove display.mmio_offset since vlv/chv are the only ones
> using it?
There should tons of other registers still using it.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915: Move common mmio base out of private macros
2023-02-01 17:39 ` Ville Syrjälä
@ 2023-02-02 10:11 ` Jani Nikula
0 siblings, 0 replies; 9+ messages in thread
From: Jani Nikula @ 2023-02-02 10:11 UTC (permalink / raw)
To: Ville Syrjälä, Lucas De Marchi; +Cc: intel-gfx, Rodrigo Vivi
On Wed, 01 Feb 2023, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Feb 01, 2023 at 09:26:29AM -0800, Lucas De Marchi wrote:
>> On Wed, Feb 01, 2023 at 02:09:54PM +0200, Ville Syrjälä wrote:
>> >On Wed, Feb 01, 2023 at 11:59:19AM +0200, Jani Nikula wrote:
>> >> On Tue, 31 Jan 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> >> > -#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
>> >> > - _DPA_AUX_CH_CTL, \
>> >> > - _DPB_AUX_CH_CTL, \
>> >> > - 0, /* port/aux_ch C is non-existent */ \
>> >> > - _XELPDP_USBC1_AUX_CH_CTL, \
>> >> > - _XELPDP_USBC2_AUX_CH_CTL, \
>> >> > - _XELPDP_USBC3_AUX_CH_CTL, \
>> >> > - _XELPDP_USBC4_AUX_CH_CTL))
>> >> > +#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
>> >>
>> >> Note that only VLV and CHV have DISPLAY_MMIO_BASE() != 0.
>> >>
>> >> This is an XELPDP specific macro. Just drop the DISPLAY_MMIO_BASE() part
>> >> altogether, and you've removed an implicit dev_priv. Yay.
>> >>
>> >> This also makes me think we should probably add VLV/CHV specific
>> >> DP_AUX_CH_CTL and DP_AUX_CH_DATA macros that just add VLV_DISPLAY_BASE
>> >> directly, and use that to ditch the implicit dev_priv there too. This
>> >> approach doesn't work for everything, but the aux channel stuff is both
>> >> fairly limited use and already has if ladders to pick the
>> >> registers. Handling VLV/CHV separately is not a big deal.
>> >>
>> >> (DPLL on the other hand seems much harder to deal that way.)
>> >
>> >Most of the DPLL code should be have vlv/chv vs. rest specific
>> >codepaths. A quick scan says readout is perhaps the only exception.
>>
>> and then remove display.mmio_offset since vlv/chv are the only ones
>> using it?
>
> There should tons of other registers still using it.
Yeah. It's just that DISPLAY_MMIO_BASE() was sprinkled around
gratuitously, when separate VLV/CHV specific macros would have been
better options. This is really case by case. Remove the requirement for
drm_i915_private access where it makes sense, and pass the pointer
explicitly elsewhere.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-02-02 10:11 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-01-31 19:15 [Intel-gfx] [PATCH 1/2] drm/i915: Split _MMIO() for _PORT3()/_PIPE3() Lucas De Marchi
2023-01-31 19:15 ` [Intel-gfx] [PATCH 2/2] drm/i915: Move common mmio base out of private macros Lucas De Marchi
2023-02-01 9:59 ` Jani Nikula
2023-02-01 12:09 ` Ville Syrjälä
2023-02-01 17:26 ` Lucas De Marchi
2023-02-01 17:39 ` Ville Syrjälä
2023-02-02 10:11 ` Jani Nikula
2023-01-31 20:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Split _MMIO() for _PORT3()/_PIPE3() Patchwork
2023-01-31 21:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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