* [Intel-gfx] [PATCH 1/8] drm/damage_helper: Fix handling of cursor dirty buffers
2021-08-18 0:42 [Intel-gfx] [PATCH 0/8] Drop frontbuffer rendering support from Skylake and newer José Roberto de Souza
@ 2021-08-18 0:42 ` José Roberto de Souza
2021-08-18 0:42 ` [Intel-gfx] [PATCH 2/8] drm/i915/display: Drop PSR support from HSW and BDW José Roberto de Souza
` (9 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: José Roberto de Souza @ 2021-08-18 0:42 UTC (permalink / raw)
To: intel-gfx
Cc: Daniel Vetter, Rob Clark, Deepak Rawat, Gwan-gyeong Mun,
José Roberto de Souza
Cursors don't have a framebuffer so the fb comparisson was always
failing and atomic state was being committed without any plane state.
So here checking if objects match when checking cursors.
Fixes: b9fc5e01d1ce ("drm: Add helper to implement legacy dirtyfb")
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Rob Clark <robdclark@gmail.com>
Cc: Deepak Rawat <drawat@vmware.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/drm_damage_helper.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_damage_helper.c b/drivers/gpu/drm/drm_damage_helper.c
index 8eeff0c7bdd47..595187d97c131 100644
--- a/drivers/gpu/drm/drm_damage_helper.c
+++ b/drivers/gpu/drm/drm_damage_helper.c
@@ -157,12 +157,18 @@ int drm_atomic_helper_dirtyfb(struct drm_framebuffer *fb,
retry:
drm_for_each_plane(plane, fb->dev) {
struct drm_plane_state *plane_state;
+ bool match;
ret = drm_modeset_lock(&plane->mutex, state->acquire_ctx);
if (ret)
goto out;
- if (plane->state->fb != fb) {
+ match = plane->state->fb == fb;
+ /* Check if objs match to handle dirty buffers of cursors */
+ if (plane->type == DRM_PLANE_TYPE_CURSOR && plane->state->fb)
+ match |= fb->obj[0] == plane->state->fb->obj[0];
+
+ if (!match) {
drm_modeset_unlock(&plane->mutex);
continue;
}
--
2.32.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [Intel-gfx] [PATCH 2/8] drm/i915/display: Drop PSR support from HSW and BDW
2021-08-18 0:42 [Intel-gfx] [PATCH 0/8] Drop frontbuffer rendering support from Skylake and newer José Roberto de Souza
2021-08-18 0:42 ` [Intel-gfx] [PATCH 1/8] drm/damage_helper: Fix handling of cursor dirty buffers José Roberto de Souza
@ 2021-08-18 0:42 ` José Roberto de Souza
2021-08-18 0:42 ` [Intel-gfx] [PATCH 3/8] drm/i915/display: Move DRRS code its own file José Roberto de Souza
` (8 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: José Roberto de Souza @ 2021-08-18 0:42 UTC (permalink / raw)
To: intel-gfx; +Cc: Gwan-gyeong Mun, José Roberto de Souza
At this point is sure that HSW and BDW will never have PSR enabled by
default, so here dropping it from device info and cleaning up code.
v2:
- enable psr support for display 9
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 97 ++++--------------------
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/i915_irq.c | 16 ----
drivers/gpu/drm/i915/i915_pci.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 21 ++---
5 files changed, 20 insertions(+), 120 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index cade37f67f33c..3f6fb7d67f84d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -364,41 +364,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
}
}
-static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u32 aux_clock_divider, aux_ctl;
- int i;
- static const u8 aux_msg[] = {
- [0] = DP_AUX_NATIVE_WRITE << 4,
- [1] = DP_SET_POWER >> 8,
- [2] = DP_SET_POWER & 0xff,
- [3] = 1 - 1,
- [4] = DP_SET_POWER_D0,
- };
- u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK |
- EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK |
- EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK |
- EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK;
-
- BUILD_BUG_ON(sizeof(aux_msg) > 20);
- for (i = 0; i < sizeof(aux_msg); i += 4)
- intel_de_write(dev_priv,
- EDP_PSR_AUX_DATA(intel_dp->psr.transcoder, i >> 2),
- intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
-
- aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
-
- /* Start with bits set for DDI_AUX_CTL register */
- aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg),
- aux_clock_divider);
-
- /* Select only valid bits for SRD_AUX_CTL */
- aux_ctl &= psr_aux_mask;
- intel_de_write(dev_priv, EDP_PSR_AUX_CTL(intel_dp->psr.transcoder),
- aux_ctl);
-}
-
static void intel_psr_enable_sink(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -621,9 +586,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
static bool
transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans)
{
- if (DISPLAY_VER(dev_priv) < 9)
- return false;
- else if (DISPLAY_VER(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
return trans == TRANSCODER_A;
else
return trans == TRANSCODER_EDP;
@@ -1114,12 +1077,6 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
u32 mask;
- /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
- * use hardcoded values PSR AUX transactions
- */
- if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- hsw_psr_setup_aux(intel_dp);
-
if (intel_dp->psr.psr2_enabled && DISPLAY_VER(dev_priv) == 9) {
i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
u32 chicken = intel_de_read(dev_priv, reg);
@@ -1460,23 +1417,16 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- if (DISPLAY_VER(dev_priv) >= 9)
- /*
- * Display WA #0884: skl+
- * This documented WA for bxt can be safely applied
- * broadly so we can force HW tracking to exit PSR
- * instead of disabling and re-enabling.
- * Workaround tells us to write 0 to CUR_SURFLIVE_A,
- * but it makes more sense write to the current active
- * pipe.
- */
- intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
- else
- /*
- * A write to CURSURFLIVE do not cause HW tracking to exit PSR
- * on older gens so doing the manual exit instead.
- */
- intel_psr_exit(intel_dp);
+ /*
+ * Display WA #0884: skl+
+ * This documented WA for bxt can be safely applied
+ * broadly so we can force HW tracking to exit PSR
+ * instead of disabling and re-enabling.
+ * Workaround tells us to write 0 to CUR_SURFLIVE_A,
+ * but it makes more sense write to the current active
+ * pipe.
+ */
+ intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
}
void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
@@ -1744,7 +1694,6 @@ void intel_psr_update(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_psr *psr = &intel_dp->psr;
bool enable, psr2_enable;
@@ -1761,15 +1710,6 @@ void intel_psr_update(struct intel_dp *intel_dp,
/* Force a PSR exit when enabling CRC to avoid CRC timeouts */
if (crtc_state->crc_enabled && psr->enabled)
psr_force_hw_tracking_exit(intel_dp);
- else if (DISPLAY_VER(dev_priv) < 9 && psr->enabled) {
- /*
- * Activate PSR again after a force exit when enabling
- * CRC in older gens
- */
- if (!intel_dp->psr.active &&
- !intel_dp->psr.busy_frontbuffer_bits)
- schedule_work(&intel_dp->psr.work);
- }
goto unlock;
}
@@ -2182,23 +2122,12 @@ void intel_psr_init(struct intel_dp *intel_dp)
intel_dp->psr.source_support = true;
- if (IS_HASWELL(dev_priv))
- /*
- * HSW don't have PSR registers on the same space as transcoder
- * so set this to a value that when subtract to the register
- * in transcoder space results in the right offset for HSW
- */
- dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE;
-
if (dev_priv->params.enable_psr == -1)
- if (DISPLAY_VER(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
+ if (!dev_priv->vbt.psr.enable)
dev_priv->params.enable_psr = 0;
/* Set link_standby x link_off defaults */
- if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- /* HSW and BDW require workarounds that we don't implement. */
- intel_dp->psr.link_standby = false;
- else if (DISPLAY_VER(dev_priv) < 12)
+ if (DISPLAY_VER(dev_priv) < 12)
/* For new platforms up to TGL let's respect VBT back again */
intel_dp->psr.link_standby = dev_priv->vbt.psr.full_link;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 005b1cec70075..1ea27c4e94a6d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -886,8 +886,6 @@ struct drm_i915_private {
*/
u32 gpio_mmio_base;
- u32 hsw_psr_mmio_adjust;
-
/* MMIO base address for MIPI regs */
u32 mipi_mmio_base;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9bc4f4a8e12ec..45c0b51a8da17 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2093,22 +2093,6 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
if (de_iir & DE_ERR_INT_IVB)
ivb_err_int_handler(dev_priv);
- if (de_iir & DE_EDP_PSR_INT_HSW) {
- struct intel_encoder *encoder;
-
- for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
- u32 psr_iir = intel_uncore_read(&dev_priv->uncore,
- EDP_PSR_IIR);
-
- intel_psr_irq_handler(intel_dp, psr_iir);
- intel_uncore_write(&dev_priv->uncore,
- EDP_PSR_IIR, psr_iir);
- break;
- }
- }
-
if (de_iir & DE_AUX_CHANNEL_A_IVB)
dp_aux_irq_handler(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 93ccdc6bbd032..895b9eeebef40 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -537,8 +537,6 @@ static const struct intel_device_info vlv_info = {
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
.display.has_ddi = 1, \
.display.has_fpga_dbg = 1, \
- .display.has_psr = 1, \
- .display.has_psr_hw_tracking = 1, \
.display.has_dp_mst = 1, \
.has_rc6p = 0 /* RC6p removed-by HSW */, \
HSW_PIPE_OFFSETS, \
@@ -642,6 +640,8 @@ static const struct intel_device_info chv_info = {
.has_gt_uc = 1, \
.display.has_hdcp = 1, \
.display.has_ipc = 1, \
+ .display.has_psr = 1, \
+ .display.has_psr_hw_tracking = 1, \
.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
.dbuf.slice_mask = BIT(DBUF_S1)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 72dd3a6d205d6..ee16a594ef995 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4512,11 +4512,9 @@ enum {
* HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one
* instance of it
*/
-#define _HSW_EDP_PSR_BASE 0x64800
#define _SRD_CTL_A 0x60800
#define _SRD_CTL_EDP 0x6f800
-#define _PSR_ADJ(tran, reg) (_TRANS2(tran, reg) - dev_priv->hsw_psr_mmio_adjust)
-#define EDP_PSR_CTL(tran) _MMIO(_PSR_ADJ(tran, _SRD_CTL_A))
+#define EDP_PSR_CTL(tran) _MMIO(_TRANS2(tran, _SRD_CTL_A))
#define EDP_PSR_ENABLE (1 << 31)
#define BDW_PSR_SINGLE_FRAME (1 << 30)
#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */
@@ -4560,22 +4558,13 @@ enum {
#define EDP_PSR_POST_EXIT(trans) (0x2 << _EDP_PSR_TRANS_SHIFT(trans))
#define EDP_PSR_PRE_ENTRY(trans) (0x1 << _EDP_PSR_TRANS_SHIFT(trans))
-#define _SRD_AUX_CTL_A 0x60810
-#define _SRD_AUX_CTL_EDP 0x6f810
-#define EDP_PSR_AUX_CTL(tran) _MMIO(_PSR_ADJ(tran, _SRD_AUX_CTL_A))
-#define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26)
-#define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
-#define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16)
-#define EDP_PSR_AUX_CTL_ERROR_INTERRUPT (1 << 11)
-#define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff)
-
#define _SRD_AUX_DATA_A 0x60814
#define _SRD_AUX_DATA_EDP 0x6f814
-#define EDP_PSR_AUX_DATA(tran, i) _MMIO(_PSR_ADJ(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */
+#define EDP_PSR_AUX_DATA(tran, i) _MMIO(_TRANS2(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */
#define _SRD_STATUS_A 0x60840
#define _SRD_STATUS_EDP 0x6f840
-#define EDP_PSR_STATUS(tran) _MMIO(_PSR_ADJ(tran, _SRD_STATUS_A))
+#define EDP_PSR_STATUS(tran) _MMIO(_TRANS2(tran, _SRD_STATUS_A))
#define EDP_PSR_STATUS_STATE_MASK (7 << 29)
#define EDP_PSR_STATUS_STATE_SHIFT 29
#define EDP_PSR_STATUS_STATE_IDLE (0 << 29)
@@ -4602,13 +4591,13 @@ enum {
#define _SRD_PERF_CNT_A 0x60844
#define _SRD_PERF_CNT_EDP 0x6f844
-#define EDP_PSR_PERF_CNT(tran) _MMIO(_PSR_ADJ(tran, _SRD_PERF_CNT_A))
+#define EDP_PSR_PERF_CNT(tran) _MMIO(_TRANS2(tran, _SRD_PERF_CNT_A))
#define EDP_PSR_PERF_CNT_MASK 0xffffff
/* PSR_MASK on SKL+ */
#define _SRD_DEBUG_A 0x60860
#define _SRD_DEBUG_EDP 0x6f860
-#define EDP_PSR_DEBUG(tran) _MMIO(_PSR_ADJ(tran, _SRD_DEBUG_A))
+#define EDP_PSR_DEBUG(tran) _MMIO(_TRANS2(tran, _SRD_DEBUG_A))
#define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28)
#define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
#define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
--
2.32.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [Intel-gfx] [PATCH 3/8] drm/i915/display: Move DRRS code its own file
2021-08-18 0:42 [Intel-gfx] [PATCH 0/8] Drop frontbuffer rendering support from Skylake and newer José Roberto de Souza
2021-08-18 0:42 ` [Intel-gfx] [PATCH 1/8] drm/damage_helper: Fix handling of cursor dirty buffers José Roberto de Souza
2021-08-18 0:42 ` [Intel-gfx] [PATCH 2/8] drm/i915/display: Drop PSR support from HSW and BDW José Roberto de Souza
@ 2021-08-18 0:42 ` José Roberto de Souza
2021-08-18 7:24 ` Jani Nikula
2021-08-18 0:42 ` [Intel-gfx] [PATCH 4/8] drm/i915/display: Some code improvements and code style fixes for DRRS José Roberto de Souza
` (7 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: José Roberto de Souza @ 2021-08-18 0:42 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Rodrigo Vivi, José Roberto de Souza
intel_dp.c is a 5k lines monster, so moving DRRS out of it to reduce
some lines from it.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
Documentation/gpu/i915.rst | 14 +-
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
.../drm/i915/display/intel_display_debugfs.c | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 467 +----------------
drivers/gpu/drm/i915/display/intel_dp.h | 11 -
drivers/gpu/drm/i915/display/intel_drrs.c | 477 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_drrs.h | 32 ++
.../gpu/drm/i915/display/intel_frontbuffer.c | 1 +
9 files changed, 521 insertions(+), 484 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_drrs.c
create mode 100644 drivers/gpu/drm/i915/display/intel_drrs.h
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 204ebdaadb45a..03021dfa0dd81 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -183,25 +183,25 @@ Frame Buffer Compression (FBC)
Display Refresh Rate Switching (DRRS)
-------------------------------------
-.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
:doc: Display Refresh Rate Switching (DRRS)
-.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
:functions: intel_dp_set_drrs_state
-.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
:functions: intel_edp_drrs_enable
-.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
:functions: intel_edp_drrs_disable
-.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
:functions: intel_edp_drrs_invalidate
-.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
:functions: intel_edp_drrs_flush
-.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
:functions: intel_dp_drrs_init
DPIO
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 642a5b5a1b81c..c7cf4dfdc6379 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -212,6 +212,7 @@ i915-y += \
display/intel_dpio_phy.o \
display/intel_dpll.o \
display/intel_dpll_mgr.o \
+ display/intel_drrs.o \
display/intel_dsb.o \
display/intel_fb.o \
display/intel_fbc.o \
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1ef7a65feb660..828df570a4809 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -40,6 +40,7 @@
#include "intel_dp_link_training.h"
#include "intel_dp_mst.h"
#include "intel_dpio_phy.h"
+#include "intel_drrs.h"
#include "intel_dsi.h"
#include "intel_fdi.h"
#include "intel_fifo_underrun.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 8fdacb252bb19..b136a0fc0963b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -13,6 +13,7 @@
#include "intel_display_types.h"
#include "intel_dmc.h"
#include "intel_dp.h"
+#include "intel_drrs.h"
#include "intel_fbc.h"
#include "intel_hdcp.h"
#include "intel_hdmi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 75d4ebc669411..10583b0aa489e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -55,6 +55,7 @@
#include "intel_dp_mst.h"
#include "intel_dpio_phy.h"
#include "intel_dpll.h"
+#include "intel_drrs.h"
#include "intel_fifo_underrun.h"
#include "intel_hdcp.h"
#include "intel_hdmi.h"
@@ -1603,46 +1604,6 @@ intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
}
-static void
-intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
- struct intel_crtc_state *pipe_config,
- int output_bpp, bool constant_n)
-{
- struct intel_connector *intel_connector = intel_dp->attached_connector;
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- int pixel_clock;
-
- if (pipe_config->vrr.enable)
- return;
-
- /*
- * DRRS and PSR can't be enable together, so giving preference to PSR
- * as it allows more power-savings by complete shutting down display,
- * so to guarantee this, intel_dp_drrs_compute_config() must be called
- * after intel_psr_compute_config().
- */
- if (pipe_config->has_psr)
- return;
-
- if (!intel_connector->panel.downclock_mode ||
- dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
- return;
-
- pipe_config->has_drrs = true;
-
- pixel_clock = intel_connector->panel.downclock_mode->clock;
- if (pipe_config->splitter.enable)
- pixel_clock /= pipe_config->splitter.link_count;
-
- intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
- pipe_config->port_clock, &pipe_config->dp_m2_n2,
- constant_n, pipe_config->fec_enable);
-
- /* FIXME: abstract this better */
- if (pipe_config->splitter.enable)
- pipe_config->dp_m2_n2.gmch_m *= pipe_config->splitter.link_count;
-}
-
int
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
@@ -4715,432 +4676,6 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
drm_connector_attach_vrr_capable_property(connector);
}
-/**
- * intel_dp_set_drrs_state - program registers for RR switch to take effect
- * @dev_priv: i915 device
- * @crtc_state: a pointer to the active intel_crtc_state
- * @refresh_rate: RR to be programmed
- *
- * This function gets called when refresh rate (RR) has to be changed from
- * one frequency to another. Switches can be between high and low RR
- * supported by the panel or to any other RR based on media playback (in
- * this case, RR value needs to be passed from user space).
- *
- * The caller of this function needs to take a lock on dev_priv->drrs.
- */
-static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
- const struct intel_crtc_state *crtc_state,
- int refresh_rate)
-{
- struct intel_dp *intel_dp = dev_priv->drrs.dp;
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
-
- if (refresh_rate <= 0) {
- drm_dbg_kms(&dev_priv->drm,
- "Refresh rate should be positive non-zero.\n");
- return;
- }
-
- if (intel_dp == NULL) {
- drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
- return;
- }
-
- if (!crtc) {
- drm_dbg_kms(&dev_priv->drm,
- "DRRS: intel_crtc not initialized\n");
- return;
- }
-
- if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
- drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
- return;
- }
-
- if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) ==
- refresh_rate)
- index = DRRS_LOW_RR;
-
- if (index == dev_priv->drrs.refresh_rate_type) {
- drm_dbg_kms(&dev_priv->drm,
- "DRRS requested for previously set RR...ignoring\n");
- return;
- }
-
- if (!crtc_state->hw.active) {
- drm_dbg_kms(&dev_priv->drm,
- "eDP encoder disabled. CRTC not Active\n");
- return;
- }
-
- if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
- switch (index) {
- case DRRS_HIGH_RR:
- intel_dp_set_m_n(crtc_state, M1_N1);
- break;
- case DRRS_LOW_RR:
- intel_dp_set_m_n(crtc_state, M2_N2);
- break;
- case DRRS_MAX_RR:
- default:
- drm_err(&dev_priv->drm,
- "Unsupported refreshrate type\n");
- }
- } else if (DISPLAY_VER(dev_priv) > 6) {
- i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
- u32 val;
-
- val = intel_de_read(dev_priv, reg);
- if (index > DRRS_HIGH_RR) {
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
- else
- val |= PIPECONF_EDP_RR_MODE_SWITCH;
- } else {
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
- else
- val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
- }
- intel_de_write(dev_priv, reg, val);
- }
-
- dev_priv->drrs.refresh_rate_type = index;
-
- drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
- refresh_rate);
-}
-
-static void
-intel_edp_drrs_enable_locked(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- dev_priv->drrs.busy_frontbuffer_bits = 0;
- dev_priv->drrs.dp = intel_dp;
-}
-
-/**
- * intel_edp_drrs_enable - init drrs struct if supported
- * @intel_dp: DP struct
- * @crtc_state: A pointer to the active crtc state.
- *
- * Initializes frontbuffer_bits and drrs.dp
- */
-void intel_edp_drrs_enable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- if (!crtc_state->has_drrs)
- return;
-
- drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
-
- mutex_lock(&dev_priv->drrs.mutex);
-
- if (dev_priv->drrs.dp) {
- drm_warn(&dev_priv->drm, "DRRS already enabled\n");
- goto unlock;
- }
-
- intel_edp_drrs_enable_locked(intel_dp);
-
-unlock:
- mutex_unlock(&dev_priv->drrs.mutex);
-}
-
-static void
-intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
- int refresh;
-
- refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
- intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
- }
-
- dev_priv->drrs.dp = NULL;
-}
-
-/**
- * intel_edp_drrs_disable - Disable DRRS
- * @intel_dp: DP struct
- * @old_crtc_state: Pointer to old crtc_state.
- *
- */
-void intel_edp_drrs_disable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *old_crtc_state)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- if (!old_crtc_state->has_drrs)
- return;
-
- mutex_lock(&dev_priv->drrs.mutex);
- if (!dev_priv->drrs.dp) {
- mutex_unlock(&dev_priv->drrs.mutex);
- return;
- }
-
- intel_edp_drrs_disable_locked(intel_dp, old_crtc_state);
- mutex_unlock(&dev_priv->drrs.mutex);
-
- cancel_delayed_work_sync(&dev_priv->drrs.work);
-}
-
-/**
- * intel_edp_drrs_update - Update DRRS state
- * @intel_dp: Intel DP
- * @crtc_state: new CRTC state
- *
- * This function will update DRRS states, disabling or enabling DRRS when
- * executing fastsets. For full modeset, intel_edp_drrs_disable() and
- * intel_edp_drrs_enable() should be called instead.
- */
-void
-intel_edp_drrs_update(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
- return;
-
- mutex_lock(&dev_priv->drrs.mutex);
-
- /* New state matches current one? */
- if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
- goto unlock;
-
- if (crtc_state->has_drrs)
- intel_edp_drrs_enable_locked(intel_dp);
- else
- intel_edp_drrs_disable_locked(intel_dp, crtc_state);
-
-unlock:
- mutex_unlock(&dev_priv->drrs.mutex);
-}
-
-static void intel_edp_drrs_downclock_work(struct work_struct *work)
-{
- struct drm_i915_private *dev_priv =
- container_of(work, typeof(*dev_priv), drrs.work.work);
- struct intel_dp *intel_dp;
-
- mutex_lock(&dev_priv->drrs.mutex);
-
- intel_dp = dev_priv->drrs.dp;
-
- if (!intel_dp)
- goto unlock;
-
- /*
- * The delayed work can race with an invalidate hence we need to
- * recheck.
- */
-
- if (dev_priv->drrs.busy_frontbuffer_bits)
- goto unlock;
-
- if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
- struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
-
- intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
- drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
- }
-
-unlock:
- mutex_unlock(&dev_priv->drrs.mutex);
-}
-
-/**
- * intel_edp_drrs_invalidate - Disable Idleness DRRS
- * @dev_priv: i915 device
- * @frontbuffer_bits: frontbuffer plane tracking bits
- *
- * This function gets called everytime rendering on the given planes start.
- * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
- *
- * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
- */
-void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
- unsigned int frontbuffer_bits)
-{
- struct intel_dp *intel_dp;
- struct drm_crtc *crtc;
- enum pipe pipe;
-
- if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
- return;
-
- cancel_delayed_work(&dev_priv->drrs.work);
-
- mutex_lock(&dev_priv->drrs.mutex);
-
- intel_dp = dev_priv->drrs.dp;
- if (!intel_dp) {
- mutex_unlock(&dev_priv->drrs.mutex);
- return;
- }
-
- crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
- pipe = to_intel_crtc(crtc)->pipe;
-
- frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
- dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
-
- /* invalidate means busy screen hence upclock */
- if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
- intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
- drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
-
- mutex_unlock(&dev_priv->drrs.mutex);
-}
-
-/**
- * intel_edp_drrs_flush - Restart Idleness DRRS
- * @dev_priv: i915 device
- * @frontbuffer_bits: frontbuffer plane tracking bits
- *
- * This function gets called every time rendering on the given planes has
- * completed or flip on a crtc is completed. So DRRS should be upclocked
- * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
- * if no other planes are dirty.
- *
- * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
- */
-void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
- unsigned int frontbuffer_bits)
-{
- struct intel_dp *intel_dp;
- struct drm_crtc *crtc;
- enum pipe pipe;
-
- if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
- return;
-
- cancel_delayed_work(&dev_priv->drrs.work);
-
- mutex_lock(&dev_priv->drrs.mutex);
-
- intel_dp = dev_priv->drrs.dp;
- if (!intel_dp) {
- mutex_unlock(&dev_priv->drrs.mutex);
- return;
- }
-
- crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
- pipe = to_intel_crtc(crtc)->pipe;
-
- frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
- dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
-
- /* flush means busy screen hence upclock */
- if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
- intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
- drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
-
- /*
- * flush also means no more activity hence schedule downclock, if all
- * other fbs are quiescent too
- */
- if (!dev_priv->drrs.busy_frontbuffer_bits)
- schedule_delayed_work(&dev_priv->drrs.work,
- msecs_to_jiffies(1000));
- mutex_unlock(&dev_priv->drrs.mutex);
-}
-
-/**
- * DOC: Display Refresh Rate Switching (DRRS)
- *
- * Display Refresh Rate Switching (DRRS) is a power conservation feature
- * which enables swtching between low and high refresh rates,
- * dynamically, based on the usage scenario. This feature is applicable
- * for internal panels.
- *
- * Indication that the panel supports DRRS is given by the panel EDID, which
- * would list multiple refresh rates for one resolution.
- *
- * DRRS is of 2 types - static and seamless.
- * Static DRRS involves changing refresh rate (RR) by doing a full modeset
- * (may appear as a blink on screen) and is used in dock-undock scenario.
- * Seamless DRRS involves changing RR without any visual effect to the user
- * and can be used during normal system usage. This is done by programming
- * certain registers.
- *
- * Support for static/seamless DRRS may be indicated in the VBT based on
- * inputs from the panel spec.
- *
- * DRRS saves power by switching to low RR based on usage scenarios.
- *
- * The implementation is based on frontbuffer tracking implementation. When
- * there is a disturbance on the screen triggered by user activity or a periodic
- * system activity, DRRS is disabled (RR is changed to high RR). When there is
- * no movement on screen, after a timeout of 1 second, a switch to low RR is
- * made.
- *
- * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
- * and intel_edp_drrs_flush() are called.
- *
- * DRRS can be further extended to support other internal panels and also
- * the scenario of video playback wherein RR is set based on the rate
- * requested by userspace.
- */
-
-/**
- * intel_dp_drrs_init - Init basic DRRS work and mutex.
- * @connector: eDP connector
- * @fixed_mode: preferred mode of panel
- *
- * This function is called only once at driver load to initialize basic
- * DRRS stuff.
- *
- * Returns:
- * Downclock mode if panel supports it, else return NULL.
- * DRRS support is determined by the presence of downclock mode (apart
- * from VBT setting).
- */
-static struct drm_display_mode *
-intel_dp_drrs_init(struct intel_connector *connector,
- struct drm_display_mode *fixed_mode)
-{
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- struct drm_display_mode *downclock_mode = NULL;
-
- INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
- mutex_init(&dev_priv->drrs.mutex);
-
- if (DISPLAY_VER(dev_priv) <= 6) {
- drm_dbg_kms(&dev_priv->drm,
- "DRRS supported for Gen7 and above\n");
- return NULL;
- }
-
- if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
- drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
- return NULL;
- }
-
- downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
- if (!downclock_mode) {
- drm_dbg_kms(&dev_priv->drm,
- "Downclock mode is not found. DRRS not supported\n");
- return NULL;
- }
-
- dev_priv->drrs.type = dev_priv->vbt.drrs_type;
-
- dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
- drm_dbg_kms(&dev_priv->drm,
- "seamless DRRS supported for eDP panel.\n");
- return downclock_mode;
-}
-
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
struct intel_connector *intel_connector)
{
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 680631b5b4378..38ff0e4f65504 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -70,17 +70,6 @@ int intel_dp_max_link_rate(struct intel_dp *intel_dp);
int intel_dp_max_lane_count(struct intel_dp *intel_dp);
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
-void intel_edp_drrs_enable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state);
-void intel_edp_drrs_disable(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state);
-void intel_edp_drrs_update(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state);
-void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
- unsigned int frontbuffer_bits);
-void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
- unsigned int frontbuffer_bits);
-
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
u8 *link_bw, u8 *rate_select);
bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
new file mode 100644
index 0000000000000..be9b6d4482f04
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -0,0 +1,477 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_atomic.h"
+#include "intel_de.h"
+#include "intel_display_types.h"
+#include "intel_drrs.h"
+#include "intel_panel.h"
+
+/**
+ * DOC: Display Refresh Rate Switching (DRRS)
+ *
+ * Display Refresh Rate Switching (DRRS) is a power conservation feature
+ * which enables swtching between low and high refresh rates,
+ * dynamically, based on the usage scenario. This feature is applicable
+ * for internal panels.
+ *
+ * Indication that the panel supports DRRS is given by the panel EDID, which
+ * would list multiple refresh rates for one resolution.
+ *
+ * DRRS is of 2 types - static and seamless.
+ * Static DRRS involves changing refresh rate (RR) by doing a full modeset
+ * (may appear as a blink on screen) and is used in dock-undock scenario.
+ * Seamless DRRS involves changing RR without any visual effect to the user
+ * and can be used during normal system usage. This is done by programming
+ * certain registers.
+ *
+ * Support for static/seamless DRRS may be indicated in the VBT based on
+ * inputs from the panel spec.
+ *
+ * DRRS saves power by switching to low RR based on usage scenarios.
+ *
+ * The implementation is based on frontbuffer tracking implementation. When
+ * there is a disturbance on the screen triggered by user activity or a periodic
+ * system activity, DRRS is disabled (RR is changed to high RR). When there is
+ * no movement on screen, after a timeout of 1 second, a switch to low RR is
+ * made.
+ *
+ * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
+ * and intel_edp_drrs_flush() are called.
+ *
+ * DRRS can be further extended to support other internal panels and also
+ * the scenario of video playback wherein RR is set based on the rate
+ * requested by userspace.
+ */
+
+void
+intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int output_bpp, bool constant_n)
+{
+ struct intel_connector *intel_connector = intel_dp->attached_connector;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ int pixel_clock;
+
+ if (pipe_config->vrr.enable)
+ return;
+
+ /*
+ * DRRS and PSR can't be enable together, so giving preference to PSR
+ * as it allows more power-savings by complete shutting down display,
+ * so to guarantee this, intel_dp_drrs_compute_config() must be called
+ * after intel_psr_compute_config().
+ */
+ if (pipe_config->has_psr)
+ return;
+
+ if (!intel_connector->panel.downclock_mode ||
+ dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
+ return;
+
+ pipe_config->has_drrs = true;
+
+ pixel_clock = intel_connector->panel.downclock_mode->clock;
+ if (pipe_config->splitter.enable)
+ pixel_clock /= pipe_config->splitter.link_count;
+
+ intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
+ pipe_config->port_clock, &pipe_config->dp_m2_n2,
+ constant_n, pipe_config->fec_enable);
+
+ /* FIXME: abstract this better */
+ if (pipe_config->splitter.enable)
+ pipe_config->dp_m2_n2.gmch_m *= pipe_config->splitter.link_count;
+}
+
+/**
+ * intel_dp_set_drrs_state - program registers for RR switch to take effect
+ * @dev_priv: i915 device
+ * @crtc_state: a pointer to the active intel_crtc_state
+ * @refresh_rate: RR to be programmed
+ *
+ * This function gets called when refresh rate (RR) has to be changed from
+ * one frequency to another. Switches can be between high and low RR
+ * supported by the panel or to any other RR based on media playback (in
+ * this case, RR value needs to be passed from user space).
+ *
+ * The caller of this function needs to take a lock on dev_priv->drrs.
+ */
+static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
+ const struct intel_crtc_state *crtc_state,
+ int refresh_rate)
+{
+ struct intel_dp *intel_dp = dev_priv->drrs.dp;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
+
+ if (refresh_rate <= 0) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Refresh rate should be positive non-zero.\n");
+ return;
+ }
+
+ if (intel_dp == NULL) {
+ drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
+ return;
+ }
+
+ if (!crtc) {
+ drm_dbg_kms(&dev_priv->drm,
+ "DRRS: intel_crtc not initialized\n");
+ return;
+ }
+
+ if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
+ drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
+ return;
+ }
+
+ if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) ==
+ refresh_rate)
+ index = DRRS_LOW_RR;
+
+ if (index == dev_priv->drrs.refresh_rate_type) {
+ drm_dbg_kms(&dev_priv->drm,
+ "DRRS requested for previously set RR...ignoring\n");
+ return;
+ }
+
+ if (!crtc_state->hw.active) {
+ drm_dbg_kms(&dev_priv->drm,
+ "eDP encoder disabled. CRTC not Active\n");
+ return;
+ }
+
+ if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
+ switch (index) {
+ case DRRS_HIGH_RR:
+ intel_dp_set_m_n(crtc_state, M1_N1);
+ break;
+ case DRRS_LOW_RR:
+ intel_dp_set_m_n(crtc_state, M2_N2);
+ break;
+ case DRRS_MAX_RR:
+ default:
+ drm_err(&dev_priv->drm,
+ "Unsupported refreshrate type\n");
+ }
+ } else if (DISPLAY_VER(dev_priv) > 6) {
+ i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
+ u32 val;
+
+ val = intel_de_read(dev_priv, reg);
+ if (index > DRRS_HIGH_RR) {
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+ val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
+ else
+ val |= PIPECONF_EDP_RR_MODE_SWITCH;
+ } else {
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+ val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
+ else
+ val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
+ }
+ intel_de_write(dev_priv, reg, val);
+ }
+
+ dev_priv->drrs.refresh_rate_type = index;
+
+ drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
+ refresh_rate);
+}
+
+static void
+intel_edp_drrs_enable_locked(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ dev_priv->drrs.busy_frontbuffer_bits = 0;
+ dev_priv->drrs.dp = intel_dp;
+}
+
+/**
+ * intel_edp_drrs_enable - init drrs struct if supported
+ * @intel_dp: DP struct
+ * @crtc_state: A pointer to the active crtc state.
+ *
+ * Initializes frontbuffer_bits and drrs.dp
+ */
+void intel_edp_drrs_enable(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ if (!crtc_state->has_drrs)
+ return;
+
+ drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
+
+ mutex_lock(&dev_priv->drrs.mutex);
+
+ if (dev_priv->drrs.dp) {
+ drm_warn(&dev_priv->drm, "DRRS already enabled\n");
+ goto unlock;
+ }
+
+ intel_edp_drrs_enable_locked(intel_dp);
+
+unlock:
+ mutex_unlock(&dev_priv->drrs.mutex);
+}
+
+static void
+intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
+ int refresh;
+
+ refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
+ intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
+ }
+
+ dev_priv->drrs.dp = NULL;
+}
+
+/**
+ * intel_edp_drrs_disable - Disable DRRS
+ * @intel_dp: DP struct
+ * @old_crtc_state: Pointer to old crtc_state.
+ *
+ */
+void intel_edp_drrs_disable(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *old_crtc_state)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ if (!old_crtc_state->has_drrs)
+ return;
+
+ mutex_lock(&dev_priv->drrs.mutex);
+ if (!dev_priv->drrs.dp) {
+ mutex_unlock(&dev_priv->drrs.mutex);
+ return;
+ }
+
+ intel_edp_drrs_disable_locked(intel_dp, old_crtc_state);
+ mutex_unlock(&dev_priv->drrs.mutex);
+
+ cancel_delayed_work_sync(&dev_priv->drrs.work);
+}
+
+/**
+ * intel_edp_drrs_update - Update DRRS state
+ * @intel_dp: Intel DP
+ * @crtc_state: new CRTC state
+ *
+ * This function will update DRRS states, disabling or enabling DRRS when
+ * executing fastsets. For full modeset, intel_edp_drrs_disable() and
+ * intel_edp_drrs_enable() should be called instead.
+ */
+void
+intel_edp_drrs_update(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
+ return;
+
+ mutex_lock(&dev_priv->drrs.mutex);
+
+ /* New state matches current one? */
+ if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
+ goto unlock;
+
+ if (crtc_state->has_drrs)
+ intel_edp_drrs_enable_locked(intel_dp);
+ else
+ intel_edp_drrs_disable_locked(intel_dp, crtc_state);
+
+unlock:
+ mutex_unlock(&dev_priv->drrs.mutex);
+}
+
+static void intel_edp_drrs_downclock_work(struct work_struct *work)
+{
+ struct drm_i915_private *dev_priv =
+ container_of(work, typeof(*dev_priv), drrs.work.work);
+ struct intel_dp *intel_dp;
+
+ mutex_lock(&dev_priv->drrs.mutex);
+
+ intel_dp = dev_priv->drrs.dp;
+
+ if (!intel_dp)
+ goto unlock;
+
+ /*
+ * The delayed work can race with an invalidate hence we need to
+ * recheck.
+ */
+
+ if (dev_priv->drrs.busy_frontbuffer_bits)
+ goto unlock;
+
+ if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
+ struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
+
+ intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
+ drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
+ }
+
+unlock:
+ mutex_unlock(&dev_priv->drrs.mutex);
+}
+
+/**
+ * intel_edp_drrs_invalidate - Disable Idleness DRRS
+ * @dev_priv: i915 device
+ * @frontbuffer_bits: frontbuffer plane tracking bits
+ *
+ * This function gets called everytime rendering on the given planes start.
+ * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
+ *
+ * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
+ */
+void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
+ unsigned int frontbuffer_bits)
+{
+ struct intel_dp *intel_dp;
+ struct drm_crtc *crtc;
+ enum pipe pipe;
+
+ if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
+ return;
+
+ cancel_delayed_work(&dev_priv->drrs.work);
+
+ mutex_lock(&dev_priv->drrs.mutex);
+
+ intel_dp = dev_priv->drrs.dp;
+ if (!intel_dp) {
+ mutex_unlock(&dev_priv->drrs.mutex);
+ return;
+ }
+
+ crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
+ pipe = to_intel_crtc(crtc)->pipe;
+
+ frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
+ dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
+
+ /* invalidate means busy screen hence upclock */
+ if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
+ intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
+ drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
+
+ mutex_unlock(&dev_priv->drrs.mutex);
+}
+
+/**
+ * intel_edp_drrs_flush - Restart Idleness DRRS
+ * @dev_priv: i915 device
+ * @frontbuffer_bits: frontbuffer plane tracking bits
+ *
+ * This function gets called every time rendering on the given planes has
+ * completed or flip on a crtc is completed. So DRRS should be upclocked
+ * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
+ * if no other planes are dirty.
+ *
+ * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
+ */
+void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
+ unsigned int frontbuffer_bits)
+{
+ struct intel_dp *intel_dp;
+ struct drm_crtc *crtc;
+ enum pipe pipe;
+
+ if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
+ return;
+
+ cancel_delayed_work(&dev_priv->drrs.work);
+
+ mutex_lock(&dev_priv->drrs.mutex);
+
+ intel_dp = dev_priv->drrs.dp;
+ if (!intel_dp) {
+ mutex_unlock(&dev_priv->drrs.mutex);
+ return;
+ }
+
+ crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
+ pipe = to_intel_crtc(crtc)->pipe;
+
+ frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
+ dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
+
+ /* flush means busy screen hence upclock */
+ if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
+ intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
+ drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
+
+ /*
+ * flush also means no more activity hence schedule downclock, if all
+ * other fbs are quiescent too
+ */
+ if (!dev_priv->drrs.busy_frontbuffer_bits)
+ schedule_delayed_work(&dev_priv->drrs.work,
+ msecs_to_jiffies(1000));
+ mutex_unlock(&dev_priv->drrs.mutex);
+}
+
+/**
+ * intel_dp_drrs_init - Init basic DRRS work and mutex.
+ * @connector: eDP connector
+ * @fixed_mode: preferred mode of panel
+ *
+ * This function is called only once at driver load to initialize basic
+ * DRRS stuff.
+ *
+ * Returns:
+ * Downclock mode if panel supports it, else return NULL.
+ * DRRS support is determined by the presence of downclock mode (apart
+ * from VBT setting).
+ */
+struct drm_display_mode *
+intel_dp_drrs_init(struct intel_connector *connector,
+ struct drm_display_mode *fixed_mode)
+{
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct drm_display_mode *downclock_mode = NULL;
+
+ INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
+ mutex_init(&dev_priv->drrs.mutex);
+
+ if (DISPLAY_VER(dev_priv) <= 6) {
+ drm_dbg_kms(&dev_priv->drm,
+ "DRRS supported for Gen7 and above\n");
+ return NULL;
+ }
+
+ if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
+ drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
+ return NULL;
+ }
+
+ downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
+ if (!downclock_mode) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Downclock mode is not found. DRRS not supported\n");
+ return NULL;
+ }
+
+ dev_priv->drrs.type = dev_priv->vbt.drrs_type;
+
+ dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
+ drm_dbg_kms(&dev_priv->drm,
+ "seamless DRRS supported for eDP panel.\n");
+ return downclock_mode;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.h b/drivers/gpu/drm/i915/display/intel_drrs.h
new file mode 100644
index 0000000000000..ffa175b4cf4f4
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_drrs.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef __INTEL_DRRS_H__
+#define __INTEL_DRRS_H__
+
+#include <linux/types.h>
+
+struct drm_i915_private;
+struct intel_crtc_state;
+struct intel_connector;
+struct intel_dp;
+
+void intel_edp_drrs_enable(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state);
+void intel_edp_drrs_disable(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state);
+void intel_edp_drrs_update(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state);
+void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
+ unsigned int frontbuffer_bits);
+void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
+ unsigned int frontbuffer_bits);
+void intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int output_bpp, bool constant_n);
+struct drm_display_mode *intel_dp_drrs_init(struct intel_connector *connector,
+ struct drm_display_mode *fixed_mode);
+
+#endif /* __INTEL_DRRS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
index 8e75debcce1a9..e4834d84ce5e3 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
@@ -62,6 +62,7 @@
#include "intel_display_types.h"
#include "intel_fbc.h"
#include "intel_frontbuffer.h"
+#include "intel_drrs.h"
#include "intel_psr.h"
/**
--
2.32.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [PATCH 3/8] drm/i915/display: Move DRRS code its own file
2021-08-18 0:42 ` [Intel-gfx] [PATCH 3/8] drm/i915/display: Move DRRS code its own file José Roberto de Souza
@ 2021-08-18 7:24 ` Jani Nikula
2021-08-19 0:44 ` Souza, Jose
0 siblings, 1 reply; 22+ messages in thread
From: Jani Nikula @ 2021-08-18 7:24 UTC (permalink / raw)
To: José Roberto de Souza, intel-gfx
Cc: Rodrigo Vivi, José Roberto de Souza
On Tue, 17 Aug 2021, José Roberto de Souza <jose.souza@intel.com> wrote:
> intel_dp.c is a 5k lines monster, so moving DRRS out of it to reduce
> some lines from it.
The functions in a file should be named after the file prefix,
i.e. intel_drrs_*() here. The renames don't need to be in the same
patch, but I think we need to have them. (Probably should be a separate
patch to keep the code movement easier to review.)
BR,
Jani.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> Documentation/gpu/i915.rst | 14 +-
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
> .../drm/i915/display/intel_display_debugfs.c | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 467 +----------------
> drivers/gpu/drm/i915/display/intel_dp.h | 11 -
> drivers/gpu/drm/i915/display/intel_drrs.c | 477 ++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_drrs.h | 32 ++
> .../gpu/drm/i915/display/intel_frontbuffer.c | 1 +
> 9 files changed, 521 insertions(+), 484 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_drrs.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_drrs.h
>
> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> index 204ebdaadb45a..03021dfa0dd81 100644
> --- a/Documentation/gpu/i915.rst
> +++ b/Documentation/gpu/i915.rst
> @@ -183,25 +183,25 @@ Frame Buffer Compression (FBC)
> Display Refresh Rate Switching (DRRS)
> -------------------------------------
>
> -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
> +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> :doc: Display Refresh Rate Switching (DRRS)
>
> -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
> +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> :functions: intel_dp_set_drrs_state
>
> -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
> +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> :functions: intel_edp_drrs_enable
>
> -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
> +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> :functions: intel_edp_drrs_disable
>
> -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
> +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> :functions: intel_edp_drrs_invalidate
>
> -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
> +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> :functions: intel_edp_drrs_flush
>
> -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
> +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> :functions: intel_dp_drrs_init
>
> DPIO
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 642a5b5a1b81c..c7cf4dfdc6379 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -212,6 +212,7 @@ i915-y += \
> display/intel_dpio_phy.o \
> display/intel_dpll.o \
> display/intel_dpll_mgr.o \
> + display/intel_drrs.o \
> display/intel_dsb.o \
> display/intel_fb.o \
> display/intel_fbc.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 1ef7a65feb660..828df570a4809 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -40,6 +40,7 @@
> #include "intel_dp_link_training.h"
> #include "intel_dp_mst.h"
> #include "intel_dpio_phy.h"
> +#include "intel_drrs.h"
> #include "intel_dsi.h"
> #include "intel_fdi.h"
> #include "intel_fifo_underrun.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 8fdacb252bb19..b136a0fc0963b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -13,6 +13,7 @@
> #include "intel_display_types.h"
> #include "intel_dmc.h"
> #include "intel_dp.h"
> +#include "intel_drrs.h"
> #include "intel_fbc.h"
> #include "intel_hdcp.h"
> #include "intel_hdmi.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 75d4ebc669411..10583b0aa489e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -55,6 +55,7 @@
> #include "intel_dp_mst.h"
> #include "intel_dpio_phy.h"
> #include "intel_dpll.h"
> +#include "intel_drrs.h"
> #include "intel_fifo_underrun.h"
> #include "intel_hdcp.h"
> #include "intel_hdmi.h"
> @@ -1603,46 +1604,6 @@ intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
> intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
> }
>
> -static void
> -intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
> - struct intel_crtc_state *pipe_config,
> - int output_bpp, bool constant_n)
> -{
> - struct intel_connector *intel_connector = intel_dp->attached_connector;
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - int pixel_clock;
> -
> - if (pipe_config->vrr.enable)
> - return;
> -
> - /*
> - * DRRS and PSR can't be enable together, so giving preference to PSR
> - * as it allows more power-savings by complete shutting down display,
> - * so to guarantee this, intel_dp_drrs_compute_config() must be called
> - * after intel_psr_compute_config().
> - */
> - if (pipe_config->has_psr)
> - return;
> -
> - if (!intel_connector->panel.downclock_mode ||
> - dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
> - return;
> -
> - pipe_config->has_drrs = true;
> -
> - pixel_clock = intel_connector->panel.downclock_mode->clock;
> - if (pipe_config->splitter.enable)
> - pixel_clock /= pipe_config->splitter.link_count;
> -
> - intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
> - pipe_config->port_clock, &pipe_config->dp_m2_n2,
> - constant_n, pipe_config->fec_enable);
> -
> - /* FIXME: abstract this better */
> - if (pipe_config->splitter.enable)
> - pipe_config->dp_m2_n2.gmch_m *= pipe_config->splitter.link_count;
> -}
> -
> int
> intel_dp_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config,
> @@ -4715,432 +4676,6 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
> drm_connector_attach_vrr_capable_property(connector);
> }
>
> -/**
> - * intel_dp_set_drrs_state - program registers for RR switch to take effect
> - * @dev_priv: i915 device
> - * @crtc_state: a pointer to the active intel_crtc_state
> - * @refresh_rate: RR to be programmed
> - *
> - * This function gets called when refresh rate (RR) has to be changed from
> - * one frequency to another. Switches can be between high and low RR
> - * supported by the panel or to any other RR based on media playback (in
> - * this case, RR value needs to be passed from user space).
> - *
> - * The caller of this function needs to take a lock on dev_priv->drrs.
> - */
> -static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
> - const struct intel_crtc_state *crtc_state,
> - int refresh_rate)
> -{
> - struct intel_dp *intel_dp = dev_priv->drrs.dp;
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
> -
> - if (refresh_rate <= 0) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Refresh rate should be positive non-zero.\n");
> - return;
> - }
> -
> - if (intel_dp == NULL) {
> - drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
> - return;
> - }
> -
> - if (!crtc) {
> - drm_dbg_kms(&dev_priv->drm,
> - "DRRS: intel_crtc not initialized\n");
> - return;
> - }
> -
> - if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
> - drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
> - return;
> - }
> -
> - if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) ==
> - refresh_rate)
> - index = DRRS_LOW_RR;
> -
> - if (index == dev_priv->drrs.refresh_rate_type) {
> - drm_dbg_kms(&dev_priv->drm,
> - "DRRS requested for previously set RR...ignoring\n");
> - return;
> - }
> -
> - if (!crtc_state->hw.active) {
> - drm_dbg_kms(&dev_priv->drm,
> - "eDP encoder disabled. CRTC not Active\n");
> - return;
> - }
> -
> - if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
> - switch (index) {
> - case DRRS_HIGH_RR:
> - intel_dp_set_m_n(crtc_state, M1_N1);
> - break;
> - case DRRS_LOW_RR:
> - intel_dp_set_m_n(crtc_state, M2_N2);
> - break;
> - case DRRS_MAX_RR:
> - default:
> - drm_err(&dev_priv->drm,
> - "Unsupported refreshrate type\n");
> - }
> - } else if (DISPLAY_VER(dev_priv) > 6) {
> - i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
> - u32 val;
> -
> - val = intel_de_read(dev_priv, reg);
> - if (index > DRRS_HIGH_RR) {
> - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> - val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
> - else
> - val |= PIPECONF_EDP_RR_MODE_SWITCH;
> - } else {
> - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> - val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
> - else
> - val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
> - }
> - intel_de_write(dev_priv, reg, val);
> - }
> -
> - dev_priv->drrs.refresh_rate_type = index;
> -
> - drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
> - refresh_rate);
> -}
> -
> -static void
> -intel_edp_drrs_enable_locked(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -
> - dev_priv->drrs.busy_frontbuffer_bits = 0;
> - dev_priv->drrs.dp = intel_dp;
> -}
> -
> -/**
> - * intel_edp_drrs_enable - init drrs struct if supported
> - * @intel_dp: DP struct
> - * @crtc_state: A pointer to the active crtc state.
> - *
> - * Initializes frontbuffer_bits and drrs.dp
> - */
> -void intel_edp_drrs_enable(struct intel_dp *intel_dp,
> - const struct intel_crtc_state *crtc_state)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -
> - if (!crtc_state->has_drrs)
> - return;
> -
> - drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
> -
> - mutex_lock(&dev_priv->drrs.mutex);
> -
> - if (dev_priv->drrs.dp) {
> - drm_warn(&dev_priv->drm, "DRRS already enabled\n");
> - goto unlock;
> - }
> -
> - intel_edp_drrs_enable_locked(intel_dp);
> -
> -unlock:
> - mutex_unlock(&dev_priv->drrs.mutex);
> -}
> -
> -static void
> -intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
> - const struct intel_crtc_state *crtc_state)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -
> - if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
> - int refresh;
> -
> - refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
> - intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
> - }
> -
> - dev_priv->drrs.dp = NULL;
> -}
> -
> -/**
> - * intel_edp_drrs_disable - Disable DRRS
> - * @intel_dp: DP struct
> - * @old_crtc_state: Pointer to old crtc_state.
> - *
> - */
> -void intel_edp_drrs_disable(struct intel_dp *intel_dp,
> - const struct intel_crtc_state *old_crtc_state)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -
> - if (!old_crtc_state->has_drrs)
> - return;
> -
> - mutex_lock(&dev_priv->drrs.mutex);
> - if (!dev_priv->drrs.dp) {
> - mutex_unlock(&dev_priv->drrs.mutex);
> - return;
> - }
> -
> - intel_edp_drrs_disable_locked(intel_dp, old_crtc_state);
> - mutex_unlock(&dev_priv->drrs.mutex);
> -
> - cancel_delayed_work_sync(&dev_priv->drrs.work);
> -}
> -
> -/**
> - * intel_edp_drrs_update - Update DRRS state
> - * @intel_dp: Intel DP
> - * @crtc_state: new CRTC state
> - *
> - * This function will update DRRS states, disabling or enabling DRRS when
> - * executing fastsets. For full modeset, intel_edp_drrs_disable() and
> - * intel_edp_drrs_enable() should be called instead.
> - */
> -void
> -intel_edp_drrs_update(struct intel_dp *intel_dp,
> - const struct intel_crtc_state *crtc_state)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -
> - if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
> - return;
> -
> - mutex_lock(&dev_priv->drrs.mutex);
> -
> - /* New state matches current one? */
> - if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
> - goto unlock;
> -
> - if (crtc_state->has_drrs)
> - intel_edp_drrs_enable_locked(intel_dp);
> - else
> - intel_edp_drrs_disable_locked(intel_dp, crtc_state);
> -
> -unlock:
> - mutex_unlock(&dev_priv->drrs.mutex);
> -}
> -
> -static void intel_edp_drrs_downclock_work(struct work_struct *work)
> -{
> - struct drm_i915_private *dev_priv =
> - container_of(work, typeof(*dev_priv), drrs.work.work);
> - struct intel_dp *intel_dp;
> -
> - mutex_lock(&dev_priv->drrs.mutex);
> -
> - intel_dp = dev_priv->drrs.dp;
> -
> - if (!intel_dp)
> - goto unlock;
> -
> - /*
> - * The delayed work can race with an invalidate hence we need to
> - * recheck.
> - */
> -
> - if (dev_priv->drrs.busy_frontbuffer_bits)
> - goto unlock;
> -
> - if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
> - struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
> -
> - intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
> - drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
> - }
> -
> -unlock:
> - mutex_unlock(&dev_priv->drrs.mutex);
> -}
> -
> -/**
> - * intel_edp_drrs_invalidate - Disable Idleness DRRS
> - * @dev_priv: i915 device
> - * @frontbuffer_bits: frontbuffer plane tracking bits
> - *
> - * This function gets called everytime rendering on the given planes start.
> - * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
> - *
> - * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
> - */
> -void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
> - unsigned int frontbuffer_bits)
> -{
> - struct intel_dp *intel_dp;
> - struct drm_crtc *crtc;
> - enum pipe pipe;
> -
> - if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
> - return;
> -
> - cancel_delayed_work(&dev_priv->drrs.work);
> -
> - mutex_lock(&dev_priv->drrs.mutex);
> -
> - intel_dp = dev_priv->drrs.dp;
> - if (!intel_dp) {
> - mutex_unlock(&dev_priv->drrs.mutex);
> - return;
> - }
> -
> - crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
> - pipe = to_intel_crtc(crtc)->pipe;
> -
> - frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
> - dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
> -
> - /* invalidate means busy screen hence upclock */
> - if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
> - intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
> - drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
> -
> - mutex_unlock(&dev_priv->drrs.mutex);
> -}
> -
> -/**
> - * intel_edp_drrs_flush - Restart Idleness DRRS
> - * @dev_priv: i915 device
> - * @frontbuffer_bits: frontbuffer plane tracking bits
> - *
> - * This function gets called every time rendering on the given planes has
> - * completed or flip on a crtc is completed. So DRRS should be upclocked
> - * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
> - * if no other planes are dirty.
> - *
> - * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
> - */
> -void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
> - unsigned int frontbuffer_bits)
> -{
> - struct intel_dp *intel_dp;
> - struct drm_crtc *crtc;
> - enum pipe pipe;
> -
> - if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
> - return;
> -
> - cancel_delayed_work(&dev_priv->drrs.work);
> -
> - mutex_lock(&dev_priv->drrs.mutex);
> -
> - intel_dp = dev_priv->drrs.dp;
> - if (!intel_dp) {
> - mutex_unlock(&dev_priv->drrs.mutex);
> - return;
> - }
> -
> - crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
> - pipe = to_intel_crtc(crtc)->pipe;
> -
> - frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
> - dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
> -
> - /* flush means busy screen hence upclock */
> - if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
> - intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
> - drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
> -
> - /*
> - * flush also means no more activity hence schedule downclock, if all
> - * other fbs are quiescent too
> - */
> - if (!dev_priv->drrs.busy_frontbuffer_bits)
> - schedule_delayed_work(&dev_priv->drrs.work,
> - msecs_to_jiffies(1000));
> - mutex_unlock(&dev_priv->drrs.mutex);
> -}
> -
> -/**
> - * DOC: Display Refresh Rate Switching (DRRS)
> - *
> - * Display Refresh Rate Switching (DRRS) is a power conservation feature
> - * which enables swtching between low and high refresh rates,
> - * dynamically, based on the usage scenario. This feature is applicable
> - * for internal panels.
> - *
> - * Indication that the panel supports DRRS is given by the panel EDID, which
> - * would list multiple refresh rates for one resolution.
> - *
> - * DRRS is of 2 types - static and seamless.
> - * Static DRRS involves changing refresh rate (RR) by doing a full modeset
> - * (may appear as a blink on screen) and is used in dock-undock scenario.
> - * Seamless DRRS involves changing RR without any visual effect to the user
> - * and can be used during normal system usage. This is done by programming
> - * certain registers.
> - *
> - * Support for static/seamless DRRS may be indicated in the VBT based on
> - * inputs from the panel spec.
> - *
> - * DRRS saves power by switching to low RR based on usage scenarios.
> - *
> - * The implementation is based on frontbuffer tracking implementation. When
> - * there is a disturbance on the screen triggered by user activity or a periodic
> - * system activity, DRRS is disabled (RR is changed to high RR). When there is
> - * no movement on screen, after a timeout of 1 second, a switch to low RR is
> - * made.
> - *
> - * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
> - * and intel_edp_drrs_flush() are called.
> - *
> - * DRRS can be further extended to support other internal panels and also
> - * the scenario of video playback wherein RR is set based on the rate
> - * requested by userspace.
> - */
> -
> -/**
> - * intel_dp_drrs_init - Init basic DRRS work and mutex.
> - * @connector: eDP connector
> - * @fixed_mode: preferred mode of panel
> - *
> - * This function is called only once at driver load to initialize basic
> - * DRRS stuff.
> - *
> - * Returns:
> - * Downclock mode if panel supports it, else return NULL.
> - * DRRS support is determined by the presence of downclock mode (apart
> - * from VBT setting).
> - */
> -static struct drm_display_mode *
> -intel_dp_drrs_init(struct intel_connector *connector,
> - struct drm_display_mode *fixed_mode)
> -{
> - struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> - struct drm_display_mode *downclock_mode = NULL;
> -
> - INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
> - mutex_init(&dev_priv->drrs.mutex);
> -
> - if (DISPLAY_VER(dev_priv) <= 6) {
> - drm_dbg_kms(&dev_priv->drm,
> - "DRRS supported for Gen7 and above\n");
> - return NULL;
> - }
> -
> - if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
> - drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
> - return NULL;
> - }
> -
> - downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
> - if (!downclock_mode) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Downclock mode is not found. DRRS not supported\n");
> - return NULL;
> - }
> -
> - dev_priv->drrs.type = dev_priv->vbt.drrs_type;
> -
> - dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
> - drm_dbg_kms(&dev_priv->drm,
> - "seamless DRRS supported for eDP panel.\n");
> - return downclock_mode;
> -}
> -
> static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> struct intel_connector *intel_connector)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 680631b5b4378..38ff0e4f65504 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -70,17 +70,6 @@ int intel_dp_max_link_rate(struct intel_dp *intel_dp);
> int intel_dp_max_lane_count(struct intel_dp *intel_dp);
> int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
>
> -void intel_edp_drrs_enable(struct intel_dp *intel_dp,
> - const struct intel_crtc_state *crtc_state);
> -void intel_edp_drrs_disable(struct intel_dp *intel_dp,
> - const struct intel_crtc_state *crtc_state);
> -void intel_edp_drrs_update(struct intel_dp *intel_dp,
> - const struct intel_crtc_state *crtc_state);
> -void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
> - unsigned int frontbuffer_bits);
> -void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
> - unsigned int frontbuffer_bits);
> -
> void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
> u8 *link_bw, u8 *rate_select);
> bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
> new file mode 100644
> index 0000000000000..be9b6d4482f04
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_drrs.c
> @@ -0,0 +1,477 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#include "i915_drv.h"
> +#include "intel_atomic.h"
> +#include "intel_de.h"
> +#include "intel_display_types.h"
> +#include "intel_drrs.h"
> +#include "intel_panel.h"
> +
> +/**
> + * DOC: Display Refresh Rate Switching (DRRS)
> + *
> + * Display Refresh Rate Switching (DRRS) is a power conservation feature
> + * which enables swtching between low and high refresh rates,
> + * dynamically, based on the usage scenario. This feature is applicable
> + * for internal panels.
> + *
> + * Indication that the panel supports DRRS is given by the panel EDID, which
> + * would list multiple refresh rates for one resolution.
> + *
> + * DRRS is of 2 types - static and seamless.
> + * Static DRRS involves changing refresh rate (RR) by doing a full modeset
> + * (may appear as a blink on screen) and is used in dock-undock scenario.
> + * Seamless DRRS involves changing RR without any visual effect to the user
> + * and can be used during normal system usage. This is done by programming
> + * certain registers.
> + *
> + * Support for static/seamless DRRS may be indicated in the VBT based on
> + * inputs from the panel spec.
> + *
> + * DRRS saves power by switching to low RR based on usage scenarios.
> + *
> + * The implementation is based on frontbuffer tracking implementation. When
> + * there is a disturbance on the screen triggered by user activity or a periodic
> + * system activity, DRRS is disabled (RR is changed to high RR). When there is
> + * no movement on screen, after a timeout of 1 second, a switch to low RR is
> + * made.
> + *
> + * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
> + * and intel_edp_drrs_flush() are called.
> + *
> + * DRRS can be further extended to support other internal panels and also
> + * the scenario of video playback wherein RR is set based on the rate
> + * requested by userspace.
> + */
> +
> +void
> +intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
> + struct intel_crtc_state *pipe_config,
> + int output_bpp, bool constant_n)
> +{
> + struct intel_connector *intel_connector = intel_dp->attached_connector;
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + int pixel_clock;
> +
> + if (pipe_config->vrr.enable)
> + return;
> +
> + /*
> + * DRRS and PSR can't be enable together, so giving preference to PSR
> + * as it allows more power-savings by complete shutting down display,
> + * so to guarantee this, intel_dp_drrs_compute_config() must be called
> + * after intel_psr_compute_config().
> + */
> + if (pipe_config->has_psr)
> + return;
> +
> + if (!intel_connector->panel.downclock_mode ||
> + dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
> + return;
> +
> + pipe_config->has_drrs = true;
> +
> + pixel_clock = intel_connector->panel.downclock_mode->clock;
> + if (pipe_config->splitter.enable)
> + pixel_clock /= pipe_config->splitter.link_count;
> +
> + intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
> + pipe_config->port_clock, &pipe_config->dp_m2_n2,
> + constant_n, pipe_config->fec_enable);
> +
> + /* FIXME: abstract this better */
> + if (pipe_config->splitter.enable)
> + pipe_config->dp_m2_n2.gmch_m *= pipe_config->splitter.link_count;
> +}
> +
> +/**
> + * intel_dp_set_drrs_state - program registers for RR switch to take effect
> + * @dev_priv: i915 device
> + * @crtc_state: a pointer to the active intel_crtc_state
> + * @refresh_rate: RR to be programmed
> + *
> + * This function gets called when refresh rate (RR) has to be changed from
> + * one frequency to another. Switches can be between high and low RR
> + * supported by the panel or to any other RR based on media playback (in
> + * this case, RR value needs to be passed from user space).
> + *
> + * The caller of this function needs to take a lock on dev_priv->drrs.
> + */
> +static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
> + const struct intel_crtc_state *crtc_state,
> + int refresh_rate)
> +{
> + struct intel_dp *intel_dp = dev_priv->drrs.dp;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
> +
> + if (refresh_rate <= 0) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Refresh rate should be positive non-zero.\n");
> + return;
> + }
> +
> + if (intel_dp == NULL) {
> + drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
> + return;
> + }
> +
> + if (!crtc) {
> + drm_dbg_kms(&dev_priv->drm,
> + "DRRS: intel_crtc not initialized\n");
> + return;
> + }
> +
> + if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
> + drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
> + return;
> + }
> +
> + if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) ==
> + refresh_rate)
> + index = DRRS_LOW_RR;
> +
> + if (index == dev_priv->drrs.refresh_rate_type) {
> + drm_dbg_kms(&dev_priv->drm,
> + "DRRS requested for previously set RR...ignoring\n");
> + return;
> + }
> +
> + if (!crtc_state->hw.active) {
> + drm_dbg_kms(&dev_priv->drm,
> + "eDP encoder disabled. CRTC not Active\n");
> + return;
> + }
> +
> + if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
> + switch (index) {
> + case DRRS_HIGH_RR:
> + intel_dp_set_m_n(crtc_state, M1_N1);
> + break;
> + case DRRS_LOW_RR:
> + intel_dp_set_m_n(crtc_state, M2_N2);
> + break;
> + case DRRS_MAX_RR:
> + default:
> + drm_err(&dev_priv->drm,
> + "Unsupported refreshrate type\n");
> + }
> + } else if (DISPLAY_VER(dev_priv) > 6) {
> + i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
> + u32 val;
> +
> + val = intel_de_read(dev_priv, reg);
> + if (index > DRRS_HIGH_RR) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> + val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
> + else
> + val |= PIPECONF_EDP_RR_MODE_SWITCH;
> + } else {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> + val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
> + else
> + val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
> + }
> + intel_de_write(dev_priv, reg, val);
> + }
> +
> + dev_priv->drrs.refresh_rate_type = index;
> +
> + drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
> + refresh_rate);
> +}
> +
> +static void
> +intel_edp_drrs_enable_locked(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + dev_priv->drrs.busy_frontbuffer_bits = 0;
> + dev_priv->drrs.dp = intel_dp;
> +}
> +
> +/**
> + * intel_edp_drrs_enable - init drrs struct if supported
> + * @intel_dp: DP struct
> + * @crtc_state: A pointer to the active crtc state.
> + *
> + * Initializes frontbuffer_bits and drrs.dp
> + */
> +void intel_edp_drrs_enable(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + if (!crtc_state->has_drrs)
> + return;
> +
> + drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
> +
> + mutex_lock(&dev_priv->drrs.mutex);
> +
> + if (dev_priv->drrs.dp) {
> + drm_warn(&dev_priv->drm, "DRRS already enabled\n");
> + goto unlock;
> + }
> +
> + intel_edp_drrs_enable_locked(intel_dp);
> +
> +unlock:
> + mutex_unlock(&dev_priv->drrs.mutex);
> +}
> +
> +static void
> +intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
> + int refresh;
> +
> + refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
> + intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
> + }
> +
> + dev_priv->drrs.dp = NULL;
> +}
> +
> +/**
> + * intel_edp_drrs_disable - Disable DRRS
> + * @intel_dp: DP struct
> + * @old_crtc_state: Pointer to old crtc_state.
> + *
> + */
> +void intel_edp_drrs_disable(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *old_crtc_state)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + if (!old_crtc_state->has_drrs)
> + return;
> +
> + mutex_lock(&dev_priv->drrs.mutex);
> + if (!dev_priv->drrs.dp) {
> + mutex_unlock(&dev_priv->drrs.mutex);
> + return;
> + }
> +
> + intel_edp_drrs_disable_locked(intel_dp, old_crtc_state);
> + mutex_unlock(&dev_priv->drrs.mutex);
> +
> + cancel_delayed_work_sync(&dev_priv->drrs.work);
> +}
> +
> +/**
> + * intel_edp_drrs_update - Update DRRS state
> + * @intel_dp: Intel DP
> + * @crtc_state: new CRTC state
> + *
> + * This function will update DRRS states, disabling or enabling DRRS when
> + * executing fastsets. For full modeset, intel_edp_drrs_disable() and
> + * intel_edp_drrs_enable() should be called instead.
> + */
> +void
> +intel_edp_drrs_update(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
> + return;
> +
> + mutex_lock(&dev_priv->drrs.mutex);
> +
> + /* New state matches current one? */
> + if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
> + goto unlock;
> +
> + if (crtc_state->has_drrs)
> + intel_edp_drrs_enable_locked(intel_dp);
> + else
> + intel_edp_drrs_disable_locked(intel_dp, crtc_state);
> +
> +unlock:
> + mutex_unlock(&dev_priv->drrs.mutex);
> +}
> +
> +static void intel_edp_drrs_downclock_work(struct work_struct *work)
> +{
> + struct drm_i915_private *dev_priv =
> + container_of(work, typeof(*dev_priv), drrs.work.work);
> + struct intel_dp *intel_dp;
> +
> + mutex_lock(&dev_priv->drrs.mutex);
> +
> + intel_dp = dev_priv->drrs.dp;
> +
> + if (!intel_dp)
> + goto unlock;
> +
> + /*
> + * The delayed work can race with an invalidate hence we need to
> + * recheck.
> + */
> +
> + if (dev_priv->drrs.busy_frontbuffer_bits)
> + goto unlock;
> +
> + if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
> + struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
> +
> + intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
> + drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
> + }
> +
> +unlock:
> + mutex_unlock(&dev_priv->drrs.mutex);
> +}
> +
> +/**
> + * intel_edp_drrs_invalidate - Disable Idleness DRRS
> + * @dev_priv: i915 device
> + * @frontbuffer_bits: frontbuffer plane tracking bits
> + *
> + * This function gets called everytime rendering on the given planes start.
> + * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
> + *
> + * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
> + */
> +void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
> + unsigned int frontbuffer_bits)
> +{
> + struct intel_dp *intel_dp;
> + struct drm_crtc *crtc;
> + enum pipe pipe;
> +
> + if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
> + return;
> +
> + cancel_delayed_work(&dev_priv->drrs.work);
> +
> + mutex_lock(&dev_priv->drrs.mutex);
> +
> + intel_dp = dev_priv->drrs.dp;
> + if (!intel_dp) {
> + mutex_unlock(&dev_priv->drrs.mutex);
> + return;
> + }
> +
> + crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
> + pipe = to_intel_crtc(crtc)->pipe;
> +
> + frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
> + dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
> +
> + /* invalidate means busy screen hence upclock */
> + if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
> + intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
> + drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
> +
> + mutex_unlock(&dev_priv->drrs.mutex);
> +}
> +
> +/**
> + * intel_edp_drrs_flush - Restart Idleness DRRS
> + * @dev_priv: i915 device
> + * @frontbuffer_bits: frontbuffer plane tracking bits
> + *
> + * This function gets called every time rendering on the given planes has
> + * completed or flip on a crtc is completed. So DRRS should be upclocked
> + * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
> + * if no other planes are dirty.
> + *
> + * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
> + */
> +void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
> + unsigned int frontbuffer_bits)
> +{
> + struct intel_dp *intel_dp;
> + struct drm_crtc *crtc;
> + enum pipe pipe;
> +
> + if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
> + return;
> +
> + cancel_delayed_work(&dev_priv->drrs.work);
> +
> + mutex_lock(&dev_priv->drrs.mutex);
> +
> + intel_dp = dev_priv->drrs.dp;
> + if (!intel_dp) {
> + mutex_unlock(&dev_priv->drrs.mutex);
> + return;
> + }
> +
> + crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
> + pipe = to_intel_crtc(crtc)->pipe;
> +
> + frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
> + dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
> +
> + /* flush means busy screen hence upclock */
> + if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
> + intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
> + drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
> +
> + /*
> + * flush also means no more activity hence schedule downclock, if all
> + * other fbs are quiescent too
> + */
> + if (!dev_priv->drrs.busy_frontbuffer_bits)
> + schedule_delayed_work(&dev_priv->drrs.work,
> + msecs_to_jiffies(1000));
> + mutex_unlock(&dev_priv->drrs.mutex);
> +}
> +
> +/**
> + * intel_dp_drrs_init - Init basic DRRS work and mutex.
> + * @connector: eDP connector
> + * @fixed_mode: preferred mode of panel
> + *
> + * This function is called only once at driver load to initialize basic
> + * DRRS stuff.
> + *
> + * Returns:
> + * Downclock mode if panel supports it, else return NULL.
> + * DRRS support is determined by the presence of downclock mode (apart
> + * from VBT setting).
> + */
> +struct drm_display_mode *
> +intel_dp_drrs_init(struct intel_connector *connector,
> + struct drm_display_mode *fixed_mode)
> +{
> + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> + struct drm_display_mode *downclock_mode = NULL;
> +
> + INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
> + mutex_init(&dev_priv->drrs.mutex);
> +
> + if (DISPLAY_VER(dev_priv) <= 6) {
> + drm_dbg_kms(&dev_priv->drm,
> + "DRRS supported for Gen7 and above\n");
> + return NULL;
> + }
> +
> + if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
> + drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
> + return NULL;
> + }
> +
> + downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
> + if (!downclock_mode) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Downclock mode is not found. DRRS not supported\n");
> + return NULL;
> + }
> +
> + dev_priv->drrs.type = dev_priv->vbt.drrs_type;
> +
> + dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
> + drm_dbg_kms(&dev_priv->drm,
> + "seamless DRRS supported for eDP panel.\n");
> + return downclock_mode;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_drrs.h b/drivers/gpu/drm/i915/display/intel_drrs.h
> new file mode 100644
> index 0000000000000..ffa175b4cf4f4
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_drrs.h
> @@ -0,0 +1,32 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#ifndef __INTEL_DRRS_H__
> +#define __INTEL_DRRS_H__
> +
> +#include <linux/types.h>
> +
> +struct drm_i915_private;
> +struct intel_crtc_state;
> +struct intel_connector;
> +struct intel_dp;
> +
> +void intel_edp_drrs_enable(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state);
> +void intel_edp_drrs_disable(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state);
> +void intel_edp_drrs_update(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state);
> +void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
> + unsigned int frontbuffer_bits);
> +void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
> + unsigned int frontbuffer_bits);
> +void intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
> + struct intel_crtc_state *pipe_config,
> + int output_bpp, bool constant_n);
> +struct drm_display_mode *intel_dp_drrs_init(struct intel_connector *connector,
> + struct drm_display_mode *fixed_mode);
> +
> +#endif /* __INTEL_DRRS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
> index 8e75debcce1a9..e4834d84ce5e3 100644
> --- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
> +++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
> @@ -62,6 +62,7 @@
> #include "intel_display_types.h"
> #include "intel_fbc.h"
> #include "intel_frontbuffer.h"
> +#include "intel_drrs.h"
> #include "intel_psr.h"
>
> /**
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [PATCH 3/8] drm/i915/display: Move DRRS code its own file
2021-08-18 7:24 ` Jani Nikula
@ 2021-08-19 0:44 ` Souza, Jose
0 siblings, 0 replies; 22+ messages in thread
From: Souza, Jose @ 2021-08-19 0:44 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Vivi, Rodrigo
On Wed, 2021-08-18 at 10:24 +0300, Jani Nikula wrote:
> On Tue, 17 Aug 2021, José Roberto de Souza <jose.souza@intel.com> wrote:
> > intel_dp.c is a 5k lines monster, so moving DRRS out of it to reduce
> > some lines from it.
>
> The functions in a file should be named after the file prefix,
> i.e. intel_drrs_*() here. The renames don't need to be in the same
> patch, but I think we need to have them. (Probably should be a separate
> patch to keep the code movement easier to review.)
>
Sure, done will be part of v2.
Will wait for more comments in the other patches to send it.
>
> BR,
> Jani.
>
>
> >
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > Documentation/gpu/i915.rst | 14 +-
> > drivers/gpu/drm/i915/Makefile | 1 +
> > drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
> > .../drm/i915/display/intel_display_debugfs.c | 1 +
> > drivers/gpu/drm/i915/display/intel_dp.c | 467 +----------------
> > drivers/gpu/drm/i915/display/intel_dp.h | 11 -
> > drivers/gpu/drm/i915/display/intel_drrs.c | 477 ++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_drrs.h | 32 ++
> > .../gpu/drm/i915/display/intel_frontbuffer.c | 1 +
> > 9 files changed, 521 insertions(+), 484 deletions(-)
> > create mode 100644 drivers/gpu/drm/i915/display/intel_drrs.c
> > create mode 100644 drivers/gpu/drm/i915/display/intel_drrs.h
> >
> > diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> > index 204ebdaadb45a..03021dfa0dd81 100644
> > --- a/Documentation/gpu/i915.rst
> > +++ b/Documentation/gpu/i915.rst
> > @@ -183,25 +183,25 @@ Frame Buffer Compression (FBC)
> > Display Refresh Rate Switching (DRRS)
> > -------------------------------------
> >
> > -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
> > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> > :doc: Display Refresh Rate Switching (DRRS)
> >
> > -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
> > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> > :functions: intel_dp_set_drrs_state
> >
> > -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
> > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> > :functions: intel_edp_drrs_enable
> >
> > -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
> > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> > :functions: intel_edp_drrs_disable
> >
> > -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
> > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> > :functions: intel_edp_drrs_invalidate
> >
> > -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
> > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> > :functions: intel_edp_drrs_flush
> >
> > -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
> > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
> > :functions: intel_dp_drrs_init
> >
> > DPIO
> > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> > index 642a5b5a1b81c..c7cf4dfdc6379 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -212,6 +212,7 @@ i915-y += \
> > display/intel_dpio_phy.o \
> > display/intel_dpll.o \
> > display/intel_dpll_mgr.o \
> > + display/intel_drrs.o \
> > display/intel_dsb.o \
> > display/intel_fb.o \
> > display/intel_fbc.o \
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 1ef7a65feb660..828df570a4809 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -40,6 +40,7 @@
> > #include "intel_dp_link_training.h"
> > #include "intel_dp_mst.h"
> > #include "intel_dpio_phy.h"
> > +#include "intel_drrs.h"
> > #include "intel_dsi.h"
> > #include "intel_fdi.h"
> > #include "intel_fifo_underrun.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index 8fdacb252bb19..b136a0fc0963b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -13,6 +13,7 @@
> > #include "intel_display_types.h"
> > #include "intel_dmc.h"
> > #include "intel_dp.h"
> > +#include "intel_drrs.h"
> > #include "intel_fbc.h"
> > #include "intel_hdcp.h"
> > #include "intel_hdmi.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 75d4ebc669411..10583b0aa489e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -55,6 +55,7 @@
> > #include "intel_dp_mst.h"
> > #include "intel_dpio_phy.h"
> > #include "intel_dpll.h"
> > +#include "intel_drrs.h"
> > #include "intel_fifo_underrun.h"
> > #include "intel_hdcp.h"
> > #include "intel_hdmi.h"
> > @@ -1603,46 +1604,6 @@ intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
> > intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
> > }
> >
> > -static void
> > -intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
> > - struct intel_crtc_state *pipe_config,
> > - int output_bpp, bool constant_n)
> > -{
> > - struct intel_connector *intel_connector = intel_dp->attached_connector;
> > - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > - int pixel_clock;
> > -
> > - if (pipe_config->vrr.enable)
> > - return;
> > -
> > - /*
> > - * DRRS and PSR can't be enable together, so giving preference to PSR
> > - * as it allows more power-savings by complete shutting down display,
> > - * so to guarantee this, intel_dp_drrs_compute_config() must be called
> > - * after intel_psr_compute_config().
> > - */
> > - if (pipe_config->has_psr)
> > - return;
> > -
> > - if (!intel_connector->panel.downclock_mode ||
> > - dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
> > - return;
> > -
> > - pipe_config->has_drrs = true;
> > -
> > - pixel_clock = intel_connector->panel.downclock_mode->clock;
> > - if (pipe_config->splitter.enable)
> > - pixel_clock /= pipe_config->splitter.link_count;
> > -
> > - intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
> > - pipe_config->port_clock, &pipe_config->dp_m2_n2,
> > - constant_n, pipe_config->fec_enable);
> > -
> > - /* FIXME: abstract this better */
> > - if (pipe_config->splitter.enable)
> > - pipe_config->dp_m2_n2.gmch_m *= pipe_config->splitter.link_count;
> > -}
> > -
> > int
> > intel_dp_compute_config(struct intel_encoder *encoder,
> > struct intel_crtc_state *pipe_config,
> > @@ -4715,432 +4676,6 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
> > drm_connector_attach_vrr_capable_property(connector);
> > }
> >
> > -/**
> > - * intel_dp_set_drrs_state - program registers for RR switch to take effect
> > - * @dev_priv: i915 device
> > - * @crtc_state: a pointer to the active intel_crtc_state
> > - * @refresh_rate: RR to be programmed
> > - *
> > - * This function gets called when refresh rate (RR) has to be changed from
> > - * one frequency to another. Switches can be between high and low RR
> > - * supported by the panel or to any other RR based on media playback (in
> > - * this case, RR value needs to be passed from user space).
> > - *
> > - * The caller of this function needs to take a lock on dev_priv->drrs.
> > - */
> > -static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
> > - const struct intel_crtc_state *crtc_state,
> > - int refresh_rate)
> > -{
> > - struct intel_dp *intel_dp = dev_priv->drrs.dp;
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > - enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
> > -
> > - if (refresh_rate <= 0) {
> > - drm_dbg_kms(&dev_priv->drm,
> > - "Refresh rate should be positive non-zero.\n");
> > - return;
> > - }
> > -
> > - if (intel_dp == NULL) {
> > - drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
> > - return;
> > - }
> > -
> > - if (!crtc) {
> > - drm_dbg_kms(&dev_priv->drm,
> > - "DRRS: intel_crtc not initialized\n");
> > - return;
> > - }
> > -
> > - if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
> > - drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
> > - return;
> > - }
> > -
> > - if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) ==
> > - refresh_rate)
> > - index = DRRS_LOW_RR;
> > -
> > - if (index == dev_priv->drrs.refresh_rate_type) {
> > - drm_dbg_kms(&dev_priv->drm,
> > - "DRRS requested for previously set RR...ignoring\n");
> > - return;
> > - }
> > -
> > - if (!crtc_state->hw.active) {
> > - drm_dbg_kms(&dev_priv->drm,
> > - "eDP encoder disabled. CRTC not Active\n");
> > - return;
> > - }
> > -
> > - if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
> > - switch (index) {
> > - case DRRS_HIGH_RR:
> > - intel_dp_set_m_n(crtc_state, M1_N1);
> > - break;
> > - case DRRS_LOW_RR:
> > - intel_dp_set_m_n(crtc_state, M2_N2);
> > - break;
> > - case DRRS_MAX_RR:
> > - default:
> > - drm_err(&dev_priv->drm,
> > - "Unsupported refreshrate type\n");
> > - }
> > - } else if (DISPLAY_VER(dev_priv) > 6) {
> > - i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
> > - u32 val;
> > -
> > - val = intel_de_read(dev_priv, reg);
> > - if (index > DRRS_HIGH_RR) {
> > - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > - val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
> > - else
> > - val |= PIPECONF_EDP_RR_MODE_SWITCH;
> > - } else {
> > - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > - val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
> > - else
> > - val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
> > - }
> > - intel_de_write(dev_priv, reg, val);
> > - }
> > -
> > - dev_priv->drrs.refresh_rate_type = index;
> > -
> > - drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
> > - refresh_rate);
> > -}
> > -
> > -static void
> > -intel_edp_drrs_enable_locked(struct intel_dp *intel_dp)
> > -{
> > - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > -
> > - dev_priv->drrs.busy_frontbuffer_bits = 0;
> > - dev_priv->drrs.dp = intel_dp;
> > -}
> > -
> > -/**
> > - * intel_edp_drrs_enable - init drrs struct if supported
> > - * @intel_dp: DP struct
> > - * @crtc_state: A pointer to the active crtc state.
> > - *
> > - * Initializes frontbuffer_bits and drrs.dp
> > - */
> > -void intel_edp_drrs_enable(struct intel_dp *intel_dp,
> > - const struct intel_crtc_state *crtc_state)
> > -{
> > - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > -
> > - if (!crtc_state->has_drrs)
> > - return;
> > -
> > - drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
> > -
> > - mutex_lock(&dev_priv->drrs.mutex);
> > -
> > - if (dev_priv->drrs.dp) {
> > - drm_warn(&dev_priv->drm, "DRRS already enabled\n");
> > - goto unlock;
> > - }
> > -
> > - intel_edp_drrs_enable_locked(intel_dp);
> > -
> > -unlock:
> > - mutex_unlock(&dev_priv->drrs.mutex);
> > -}
> > -
> > -static void
> > -intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
> > - const struct intel_crtc_state *crtc_state)
> > -{
> > - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > -
> > - if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
> > - int refresh;
> > -
> > - refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
> > - intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
> > - }
> > -
> > - dev_priv->drrs.dp = NULL;
> > -}
> > -
> > -/**
> > - * intel_edp_drrs_disable - Disable DRRS
> > - * @intel_dp: DP struct
> > - * @old_crtc_state: Pointer to old crtc_state.
> > - *
> > - */
> > -void intel_edp_drrs_disable(struct intel_dp *intel_dp,
> > - const struct intel_crtc_state *old_crtc_state)
> > -{
> > - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > -
> > - if (!old_crtc_state->has_drrs)
> > - return;
> > -
> > - mutex_lock(&dev_priv->drrs.mutex);
> > - if (!dev_priv->drrs.dp) {
> > - mutex_unlock(&dev_priv->drrs.mutex);
> > - return;
> > - }
> > -
> > - intel_edp_drrs_disable_locked(intel_dp, old_crtc_state);
> > - mutex_unlock(&dev_priv->drrs.mutex);
> > -
> > - cancel_delayed_work_sync(&dev_priv->drrs.work);
> > -}
> > -
> > -/**
> > - * intel_edp_drrs_update - Update DRRS state
> > - * @intel_dp: Intel DP
> > - * @crtc_state: new CRTC state
> > - *
> > - * This function will update DRRS states, disabling or enabling DRRS when
> > - * executing fastsets. For full modeset, intel_edp_drrs_disable() and
> > - * intel_edp_drrs_enable() should be called instead.
> > - */
> > -void
> > -intel_edp_drrs_update(struct intel_dp *intel_dp,
> > - const struct intel_crtc_state *crtc_state)
> > -{
> > - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > -
> > - if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
> > - return;
> > -
> > - mutex_lock(&dev_priv->drrs.mutex);
> > -
> > - /* New state matches current one? */
> > - if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
> > - goto unlock;
> > -
> > - if (crtc_state->has_drrs)
> > - intel_edp_drrs_enable_locked(intel_dp);
> > - else
> > - intel_edp_drrs_disable_locked(intel_dp, crtc_state);
> > -
> > -unlock:
> > - mutex_unlock(&dev_priv->drrs.mutex);
> > -}
> > -
> > -static void intel_edp_drrs_downclock_work(struct work_struct *work)
> > -{
> > - struct drm_i915_private *dev_priv =
> > - container_of(work, typeof(*dev_priv), drrs.work.work);
> > - struct intel_dp *intel_dp;
> > -
> > - mutex_lock(&dev_priv->drrs.mutex);
> > -
> > - intel_dp = dev_priv->drrs.dp;
> > -
> > - if (!intel_dp)
> > - goto unlock;
> > -
> > - /*
> > - * The delayed work can race with an invalidate hence we need to
> > - * recheck.
> > - */
> > -
> > - if (dev_priv->drrs.busy_frontbuffer_bits)
> > - goto unlock;
> > -
> > - if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
> > - struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
> > -
> > - intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
> > - drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
> > - }
> > -
> > -unlock:
> > - mutex_unlock(&dev_priv->drrs.mutex);
> > -}
> > -
> > -/**
> > - * intel_edp_drrs_invalidate - Disable Idleness DRRS
> > - * @dev_priv: i915 device
> > - * @frontbuffer_bits: frontbuffer plane tracking bits
> > - *
> > - * This function gets called everytime rendering on the given planes start.
> > - * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
> > - *
> > - * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
> > - */
> > -void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
> > - unsigned int frontbuffer_bits)
> > -{
> > - struct intel_dp *intel_dp;
> > - struct drm_crtc *crtc;
> > - enum pipe pipe;
> > -
> > - if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
> > - return;
> > -
> > - cancel_delayed_work(&dev_priv->drrs.work);
> > -
> > - mutex_lock(&dev_priv->drrs.mutex);
> > -
> > - intel_dp = dev_priv->drrs.dp;
> > - if (!intel_dp) {
> > - mutex_unlock(&dev_priv->drrs.mutex);
> > - return;
> > - }
> > -
> > - crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
> > - pipe = to_intel_crtc(crtc)->pipe;
> > -
> > - frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
> > - dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
> > -
> > - /* invalidate means busy screen hence upclock */
> > - if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
> > - intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
> > - drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
> > -
> > - mutex_unlock(&dev_priv->drrs.mutex);
> > -}
> > -
> > -/**
> > - * intel_edp_drrs_flush - Restart Idleness DRRS
> > - * @dev_priv: i915 device
> > - * @frontbuffer_bits: frontbuffer plane tracking bits
> > - *
> > - * This function gets called every time rendering on the given planes has
> > - * completed or flip on a crtc is completed. So DRRS should be upclocked
> > - * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
> > - * if no other planes are dirty.
> > - *
> > - * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
> > - */
> > -void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
> > - unsigned int frontbuffer_bits)
> > -{
> > - struct intel_dp *intel_dp;
> > - struct drm_crtc *crtc;
> > - enum pipe pipe;
> > -
> > - if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
> > - return;
> > -
> > - cancel_delayed_work(&dev_priv->drrs.work);
> > -
> > - mutex_lock(&dev_priv->drrs.mutex);
> > -
> > - intel_dp = dev_priv->drrs.dp;
> > - if (!intel_dp) {
> > - mutex_unlock(&dev_priv->drrs.mutex);
> > - return;
> > - }
> > -
> > - crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
> > - pipe = to_intel_crtc(crtc)->pipe;
> > -
> > - frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
> > - dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
> > -
> > - /* flush means busy screen hence upclock */
> > - if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
> > - intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
> > - drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
> > -
> > - /*
> > - * flush also means no more activity hence schedule downclock, if all
> > - * other fbs are quiescent too
> > - */
> > - if (!dev_priv->drrs.busy_frontbuffer_bits)
> > - schedule_delayed_work(&dev_priv->drrs.work,
> > - msecs_to_jiffies(1000));
> > - mutex_unlock(&dev_priv->drrs.mutex);
> > -}
> > -
> > -/**
> > - * DOC: Display Refresh Rate Switching (DRRS)
> > - *
> > - * Display Refresh Rate Switching (DRRS) is a power conservation feature
> > - * which enables swtching between low and high refresh rates,
> > - * dynamically, based on the usage scenario. This feature is applicable
> > - * for internal panels.
> > - *
> > - * Indication that the panel supports DRRS is given by the panel EDID, which
> > - * would list multiple refresh rates for one resolution.
> > - *
> > - * DRRS is of 2 types - static and seamless.
> > - * Static DRRS involves changing refresh rate (RR) by doing a full modeset
> > - * (may appear as a blink on screen) and is used in dock-undock scenario.
> > - * Seamless DRRS involves changing RR without any visual effect to the user
> > - * and can be used during normal system usage. This is done by programming
> > - * certain registers.
> > - *
> > - * Support for static/seamless DRRS may be indicated in the VBT based on
> > - * inputs from the panel spec.
> > - *
> > - * DRRS saves power by switching to low RR based on usage scenarios.
> > - *
> > - * The implementation is based on frontbuffer tracking implementation. When
> > - * there is a disturbance on the screen triggered by user activity or a periodic
> > - * system activity, DRRS is disabled (RR is changed to high RR). When there is
> > - * no movement on screen, after a timeout of 1 second, a switch to low RR is
> > - * made.
> > - *
> > - * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
> > - * and intel_edp_drrs_flush() are called.
> > - *
> > - * DRRS can be further extended to support other internal panels and also
> > - * the scenario of video playback wherein RR is set based on the rate
> > - * requested by userspace.
> > - */
> > -
> > -/**
> > - * intel_dp_drrs_init - Init basic DRRS work and mutex.
> > - * @connector: eDP connector
> > - * @fixed_mode: preferred mode of panel
> > - *
> > - * This function is called only once at driver load to initialize basic
> > - * DRRS stuff.
> > - *
> > - * Returns:
> > - * Downclock mode if panel supports it, else return NULL.
> > - * DRRS support is determined by the presence of downclock mode (apart
> > - * from VBT setting).
> > - */
> > -static struct drm_display_mode *
> > -intel_dp_drrs_init(struct intel_connector *connector,
> > - struct drm_display_mode *fixed_mode)
> > -{
> > - struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > - struct drm_display_mode *downclock_mode = NULL;
> > -
> > - INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
> > - mutex_init(&dev_priv->drrs.mutex);
> > -
> > - if (DISPLAY_VER(dev_priv) <= 6) {
> > - drm_dbg_kms(&dev_priv->drm,
> > - "DRRS supported for Gen7 and above\n");
> > - return NULL;
> > - }
> > -
> > - if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
> > - drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
> > - return NULL;
> > - }
> > -
> > - downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
> > - if (!downclock_mode) {
> > - drm_dbg_kms(&dev_priv->drm,
> > - "Downclock mode is not found. DRRS not supported\n");
> > - return NULL;
> > - }
> > -
> > - dev_priv->drrs.type = dev_priv->vbt.drrs_type;
> > -
> > - dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
> > - drm_dbg_kms(&dev_priv->drm,
> > - "seamless DRRS supported for eDP panel.\n");
> > - return downclock_mode;
> > -}
> > -
> > static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> > struct intel_connector *intel_connector)
> > {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> > index 680631b5b4378..38ff0e4f65504 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -70,17 +70,6 @@ int intel_dp_max_link_rate(struct intel_dp *intel_dp);
> > int intel_dp_max_lane_count(struct intel_dp *intel_dp);
> > int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
> >
> > -void intel_edp_drrs_enable(struct intel_dp *intel_dp,
> > - const struct intel_crtc_state *crtc_state);
> > -void intel_edp_drrs_disable(struct intel_dp *intel_dp,
> > - const struct intel_crtc_state *crtc_state);
> > -void intel_edp_drrs_update(struct intel_dp *intel_dp,
> > - const struct intel_crtc_state *crtc_state);
> > -void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
> > - unsigned int frontbuffer_bits);
> > -void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
> > - unsigned int frontbuffer_bits);
> > -
> > void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
> > u8 *link_bw, u8 *rate_select);
> > bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
> > diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
> > new file mode 100644
> > index 0000000000000..be9b6d4482f04
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/display/intel_drrs.c
> > @@ -0,0 +1,477 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2021 Intel Corporation
> > + */
> > +
> > +#include "i915_drv.h"
> > +#include "intel_atomic.h"
> > +#include "intel_de.h"
> > +#include "intel_display_types.h"
> > +#include "intel_drrs.h"
> > +#include "intel_panel.h"
> > +
> > +/**
> > + * DOC: Display Refresh Rate Switching (DRRS)
> > + *
> > + * Display Refresh Rate Switching (DRRS) is a power conservation feature
> > + * which enables swtching between low and high refresh rates,
> > + * dynamically, based on the usage scenario. This feature is applicable
> > + * for internal panels.
> > + *
> > + * Indication that the panel supports DRRS is given by the panel EDID, which
> > + * would list multiple refresh rates for one resolution.
> > + *
> > + * DRRS is of 2 types - static and seamless.
> > + * Static DRRS involves changing refresh rate (RR) by doing a full modeset
> > + * (may appear as a blink on screen) and is used in dock-undock scenario.
> > + * Seamless DRRS involves changing RR without any visual effect to the user
> > + * and can be used during normal system usage. This is done by programming
> > + * certain registers.
> > + *
> > + * Support for static/seamless DRRS may be indicated in the VBT based on
> > + * inputs from the panel spec.
> > + *
> > + * DRRS saves power by switching to low RR based on usage scenarios.
> > + *
> > + * The implementation is based on frontbuffer tracking implementation. When
> > + * there is a disturbance on the screen triggered by user activity or a periodic
> > + * system activity, DRRS is disabled (RR is changed to high RR). When there is
> > + * no movement on screen, after a timeout of 1 second, a switch to low RR is
> > + * made.
> > + *
> > + * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
> > + * and intel_edp_drrs_flush() are called.
> > + *
> > + * DRRS can be further extended to support other internal panels and also
> > + * the scenario of video playback wherein RR is set based on the rate
> > + * requested by userspace.
> > + */
> > +
> > +void
> > +intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
> > + struct intel_crtc_state *pipe_config,
> > + int output_bpp, bool constant_n)
> > +{
> > + struct intel_connector *intel_connector = intel_dp->attached_connector;
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > + int pixel_clock;
> > +
> > + if (pipe_config->vrr.enable)
> > + return;
> > +
> > + /*
> > + * DRRS and PSR can't be enable together, so giving preference to PSR
> > + * as it allows more power-savings by complete shutting down display,
> > + * so to guarantee this, intel_dp_drrs_compute_config() must be called
> > + * after intel_psr_compute_config().
> > + */
> > + if (pipe_config->has_psr)
> > + return;
> > +
> > + if (!intel_connector->panel.downclock_mode ||
> > + dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
> > + return;
> > +
> > + pipe_config->has_drrs = true;
> > +
> > + pixel_clock = intel_connector->panel.downclock_mode->clock;
> > + if (pipe_config->splitter.enable)
> > + pixel_clock /= pipe_config->splitter.link_count;
> > +
> > + intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
> > + pipe_config->port_clock, &pipe_config->dp_m2_n2,
> > + constant_n, pipe_config->fec_enable);
> > +
> > + /* FIXME: abstract this better */
> > + if (pipe_config->splitter.enable)
> > + pipe_config->dp_m2_n2.gmch_m *= pipe_config->splitter.link_count;
> > +}
> > +
> > +/**
> > + * intel_dp_set_drrs_state - program registers for RR switch to take effect
> > + * @dev_priv: i915 device
> > + * @crtc_state: a pointer to the active intel_crtc_state
> > + * @refresh_rate: RR to be programmed
> > + *
> > + * This function gets called when refresh rate (RR) has to be changed from
> > + * one frequency to another. Switches can be between high and low RR
> > + * supported by the panel or to any other RR based on media playback (in
> > + * this case, RR value needs to be passed from user space).
> > + *
> > + * The caller of this function needs to take a lock on dev_priv->drrs.
> > + */
> > +static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
> > + const struct intel_crtc_state *crtc_state,
> > + int refresh_rate)
> > +{
> > + struct intel_dp *intel_dp = dev_priv->drrs.dp;
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
> > +
> > + if (refresh_rate <= 0) {
> > + drm_dbg_kms(&dev_priv->drm,
> > + "Refresh rate should be positive non-zero.\n");
> > + return;
> > + }
> > +
> > + if (intel_dp == NULL) {
> > + drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
> > + return;
> > + }
> > +
> > + if (!crtc) {
> > + drm_dbg_kms(&dev_priv->drm,
> > + "DRRS: intel_crtc not initialized\n");
> > + return;
> > + }
> > +
> > + if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
> > + drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
> > + return;
> > + }
> > +
> > + if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) ==
> > + refresh_rate)
> > + index = DRRS_LOW_RR;
> > +
> > + if (index == dev_priv->drrs.refresh_rate_type) {
> > + drm_dbg_kms(&dev_priv->drm,
> > + "DRRS requested for previously set RR...ignoring\n");
> > + return;
> > + }
> > +
> > + if (!crtc_state->hw.active) {
> > + drm_dbg_kms(&dev_priv->drm,
> > + "eDP encoder disabled. CRTC not Active\n");
> > + return;
> > + }
> > +
> > + if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
> > + switch (index) {
> > + case DRRS_HIGH_RR:
> > + intel_dp_set_m_n(crtc_state, M1_N1);
> > + break;
> > + case DRRS_LOW_RR:
> > + intel_dp_set_m_n(crtc_state, M2_N2);
> > + break;
> > + case DRRS_MAX_RR:
> > + default:
> > + drm_err(&dev_priv->drm,
> > + "Unsupported refreshrate type\n");
> > + }
> > + } else if (DISPLAY_VER(dev_priv) > 6) {
> > + i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
> > + u32 val;
> > +
> > + val = intel_de_read(dev_priv, reg);
> > + if (index > DRRS_HIGH_RR) {
> > + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > + val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
> > + else
> > + val |= PIPECONF_EDP_RR_MODE_SWITCH;
> > + } else {
> > + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > + val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
> > + else
> > + val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
> > + }
> > + intel_de_write(dev_priv, reg, val);
> > + }
> > +
> > + dev_priv->drrs.refresh_rate_type = index;
> > +
> > + drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
> > + refresh_rate);
> > +}
> > +
> > +static void
> > +intel_edp_drrs_enable_locked(struct intel_dp *intel_dp)
> > +{
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > + dev_priv->drrs.busy_frontbuffer_bits = 0;
> > + dev_priv->drrs.dp = intel_dp;
> > +}
> > +
> > +/**
> > + * intel_edp_drrs_enable - init drrs struct if supported
> > + * @intel_dp: DP struct
> > + * @crtc_state: A pointer to the active crtc state.
> > + *
> > + * Initializes frontbuffer_bits and drrs.dp
> > + */
> > +void intel_edp_drrs_enable(struct intel_dp *intel_dp,
> > + const struct intel_crtc_state *crtc_state)
> > +{
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > + if (!crtc_state->has_drrs)
> > + return;
> > +
> > + drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
> > +
> > + mutex_lock(&dev_priv->drrs.mutex);
> > +
> > + if (dev_priv->drrs.dp) {
> > + drm_warn(&dev_priv->drm, "DRRS already enabled\n");
> > + goto unlock;
> > + }
> > +
> > + intel_edp_drrs_enable_locked(intel_dp);
> > +
> > +unlock:
> > + mutex_unlock(&dev_priv->drrs.mutex);
> > +}
> > +
> > +static void
> > +intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
> > + const struct intel_crtc_state *crtc_state)
> > +{
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > + if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
> > + int refresh;
> > +
> > + refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
> > + intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
> > + }
> > +
> > + dev_priv->drrs.dp = NULL;
> > +}
> > +
> > +/**
> > + * intel_edp_drrs_disable - Disable DRRS
> > + * @intel_dp: DP struct
> > + * @old_crtc_state: Pointer to old crtc_state.
> > + *
> > + */
> > +void intel_edp_drrs_disable(struct intel_dp *intel_dp,
> > + const struct intel_crtc_state *old_crtc_state)
> > +{
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > + if (!old_crtc_state->has_drrs)
> > + return;
> > +
> > + mutex_lock(&dev_priv->drrs.mutex);
> > + if (!dev_priv->drrs.dp) {
> > + mutex_unlock(&dev_priv->drrs.mutex);
> > + return;
> > + }
> > +
> > + intel_edp_drrs_disable_locked(intel_dp, old_crtc_state);
> > + mutex_unlock(&dev_priv->drrs.mutex);
> > +
> > + cancel_delayed_work_sync(&dev_priv->drrs.work);
> > +}
> > +
> > +/**
> > + * intel_edp_drrs_update - Update DRRS state
> > + * @intel_dp: Intel DP
> > + * @crtc_state: new CRTC state
> > + *
> > + * This function will update DRRS states, disabling or enabling DRRS when
> > + * executing fastsets. For full modeset, intel_edp_drrs_disable() and
> > + * intel_edp_drrs_enable() should be called instead.
> > + */
> > +void
> > +intel_edp_drrs_update(struct intel_dp *intel_dp,
> > + const struct intel_crtc_state *crtc_state)
> > +{
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > + if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
> > + return;
> > +
> > + mutex_lock(&dev_priv->drrs.mutex);
> > +
> > + /* New state matches current one? */
> > + if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
> > + goto unlock;
> > +
> > + if (crtc_state->has_drrs)
> > + intel_edp_drrs_enable_locked(intel_dp);
> > + else
> > + intel_edp_drrs_disable_locked(intel_dp, crtc_state);
> > +
> > +unlock:
> > + mutex_unlock(&dev_priv->drrs.mutex);
> > +}
> > +
> > +static void intel_edp_drrs_downclock_work(struct work_struct *work)
> > +{
> > + struct drm_i915_private *dev_priv =
> > + container_of(work, typeof(*dev_priv), drrs.work.work);
> > + struct intel_dp *intel_dp;
> > +
> > + mutex_lock(&dev_priv->drrs.mutex);
> > +
> > + intel_dp = dev_priv->drrs.dp;
> > +
> > + if (!intel_dp)
> > + goto unlock;
> > +
> > + /*
> > + * The delayed work can race with an invalidate hence we need to
> > + * recheck.
> > + */
> > +
> > + if (dev_priv->drrs.busy_frontbuffer_bits)
> > + goto unlock;
> > +
> > + if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
> > + struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
> > +
> > + intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
> > + drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
> > + }
> > +
> > +unlock:
> > + mutex_unlock(&dev_priv->drrs.mutex);
> > +}
> > +
> > +/**
> > + * intel_edp_drrs_invalidate - Disable Idleness DRRS
> > + * @dev_priv: i915 device
> > + * @frontbuffer_bits: frontbuffer plane tracking bits
> > + *
> > + * This function gets called everytime rendering on the given planes start.
> > + * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
> > + *
> > + * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
> > + */
> > +void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
> > + unsigned int frontbuffer_bits)
> > +{
> > + struct intel_dp *intel_dp;
> > + struct drm_crtc *crtc;
> > + enum pipe pipe;
> > +
> > + if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
> > + return;
> > +
> > + cancel_delayed_work(&dev_priv->drrs.work);
> > +
> > + mutex_lock(&dev_priv->drrs.mutex);
> > +
> > + intel_dp = dev_priv->drrs.dp;
> > + if (!intel_dp) {
> > + mutex_unlock(&dev_priv->drrs.mutex);
> > + return;
> > + }
> > +
> > + crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
> > + pipe = to_intel_crtc(crtc)->pipe;
> > +
> > + frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
> > + dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
> > +
> > + /* invalidate means busy screen hence upclock */
> > + if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
> > + intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
> > + drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
> > +
> > + mutex_unlock(&dev_priv->drrs.mutex);
> > +}
> > +
> > +/**
> > + * intel_edp_drrs_flush - Restart Idleness DRRS
> > + * @dev_priv: i915 device
> > + * @frontbuffer_bits: frontbuffer plane tracking bits
> > + *
> > + * This function gets called every time rendering on the given planes has
> > + * completed or flip on a crtc is completed. So DRRS should be upclocked
> > + * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
> > + * if no other planes are dirty.
> > + *
> > + * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
> > + */
> > +void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
> > + unsigned int frontbuffer_bits)
> > +{
> > + struct intel_dp *intel_dp;
> > + struct drm_crtc *crtc;
> > + enum pipe pipe;
> > +
> > + if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
> > + return;
> > +
> > + cancel_delayed_work(&dev_priv->drrs.work);
> > +
> > + mutex_lock(&dev_priv->drrs.mutex);
> > +
> > + intel_dp = dev_priv->drrs.dp;
> > + if (!intel_dp) {
> > + mutex_unlock(&dev_priv->drrs.mutex);
> > + return;
> > + }
> > +
> > + crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
> > + pipe = to_intel_crtc(crtc)->pipe;
> > +
> > + frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
> > + dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
> > +
> > + /* flush means busy screen hence upclock */
> > + if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
> > + intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
> > + drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
> > +
> > + /*
> > + * flush also means no more activity hence schedule downclock, if all
> > + * other fbs are quiescent too
> > + */
> > + if (!dev_priv->drrs.busy_frontbuffer_bits)
> > + schedule_delayed_work(&dev_priv->drrs.work,
> > + msecs_to_jiffies(1000));
> > + mutex_unlock(&dev_priv->drrs.mutex);
> > +}
> > +
> > +/**
> > + * intel_dp_drrs_init - Init basic DRRS work and mutex.
> > + * @connector: eDP connector
> > + * @fixed_mode: preferred mode of panel
> > + *
> > + * This function is called only once at driver load to initialize basic
> > + * DRRS stuff.
> > + *
> > + * Returns:
> > + * Downclock mode if panel supports it, else return NULL.
> > + * DRRS support is determined by the presence of downclock mode (apart
> > + * from VBT setting).
> > + */
> > +struct drm_display_mode *
> > +intel_dp_drrs_init(struct intel_connector *connector,
> > + struct drm_display_mode *fixed_mode)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > + struct drm_display_mode *downclock_mode = NULL;
> > +
> > + INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
> > + mutex_init(&dev_priv->drrs.mutex);
> > +
> > + if (DISPLAY_VER(dev_priv) <= 6) {
> > + drm_dbg_kms(&dev_priv->drm,
> > + "DRRS supported for Gen7 and above\n");
> > + return NULL;
> > + }
> > +
> > + if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
> > + drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
> > + return NULL;
> > + }
> > +
> > + downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
> > + if (!downclock_mode) {
> > + drm_dbg_kms(&dev_priv->drm,
> > + "Downclock mode is not found. DRRS not supported\n");
> > + return NULL;
> > + }
> > +
> > + dev_priv->drrs.type = dev_priv->vbt.drrs_type;
> > +
> > + dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
> > + drm_dbg_kms(&dev_priv->drm,
> > + "seamless DRRS supported for eDP panel.\n");
> > + return downclock_mode;
> > +}
> > diff --git a/drivers/gpu/drm/i915/display/intel_drrs.h b/drivers/gpu/drm/i915/display/intel_drrs.h
> > new file mode 100644
> > index 0000000000000..ffa175b4cf4f4
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/display/intel_drrs.h
> > @@ -0,0 +1,32 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2021 Intel Corporation
> > + */
> > +
> > +#ifndef __INTEL_DRRS_H__
> > +#define __INTEL_DRRS_H__
> > +
> > +#include <linux/types.h>
> > +
> > +struct drm_i915_private;
> > +struct intel_crtc_state;
> > +struct intel_connector;
> > +struct intel_dp;
> > +
> > +void intel_edp_drrs_enable(struct intel_dp *intel_dp,
> > + const struct intel_crtc_state *crtc_state);
> > +void intel_edp_drrs_disable(struct intel_dp *intel_dp,
> > + const struct intel_crtc_state *crtc_state);
> > +void intel_edp_drrs_update(struct intel_dp *intel_dp,
> > + const struct intel_crtc_state *crtc_state);
> > +void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
> > + unsigned int frontbuffer_bits);
> > +void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
> > + unsigned int frontbuffer_bits);
> > +void intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
> > + struct intel_crtc_state *pipe_config,
> > + int output_bpp, bool constant_n);
> > +struct drm_display_mode *intel_dp_drrs_init(struct intel_connector *connector,
> > + struct drm_display_mode *fixed_mode);
> > +
> > +#endif /* __INTEL_DRRS_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
> > index 8e75debcce1a9..e4834d84ce5e3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
> > +++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
> > @@ -62,6 +62,7 @@
> > #include "intel_display_types.h"
> > #include "intel_fbc.h"
> > #include "intel_frontbuffer.h"
> > +#include "intel_drrs.h"
> > #include "intel_psr.h"
> >
> > /**
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH 4/8] drm/i915/display: Some code improvements and code style fixes for DRRS
2021-08-18 0:42 [Intel-gfx] [PATCH 0/8] Drop frontbuffer rendering support from Skylake and newer José Roberto de Souza
` (2 preceding siblings ...)
2021-08-18 0:42 ` [Intel-gfx] [PATCH 3/8] drm/i915/display: Move DRRS code its own file José Roberto de Souza
@ 2021-08-18 0:42 ` José Roberto de Souza
2021-08-18 0:42 ` [Intel-gfx] [PATCH 5/8] drm/i915/display: Share code between intel_edp_drrs_flush and invalidate José Roberto de Souza
` (6 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: José Roberto de Souza @ 2021-08-18 0:42 UTC (permalink / raw)
To: intel-gfx; +Cc: José Roberto de Souza
It started as a code style fix for the lines above 100 col but it
turned out to simplyfications to intel_dp_set_drrs_state().
Now it receives the desired refresh rate type, high or low.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_drrs.c | 60 ++++++++---------------
1 file changed, 21 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index be9b6d4482f04..e96033bc6c658 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -91,7 +91,7 @@ intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
* intel_dp_set_drrs_state - program registers for RR switch to take effect
* @dev_priv: i915 device
* @crtc_state: a pointer to the active intel_crtc_state
- * @refresh_rate: RR to be programmed
+ * @refresh_type: high or low refresh rate to be programmed
*
* This function gets called when refresh rate (RR) has to be changed from
* one frequency to another. Switches can be between high and low RR
@@ -102,19 +102,13 @@ intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
*/
static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
- int refresh_rate)
+ enum drrs_refresh_rate_type refresh_type)
{
struct intel_dp *intel_dp = dev_priv->drrs.dp;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
+ struct drm_display_mode *mode;
- if (refresh_rate <= 0) {
- drm_dbg_kms(&dev_priv->drm,
- "Refresh rate should be positive non-zero.\n");
- return;
- }
-
- if (intel_dp == NULL) {
+ if (!intel_dp) {
drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
return;
}
@@ -130,15 +124,8 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
return;
}
- if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) ==
- refresh_rate)
- index = DRRS_LOW_RR;
-
- if (index == dev_priv->drrs.refresh_rate_type) {
- drm_dbg_kms(&dev_priv->drm,
- "DRRS requested for previously set RR...ignoring\n");
+ if (refresh_type == dev_priv->drrs.refresh_rate_type)
return;
- }
if (!crtc_state->hw.active) {
drm_dbg_kms(&dev_priv->drm,
@@ -147,7 +134,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
}
if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
- switch (index) {
+ switch (refresh_type) {
case DRRS_HIGH_RR:
intel_dp_set_m_n(crtc_state, M1_N1);
break;
@@ -164,7 +151,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
u32 val;
val = intel_de_read(dev_priv, reg);
- if (index > DRRS_HIGH_RR) {
+ if (refresh_type == DRRS_LOW_RR) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
else
@@ -178,10 +165,14 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
intel_de_write(dev_priv, reg, val);
}
- dev_priv->drrs.refresh_rate_type = index;
+ dev_priv->drrs.refresh_rate_type = refresh_type;
+ if (refresh_type == DRRS_LOW_RR)
+ mode = intel_dp->attached_connector->panel.fixed_mode;
+ else
+ mode = intel_dp->attached_connector->panel.downclock_mode;
drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
- refresh_rate);
+ drm_mode_vrefresh(mode));
}
static void
@@ -229,13 +220,7 @@ intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
- int refresh;
-
- refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
- intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
- }
-
+ intel_dp_set_drrs_state(dev_priv, crtc_state, DRRS_HIGH_RR);
dev_priv->drrs.dp = NULL;
}
@@ -303,6 +288,7 @@ static void intel_edp_drrs_downclock_work(struct work_struct *work)
struct drm_i915_private *dev_priv =
container_of(work, typeof(*dev_priv), drrs.work.work);
struct intel_dp *intel_dp;
+ struct drm_crtc *crtc;
mutex_lock(&dev_priv->drrs.mutex);
@@ -319,12 +305,8 @@ static void intel_edp_drrs_downclock_work(struct work_struct *work)
if (dev_priv->drrs.busy_frontbuffer_bits)
goto unlock;
- if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
- struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
-
- intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
- drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
- }
+ crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
+ intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, DRRS_LOW_RR);
unlock:
mutex_unlock(&dev_priv->drrs.mutex);
@@ -367,9 +349,9 @@ void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
/* invalidate means busy screen hence upclock */
- if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
+ if (frontbuffer_bits)
intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
- drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
+ DRRS_HIGH_RR);
mutex_unlock(&dev_priv->drrs.mutex);
}
@@ -413,9 +395,9 @@ void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
/* flush means busy screen hence upclock */
- if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
+ if (frontbuffer_bits)
intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
- drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
+ DRRS_HIGH_RR);
/*
* flush also means no more activity hence schedule downclock, if all
--
2.32.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [Intel-gfx] [PATCH 5/8] drm/i915/display: Share code between intel_edp_drrs_flush and invalidate
2021-08-18 0:42 [Intel-gfx] [PATCH 0/8] Drop frontbuffer rendering support from Skylake and newer José Roberto de Souza
` (3 preceding siblings ...)
2021-08-18 0:42 ` [Intel-gfx] [PATCH 4/8] drm/i915/display: Some code improvements and code style fixes for DRRS José Roberto de Souza
@ 2021-08-18 0:42 ` José Roberto de Souza
2021-08-18 0:42 ` [Intel-gfx] [PATCH 6/8] drm/i915/display: Prepare DRRS for frontbuffer rendering drop José Roberto de Souza
` (5 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: José Roberto de Souza @ 2021-08-18 0:42 UTC (permalink / raw)
To: intel-gfx; +Cc: José Roberto de Souza
Both functions are pretty much equal, with minor changes that can be
handled by a single parameter.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_drrs.c | 82 +++++++++--------------
1 file changed, 32 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index e96033bc6c658..b885c1ec76bf9 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -312,18 +312,9 @@ static void intel_edp_drrs_downclock_work(struct work_struct *work)
mutex_unlock(&dev_priv->drrs.mutex);
}
-/**
- * intel_edp_drrs_invalidate - Disable Idleness DRRS
- * @dev_priv: i915 device
- * @frontbuffer_bits: frontbuffer plane tracking bits
- *
- * This function gets called everytime rendering on the given planes start.
- * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
- *
- * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
- */
-void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
- unsigned int frontbuffer_bits)
+static void intel_edp_drrs_frontbuffer_update(struct drm_i915_private *dev_priv,
+ unsigned int frontbuffer_bits,
+ bool invalidate)
{
struct intel_dp *intel_dp;
struct drm_crtc *crtc;
@@ -346,16 +337,42 @@ void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
pipe = to_intel_crtc(crtc)->pipe;
frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
- dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
+ if (invalidate)
+ dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
+ else
+ dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
- /* invalidate means busy screen hence upclock */
+ /* flush/invalidate means busy screen hence upclock */
if (frontbuffer_bits)
intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
DRRS_HIGH_RR);
+ /*
+ * flush also means no more activity hence schedule downclock, if all
+ * other fbs are quiescent too
+ */
+ if (!dev_priv->drrs.busy_frontbuffer_bits)
+ schedule_delayed_work(&dev_priv->drrs.work,
+ msecs_to_jiffies(1000));
mutex_unlock(&dev_priv->drrs.mutex);
}
+/**
+ * intel_edp_drrs_invalidate - Disable Idleness DRRS
+ * @dev_priv: i915 device
+ * @frontbuffer_bits: frontbuffer plane tracking bits
+ *
+ * This function gets called everytime rendering on the given planes start.
+ * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
+ *
+ * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
+ */
+void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
+ unsigned int frontbuffer_bits)
+{
+ intel_edp_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, true);
+}
+
/**
* intel_edp_drrs_flush - Restart Idleness DRRS
* @dev_priv: i915 device
@@ -371,42 +388,7 @@ void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits)
{
- struct intel_dp *intel_dp;
- struct drm_crtc *crtc;
- enum pipe pipe;
-
- if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
- return;
-
- cancel_delayed_work(&dev_priv->drrs.work);
-
- mutex_lock(&dev_priv->drrs.mutex);
-
- intel_dp = dev_priv->drrs.dp;
- if (!intel_dp) {
- mutex_unlock(&dev_priv->drrs.mutex);
- return;
- }
-
- crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
- pipe = to_intel_crtc(crtc)->pipe;
-
- frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
- dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
-
- /* flush means busy screen hence upclock */
- if (frontbuffer_bits)
- intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
- DRRS_HIGH_RR);
-
- /*
- * flush also means no more activity hence schedule downclock, if all
- * other fbs are quiescent too
- */
- if (!dev_priv->drrs.busy_frontbuffer_bits)
- schedule_delayed_work(&dev_priv->drrs.work,
- msecs_to_jiffies(1000));
- mutex_unlock(&dev_priv->drrs.mutex);
+ intel_edp_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false);
}
/**
--
2.32.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [Intel-gfx] [PATCH 6/8] drm/i915/display: Prepare DRRS for frontbuffer rendering drop
2021-08-18 0:42 [Intel-gfx] [PATCH 0/8] Drop frontbuffer rendering support from Skylake and newer José Roberto de Souza
` (4 preceding siblings ...)
2021-08-18 0:42 ` [Intel-gfx] [PATCH 5/8] drm/i915/display: Share code between intel_edp_drrs_flush and invalidate José Roberto de Souza
@ 2021-08-18 0:42 ` José Roberto de Souza
2021-08-18 0:42 ` [Intel-gfx] [PATCH 7/8] drm/i915/display/skl+: Drop frontbuffer rendering support José Roberto de Souza
` (4 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: José Roberto de Souza @ 2021-08-18 0:42 UTC (permalink / raw)
To: intel-gfx; +Cc: José Roberto de Souza
Frontbuffer rendering will be dropped for modern platforms but
before that we to prepare DRRS for it.
intel_edp_drrs_flush and intel_edp_drrs_invalidate will not be called
for platforms that will not support frontbuffer rendering so DRRS
needs another way to be notified about to page flips so it can change
between high and low refresh rates as needed.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 ++
drivers/gpu/drm/i915/display/intel_drrs.c | 9 +++++++++
drivers/gpu/drm/i915/display/intel_drrs.h | 4 ++++
3 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a257e5dc381c6..e55c9e2cb254a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -52,6 +52,7 @@
#include "display/intel_dp_mst.h"
#include "display/intel_dpll.h"
#include "display/intel_dpll_mgr.h"
+#include "display/intel_drrs.h"
#include "display/intel_dsi.h"
#include "display/intel_dvo.h"
#include "display/intel_fb.h"
@@ -2872,6 +2873,7 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
hsw_enable_ips(new_crtc_state);
intel_fbc_post_update(state, crtc);
+ intel_edp_drrs_page_flip(state, crtc);
if (needs_nv12_wa(old_crtc_state) &&
!needs_nv12_wa(new_crtc_state))
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index b885c1ec76bf9..c5509ed9666be 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -391,6 +391,15 @@ void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
intel_edp_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false);
}
+void intel_edp_drrs_page_flip(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ unsigned int frontbuffer_bits = INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe);
+
+ intel_edp_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false);
+}
+
/**
* intel_dp_drrs_init - Init basic DRRS work and mutex.
* @connector: eDP connector
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.h b/drivers/gpu/drm/i915/display/intel_drrs.h
index ffa175b4cf4f4..5ae3769700bf3 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.h
+++ b/drivers/gpu/drm/i915/display/intel_drrs.h
@@ -9,6 +9,8 @@
#include <linux/types.h>
struct drm_i915_private;
+struct intel_atomic_state;
+struct intel_crtc;
struct intel_crtc_state;
struct intel_connector;
struct intel_dp;
@@ -23,6 +25,8 @@ void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits);
void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits);
+void intel_edp_drrs_page_flip(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
void intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
int output_bpp, bool constant_n);
--
2.32.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [Intel-gfx] [PATCH 7/8] drm/i915/display/skl+: Drop frontbuffer rendering support
2021-08-18 0:42 [Intel-gfx] [PATCH 0/8] Drop frontbuffer rendering support from Skylake and newer José Roberto de Souza
` (5 preceding siblings ...)
2021-08-18 0:42 ` [Intel-gfx] [PATCH 6/8] drm/i915/display: Prepare DRRS for frontbuffer rendering drop José Roberto de Souza
@ 2021-08-18 0:42 ` José Roberto de Souza
2021-08-18 14:55 ` Ville Syrjälä
2021-08-24 7:21 ` Daniel Vetter
2021-08-18 0:42 ` [Intel-gfx] [PATCH 8/8] drm/i915/display: Drop PSR " José Roberto de Souza
` (3 subsequent siblings)
10 siblings, 2 replies; 22+ messages in thread
From: José Roberto de Souza @ 2021-08-18 0:42 UTC (permalink / raw)
To: intel-gfx
Cc: Daniel Vetter, Gwan-gyeong Mun, Ville Syrjälä,
Jani Nikula, Rodrigo Vivi, José Roberto de Souza
By now all the userspace applications should have migrated to atomic
or at least be calling DRM_IOCTL_MODE_DIRTYFB.
With that we can kill frontbuffer rendering support in i915 for
modern platforms.
So here converting legacy APIs into atomic commits so it can be
properly handled by driver i915.
Several IGT tests will fail with this changes, because some tests
were stressing those frontbuffer rendering scenarios that no userspace
should be using by now, fixes to IGT should be sent soon.
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_cursor.c | 6 ++----
drivers/gpu/drm/i915/display/intel_display.c | 7 ++++++-
drivers/gpu/drm/i915/display/intel_frontbuffer.c | 6 ++++++
drivers/gpu/drm/i915/i915_drv.h | 2 ++
4 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index c7618fef01439..5aa996c3b7980 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -617,6 +617,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
u32 src_w, u32 src_h,
struct drm_modeset_acquire_ctx *ctx)
{
+ struct drm_i915_private *i915 = to_i915(_crtc->dev);
struct intel_plane *plane = to_intel_plane(_plane);
struct intel_crtc *crtc = to_intel_crtc(_crtc);
struct intel_plane_state *old_plane_state =
@@ -633,12 +634,9 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
* PSR2 selective fetch also requires the slow path as
* PSR2 plane and transcoder registers can only be updated during
* vblank.
- *
- * FIXME bigjoiner fastpath would be good
*/
if (!crtc_state->hw.active || intel_crtc_needs_modeset(crtc_state) ||
- crtc_state->update_pipe || crtc_state->bigjoiner ||
- crtc_state->enable_psr2_sel_fetch)
+ crtc_state->update_pipe || !HAS_FRONTBUFFER_RENDERING(i915))
goto slow;
/*
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e55c9e2cb254a..f700544454ad5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11744,10 +11744,15 @@ static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
unsigned num_clips)
{
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
i915_gem_object_flush_if_display(obj);
- intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
+ if (!HAS_FRONTBUFFER_RENDERING(i915))
+ return drm_atomic_helper_dirtyfb(fb, file, flags, color, clips,
+ num_clips);
+
+ intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
index e4834d84ce5e3..6be2f767a203c 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
@@ -91,6 +91,9 @@ static void frontbuffer_flush(struct drm_i915_private *i915,
trace_intel_frontbuffer_flush(frontbuffer_bits, origin);
+ if (!HAS_FRONTBUFFER_RENDERING(i915))
+ return;
+
might_sleep();
intel_edp_drrs_flush(i915, frontbuffer_bits);
intel_psr_flush(i915, frontbuffer_bits, origin);
@@ -179,6 +182,9 @@ void __intel_fb_invalidate(struct intel_frontbuffer *front,
trace_intel_frontbuffer_invalidate(frontbuffer_bits, origin);
+ if (!HAS_FRONTBUFFER_RENDERING(i915))
+ return;
+
might_sleep();
intel_psr_invalidate(i915, frontbuffer_bits, origin);
intel_edp_drrs_invalidate(i915, frontbuffer_bits);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1ea27c4e94a6d..fe1dc8b7871a0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1719,6 +1719,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_VRR(i915) (GRAPHICS_VER(i915) >= 12)
+#define HAS_FRONTBUFFER_RENDERING(i915) (GRAPHICS_VER(i915) < 9)
+
/* Only valid when HAS_DISPLAY() is true */
#define INTEL_DISPLAY_ENABLED(dev_priv) \
(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
--
2.32.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [PATCH 7/8] drm/i915/display/skl+: Drop frontbuffer rendering support
2021-08-18 0:42 ` [Intel-gfx] [PATCH 7/8] drm/i915/display/skl+: Drop frontbuffer rendering support José Roberto de Souza
@ 2021-08-18 14:55 ` Ville Syrjälä
2021-08-18 19:48 ` Souza, Jose
2021-08-24 7:21 ` Daniel Vetter
1 sibling, 1 reply; 22+ messages in thread
From: Ville Syrjälä @ 2021-08-18 14:55 UTC (permalink / raw)
To: José Roberto de Souza
Cc: intel-gfx, Daniel Vetter, Gwan-gyeong Mun, Jani Nikula, Rodrigo Vivi
On Tue, Aug 17, 2021 at 05:42:15PM -0700, José Roberto de Souza wrote:
> By now all the userspace applications should have migrated to atomic
> or at least be calling DRM_IOCTL_MODE_DIRTYFB.
>
> With that we can kill frontbuffer rendering support in i915 for
> modern platforms.
>
> So here converting legacy APIs into atomic commits so it can be
> properly handled by driver i915.
>
> Several IGT tests will fail with this changes, because some tests
> were stressing those frontbuffer rendering scenarios that no userspace
> should be using by now, fixes to IGT should be sent soon.
Blocking atomic commits instead of the current lightweight frontbuffer
interface sounds like a terrible plan. How unusable is X with this
approach?
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 7/8] drm/i915/display/skl+: Drop frontbuffer rendering support
2021-08-18 14:55 ` Ville Syrjälä
@ 2021-08-18 19:48 ` Souza, Jose
2021-08-19 16:07 ` Ville Syrjälä
0 siblings, 1 reply; 22+ messages in thread
From: Souza, Jose @ 2021-08-18 19:48 UTC (permalink / raw)
To: ville.syrjala
Cc: daniel, Mun, Gwan-gyeong, Nikula, Jani, intel-gfx, Vivi, Rodrigo
On Wed, 2021-08-18 at 17:55 +0300, Ville Syrjälä wrote:
> On Tue, Aug 17, 2021 at 05:42:15PM -0700, José Roberto de Souza wrote:
> > By now all the userspace applications should have migrated to atomic
> > or at least be calling DRM_IOCTL_MODE_DIRTYFB.
> >
> > With that we can kill frontbuffer rendering support in i915 for
> > modern platforms.
> >
> > So here converting legacy APIs into atomic commits so it can be
> > properly handled by driver i915.
> >
> > Several IGT tests will fail with this changes, because some tests
> > were stressing those frontbuffer rendering scenarios that no userspace
> > should be using by now, fixes to IGT should be sent soon.
>
> Blocking atomic commits instead of the current lightweight frontbuffer
> interface sounds like a terrible plan. How unusable is X with this
> approach?
100% usable, had no issues when running X in TGL and ADL-P.
Added a debug message in intel_user_framebuffer_dirty() and X is not even using frontbuffer rendering at all.
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 7/8] drm/i915/display/skl+: Drop frontbuffer rendering support
2021-08-18 19:48 ` Souza, Jose
@ 2021-08-19 16:07 ` Ville Syrjälä
2021-08-25 0:49 ` Souza, Jose
0 siblings, 1 reply; 22+ messages in thread
From: Ville Syrjälä @ 2021-08-19 16:07 UTC (permalink / raw)
To: Souza, Jose
Cc: daniel, Mun, Gwan-gyeong, Nikula, Jani, intel-gfx, Vivi, Rodrigo
On Wed, Aug 18, 2021 at 07:48:03PM +0000, Souza, Jose wrote:
> On Wed, 2021-08-18 at 17:55 +0300, Ville Syrjälä wrote:
> > On Tue, Aug 17, 2021 at 05:42:15PM -0700, José Roberto de Souza wrote:
> > > By now all the userspace applications should have migrated to atomic
> > > or at least be calling DRM_IOCTL_MODE_DIRTYFB.
> > >
> > > With that we can kill frontbuffer rendering support in i915 for
> > > modern platforms.
> > >
> > > So here converting legacy APIs into atomic commits so it can be
> > > properly handled by driver i915.
> > >
> > > Several IGT tests will fail with this changes, because some tests
> > > were stressing those frontbuffer rendering scenarios that no userspace
> > > should be using by now, fixes to IGT should be sent soon.
> >
> > Blocking atomic commits instead of the current lightweight frontbuffer
> > interface sounds like a terrible plan. How unusable is X with this
> > approach?
>
> 100% usable, had no issues when running X in TGL and ADL-P.
> Added a debug message in intel_user_framebuffer_dirty() and X is not even using frontbuffer rendering at all.
Turn off your compositor if you want to test front buffer rendering.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 7/8] drm/i915/display/skl+: Drop frontbuffer rendering support
2021-08-19 16:07 ` Ville Syrjälä
@ 2021-08-25 0:49 ` Souza, Jose
2021-08-25 12:47 ` Ville Syrjälä
0 siblings, 1 reply; 22+ messages in thread
From: Souza, Jose @ 2021-08-25 0:49 UTC (permalink / raw)
To: ville.syrjala
Cc: daniel, Mun, Gwan-gyeong, Nikula, Jani, intel-gfx, Vivi, Rodrigo
On Thu, 2021-08-19 at 19:07 +0300, Ville Syrjälä wrote:
> On Wed, Aug 18, 2021 at 07:48:03PM +0000, Souza, Jose wrote:
> > On Wed, 2021-08-18 at 17:55 +0300, Ville Syrjälä wrote:
> > > On Tue, Aug 17, 2021 at 05:42:15PM -0700, José Roberto de Souza wrote:
> > > > By now all the userspace applications should have migrated to atomic
> > > > or at least be calling DRM_IOCTL_MODE_DIRTYFB.
> > > >
> > > > With that we can kill frontbuffer rendering support in i915 for
> > > > modern platforms.
> > > >
> > > > So here converting legacy APIs into atomic commits so it can be
> > > > properly handled by driver i915.
> > > >
> > > > Several IGT tests will fail with this changes, because some tests
> > > > were stressing those frontbuffer rendering scenarios that no userspace
> > > > should be using by now, fixes to IGT should be sent soon.
> > >
> > > Blocking atomic commits instead of the current lightweight frontbuffer
> > > interface sounds like a terrible plan. How unusable is X with this
> > > approach?
> >
> > 100% usable, had no issues when running X in TGL and ADL-P.
> > Added a debug message in intel_user_framebuffer_dirty() and X is not even using frontbuffer rendering at all.
>
> Turn off your compositor if you want to test front buffer rendering.
Worked fine on Plasma with a 4K panel, was not able to find how to do that in Gnome.
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 7/8] drm/i915/display/skl+: Drop frontbuffer rendering support
2021-08-25 0:49 ` Souza, Jose
@ 2021-08-25 12:47 ` Ville Syrjälä
2021-08-25 13:43 ` Ville Syrjälä
0 siblings, 1 reply; 22+ messages in thread
From: Ville Syrjälä @ 2021-08-25 12:47 UTC (permalink / raw)
To: Souza, Jose
Cc: daniel, Mun, Gwan-gyeong, Nikula, Jani, intel-gfx, Vivi, Rodrigo
On Wed, Aug 25, 2021 at 12:49:25AM +0000, Souza, Jose wrote:
> On Thu, 2021-08-19 at 19:07 +0300, Ville Syrjälä wrote:
> > On Wed, Aug 18, 2021 at 07:48:03PM +0000, Souza, Jose wrote:
> > > On Wed, 2021-08-18 at 17:55 +0300, Ville Syrjälä wrote:
> > > > On Tue, Aug 17, 2021 at 05:42:15PM -0700, José Roberto de Souza wrote:
> > > > > By now all the userspace applications should have migrated to atomic
> > > > > or at least be calling DRM_IOCTL_MODE_DIRTYFB.
> > > > >
> > > > > With that we can kill frontbuffer rendering support in i915 for
> > > > > modern platforms.
> > > > >
> > > > > So here converting legacy APIs into atomic commits so it can be
> > > > > properly handled by driver i915.
> > > > >
> > > > > Several IGT tests will fail with this changes, because some tests
> > > > > were stressing those frontbuffer rendering scenarios that no userspace
> > > > > should be using by now, fixes to IGT should be sent soon.
> > > >
> > > > Blocking atomic commits instead of the current lightweight frontbuffer
> > > > interface sounds like a terrible plan. How unusable is X with this
> > > > approach?
> > >
> > > 100% usable, had no issues when running X in TGL and ADL-P.
> > > Added a debug message in intel_user_framebuffer_dirty() and X is not even using frontbuffer rendering at all.
> >
> > Turn off your compositor if you want to test front buffer rendering.
>
> Worked fine on Plasma with a 4K panel, was not able to find how to do that in Gnome.
I didn't think you can turn off composition with either one of those.
You actually confirmed it's running with everytithing unredirected and
eg. there was no lag moving windows around and wiggling the mouse?
Avoiding that lag is pretty much the sole reason why the legacy
cursor unsynced update stuff even exists in the driver. Hard to
imagine you wouldn't hit the same issue with the server getting
blocked on dirtyfb all the time.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 7/8] drm/i915/display/skl+: Drop frontbuffer rendering support
2021-08-25 12:47 ` Ville Syrjälä
@ 2021-08-25 13:43 ` Ville Syrjälä
2021-08-26 1:23 ` Souza, Jose
0 siblings, 1 reply; 22+ messages in thread
From: Ville Syrjälä @ 2021-08-25 13:43 UTC (permalink / raw)
To: Souza, Jose
Cc: daniel, Mun, Gwan-gyeong, Nikula, Jani, intel-gfx, Vivi, Rodrigo
On Wed, Aug 25, 2021 at 03:47:12PM +0300, Ville Syrjälä wrote:
> On Wed, Aug 25, 2021 at 12:49:25AM +0000, Souza, Jose wrote:
> > On Thu, 2021-08-19 at 19:07 +0300, Ville Syrjälä wrote:
> > > On Wed, Aug 18, 2021 at 07:48:03PM +0000, Souza, Jose wrote:
> > > > On Wed, 2021-08-18 at 17:55 +0300, Ville Syrjälä wrote:
> > > > > On Tue, Aug 17, 2021 at 05:42:15PM -0700, José Roberto de Souza wrote:
> > > > > > By now all the userspace applications should have migrated to atomic
> > > > > > or at least be calling DRM_IOCTL_MODE_DIRTYFB.
> > > > > >
> > > > > > With that we can kill frontbuffer rendering support in i915 for
> > > > > > modern platforms.
> > > > > >
> > > > > > So here converting legacy APIs into atomic commits so it can be
> > > > > > properly handled by driver i915.
> > > > > >
> > > > > > Several IGT tests will fail with this changes, because some tests
> > > > > > were stressing those frontbuffer rendering scenarios that no userspace
> > > > > > should be using by now, fixes to IGT should be sent soon.
> > > > >
> > > > > Blocking atomic commits instead of the current lightweight frontbuffer
> > > > > interface sounds like a terrible plan. How unusable is X with this
> > > > > approach?
> > > >
> > > > 100% usable, had no issues when running X in TGL and ADL-P.
> > > > Added a debug message in intel_user_framebuffer_dirty() and X is not even using frontbuffer rendering at all.
> > >
> > > Turn off your compositor if you want to test front buffer rendering.
> >
> > Worked fine on Plasma with a 4K panel, was not able to find how to do that in Gnome.
>
> I didn't think you can turn off composition with either one of those.
> You actually confirmed it's running with everytithing unredirected and
> eg. there was no lag moving windows around and wiggling the mouse?
>
> Avoiding that lag is pretty much the sole reason why the legacy
> cursor unsynced update stuff even exists in the driver. Hard to
> imagine you wouldn't hit the same issue with the server getting
> blocked on dirtyfb all the time.
Oh and running x11perf/etc. to see the impact on the raw numbers would
probably be good idea.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 7/8] drm/i915/display/skl+: Drop frontbuffer rendering support
2021-08-25 13:43 ` Ville Syrjälä
@ 2021-08-26 1:23 ` Souza, Jose
0 siblings, 0 replies; 22+ messages in thread
From: Souza, Jose @ 2021-08-26 1:23 UTC (permalink / raw)
To: ville.syrjala
Cc: daniel, Mun, Gwan-gyeong, Nikula, Jani, intel-gfx, Vivi, Rodrigo
[-- Attachment #1: Type: text/plain, Size: 4119 bytes --]
On Wed, 2021-08-25 at 16:43 +0300, Ville Syrjälä wrote:
> On Wed, Aug 25, 2021 at 03:47:12PM +0300, Ville Syrjälä wrote:
> > On Wed, Aug 25, 2021 at 12:49:25AM +0000, Souza, Jose wrote:
> > > On Thu, 2021-08-19 at 19:07 +0300, Ville Syrjälä wrote:
> > > > On Wed, Aug 18, 2021 at 07:48:03PM +0000, Souza, Jose wrote:
> > > > > On Wed, 2021-08-18 at 17:55 +0300, Ville Syrjälä wrote:
> > > > > > On Tue, Aug 17, 2021 at 05:42:15PM -0700, José Roberto de Souza wrote:
> > > > > > > By now all the userspace applications should have migrated to atomic
> > > > > > > or at least be calling DRM_IOCTL_MODE_DIRTYFB.
> > > > > > >
> > > > > > > With that we can kill frontbuffer rendering support in i915 for
> > > > > > > modern platforms.
> > > > > > >
> > > > > > > So here converting legacy APIs into atomic commits so it can be
> > > > > > > properly handled by driver i915.
> > > > > > >
> > > > > > > Several IGT tests will fail with this changes, because some tests
> > > > > > > were stressing those frontbuffer rendering scenarios that no userspace
> > > > > > > should be using by now, fixes to IGT should be sent soon.
> > > > > >
> > > > > > Blocking atomic commits instead of the current lightweight frontbuffer
> > > > > > interface sounds like a terrible plan. How unusable is X with this
> > > > > > approach?
> > > > >
> > > > > 100% usable, had no issues when running X in TGL and ADL-P.
> > > > > Added a debug message in intel_user_framebuffer_dirty() and X is not even using frontbuffer rendering at all.
> > > >
> > > > Turn off your compositor if you want to test front buffer rendering.
> > >
> > > Worked fine on Plasma with a 4K panel, was not able to find how to do that in Gnome.
> >
> > I didn't think you can turn off composition with either one of those.
> > You actually confirmed it's running with everytithing unredirected and
> > eg. there was no lag moving windows around and wiggling the mouse?
> >
> > Avoiding that lag is pretty much the sole reason why the legacy
> > cursor unsynced update stuff even exists in the driver. Hard to
> > imagine you wouldn't hit the same issue with the server getting
> > blocked on dirtyfb all the time.
That is not the only path that Windows servers that implements Wayland protocol have?
From a user experience I can't see any difference when moving the cursor around and dragging windows.
>
> Oh and running x11perf/etc. to see the impact on the raw numbers would
> probably be good idea.
>
Attached two x11perf runs using the cmd line below, "with-front-buffer-rendering.txt" with patches up to "drm/i915/display: Prepare DRRS for
frontbuffer rendering drop" and "no-front-buffer-rendering.txt" with all the patches in this series.
CMD line: sudo DISPLAY=:0.0 x11perf -su -dot -rect500 -srect500 -osrect500 -tilerect500 -oddsrect500 -oddosrect500 -oddtilerect500 -bigsrect500 -
bigosrect500 -bigtilerect500 -eschertilerect500 -seg500 -hseg500 -vseg500 -whseg500 -wvseg500 -line500 -wline500 -orect500 -worect500 -circle500 -
wcircle500 -fcircle500 -ellipse500 -wellipse500 -fellipse500 -trap300 -strap300 -ostrap300 -tiletrap300 -oddstrap300 -oddostrap300 -oddtiletrap300 -
bigstrap300 -bigostrap300 -bigtiletrap300 -eschertiletrap300 -aatrap300 -aa4trap300 -aa1trap300 -aatrap2x300 -aatrapezoid300 -addaatrapezoid300 -ftext
-f8text -f9text -f14text16 -f24text16 -tr10text -tr24text -polytext -polytext16 -fitext -f8itext -f9itext -f14itext16 -f24itext16 -tr10itext -
tr24itext -aa10text -aa24text -aaftext -a10text -a24text -aftext -rgb10text -rgb24text -rgbftext -caa10text -caa24text -caaftext -ca10text -ca24text -
caftext -crgb10text -crgb24text -crgbftext -scroll500 -copywinwin500 -copypixwin500 -copywinpix500 -copypixpix500 -copyplane500 -deepcopyplane500 -
putimage500 -putimagexy500 -shmput500 -shmputxy500 -shmget500 -shmgetxy500 -getimage500 -getimagexy500 -compwinwin500 -comppixwin500 -magpixwin500 -
minpixwin500 -noop -pointer -prop -gc -create -ucreate -map -unmap -destroy -popup -move -umove -movetree -resize -uresize -circulate -ucirculate
[-- Attachment #2: with-front-buffer-rendering.txt --]
[-- Type: text/plain, Size: 89345 bytes --]
x11perf - X11 performance program, version 1.2
The X.Org Foundation server version 12005000 on :0.0
from stark01
Wed Aug 25 16:52:08 2021
Sync time adjustment is 0.0542 msecs.
800000000 reps @ 0.0000 msec (171000000.0/sec): Dot
800000000 reps @ 0.0000 msec (168000000.0/sec): Dot
800000000 reps @ 0.0000 msec (162000000.0/sec): Dot
800000000 reps @ 0.0000 msec (170000000.0/sec): Dot
800000000 reps @ 0.0000 msec (166000000.0/sec): Dot
4000000000 trep @ 0.0000 msec (167000000.0/sec): Dot
200000 reps @ 0.0251 msec ( 39800.0/sec): 500x500 rectangle
200000 reps @ 0.0253 msec ( 39600.0/sec): 500x500 rectangle
200000 reps @ 0.0251 msec ( 39800.0/sec): 500x500 rectangle
200000 reps @ 0.0251 msec ( 39800.0/sec): 500x500 rectangle
200000 reps @ 0.0251 msec ( 39900.0/sec): 500x500 rectangle
1000000 trep @ 0.0252 msec ( 39800.0/sec): 500x500 rectangle
80000 reps @ 0.0690 msec ( 14500.0/sec): 500x500 stippled rectangle (8x8 stipple)
80000 reps @ 0.0689 msec ( 14500.0/sec): 500x500 stippled rectangle (8x8 stipple)
80000 reps @ 0.0687 msec ( 14500.0/sec): 500x500 stippled rectangle (8x8 stipple)
80000 reps @ 0.0691 msec ( 14500.0/sec): 500x500 stippled rectangle (8x8 stipple)
80000 reps @ 0.0653 msec ( 15300.0/sec): 500x500 stippled rectangle (8x8 stipple)
400000 trep @ 0.0682 msec ( 14700.0/sec): 500x500 stippled rectangle (8x8 stipple)
300000 reps @ 0.0245 msec ( 40800.0/sec): 500x500 opaque stippled rectangle (8x8 stipple)
300000 reps @ 0.0245 msec ( 40900.0/sec): 500x500 opaque stippled rectangle (8x8 stipple)
300000 reps @ 0.0245 msec ( 40900.0/sec): 500x500 opaque stippled rectangle (8x8 stipple)
300000 reps @ 0.0244 msec ( 40900.0/sec): 500x500 opaque stippled rectangle (8x8 stipple)
300000 reps @ 0.0245 msec ( 40900.0/sec): 500x500 opaque stippled rectangle (8x8 stipple)
1500000 trep @ 0.0245 msec ( 40900.0/sec): 500x500 opaque stippled rectangle (8x8 stipple)
300000 reps @ 0.0246 msec ( 40600.0/sec): 500x500 tiled rectangle (4x4 tile)
300000 reps @ 0.0247 msec ( 40500.0/sec): 500x500 tiled rectangle (4x4 tile)
300000 reps @ 0.0250 msec ( 40100.0/sec): 500x500 tiled rectangle (4x4 tile)
300000 reps @ 0.0246 msec ( 40600.0/sec): 500x500 tiled rectangle (4x4 tile)
300000 reps @ 0.0246 msec ( 40600.0/sec): 500x500 tiled rectangle (4x4 tile)
1500000 trep @ 0.0247 msec ( 40500.0/sec): 500x500 tiled rectangle (4x4 tile)
80000 reps @ 0.0670 msec ( 14900.0/sec): 500x500 stippled rectangle (17x15 stipple)
80000 reps @ 0.0668 msec ( 15000.0/sec): 500x500 stippled rectangle (17x15 stipple)
80000 reps @ 0.0612 msec ( 16300.0/sec): 500x500 stippled rectangle (17x15 stipple)
80000 reps @ 0.0672 msec ( 14900.0/sec): 500x500 stippled rectangle (17x15 stipple)
80000 reps @ 0.0673 msec ( 14900.0/sec): 500x500 stippled rectangle (17x15 stipple)
400000 trep @ 0.0659 msec ( 15200.0/sec): 500x500 stippled rectangle (17x15 stipple)
300000 reps @ 0.0245 msec ( 40900.0/sec): 500x500 opaque stippled rectangle (17x15 stipple)
300000 reps @ 0.0244 msec ( 40900.0/sec): 500x500 opaque stippled rectangle (17x15 stipple)
300000 reps @ 0.0244 msec ( 40900.0/sec): 500x500 opaque stippled rectangle (17x15 stipple)
300000 reps @ 0.0244 msec ( 40900.0/sec): 500x500 opaque stippled rectangle (17x15 stipple)
300000 reps @ 0.0245 msec ( 40900.0/sec): 500x500 opaque stippled rectangle (17x15 stipple)
1500000 trep @ 0.0244 msec ( 40900.0/sec): 500x500 opaque stippled rectangle (17x15 stipple)
300000 reps @ 0.0248 msec ( 40400.0/sec): 500x500 tiled rectangle (17x15 tile)
300000 reps @ 0.0247 msec ( 40600.0/sec): 500x500 tiled rectangle (17x15 tile)
300000 reps @ 0.0248 msec ( 40400.0/sec): 500x500 tiled rectangle (17x15 tile)
300000 reps @ 0.0247 msec ( 40500.0/sec): 500x500 tiled rectangle (17x15 tile)
300000 reps @ 0.0248 msec ( 40400.0/sec): 500x500 tiled rectangle (17x15 tile)
1500000 trep @ 0.0247 msec ( 40500.0/sec): 500x500 tiled rectangle (17x15 tile)
200000 reps @ 0.0365 msec ( 27400.0/sec): 500x500 stippled rectangle (161x145 stipple)
200000 reps @ 0.0366 msec ( 27300.0/sec): 500x500 stippled rectangle (161x145 stipple)
200000 reps @ 0.0366 msec ( 27300.0/sec): 500x500 stippled rectangle (161x145 stipple)
200000 reps @ 0.0365 msec ( 27400.0/sec): 500x500 stippled rectangle (161x145 stipple)
200000 reps @ 0.0364 msec ( 27500.0/sec): 500x500 stippled rectangle (161x145 stipple)
1000000 trep @ 0.0365 msec ( 27400.0/sec): 500x500 stippled rectangle (161x145 stipple)
300000 reps @ 0.0245 msec ( 40800.0/sec): 500x500 opaque stippled rectangle (161x145 stipple)
300000 reps @ 0.0244 msec ( 40900.0/sec): 500x500 opaque stippled rectangle (161x145 stipple)
300000 reps @ 0.0245 msec ( 40900.0/sec): 500x500 opaque stippled rectangle (161x145 stipple)
300000 reps @ 0.0245 msec ( 40900.0/sec): 500x500 opaque stippled rectangle (161x145 stipple)
300000 reps @ 0.0245 msec ( 40900.0/sec): 500x500 opaque stippled rectangle (161x145 stipple)
1500000 trep @ 0.0245 msec ( 40900.0/sec): 500x500 opaque stippled rectangle (161x145 stipple)
300000 reps @ 0.0246 msec ( 40600.0/sec): 500x500 tiled rectangle (161x145 tile)
300000 reps @ 0.0246 msec ( 40600.0/sec): 500x500 tiled rectangle (161x145 tile)
300000 reps @ 0.0247 msec ( 40600.0/sec): 500x500 tiled rectangle (161x145 tile)
300000 reps @ 0.0246 msec ( 40600.0/sec): 500x500 tiled rectangle (161x145 tile)
300000 reps @ 0.0246 msec ( 40600.0/sec): 500x500 tiled rectangle (161x145 tile)
1500000 trep @ 0.0246 msec ( 40600.0/sec): 500x500 tiled rectangle (161x145 tile)
300000 reps @ 0.0248 msec ( 40300.0/sec): 500x500 tiled rectangle (216x208 tile)
300000 reps @ 0.0249 msec ( 40200.0/sec): 500x500 tiled rectangle (216x208 tile)
300000 reps @ 0.0248 msec ( 40300.0/sec): 500x500 tiled rectangle (216x208 tile)
300000 reps @ 0.0248 msec ( 40200.0/sec): 500x500 tiled rectangle (216x208 tile)
300000 reps @ 0.0248 msec ( 40300.0/sec): 500x500 tiled rectangle (216x208 tile)
1500000 trep @ 0.0248 msec ( 40300.0/sec): 500x500 tiled rectangle (216x208 tile)
30000000 reps @ 0.0003 msec (3970000.0/sec): 500-pixel line segment
30000000 reps @ 0.0003 msec (3980000.0/sec): 500-pixel line segment
30000000 reps @ 0.0003 msec (3970000.0/sec): 500-pixel line segment
30000000 reps @ 0.0003 msec (3980000.0/sec): 500-pixel line segment
30000000 reps @ 0.0003 msec (3980000.0/sec): 500-pixel line segment
150000000 trep @ 0.0003 msec (3980000.0/sec): 500-pixel line segment
200000000 reps @ 0.0000 msec (21800000.0/sec): 500-pixel horizontal line segment
200000000 reps @ 0.0000 msec (21800000.0/sec): 500-pixel horizontal line segment
200000000 reps @ 0.0000 msec (21800000.0/sec): 500-pixel horizontal line segment
200000000 reps @ 0.0000 msec (21800000.0/sec): 500-pixel horizontal line segment
200000000 reps @ 0.0000 msec (21800000.0/sec): 500-pixel horizontal line segment
1000000000 trep @ 0.0000 msec (21800000.0/sec): 500-pixel horizontal line segment
80000000 reps @ 0.0001 msec (15800000.0/sec): 500-pixel vertical line segment
80000000 reps @ 0.0001 msec (15800000.0/sec): 500-pixel vertical line segment
80000000 reps @ 0.0001 msec (15800000.0/sec): 500-pixel vertical line segment
80000000 reps @ 0.0001 msec (15800000.0/sec): 500-pixel vertical line segment
80000000 reps @ 0.0001 msec (15800000.0/sec): 500-pixel vertical line segment
400000000 trep @ 0.0001 msec (15800000.0/sec): 500-pixel vertical line segment
1000000 reps @ 0.0072 msec (138000.0/sec): 500x50 wide horizontal line segment
1000000 reps @ 0.0073 msec (137000.0/sec): 500x50 wide horizontal line segment
1000000 reps @ 0.0072 msec (138000.0/sec): 500x50 wide horizontal line segment
1000000 reps @ 0.0073 msec (138000.0/sec): 500x50 wide horizontal line segment
1000000 reps @ 0.0072 msec (138000.0/sec): 500x50 wide horizontal line segment
5000000 trep @ 0.0073 msec (138000.0/sec): 500x50 wide horizontal line segment
1000000 reps @ 0.0073 msec (137000.0/sec): 500x50 wide vertical line segment
1000000 reps @ 0.0073 msec (137000.0/sec): 500x50 wide vertical line segment
1000000 reps @ 0.0073 msec (137000.0/sec): 500x50 wide vertical line segment
1000000 reps @ 0.0073 msec (137000.0/sec): 500x50 wide vertical line segment
1000000 reps @ 0.0073 msec (137000.0/sec): 500x50 wide vertical line segment
5000000 trep @ 0.0073 msec (137000.0/sec): 500x50 wide vertical line segment
40000000 reps @ 0.0002 msec (6060000.0/sec): 500-pixel line
40000000 reps @ 0.0002 msec (6050000.0/sec): 500-pixel line
40000000 reps @ 0.0002 msec (6050000.0/sec): 500-pixel line
40000000 reps @ 0.0002 msec (6050000.0/sec): 500-pixel line
40000000 reps @ 0.0002 msec (6040000.0/sec): 500-pixel line
200000000 trep @ 0.0002 msec (6050000.0/sec): 500-pixel line
1000000 reps @ 0.0051 msec (196000.0/sec): 500x50 wide line
1000000 reps @ 0.0051 msec (196000.0/sec): 500x50 wide line
1000000 reps @ 0.0051 msec (196000.0/sec): 500x50 wide line
1000000 reps @ 0.0051 msec (197000.0/sec): 500x50 wide line
1000000 reps @ 0.0051 msec (197000.0/sec): 500x50 wide line
5000000 trep @ 0.0051 msec (196000.0/sec): 500x50 wide line
4000000 reps @ 0.0016 msec (606000.0/sec): 500x500 rectangle outline
4000000 reps @ 0.0017 msec (602000.0/sec): 500x500 rectangle outline
4000000 reps @ 0.0016 msec (608000.0/sec): 500x500 rectangle outline
4000000 reps @ 0.0017 msec (605000.0/sec): 500x500 rectangle outline
4000000 reps @ 0.0016 msec (608000.0/sec): 500x500 rectangle outline
20000000 trep @ 0.0017 msec (606000.0/sec): 500x500 rectangle outline
400000 reps @ 0.0132 msec ( 75700.0/sec): 500x500 wide rectangle outline
400000 reps @ 0.0132 msec ( 75600.0/sec): 500x500 wide rectangle outline
400000 reps @ 0.0132 msec ( 75700.0/sec): 500x500 wide rectangle outline
400000 reps @ 0.0132 msec ( 75700.0/sec): 500x500 wide rectangle outline
400000 reps @ 0.0132 msec ( 75800.0/sec): 500x500 wide rectangle outline
2000000 trep @ 0.0132 msec ( 75700.0/sec): 500x500 wide rectangle outline
2000000 reps @ 0.0029 msec (346000.0/sec): 500-pixel circle
2000000 reps @ 0.0029 msec (346000.0/sec): 500-pixel circle
2000000 reps @ 0.0029 msec (346000.0/sec): 500-pixel circle
2000000 reps @ 0.0029 msec (346000.0/sec): 500-pixel circle
2000000 reps @ 0.0029 msec (346000.0/sec): 500-pixel circle
10000000 trep @ 0.0029 msec (346000.0/sec): 500-pixel circle
500000 reps @ 0.0139 msec ( 72000.0/sec): 500-pixel wide circle
500000 reps @ 0.0139 msec ( 71700.0/sec): 500-pixel wide circle
500000 reps @ 0.0140 msec ( 71500.0/sec): 500-pixel wide circle
500000 reps @ 0.0139 msec ( 71900.0/sec): 500-pixel wide circle
500000 reps @ 0.0139 msec ( 72100.0/sec): 500-pixel wide circle
2500000 trep @ 0.0139 msec ( 71800.0/sec): 500-pixel wide circle
200000 reps @ 0.0265 msec ( 37700.0/sec): 500-pixel solid circle
200000 reps @ 0.0267 msec ( 37400.0/sec): 500-pixel solid circle
200000 reps @ 0.0265 msec ( 37700.0/sec): 500-pixel solid circle
200000 reps @ 0.0265 msec ( 37700.0/sec): 500-pixel solid circle
200000 reps @ 0.0267 msec ( 37500.0/sec): 500-pixel solid circle
1000000 trep @ 0.0266 msec ( 37600.0/sec): 500-pixel solid circle
3000000 reps @ 0.0023 msec (428000.0/sec): 500-pixel ellipse
3000000 reps @ 0.0023 msec (427000.0/sec): 500-pixel ellipse
3000000 reps @ 0.0023 msec (427000.0/sec): 500-pixel ellipse
3000000 reps @ 0.0023 msec (427000.0/sec): 500-pixel ellipse
3000000 reps @ 0.0023 msec (428000.0/sec): 500-pixel ellipse
15000000 trep @ 0.0023 msec (427000.0/sec): 500-pixel ellipse
400000 reps @ 0.0186 msec ( 53700.0/sec): 500-pixel wide ellipse
400000 reps @ 0.0186 msec ( 53800.0/sec): 500-pixel wide ellipse
400000 reps @ 0.0184 msec ( 54200.0/sec): 500-pixel wide ellipse
400000 reps @ 0.0185 msec ( 53900.0/sec): 500-pixel wide ellipse
400000 reps @ 0.0183 msec ( 54600.0/sec): 500-pixel wide ellipse
2000000 trep @ 0.0185 msec ( 54000.0/sec): 500-pixel wide ellipse
400000 reps @ 0.0134 msec ( 74500.0/sec): 500-pixel filled ellipse
400000 reps @ 0.0134 msec ( 74500.0/sec): 500-pixel filled ellipse
400000 reps @ 0.0134 msec ( 74500.0/sec): 500-pixel filled ellipse
400000 reps @ 0.0134 msec ( 74500.0/sec): 500-pixel filled ellipse
400000 reps @ 0.0134 msec ( 74500.0/sec): 500-pixel filled ellipse
2000000 trep @ 0.0134 msec ( 74500.0/sec): 500-pixel filled ellipse
600000 reps @ 0.0123 msec ( 81100.0/sec): Fill 300x300 trapezoid
600000 reps @ 0.0123 msec ( 81000.0/sec): Fill 300x300 trapezoid
600000 reps @ 0.0123 msec ( 81100.0/sec): Fill 300x300 trapezoid
600000 reps @ 0.0123 msec ( 81000.0/sec): Fill 300x300 trapezoid
600000 reps @ 0.0123 msec ( 81100.0/sec): Fill 300x300 trapezoid
3000000 trep @ 0.0123 msec ( 81100.0/sec): Fill 300x300 trapezoid
400000 reps @ 0.0231 msec ( 43200.0/sec): Fill 300x300 stippled trapezoid (8x8 stipple)
400000 reps @ 0.0228 msec ( 43800.0/sec): Fill 300x300 stippled trapezoid (8x8 stipple)
400000 reps @ 0.0229 msec ( 43800.0/sec): Fill 300x300 stippled trapezoid (8x8 stipple)
400000 reps @ 0.0229 msec ( 43600.0/sec): Fill 300x300 stippled trapezoid (8x8 stipple)
400000 reps @ 0.0231 msec ( 43200.0/sec): Fill 300x300 stippled trapezoid (8x8 stipple)
2000000 trep @ 0.0230 msec ( 43500.0/sec): Fill 300x300 stippled trapezoid (8x8 stipple)
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 opaque stippled trapezoid (8x8 stipple)
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 opaque stippled trapezoid (8x8 stipple)
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 opaque stippled trapezoid (8x8 stipple)
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 opaque stippled trapezoid (8x8 stipple)
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 opaque stippled trapezoid (8x8 stipple)
3000000 trep @ 0.0124 msec ( 80900.0/sec): Fill 300x300 opaque stippled trapezoid (8x8 stipple)
600000 reps @ 0.0123 msec ( 81000.0/sec): Fill 300x300 tiled trapezoid (4x4 tile)
600000 reps @ 0.0123 msec ( 81000.0/sec): Fill 300x300 tiled trapezoid (4x4 tile)
600000 reps @ 0.0123 msec ( 81100.0/sec): Fill 300x300 tiled trapezoid (4x4 tile)
600000 reps @ 0.0123 msec ( 81100.0/sec): Fill 300x300 tiled trapezoid (4x4 tile)
600000 reps @ 0.0123 msec ( 81100.0/sec): Fill 300x300 tiled trapezoid (4x4 tile)
3000000 trep @ 0.0123 msec ( 81000.0/sec): Fill 300x300 tiled trapezoid (4x4 tile)
400000 reps @ 0.0219 msec ( 45600.0/sec): Fill 300x300 stippled trapezoid (17x15 stipple)
400000 reps @ 0.0220 msec ( 45400.0/sec): Fill 300x300 stippled trapezoid (17x15 stipple)
400000 reps @ 0.0220 msec ( 45500.0/sec): Fill 300x300 stippled trapezoid (17x15 stipple)
400000 reps @ 0.0219 msec ( 45600.0/sec): Fill 300x300 stippled trapezoid (17x15 stipple)
400000 reps @ 0.0218 msec ( 45900.0/sec): Fill 300x300 stippled trapezoid (17x15 stipple)
2000000 trep @ 0.0219 msec ( 45600.0/sec): Fill 300x300 stippled trapezoid (17x15 stipple)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 opaque stippled trapezoid (17x15 stipple)
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 opaque stippled trapezoid (17x15 stipple)
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 opaque stippled trapezoid (17x15 stipple)
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 opaque stippled trapezoid (17x15 stipple)
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 opaque stippled trapezoid (17x15 stipple)
3000000 trep @ 0.0124 msec ( 80900.0/sec): Fill 300x300 opaque stippled trapezoid (17x15 stipple)
600000 reps @ 0.0123 msec ( 81100.0/sec): Fill 300x300 tiled trapezoid (17x15 tile)
600000 reps @ 0.0123 msec ( 81100.0/sec): Fill 300x300 tiled trapezoid (17x15 tile)
600000 reps @ 0.0123 msec ( 81100.0/sec): Fill 300x300 tiled trapezoid (17x15 tile)
600000 reps @ 0.0123 msec ( 81000.0/sec): Fill 300x300 tiled trapezoid (17x15 tile)
600000 reps @ 0.0123 msec ( 81100.0/sec): Fill 300x300 tiled trapezoid (17x15 tile)
3000000 trep @ 0.0123 msec ( 81100.0/sec): Fill 300x300 tiled trapezoid (17x15 tile)
400000 reps @ 0.0129 msec ( 77600.0/sec): Fill 300x300 stippled trapezoid (161x145 stipple)
400000 reps @ 0.0129 msec ( 77600.0/sec): Fill 300x300 stippled trapezoid (161x145 stipple)
400000 reps @ 0.0129 msec ( 77500.0/sec): Fill 300x300 stippled trapezoid (161x145 stipple)
400000 reps @ 0.0129 msec ( 77700.0/sec): Fill 300x300 stippled trapezoid (161x145 stipple)
400000 reps @ 0.0129 msec ( 77700.0/sec): Fill 300x300 stippled trapezoid (161x145 stipple)
2000000 trep @ 0.0129 msec ( 77600.0/sec): Fill 300x300 stippled trapezoid (161x145 stipple)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 opaque stippled trapezoid (161x145 stipple)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 opaque stippled trapezoid (161x145 stipple)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 opaque stippled trapezoid (161x145 stipple)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 opaque stippled trapezoid (161x145 stipple)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 opaque stippled trapezoid (161x145 stipple)
3000000 trep @ 0.0124 msec ( 80800.0/sec): Fill 300x300 opaque stippled trapezoid (161x145 stipple)
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 tiled trapezoid (161x145 tile)
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 tiled trapezoid (161x145 tile)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 tiled trapezoid (161x145 tile)
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 tiled trapezoid (161x145 tile)
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 tiled trapezoid (161x145 tile)
3000000 trep @ 0.0124 msec ( 80900.0/sec): Fill 300x300 tiled trapezoid (161x145 tile)
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 tiled trapezoid (216x208 tile)
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 tiled trapezoid (216x208 tile)
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 tiled trapezoid (216x208 tile)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 tiled trapezoid (216x208 tile)
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 tiled trapezoid (216x208 tile)
3000000 trep @ 0.0124 msec ( 80900.0/sec): Fill 300x300 tiled trapezoid (216x208 tile)
200000 reps @ 0.0243 msec ( 41200.0/sec): Fill 300x300 aa trap
200000 reps @ 0.0244 msec ( 40900.0/sec): Fill 300x300 aa trap
200000 reps @ 0.0247 msec ( 40500.0/sec): Fill 300x300 aa trap
200000 reps @ 0.0246 msec ( 40600.0/sec): Fill 300x300 aa trap
200000 reps @ 0.0244 msec ( 41000.0/sec): Fill 300x300 aa trap
1000000 trep @ 0.0245 msec ( 40900.0/sec): Fill 300x300 aa trap
300000 reps @ 0.0245 msec ( 40800.0/sec): Fill 300x300 aa trap with 4 bit alpha
300000 reps @ 0.0246 msec ( 40700.0/sec): Fill 300x300 aa trap with 4 bit alpha
300000 reps @ 0.0249 msec ( 40100.0/sec): Fill 300x300 aa trap with 4 bit alpha
300000 reps @ 0.0245 msec ( 40800.0/sec): Fill 300x300 aa trap with 4 bit alpha
300000 reps @ 0.0245 msec ( 40700.0/sec): Fill 300x300 aa trap with 4 bit alpha
1500000 trep @ 0.0246 msec ( 40600.0/sec): Fill 300x300 aa trap with 4 bit alpha
2000000 reps @ 0.0032 msec (314000.0/sec): Fill 300x300 aa trap with 1 bit alpha
2000000 reps @ 0.0032 msec (308000.0/sec): Fill 300x300 aa trap with 1 bit alpha
2000000 reps @ 0.0030 msec (335000.0/sec): Fill 300x300 aa trap with 1 bit alpha
2000000 reps @ 0.0029 msec (345000.0/sec): Fill 300x300 aa trap with 1 bit alpha
2000000 reps @ 0.0029 msec (341000.0/sec): Fill 300x300 aa trap with 1 bit alpha
10000000 trep @ 0.0030 msec (328000.0/sec): Fill 300x300 aa trap with 1 bit alpha
300000 reps @ 0.0214 msec ( 46600.0/sec): Fill 2x300 aa trap
300000 reps @ 0.0214 msec ( 46700.0/sec): Fill 2x300 aa trap
300000 reps @ 0.0214 msec ( 46800.0/sec): Fill 2x300 aa trap
300000 reps @ 0.0214 msec ( 46600.0/sec): Fill 2x300 aa trap
300000 reps @ 0.0215 msec ( 46600.0/sec): Fill 2x300 aa trap
1500000 trep @ 0.0214 msec ( 46700.0/sec): Fill 2x300 aa trap
20000 reps @ 0.2964 msec ( 3370.0/sec): Fill 300x300 aa trapezoid
20000 reps @ 0.2963 msec ( 3380.0/sec): Fill 300x300 aa trapezoid
20000 reps @ 0.2961 msec ( 3380.0/sec): Fill 300x300 aa trapezoid
20000 reps @ 0.2966 msec ( 3370.0/sec): Fill 300x300 aa trapezoid
20000 reps @ 0.2966 msec ( 3370.0/sec): Fill 300x300 aa trapezoid
100000 trep @ 0.2964 msec ( 3370.0/sec): Fill 300x300 aa trapezoid
300000 reps @ 0.0238 msec ( 42100.0/sec): Fill 300x300 aa pre-added trapezoid
300000 reps @ 0.0237 msec ( 42100.0/sec): Fill 300x300 aa pre-added trapezoid
300000 reps @ 0.0237 msec ( 42100.0/sec): Fill 300x300 aa pre-added trapezoid
300000 reps @ 0.0248 msec ( 40300.0/sec): Fill 300x300 aa pre-added trapezoid
300000 reps @ 0.0243 msec ( 41100.0/sec): Fill 300x300 aa pre-added trapezoid
1500000 trep @ 0.0241 msec ( 41500.0/sec): Fill 300x300 aa pre-added trapezoid
160000000 reps @ 0.0000 msec (31600000.0/sec): Char in 80-char line (6x13)
160000000 reps @ 0.0000 msec (31500000.0/sec): Char in 80-char line (6x13)
160000000 reps @ 0.0000 msec (31700000.0/sec): Char in 80-char line (6x13)
160000000 reps @ 0.0000 msec (31900000.0/sec): Char in 80-char line (6x13)
160000000 reps @ 0.0000 msec (32100000.0/sec): Char in 80-char line (6x13)
800000000 trep @ 0.0000 msec (31800000.0/sec): Char in 80-char line (6x13)
216000000 reps @ 0.0000 msec (29200000.0/sec): Char in 70-char line (8x13)
216000000 reps @ 0.0000 msec (29100000.0/sec): Char in 70-char line (8x13)
216000000 reps @ 0.0000 msec (29100000.0/sec): Char in 70-char line (8x13)
216000000 reps @ 0.0000 msec (29500000.0/sec): Char in 70-char line (8x13)
216000000 reps @ 0.0000 msec (29300000.0/sec): Char in 70-char line (8x13)
1080000000 trep @ 0.0000 msec (29200000.0/sec): Char in 70-char line (8x13)
180000000 reps @ 0.0000 msec (25400000.0/sec): Char in 60-char line (9x15)
180000000 reps @ 0.0000 msec (25100000.0/sec): Char in 60-char line (9x15)
180000000 reps @ 0.0000 msec (24800000.0/sec): Char in 60-char line (9x15)
180000000 reps @ 0.0000 msec (25400000.0/sec): Char in 60-char line (9x15)
180000000 reps @ 0.0000 msec (25300000.0/sec): Char in 60-char line (9x15)
900000000 trep @ 0.0000 msec (25200000.0/sec): Char in 60-char line (9x15)
120000000 reps @ 0.0001 msec (16500000.0/sec): Char16 in 40-char line (k14)
120000000 reps @ 0.0001 msec (16300000.0/sec): Char16 in 40-char line (k14)
120000000 reps @ 0.0001 msec (16600000.0/sec): Char16 in 40-char line (k14)
120000000 reps @ 0.0001 msec (16600000.0/sec): Char16 in 40-char line (k14)
120000000 reps @ 0.0001 msec (16200000.0/sec): Char16 in 40-char line (k14)
600000000 trep @ 0.0001 msec (16400000.0/sec): Char16 in 40-char line (k14)
46000000 reps @ 0.0001 msec (7300000.0/sec): Char16 in 23-char line (k24)
46000000 reps @ 0.0001 msec (7310000.0/sec): Char16 in 23-char line (k24)
46000000 reps @ 0.0001 msec (7330000.0/sec): Char16 in 23-char line (k24)
46000000 reps @ 0.0001 msec (7340000.0/sec): Char16 in 23-char line (k24)
46000000 reps @ 0.0001 msec (7390000.0/sec): Char16 in 23-char line (k24)
230000000 trep @ 0.0001 msec (7330000.0/sec): Char16 in 23-char line (k24)
Could not load font '-adobe-times-medium-r-normal--10-100-75-75-p-54-iso8859-1', benchmark omitted
Could not load font '-adobe-times-medium-r-normal--24-240-75-75-p-124-iso8859-1', benchmark omitted
Could not load font '-adobe-times-medium-r-normal--10-100-75-75-p-54-iso8859-1', benchmark omitted
16800000 reps @ 0.0003 msec (3330000.0/sec): Char16 in 7/14/7 line (k14, k24)
16800000 reps @ 0.0003 msec (3360000.0/sec): Char16 in 7/14/7 line (k14, k24)
16800000 reps @ 0.0003 msec (3280000.0/sec): Char16 in 7/14/7 line (k14, k24)
16800000 reps @ 0.0003 msec (3280000.0/sec): Char16 in 7/14/7 line (k14, k24)
16800000 reps @ 0.0003 msec (3310000.0/sec): Char16 in 7/14/7 line (k14, k24)
84000000 trep @ 0.0003 msec (3310000.0/sec): Char16 in 7/14/7 line (k14, k24)
240000000 reps @ 0.0000 msec (32200000.0/sec): Char in 80-char image line (6x13)
240000000 reps @ 0.0000 msec (32300000.0/sec): Char in 80-char image line (6x13)
240000000 reps @ 0.0000 msec (32200000.0/sec): Char in 80-char image line (6x13)
240000000 reps @ 0.0000 msec (32100000.0/sec): Char in 80-char image line (6x13)
240000000 reps @ 0.0000 msec (32300000.0/sec): Char in 80-char image line (6x13)
1200000000 trep @ 0.0000 msec (32200000.0/sec): Char in 80-char image line (6x13)
216000000 reps @ 0.0000 msec (29100000.0/sec): Char in 70-char image line (8x13)
216000000 reps @ 0.0000 msec (28700000.0/sec): Char in 70-char image line (8x13)
216000000 reps @ 0.0000 msec (28800000.0/sec): Char in 70-char image line (8x13)
216000000 reps @ 0.0000 msec (28700000.0/sec): Char in 70-char image line (8x13)
216000000 reps @ 0.0000 msec (29200000.0/sec): Char in 70-char image line (8x13)
1080000000 trep @ 0.0000 msec (28900000.0/sec): Char in 70-char image line (8x13)
180000000 reps @ 0.0000 msec (25400000.0/sec): Char in 60-char image line (9x15)
180000000 reps @ 0.0000 msec (25400000.0/sec): Char in 60-char image line (9x15)
180000000 reps @ 0.0000 msec (25100000.0/sec): Char in 60-char image line (9x15)
180000000 reps @ 0.0000 msec (25400000.0/sec): Char in 60-char image line (9x15)
180000000 reps @ 0.0000 msec (25000000.0/sec): Char in 60-char image line (9x15)
900000000 trep @ 0.0000 msec (25300000.0/sec): Char in 60-char image line (9x15)
120000000 reps @ 0.0001 msec (16700000.0/sec): Char16 in 40-char image line (k14)
120000000 reps @ 0.0001 msec (16800000.0/sec): Char16 in 40-char image line (k14)
120000000 reps @ 0.0001 msec (17000000.0/sec): Char16 in 40-char image line (k14)
120000000 reps @ 0.0001 msec (16900000.0/sec): Char16 in 40-char image line (k14)
120000000 reps @ 0.0001 msec (17000000.0/sec): Char16 in 40-char image line (k14)
600000000 trep @ 0.0001 msec (16900000.0/sec): Char16 in 40-char image line (k14)
69000000 reps @ 0.0001 msec (10600000.0/sec): Char16 in 23-char image line (k24)
69000000 reps @ 0.0001 msec (10600000.0/sec): Char16 in 23-char image line (k24)
69000000 reps @ 0.0001 msec (10600000.0/sec): Char16 in 23-char image line (k24)
69000000 reps @ 0.0001 msec (10600000.0/sec): Char16 in 23-char image line (k24)
69000000 reps @ 0.0001 msec (10600000.0/sec): Char16 in 23-char image line (k24)
345000000 trep @ 0.0001 msec (10600000.0/sec): Char16 in 23-char image line (k24)
Could not load font '-adobe-times-medium-r-normal--10-100-75-75-p-54-iso8859-1', benchmark omitted
Could not load font '-adobe-times-medium-r-normal--24-240-75-75-p-124-iso8859-1', benchmark omitted
160000000 reps @ 0.0001 msec (17200000.0/sec): Char in 80-char aa line (Charter 10)
160000000 reps @ 0.0001 msec (17300000.0/sec): Char in 80-char aa line (Charter 10)
160000000 reps @ 0.0001 msec (17500000.0/sec): Char in 80-char aa line (Charter 10)
160000000 reps @ 0.0001 msec (17500000.0/sec): Char in 80-char aa line (Charter 10)
160000000 reps @ 0.0001 msec (17600000.0/sec): Char in 80-char aa line (Charter 10)
800000000 trep @ 0.0001 msec (17400000.0/sec): Char in 80-char aa line (Charter 10)
64000000 reps @ 0.0001 msec (8080000.0/sec): Char in 30-char aa line (Charter 24)
64000000 reps @ 0.0001 msec (8090000.0/sec): Char in 30-char aa line (Charter 24)
64000000 reps @ 0.0001 msec (7920000.0/sec): Char in 30-char aa line (Charter 24)
64000000 reps @ 0.0001 msec (8020000.0/sec): Char in 30-char aa line (Charter 24)
64000000 reps @ 0.0001 msec (8110000.0/sec): Char in 30-char aa line (Charter 24)
320000000 trep @ 0.0001 msec (8050000.0/sec): Char in 30-char aa line (Charter 24)
160000000 reps @ 0.0001 msec (17300000.0/sec): Char in 80-char aa line (Courier 12)
160000000 reps @ 0.0001 msec (17200000.0/sec): Char in 80-char aa line (Courier 12)
160000000 reps @ 0.0001 msec (16900000.0/sec): Char in 80-char aa line (Courier 12)
160000000 reps @ 0.0001 msec (17000000.0/sec): Char in 80-char aa line (Courier 12)
160000000 reps @ 0.0001 msec (17200000.0/sec): Char in 80-char aa line (Courier 12)
800000000 trep @ 0.0001 msec (17100000.0/sec): Char in 80-char aa line (Courier 12)
160000000 reps @ 0.0001 msec (17500000.0/sec): Char in 80-char a line (Charter 10)
160000000 reps @ 0.0001 msec (17400000.0/sec): Char in 80-char a line (Charter 10)
160000000 reps @ 0.0001 msec (17600000.0/sec): Char in 80-char a line (Charter 10)
160000000 reps @ 0.0001 msec (17400000.0/sec): Char in 80-char a line (Charter 10)
160000000 reps @ 0.0001 msec (17200000.0/sec): Char in 80-char a line (Charter 10)
800000000 trep @ 0.0001 msec (17400000.0/sec): Char in 80-char a line (Charter 10)
64000000 reps @ 0.0001 msec (8140000.0/sec): Char in 30-char a line (Charter 24)
64000000 reps @ 0.0001 msec (8080000.0/sec): Char in 30-char a line (Charter 24)
64000000 reps @ 0.0001 msec (8090000.0/sec): Char in 30-char a line (Charter 24)
64000000 reps @ 0.0001 msec (8070000.0/sec): Char in 30-char a line (Charter 24)
64000000 reps @ 0.0001 msec (8130000.0/sec): Char in 30-char a line (Charter 24)
320000000 trep @ 0.0001 msec (8100000.0/sec): Char in 30-char a line (Charter 24)
160000000 reps @ 0.0001 msec (17700000.0/sec): Char in 80-char a line (Courier 12)
160000000 reps @ 0.0001 msec (17500000.0/sec): Char in 80-char a line (Courier 12)
160000000 reps @ 0.0001 msec (17500000.0/sec): Char in 80-char a line (Courier 12)
160000000 reps @ 0.0001 msec (17600000.0/sec): Char in 80-char a line (Courier 12)
160000000 reps @ 0.0001 msec (17300000.0/sec): Char in 80-char a line (Courier 12)
800000000 trep @ 0.0001 msec (17500000.0/sec): Char in 80-char a line (Courier 12)
160000000 reps @ 0.0000 msec (23600000.0/sec): Char in 80-char rgb line (Charter 10)
160000000 reps @ 0.0000 msec (24700000.0/sec): Char in 80-char rgb line (Charter 10)
160000000 reps @ 0.0000 msec (24300000.0/sec): Char in 80-char rgb line (Charter 10)
160000000 reps @ 0.0000 msec (24200000.0/sec): Char in 80-char rgb line (Charter 10)
160000000 reps @ 0.0000 msec (24200000.0/sec): Char in 80-char rgb line (Charter 10)
800000000 trep @ 0.0000 msec (24200000.0/sec): Char in 80-char rgb line (Charter 10)
64000000 reps @ 0.0001 msec (11600000.0/sec): Char in 30-char rgb line (Charter 24)
64000000 reps @ 0.0001 msec (11600000.0/sec): Char in 30-char rgb line (Charter 24)
64000000 reps @ 0.0001 msec (11700000.0/sec): Char in 30-char rgb line (Charter 24)
64000000 reps @ 0.0001 msec (11600000.0/sec): Char in 30-char rgb line (Charter 24)
64000000 reps @ 0.0001 msec (11700000.0/sec): Char in 30-char rgb line (Charter 24)
320000000 trep @ 0.0001 msec (11700000.0/sec): Char in 30-char rgb line (Charter 24)
160000000 reps @ 0.0000 msec (23300000.0/sec): Char in 80-char rgb line (Courier 12)
160000000 reps @ 0.0000 msec (23500000.0/sec): Char in 80-char rgb line (Courier 12)
160000000 reps @ 0.0000 msec (23700000.0/sec): Char in 80-char rgb line (Courier 12)
160000000 reps @ 0.0000 msec (23300000.0/sec): Char in 80-char rgb line (Courier 12)
160000000 reps @ 0.0000 msec (23400000.0/sec): Char in 80-char rgb line (Courier 12)
800000000 trep @ 0.0000 msec (23400000.0/sec): Char in 80-char rgb line (Courier 12)
Could not load font 'charter:antialias=true:render=false:rgba=0:pixelsize=10', benchmark omitted
Could not load font 'charter:antialias=true:render=false:rgba=0:pixelsize=24', benchmark omitted
Could not load font 'courier:antialias=true:render=false:rgba=0:pixelsize=12', benchmark omitted
Could not load font 'charter:antialias=false:render=false:rgba=0:pixelsize=10', benchmark omitted
Could not load font 'charter:antialias=false:render=false:rgba=0:pixelsize=24', benchmark omitted
Could not load font 'courier:antialias=false:render=false:rgba=0:pixelsize=12', benchmark omitted
Could not load font 'charter:antialias=true:render=false:rgba=rgb:pixelsize=10', benchmark omitted
Could not load font 'charter:antialias=true:render=false:rgba=rgb:pixelsize=24', benchmark omitted
Could not load font 'courier:antialias=true:render=false:rgba=rgb:pixelsize=12', benchmark omitted
60000 reps @ 0.0887 msec ( 11300.0/sec): Scroll 500x500 pixels
60000 reps @ 0.0881 msec ( 11400.0/sec): Scroll 500x500 pixels
60000 reps @ 0.0867 msec ( 11500.0/sec): Scroll 500x500 pixels
60000 reps @ 0.0862 msec ( 11600.0/sec): Scroll 500x500 pixels
60000 reps @ 0.0862 msec ( 11600.0/sec): Scroll 500x500 pixels
300000 trep @ 0.0872 msec ( 11500.0/sec): Scroll 500x500 pixels
80000 reps @ 0.0831 msec ( 12000.0/sec): Copy 500x500 from window to window
80000 reps @ 0.0831 msec ( 12000.0/sec): Copy 500x500 from window to window
80000 reps @ 0.0830 msec ( 12000.0/sec): Copy 500x500 from window to window
80000 reps @ 0.0829 msec ( 12100.0/sec): Copy 500x500 from window to window
80000 reps @ 0.0829 msec ( 12100.0/sec): Copy 500x500 from window to window
400000 trep @ 0.0830 msec ( 12000.0/sec): Copy 500x500 from window to window
200000 reps @ 0.0262 msec ( 38200.0/sec): Copy 500x500 from pixmap to window
200000 reps @ 0.0262 msec ( 38200.0/sec): Copy 500x500 from pixmap to window
200000 reps @ 0.0262 msec ( 38200.0/sec): Copy 500x500 from pixmap to window
200000 reps @ 0.0262 msec ( 38100.0/sec): Copy 500x500 from pixmap to window
200000 reps @ 0.0262 msec ( 38100.0/sec): Copy 500x500 from pixmap to window
1000000 trep @ 0.0262 msec ( 38200.0/sec): Copy 500x500 from pixmap to window
160000 reps @ 0.0370 msec ( 27000.0/sec): Copy 500x500 from window to pixmap
160000 reps @ 0.0370 msec ( 27000.0/sec): Copy 500x500 from window to pixmap
160000 reps @ 0.0369 msec ( 27100.0/sec): Copy 500x500 from window to pixmap
160000 reps @ 0.0369 msec ( 27100.0/sec): Copy 500x500 from window to pixmap
160000 reps @ 0.0369 msec ( 27100.0/sec): Copy 500x500 from window to pixmap
800000 trep @ 0.0369 msec ( 27100.0/sec): Copy 500x500 from window to pixmap
80000 reps @ 0.0633 msec ( 15800.0/sec): Copy 500x500 from pixmap to pixmap
80000 reps @ 0.0634 msec ( 15800.0/sec): Copy 500x500 from pixmap to pixmap
80000 reps @ 0.0638 msec ( 15700.0/sec): Copy 500x500 from pixmap to pixmap
80000 reps @ 0.0649 msec ( 15400.0/sec): Copy 500x500 from pixmap to pixmap
80000 reps @ 0.0647 msec ( 15500.0/sec): Copy 500x500 from pixmap to pixmap
400000 trep @ 0.0640 msec ( 15600.0/sec): Copy 500x500 from pixmap to pixmap
12000 reps @ 0.3913 msec ( 2560.0/sec): Copy 500x500 1-bit deep plane
12000 reps @ 0.3780 msec ( 2650.0/sec): Copy 500x500 1-bit deep plane
12000 reps @ 0.3798 msec ( 2630.0/sec): Copy 500x500 1-bit deep plane
12000 reps @ 0.3784 msec ( 2640.0/sec): Copy 500x500 1-bit deep plane
12000 reps @ 0.3774 msec ( 2650.0/sec): Copy 500x500 1-bit deep plane
60000 trep @ 0.3810 msec ( 2620.0/sec): Copy 500x500 1-bit deep plane
200000 reps @ 0.0260 msec ( 38500.0/sec): Copy 500x500 n-bit deep plane
200000 reps @ 0.0260 msec ( 38500.0/sec): Copy 500x500 n-bit deep plane
200000 reps @ 0.0260 msec ( 38500.0/sec): Copy 500x500 n-bit deep plane
200000 reps @ 0.0260 msec ( 38400.0/sec): Copy 500x500 n-bit deep plane
200000 reps @ 0.0260 msec ( 38500.0/sec): Copy 500x500 n-bit deep plane
1000000 trep @ 0.0260 msec ( 38500.0/sec): Copy 500x500 n-bit deep plane
12000 reps @ 0.5847 msec ( 1710.0/sec): PutImage 500x500 square
12000 reps @ 0.5787 msec ( 1730.0/sec): PutImage 500x500 square
12000 reps @ 0.5832 msec ( 1710.0/sec): PutImage 500x500 square
12000 reps @ 0.5956 msec ( 1680.0/sec): PutImage 500x500 square
12000 reps @ 0.5961 msec ( 1680.0/sec): PutImage 500x500 square
60000 trep @ 0.5877 msec ( 1700.0/sec): PutImage 500x500 square
800 reps @ 9.3360 msec ( 107.0/sec): PutImage XY 500x500 square
800 reps @ 9.3481 msec ( 107.0/sec): PutImage XY 500x500 square
800 reps @ 9.2877 msec ( 108.0/sec): PutImage XY 500x500 square
800 reps @ 9.3247 msec ( 107.0/sec): PutImage XY 500x500 square
800 reps @ 9.2843 msec ( 108.0/sec): PutImage XY 500x500 square
4000 trep @ 9.3161 msec ( 107.0/sec): PutImage XY 500x500 square
32000 reps @ 0.1603 msec ( 6240.0/sec): ShmPutImage 500x500 square
32000 reps @ 0.1609 msec ( 6220.0/sec): ShmPutImage 500x500 square
32000 reps @ 0.1602 msec ( 6240.0/sec): ShmPutImage 500x500 square
32000 reps @ 0.1605 msec ( 6230.0/sec): ShmPutImage 500x500 square
32000 reps @ 0.1614 msec ( 6190.0/sec): ShmPutImage 500x500 square
160000 trep @ 0.1606 msec ( 6220.0/sec): ShmPutImage 500x500 square
800 reps @ 7.3666 msec ( 136.0/sec): ShmPutImage XY 500x500 square
800 reps @ 7.3732 msec ( 136.0/sec): ShmPutImage XY 500x500 square
800 reps @ 7.3740 msec ( 136.0/sec): ShmPutImage XY 500x500 square
800 reps @ 7.3916 msec ( 135.0/sec): ShmPutImage XY 500x500 square
800 reps @ 7.4018 msec ( 135.0/sec): ShmPutImage XY 500x500 square
4000 trep @ 7.3814 msec ( 135.0/sec): ShmPutImage XY 500x500 square
80000 reps @ 0.0861 msec ( 11600.0/sec): ShmGetImage 500x500 square
80000 reps @ 0.0857 msec ( 11700.0/sec): ShmGetImage 500x500 square
80000 reps @ 0.0883 msec ( 11300.0/sec): ShmGetImage 500x500 square
80000 reps @ 0.0861 msec ( 11600.0/sec): ShmGetImage 500x500 square
80000 reps @ 0.0880 msec ( 11400.0/sec): ShmGetImage 500x500 square
400000 trep @ 0.0868 msec ( 11500.0/sec): ShmGetImage 500x500 square
320 reps @ 17.2745 msec ( 57.9/sec): ShmGetImage XY 500x500 square
320 reps @ 17.4005 msec ( 57.5/sec): ShmGetImage XY 500x500 square
320 reps @ 17.4432 msec ( 57.3/sec): ShmGetImage XY 500x500 square
320 reps @ 17.2486 msec ( 58.0/sec): ShmGetImage XY 500x500 square
320 reps @ 17.4224 msec ( 57.4/sec): ShmGetImage XY 500x500 square
1600 trep @ 17.3578 msec ( 57.6/sec): ShmGetImage XY 500x500 square
12000 reps @ 0.5191 msec ( 1930.0/sec): GetImage 500x500 square
12000 reps @ 0.5169 msec ( 1930.0/sec): GetImage 500x500 square
12000 reps @ 0.5189 msec ( 1930.0/sec): GetImage 500x500 square
12000 reps @ 0.4890 msec ( 2040.0/sec): GetImage 500x500 square
12000 reps @ 0.5238 msec ( 1910.0/sec): GetImage 500x500 square
60000 trep @ 0.5136 msec ( 1950.0/sec): GetImage 500x500 square
280 reps @ 16.6968 msec ( 59.9/sec): GetImage XY 500x500 square
280 reps @ 16.9655 msec ( 58.9/sec): GetImage XY 500x500 square
280 reps @ 17.0177 msec ( 58.8/sec): GetImage XY 500x500 square
280 reps @ 17.0088 msec ( 58.8/sec): GetImage XY 500x500 square
280 reps @ 17.0839 msec ( 58.5/sec): GetImage XY 500x500 square
1400 trep @ 16.9546 msec ( 59.0/sec): GetImage XY 500x500 square
80000 reps @ 0.0858 msec ( 11700.0/sec): Composite 500x500 from window to window
80000 reps @ 0.0845 msec ( 11800.0/sec): Composite 500x500 from window to window
80000 reps @ 0.0837 msec ( 11900.0/sec): Composite 500x500 from window to window
80000 reps @ 0.0836 msec ( 12000.0/sec): Composite 500x500 from window to window
80000 reps @ 0.0833 msec ( 12000.0/sec): Composite 500x500 from window to window
400000 trep @ 0.0842 msec ( 11900.0/sec): Composite 500x500 from window to window
200000 reps @ 0.0262 msec ( 38100.0/sec): Composite 500x500 from pixmap to window
200000 reps @ 0.0262 msec ( 38100.0/sec): Composite 500x500 from pixmap to window
200000 reps @ 0.0262 msec ( 38200.0/sec): Composite 500x500 from pixmap to window
200000 reps @ 0.0262 msec ( 38100.0/sec): Composite 500x500 from pixmap to window
200000 reps @ 0.0262 msec ( 38100.0/sec): Composite 500x500 from pixmap to window
1000000 trep @ 0.0262 msec ( 38100.0/sec): Composite 500x500 from pixmap to window
200000 reps @ 0.0259 msec ( 38600.0/sec): Scale 250x250 from pixmap to 500x500 window
200000 reps @ 0.0258 msec ( 38700.0/sec): Scale 250x250 from pixmap to 500x500 window
200000 reps @ 0.0259 msec ( 38600.0/sec): Scale 250x250 from pixmap to 500x500 window
200000 reps @ 0.0259 msec ( 38700.0/sec): Scale 250x250 from pixmap to 500x500 window
200000 reps @ 0.0259 msec ( 38700.0/sec): Scale 250x250 from pixmap to 500x500 window
1000000 trep @ 0.0259 msec ( 38700.0/sec): Scale 250x250 from pixmap to 500x500 window
800000 reps @ 0.0069 msec (145000.0/sec): Scale 500x500 from pixmap to 250x250 window
800000 reps @ 0.0069 msec (145000.0/sec): Scale 500x500 from pixmap to 250x250 window
800000 reps @ 0.0069 msec (145000.0/sec): Scale 500x500 from pixmap to 250x250 window
800000 reps @ 0.0069 msec (145000.0/sec): Scale 500x500 from pixmap to 250x250 window
800000 reps @ 0.0069 msec (145000.0/sec): Scale 500x500 from pixmap to 250x250 window
4000000 trep @ 0.0069 msec (145000.0/sec): Scale 500x500 from pixmap to 250x250 window
600000000 reps @ 0.0000 msec (101000000.0/sec): X protocol NoOperation
600000000 reps @ 0.0000 msec (102000000.0/sec): X protocol NoOperation
600000000 reps @ 0.0000 msec (105000000.0/sec): X protocol NoOperation
600000000 reps @ 0.0000 msec (101000000.0/sec): X protocol NoOperation
600000000 reps @ 0.0000 msec (102000000.0/sec): X protocol NoOperation
3000000000 trep @ 0.0000 msec (102000000.0/sec): X protocol NoOperation
200000 reps @ 0.0393 msec ( 25400.0/sec): QueryPointer
200000 reps @ 0.0391 msec ( 25600.0/sec): QueryPointer
200000 reps @ 0.0360 msec ( 27800.0/sec): QueryPointer
200000 reps @ 0.0357 msec ( 28000.0/sec): QueryPointer
200000 reps @ 0.0393 msec ( 25500.0/sec): QueryPointer
1000000 trep @ 0.0379 msec ( 26400.0/sec): QueryPointer
200000 reps @ 0.0450 msec ( 22200.0/sec): GetProperty
200000 reps @ 0.0458 msec ( 21800.0/sec): GetProperty
200000 reps @ 0.0437 msec ( 22900.0/sec): GetProperty
200000 reps @ 0.0440 msec ( 22700.0/sec): GetProperty
200000 reps @ 0.0413 msec ( 24200.0/sec): GetProperty
1000000 trep @ 0.0440 msec ( 22700.0/sec): GetProperty
3200000 reps @ 0.0016 msec (630000.0/sec): Change graphics context
3200000 reps @ 0.0016 msec (625000.0/sec): Change graphics context
3200000 reps @ 0.0016 msec (617000.0/sec): Change graphics context
3200000 reps @ 0.0016 msec (617000.0/sec): Change graphics context
3200000 reps @ 0.0017 msec (603000.0/sec): Change graphics context
16000000 trep @ 0.0016 msec (618000.0/sec): Change graphics context
2400 reps @ 0.0026 msec (391000.0/sec): Create and map subwindows (4 kids)
2400 reps @ 0.0046 msec (219000.0/sec): Create and map subwindows (4 kids)
2400 reps @ 0.0048 msec (207000.0/sec): Create and map subwindows (4 kids)
2400 reps @ 0.0050 msec (198000.0/sec): Create and map subwindows (4 kids)
2400 reps @ 0.0049 msec (203000.0/sec): Create and map subwindows (4 kids)
12000 trep @ 0.0044 msec (228000.0/sec): Create and map subwindows (4 kids)
2400 reps @ 0.0032 msec (309000.0/sec): Create and map subwindows (16 kids)
2400 reps @ 0.0054 msec (186000.0/sec): Create and map subwindows (16 kids)
2400 reps @ 0.0054 msec (184000.0/sec): Create and map subwindows (16 kids)
2400 reps @ 0.0050 msec (198000.0/sec): Create and map subwindows (16 kids)
2400 reps @ 0.0053 msec (190000.0/sec): Create and map subwindows (16 kids)
12000 trep @ 0.0049 msec (205000.0/sec): Create and map subwindows (16 kids)
2500 reps @ 0.0041 msec (243000.0/sec): Create and map subwindows (25 kids)
2500 reps @ 0.0039 msec (259000.0/sec): Create and map subwindows (25 kids)
2500 reps @ 0.0063 msec (159000.0/sec): Create and map subwindows (25 kids)
2500 reps @ 0.0052 msec (191000.0/sec): Create and map subwindows (25 kids)
2500 reps @ 0.0053 msec (187000.0/sec): Create and map subwindows (25 kids)
12500 trep @ 0.0050 msec (201000.0/sec): Create and map subwindows (25 kids)
2500 reps @ 0.0053 msec (188000.0/sec): Create and map subwindows (50 kids)
2500 reps @ 0.0051 msec (194000.0/sec): Create and map subwindows (50 kids)
2500 reps @ 0.0060 msec (166000.0/sec): Create and map subwindows (50 kids)
2500 reps @ 0.0078 msec (128000.0/sec): Create and map subwindows (50 kids)
2500 reps @ 0.0057 msec (176000.0/sec): Create and map subwindows (50 kids)
12500 trep @ 0.0060 msec (167000.0/sec): Create and map subwindows (50 kids)
2400 reps @ 0.0050 msec (200000.0/sec): Create and map subwindows (75 kids)
2400 reps @ 0.0056 msec (178000.0/sec): Create and map subwindows (75 kids)
2400 reps @ 0.0055 msec (182000.0/sec): Create and map subwindows (75 kids)
2400 reps @ 0.0055 msec (183000.0/sec): Create and map subwindows (75 kids)
2400 reps @ 0.0056 msec (180000.0/sec): Create and map subwindows (75 kids)
12000 trep @ 0.0054 msec (184000.0/sec): Create and map subwindows (75 kids)
2400 reps @ 0.0049 msec (203000.0/sec): Create and map subwindows (100 kids)
2400 reps @ 0.0055 msec (180000.0/sec): Create and map subwindows (100 kids)
2400 reps @ 0.0055 msec (181000.0/sec): Create and map subwindows (100 kids)
2400 reps @ 0.0056 msec (180000.0/sec): Create and map subwindows (100 kids)
2400 reps @ 0.0056 msec (179000.0/sec): Create and map subwindows (100 kids)
12000 trep @ 0.0054 msec (184000.0/sec): Create and map subwindows (100 kids)
2400 reps @ 0.0069 msec (145000.0/sec): Create and map subwindows (200 kids)
2400 reps @ 0.0037 msec (270000.0/sec): Create and map subwindows (200 kids)
2400 reps @ 0.0068 msec (148000.0/sec): Create and map subwindows (200 kids)
2400 reps @ 0.0082 msec (123000.0/sec): Create and map subwindows (200 kids)
2400 reps @ 0.0034 msec (297000.0/sec): Create and map subwindows (200 kids)
12000 trep @ 0.0058 msec (173000.0/sec): Create and map subwindows (200 kids)
2400 reps @ 0.0004 msec (2380000.0/sec): Create unmapped window (4 kids)
2400 reps @ 0.0014 msec (702000.0/sec): Create unmapped window (4 kids)
2400 reps @ 0.0012 msec (806000.0/sec): Create unmapped window (4 kids)
2400 reps @ 0.0013 msec (751000.0/sec): Create unmapped window (4 kids)
2400 reps @ 0.0014 msec (711000.0/sec): Create unmapped window (4 kids)
12000 trep @ 0.0012 msec (858000.0/sec): Create unmapped window (4 kids)
2400 reps @ 0.0013 msec (796000.0/sec): Create unmapped window (16 kids)
2400 reps @ 0.0013 msec (765000.0/sec): Create unmapped window (16 kids)
2400 reps @ 0.0013 msec (791000.0/sec): Create unmapped window (16 kids)
2400 reps @ 0.0013 msec (795000.0/sec): Create unmapped window (16 kids)
2400 reps @ 0.0013 msec (769000.0/sec): Create unmapped window (16 kids)
12000 trep @ 0.0013 msec (783000.0/sec): Create unmapped window (16 kids)
2500 reps @ 0.0008 msec (1250000.0/sec): Create unmapped window (25 kids)
2500 reps @ 0.0012 msec (834000.0/sec): Create unmapped window (25 kids)
2500 reps @ 0.0013 msec (781000.0/sec): Create unmapped window (25 kids)
2500 reps @ 0.0014 msec (690000.0/sec): Create unmapped window (25 kids)
2500 reps @ 0.0014 msec (721000.0/sec): Create unmapped window (25 kids)
12500 trep @ 0.0012 msec (817000.0/sec): Create unmapped window (25 kids)
2500 reps @ 0.0010 msec (1020000.0/sec): Create unmapped window (50 kids)
2500 reps @ 0.0013 msec (765000.0/sec): Create unmapped window (50 kids)
2500 reps @ 0.0012 msec (833000.0/sec): Create unmapped window (50 kids)
2500 reps @ 0.0015 msec (688000.0/sec): Create unmapped window (50 kids)
2500 reps @ 0.0014 msec (728000.0/sec): Create unmapped window (50 kids)
12500 trep @ 0.0013 msec (791000.0/sec): Create unmapped window (50 kids)
2400 reps @ 0.0013 msec (786000.0/sec): Create unmapped window (75 kids)
2400 reps @ 0.0014 msec (711000.0/sec): Create unmapped window (75 kids)
2400 reps @ 0.0014 msec (709000.0/sec): Create unmapped window (75 kids)
2400 reps @ 0.0016 msec (624000.0/sec): Create unmapped window (75 kids)
2400 reps @ 0.0014 msec (704000.0/sec): Create unmapped window (75 kids)
12000 trep @ 0.0014 msec (703000.0/sec): Create unmapped window (75 kids)
2400 reps @ 0.0015 msec (687000.0/sec): Create unmapped window (100 kids)
2400 reps @ 0.0014 msec (712000.0/sec): Create unmapped window (100 kids)
2400 reps @ 0.0014 msec (739000.0/sec): Create unmapped window (100 kids)
2400 reps @ 0.0016 msec (633000.0/sec): Create unmapped window (100 kids)
2400 reps @ 0.0018 msec (543000.0/sec): Create unmapped window (100 kids)
12000 trep @ 0.0015 msec (655000.0/sec): Create unmapped window (100 kids)
2400 reps @ 0.0012 msec (855000.0/sec): Create unmapped window (200 kids)
2400 reps @ 0.0014 msec (693000.0/sec): Create unmapped window (200 kids)
2400 reps @ 0.0011 msec (901000.0/sec): Create unmapped window (200 kids)
2400 reps @ 0.0015 msec (655000.0/sec): Create unmapped window (200 kids)
2400 reps @ 0.0014 msec (701000.0/sec): Create unmapped window (200 kids)
12000 trep @ 0.0013 msec (749000.0/sec): Create unmapped window (200 kids)
2400 reps @ 0.0053 msec (189000.0/sec): Map window via parent (4 kids)
2400 reps @ 0.0058 msec (173000.0/sec): Map window via parent (4 kids)
2400 reps @ 0.0048 msec (209000.0/sec): Map window via parent (4 kids)
2400 reps @ 0.0053 msec (189000.0/sec): Map window via parent (4 kids)
2400 reps @ 0.0052 msec (191000.0/sec): Map window via parent (4 kids)
12000 trep @ 0.0053 msec (190000.0/sec): Map window via parent (4 kids)
2400 reps @ 0.0047 msec (211000.0/sec): Map window via parent (16 kids)
2400 reps @ 0.0053 msec (188000.0/sec): Map window via parent (16 kids)
2400 reps @ 0.0056 msec (179000.0/sec): Map window via parent (16 kids)
2400 reps @ 0.0075 msec (133000.0/sec): Map window via parent (16 kids)
2400 reps @ 0.0065 msec (153000.0/sec): Map window via parent (16 kids)
12000 trep @ 0.0059 msec (168000.0/sec): Map window via parent (16 kids)
2500 reps @ 0.0026 msec (383000.0/sec): Map window via parent (25 kids)
2500 reps @ 0.0048 msec (207000.0/sec): Map window via parent (25 kids)
2500 reps @ 0.0054 msec (184000.0/sec): Map window via parent (25 kids)
2500 reps @ 0.0072 msec (138000.0/sec): Map window via parent (25 kids)
2500 reps @ 0.0060 msec (167000.0/sec): Map window via parent (25 kids)
12500 trep @ 0.0052 msec (191000.0/sec): Map window via parent (25 kids)
2500 reps @ 0.0028 msec (357000.0/sec): Map window via parent (50 kids)
2500 reps @ 0.0051 msec (195000.0/sec): Map window via parent (50 kids)
2500 reps @ 0.0042 msec (240000.0/sec): Map window via parent (50 kids)
2500 reps @ 0.0045 msec (223000.0/sec): Map window via parent (50 kids)
2500 reps @ 0.0044 msec (230000.0/sec): Map window via parent (50 kids)
12500 trep @ 0.0042 msec (239000.0/sec): Map window via parent (50 kids)
2400 reps @ 0.0027 msec (376000.0/sec): Map window via parent (75 kids)
2400 reps @ 0.0079 msec (126000.0/sec): Map window via parent (75 kids)
2400 reps @ 0.0048 msec (208000.0/sec): Map window via parent (75 kids)
2400 reps @ 0.0057 msec (176000.0/sec): Map window via parent (75 kids)
2400 reps @ 0.0054 msec (187000.0/sec): Map window via parent (75 kids)
12000 trep @ 0.0053 msec (189000.0/sec): Map window via parent (75 kids)
2400 reps @ 0.0066 msec (152000.0/sec): Map window via parent (100 kids)
2400 reps @ 0.0073 msec (138000.0/sec): Map window via parent (100 kids)
2400 reps @ 0.0093 msec (107000.0/sec): Map window via parent (100 kids)
2400 reps @ 0.0038 msec (261000.0/sec): Map window via parent (100 kids)
2400 reps @ 0.0051 msec (196000.0/sec): Map window via parent (100 kids)
12000 trep @ 0.0064 msec (156000.0/sec): Map window via parent (100 kids)
2400 reps @ 0.0076 msec (131000.0/sec): Map window via parent (200 kids)
2400 reps @ 0.0070 msec (143000.0/sec): Map window via parent (200 kids)
2400 reps @ 0.0049 msec (205000.0/sec): Map window via parent (200 kids)
2400 reps @ 0.0090 msec (111000.0/sec): Map window via parent (200 kids)
2400 reps @ 0.0079 msec (127000.0/sec): Map window via parent (200 kids)
12000 trep @ 0.0073 msec (137000.0/sec): Map window via parent (200 kids)
2400 reps @ 0.0012 msec (844000.0/sec): Unmap window via parent (4 kids)
2400 reps @ 0.0036 msec (277000.0/sec): Unmap window via parent (4 kids)
2400 reps @ 0.0034 msec (295000.0/sec): Unmap window via parent (4 kids)
2400 reps @ 0.0017 msec (594000.0/sec): Unmap window via parent (4 kids)
2400 reps @ 0.0010 msec (998000.0/sec): Unmap window via parent (4 kids)
12000 trep @ 0.0022 msec (460000.0/sec): Unmap window via parent (4 kids)
2400 reps @ 0.0013 msec (781000.0/sec): Unmap window via parent (16 kids)
2400 reps @ 0.0006 msec (1770000.0/sec): Unmap window via parent (16 kids)
2400 reps @ 0.0012 msec (822000.0/sec): Unmap window via parent (16 kids)
2400 reps @ 0.0012 msec (813000.0/sec): Unmap window via parent (16 kids)
2400 reps @ 0.0017 msec (588000.0/sec): Unmap window via parent (16 kids)
12000 trep @ 0.0012 msec (834000.0/sec): Unmap window via parent (16 kids)
2500 reps @ 0.0010 msec (961000.0/sec): Unmap window via parent (25 kids)
2500 reps @ 0.0010 msec (988000.0/sec): Unmap window via parent (25 kids)
2500 reps @ 0.0015 msec (676000.0/sec): Unmap window via parent (25 kids)
2500 reps @ 0.0005 msec (2070000.0/sec): Unmap window via parent (25 kids)
2500 reps @ 0.0011 msec (912000.0/sec): Unmap window via parent (25 kids)
12500 trep @ 0.0010 msec (978000.0/sec): Unmap window via parent (25 kids)
2500 reps @ 0.0007 msec (1370000.0/sec): Unmap window via parent (50 kids)
2500 reps @ 0.0009 msec (1110000.0/sec): Unmap window via parent (50 kids)
2500 reps @ 0.0012 msec (806000.0/sec): Unmap window via parent (50 kids)
2500 reps @ 0.0004 msec (2320000.0/sec): Unmap window via parent (50 kids)
2500 reps @ 0.0010 msec (995000.0/sec): Unmap window via parent (50 kids)
12500 trep @ 0.0009 msec (1160000.0/sec): Unmap window via parent (50 kids)
2400 reps @ 0.0005 msec (2210000.0/sec): Unmap window via parent (75 kids)
2400 reps @ 0.0009 msec (1080000.0/sec): Unmap window via parent (75 kids)
2400 reps @ 0.0012 msec (865000.0/sec): Unmap window via parent (75 kids)
2400 reps @ 0.0005 msec (2170000.0/sec): Unmap window via parent (75 kids)
2400 reps @ 0.0014 msec (739000.0/sec): Unmap window via parent (75 kids)
12000 trep @ 0.0009 msec (1150000.0/sec): Unmap window via parent (75 kids)
2400 reps @ 0.0004 msec (2310000.0/sec): Unmap window via parent (100 kids)
2400 reps @ 0.0010 msec (1040000.0/sec): Unmap window via parent (100 kids)
2400 reps @ 0.0011 msec (871000.0/sec): Unmap window via parent (100 kids)
2400 reps @ 0.0014 msec (707000.0/sec): Unmap window via parent (100 kids)
2400 reps @ 0.0012 msec (818000.0/sec): Unmap window via parent (100 kids)
12000 trep @ 0.0010 msec (966000.0/sec): Unmap window via parent (100 kids)
2400 reps @ 0.0008 msec (1210000.0/sec): Unmap window via parent (200 kids)
2400 reps @ 0.0010 msec (1030000.0/sec): Unmap window via parent (200 kids)
2400 reps @ 0.0012 msec (840000.0/sec): Unmap window via parent (200 kids)
2400 reps @ 0.0011 msec (934000.0/sec): Unmap window via parent (200 kids)
2400 reps @ 0.0004 msec (2270000.0/sec): Unmap window via parent (200 kids)
12000 trep @ 0.0009 msec (1110000.0/sec): Unmap window via parent (200 kids)
2400 reps @ 0.0016 msec (635000.0/sec): Destroy window via parent (4 kids)
2400 reps @ 0.0025 msec (408000.0/sec): Destroy window via parent (4 kids)
2400 reps @ 0.0024 msec (424000.0/sec): Destroy window via parent (4 kids)
2400 reps @ 0.0022 msec (449000.0/sec): Destroy window via parent (4 kids)
2400 reps @ 0.0022 msec (462000.0/sec): Destroy window via parent (4 kids)
12000 trep @ 0.0022 msec (464000.0/sec): Destroy window via parent (4 kids)
2400 reps @ 0.0010 msec (974000.0/sec): Destroy window via parent (16 kids)
2400 reps @ 0.0017 msec (593000.0/sec): Destroy window via parent (16 kids)
2400 reps @ 0.0020 msec (494000.0/sec): Destroy window via parent (16 kids)
2400 reps @ 0.0021 msec (466000.0/sec): Destroy window via parent (16 kids)
2400 reps @ 0.0021 msec (476000.0/sec): Destroy window via parent (16 kids)
12000 trep @ 0.0018 msec (557000.0/sec): Destroy window via parent (16 kids)
2500 reps @ 0.0012 msec (863000.0/sec): Destroy window via parent (25 kids)
2500 reps @ 0.0025 msec (404000.0/sec): Destroy window via parent (25 kids)
2500 reps @ 0.0021 msec (476000.0/sec): Destroy window via parent (25 kids)
2500 reps @ 0.0013 msec (793000.0/sec): Destroy window via parent (25 kids)
2500 reps @ 0.0016 msec (643000.0/sec): Destroy window via parent (25 kids)
12500 trep @ 0.0017 msec (585000.0/sec): Destroy window via parent (25 kids)
2500 reps @ 0.0007 msec (1390000.0/sec): Destroy window via parent (50 kids)
2500 reps @ 0.0013 msec (790000.0/sec): Destroy window via parent (50 kids)
2500 reps @ 0.0014 msec (694000.0/sec): Destroy window via parent (50 kids)
2500 reps @ 0.0017 msec (588000.0/sec): Destroy window via parent (50 kids)
2500 reps @ 0.0007 msec (1350000.0/sec): Destroy window via parent (50 kids)
12500 trep @ 0.0012 msec (852000.0/sec): Destroy window via parent (50 kids)
2400 reps @ 0.0014 msec (722000.0/sec): Destroy window via parent (75 kids)
2400 reps @ 0.0006 msec (1600000.0/sec): Destroy window via parent (75 kids)
2400 reps @ 0.0016 msec (629000.0/sec): Destroy window via parent (75 kids)
2400 reps @ 0.0016 msec (619000.0/sec): Destroy window via parent (75 kids)
2400 reps @ 0.0006 msec (1630000.0/sec): Destroy window via parent (75 kids)
12000 trep @ 0.0012 msec (858000.0/sec): Destroy window via parent (75 kids)
2400 reps @ 0.0020 msec (511000.0/sec): Destroy window via parent (100 kids)
2400 reps @ 0.0025 msec (405000.0/sec): Destroy window via parent (100 kids)
2400 reps @ 0.0015 msec (673000.0/sec): Destroy window via parent (100 kids)
2400 reps @ 0.0006 msec (1560000.0/sec): Destroy window via parent (100 kids)
2400 reps @ 0.0015 msec (652000.0/sec): Destroy window via parent (100 kids)
12000 trep @ 0.0016 msec (618000.0/sec): Destroy window via parent (100 kids)
2400 reps @ 0.0007 msec (1390000.0/sec): Destroy window via parent (200 kids)
2400 reps @ 0.0013 msec (752000.0/sec): Destroy window via parent (200 kids)
2400 reps @ 0.0016 msec (637000.0/sec): Destroy window via parent (200 kids)
2400 reps @ 0.0016 msec (616000.0/sec): Destroy window via parent (200 kids)
2400 reps @ 0.0006 msec (1580000.0/sec): Destroy window via parent (200 kids)
12000 trep @ 0.0012 msec (851000.0/sec): Destroy window via parent (200 kids)
1600000 reps @ 0.0039 msec (258000.0/sec): Hide/expose window via popup (4 kids)
1600000 reps @ 0.0039 msec (257000.0/sec): Hide/expose window via popup (4 kids)
1600000 reps @ 0.0039 msec (255000.0/sec): Hide/expose window via popup (4 kids)
1600000 reps @ 0.0039 msec (256000.0/sec): Hide/expose window via popup (4 kids)
1600000 reps @ 0.0039 msec (255000.0/sec): Hide/expose window via popup (4 kids)
8000000 trep @ 0.0039 msec (256000.0/sec): Hide/expose window via popup (4 kids)
3200000 reps @ 0.0026 msec (383000.0/sec): Hide/expose window via popup (16 kids)
3200000 reps @ 0.0026 msec (380000.0/sec): Hide/expose window via popup (16 kids)
3200000 reps @ 0.0026 msec (381000.0/sec): Hide/expose window via popup (16 kids)
3200000 reps @ 0.0026 msec (382000.0/sec): Hide/expose window via popup (16 kids)
3200000 reps @ 0.0026 msec (382000.0/sec): Hide/expose window via popup (16 kids)
16000000 trep @ 0.0026 msec (382000.0/sec): Hide/expose window via popup (16 kids)
2000000 reps @ 0.0025 msec (401000.0/sec): Hide/expose window via popup (25 kids)
2000000 reps @ 0.0025 msec (406000.0/sec): Hide/expose window via popup (25 kids)
2000000 reps @ 0.0025 msec (402000.0/sec): Hide/expose window via popup (25 kids)
2000000 reps @ 0.0025 msec (401000.0/sec): Hide/expose window via popup (25 kids)
2000000 reps @ 0.0025 msec (406000.0/sec): Hide/expose window via popup (25 kids)
10000000 trep @ 0.0025 msec (403000.0/sec): Hide/expose window via popup (25 kids)
2500000 reps @ 0.0024 msec (419000.0/sec): Hide/expose window via popup (50 kids)
2500000 reps @ 0.0024 msec (419000.0/sec): Hide/expose window via popup (50 kids)
2500000 reps @ 0.0024 msec (420000.0/sec): Hide/expose window via popup (50 kids)
2500000 reps @ 0.0024 msec (422000.0/sec): Hide/expose window via popup (50 kids)
2500000 reps @ 0.0024 msec (420000.0/sec): Hide/expose window via popup (50 kids)
12500000 trep @ 0.0024 msec (420000.0/sec): Hide/expose window via popup (50 kids)
2250000 reps @ 0.0024 msec (422000.0/sec): Hide/expose window via popup (75 kids)
2250000 reps @ 0.0024 msec (424000.0/sec): Hide/expose window via popup (75 kids)
2250000 reps @ 0.0024 msec (425000.0/sec): Hide/expose window via popup (75 kids)
2250000 reps @ 0.0024 msec (423000.0/sec): Hide/expose window via popup (75 kids)
2250000 reps @ 0.0024 msec (424000.0/sec): Hide/expose window via popup (75 kids)
11250000 trep @ 0.0024 msec (424000.0/sec): Hide/expose window via popup (75 kids)
3000000 reps @ 0.0023 msec (436000.0/sec): Hide/expose window via popup (100 kids)
3000000 reps @ 0.0023 msec (433000.0/sec): Hide/expose window via popup (100 kids)
3000000 reps @ 0.0023 msec (433000.0/sec): Hide/expose window via popup (100 kids)
3000000 reps @ 0.0023 msec (430000.0/sec): Hide/expose window via popup (100 kids)
3000000 reps @ 0.0023 msec (434000.0/sec): Hide/expose window via popup (100 kids)
15000000 trep @ 0.0023 msec (433000.0/sec): Hide/expose window via popup (100 kids)
4000000 reps @ 0.0023 msec (437000.0/sec): Hide/expose window via popup (200 kids)
4000000 reps @ 0.0023 msec (440000.0/sec): Hide/expose window via popup (200 kids)
4000000 reps @ 0.0023 msec (438000.0/sec): Hide/expose window via popup (200 kids)
4000000 reps @ 0.0023 msec (437000.0/sec): Hide/expose window via popup (200 kids)
4000000 reps @ 0.0023 msec (438000.0/sec): Hide/expose window via popup (200 kids)
20000000 trep @ 0.0023 msec (438000.0/sec): Hide/expose window via popup (200 kids)
160000 reps @ 0.0402 msec ( 24800.0/sec): Move window (4 kids)
160000 reps @ 0.0393 msec ( 25400.0/sec): Move window (4 kids)
160000 reps @ 0.0394 msec ( 25400.0/sec): Move window (4 kids)
160000 reps @ 0.0392 msec ( 25500.0/sec): Move window (4 kids)
160000 reps @ 0.0404 msec ( 24700.0/sec): Move window (4 kids)
800000 trep @ 0.0397 msec ( 25200.0/sec): Move window (4 kids)
144000 reps @ 0.0372 msec ( 26900.0/sec): Move window (16 kids)
144000 reps @ 0.0374 msec ( 26700.0/sec): Move window (16 kids)
144000 reps @ 0.0371 msec ( 27000.0/sec): Move window (16 kids)
144000 reps @ 0.0374 msec ( 26800.0/sec): Move window (16 kids)
144000 reps @ 0.0370 msec ( 27000.0/sec): Move window (16 kids)
720000 trep @ 0.0372 msec ( 26900.0/sec): Move window (16 kids)
150000 reps @ 0.0373 msec ( 26800.0/sec): Move window (25 kids)
150000 reps @ 0.0375 msec ( 26600.0/sec): Move window (25 kids)
150000 reps @ 0.0374 msec ( 26700.0/sec): Move window (25 kids)
150000 reps @ 0.0374 msec ( 26800.0/sec): Move window (25 kids)
150000 reps @ 0.0377 msec ( 26500.0/sec): Move window (25 kids)
750000 trep @ 0.0375 msec ( 26700.0/sec): Move window (25 kids)
150000 reps @ 0.0383 msec ( 26100.0/sec): Move window (50 kids)
150000 reps @ 0.0370 msec ( 27000.0/sec): Move window (50 kids)
150000 reps @ 0.0366 msec ( 27300.0/sec): Move window (50 kids)
150000 reps @ 0.0368 msec ( 27200.0/sec): Move window (50 kids)
150000 reps @ 0.0369 msec ( 27100.0/sec): Move window (50 kids)
750000 trep @ 0.0371 msec ( 26900.0/sec): Move window (50 kids)
150000 reps @ 0.0387 msec ( 25900.0/sec): Move window (75 kids)
150000 reps @ 0.0374 msec ( 26700.0/sec): Move window (75 kids)
150000 reps @ 0.0374 msec ( 26700.0/sec): Move window (75 kids)
150000 reps @ 0.0376 msec ( 26600.0/sec): Move window (75 kids)
150000 reps @ 0.0378 msec ( 26400.0/sec): Move window (75 kids)
750000 trep @ 0.0378 msec ( 26500.0/sec): Move window (75 kids)
200000 reps @ 0.0386 msec ( 25900.0/sec): Move window (100 kids)
200000 reps @ 0.0382 msec ( 26200.0/sec): Move window (100 kids)
200000 reps @ 0.0383 msec ( 26100.0/sec): Move window (100 kids)
200000 reps @ 0.0381 msec ( 26300.0/sec): Move window (100 kids)
200000 reps @ 0.0384 msec ( 26100.0/sec): Move window (100 kids)
1000000 trep @ 0.0383 msec ( 26100.0/sec): Move window (100 kids)
140000 reps @ 0.0408 msec ( 24500.0/sec): Move window (200 kids)
140000 reps @ 0.0411 msec ( 24300.0/sec): Move window (200 kids)
140000 reps @ 0.0416 msec ( 24000.0/sec): Move window (200 kids)
140000 reps @ 0.0412 msec ( 24200.0/sec): Move window (200 kids)
140000 reps @ 0.0412 msec ( 24300.0/sec): Move window (200 kids)
700000 trep @ 0.0412 msec ( 24300.0/sec): Move window (200 kids)
80000000 reps @ 0.0001 msec (8750000.0/sec): Moved unmapped window (4 kids)
80000000 reps @ 0.0001 msec (8720000.0/sec): Moved unmapped window (4 kids)
80000000 reps @ 0.0001 msec (8740000.0/sec): Moved unmapped window (4 kids)
80000000 reps @ 0.0001 msec (8740000.0/sec): Moved unmapped window (4 kids)
80000000 reps @ 0.0001 msec (8850000.0/sec): Moved unmapped window (4 kids)
400000000 trep @ 0.0001 msec (8760000.0/sec): Moved unmapped window (4 kids)
48000000 reps @ 0.0001 msec (8800000.0/sec): Moved unmapped window (16 kids)
48000000 reps @ 0.0001 msec (8730000.0/sec): Moved unmapped window (16 kids)
48000000 reps @ 0.0001 msec (8720000.0/sec): Moved unmapped window (16 kids)
48000000 reps @ 0.0001 msec (8710000.0/sec): Moved unmapped window (16 kids)
48000000 reps @ 0.0001 msec (8730000.0/sec): Moved unmapped window (16 kids)
240000000 trep @ 0.0001 msec (8740000.0/sec): Moved unmapped window (16 kids)
50000000 reps @ 0.0001 msec (8420000.0/sec): Moved unmapped window (25 kids)
50000000 reps @ 0.0001 msec (8750000.0/sec): Moved unmapped window (25 kids)
50000000 reps @ 0.0001 msec (8740000.0/sec): Moved unmapped window (25 kids)
50000000 reps @ 0.0001 msec (8780000.0/sec): Moved unmapped window (25 kids)
50000000 reps @ 0.0001 msec (8540000.0/sec): Moved unmapped window (25 kids)
250000000 trep @ 0.0001 msec (8640000.0/sec): Moved unmapped window (25 kids)
45000000 reps @ 0.0001 msec (8390000.0/sec): Moved unmapped window (50 kids)
45000000 reps @ 0.0001 msec (8810000.0/sec): Moved unmapped window (50 kids)
45000000 reps @ 0.0001 msec (8840000.0/sec): Moved unmapped window (50 kids)
45000000 reps @ 0.0001 msec (8340000.0/sec): Moved unmapped window (50 kids)
45000000 reps @ 0.0001 msec (8560000.0/sec): Moved unmapped window (50 kids)
225000000 trep @ 0.0001 msec (8580000.0/sec): Moved unmapped window (50 kids)
45000000 reps @ 0.0001 msec (8750000.0/sec): Moved unmapped window (75 kids)
45000000 reps @ 0.0001 msec (8770000.0/sec): Moved unmapped window (75 kids)
45000000 reps @ 0.0001 msec (8780000.0/sec): Moved unmapped window (75 kids)
45000000 reps @ 0.0001 msec (8400000.0/sec): Moved unmapped window (75 kids)
45000000 reps @ 0.0001 msec (8640000.0/sec): Moved unmapped window (75 kids)
225000000 trep @ 0.0001 msec (8660000.0/sec): Moved unmapped window (75 kids)
50000000 reps @ 0.0001 msec (8810000.0/sec): Moved unmapped window (100 kids)
50000000 reps @ 0.0001 msec (8820000.0/sec): Moved unmapped window (100 kids)
50000000 reps @ 0.0001 msec (8590000.0/sec): Moved unmapped window (100 kids)
50000000 reps @ 0.0001 msec (8490000.0/sec): Moved unmapped window (100 kids)
50000000 reps @ 0.0001 msec (8750000.0/sec): Moved unmapped window (100 kids)
250000000 trep @ 0.0001 msec (8690000.0/sec): Moved unmapped window (100 kids)
60000000 reps @ 0.0001 msec (8750000.0/sec): Moved unmapped window (200 kids)
60000000 reps @ 0.0001 msec (8760000.0/sec): Moved unmapped window (200 kids)
60000000 reps @ 0.0001 msec (8760000.0/sec): Moved unmapped window (200 kids)
60000000 reps @ 0.0001 msec (8760000.0/sec): Moved unmapped window (200 kids)
60000000 reps @ 0.0001 msec (8760000.0/sec): Moved unmapped window (200 kids)
300000000 trep @ 0.0001 msec (8760000.0/sec): Moved unmapped window (200 kids)
800000 reps @ 0.0096 msec (104000.0/sec): Move window via parent (4 kids)
800000 reps @ 0.0097 msec (103000.0/sec): Move window via parent (4 kids)
800000 reps @ 0.0097 msec (103000.0/sec): Move window via parent (4 kids)
800000 reps @ 0.0096 msec (104000.0/sec): Move window via parent (4 kids)
800000 reps @ 0.0096 msec (104000.0/sec): Move window via parent (4 kids)
4000000 trep @ 0.0097 msec (104000.0/sec): Move window via parent (4 kids)
3200000 reps @ 0.0025 msec (402000.0/sec): Move window via parent (16 kids)
3200000 reps @ 0.0024 msec (409000.0/sec): Move window via parent (16 kids)
3200000 reps @ 0.0024 msec (409000.0/sec): Move window via parent (16 kids)
3200000 reps @ 0.0024 msec (410000.0/sec): Move window via parent (16 kids)
3200000 reps @ 0.0025 msec (406000.0/sec): Move window via parent (16 kids)
16000000 trep @ 0.0025 msec (407000.0/sec): Move window via parent (16 kids)
5000000 reps @ 0.0016 msec (632000.0/sec): Move window via parent (25 kids)
5000000 reps @ 0.0015 msec (646000.0/sec): Move window via parent (25 kids)
5000000 reps @ 0.0016 msec (639000.0/sec): Move window via parent (25 kids)
5000000 reps @ 0.0016 msec (642000.0/sec): Move window via parent (25 kids)
5000000 reps @ 0.0015 msec (652000.0/sec): Move window via parent (25 kids)
25000000 trep @ 0.0016 msec (642000.0/sec): Move window via parent (25 kids)
10000000 reps @ 0.0008 msec (1210000.0/sec): Move window via parent (50 kids)
10000000 reps @ 0.0008 msec (1210000.0/sec): Move window via parent (50 kids)
10000000 reps @ 0.0008 msec (1220000.0/sec): Move window via parent (50 kids)
10000000 reps @ 0.0009 msec (1160000.0/sec): Move window via parent (50 kids)
10000000 reps @ 0.0008 msec (1200000.0/sec): Move window via parent (50 kids)
50000000 trep @ 0.0008 msec (1200000.0/sec): Move window via parent (50 kids)
15000000 reps @ 0.0006 msec (1760000.0/sec): Move window via parent (75 kids)
15000000 reps @ 0.0006 msec (1760000.0/sec): Move window via parent (75 kids)
15000000 reps @ 0.0006 msec (1760000.0/sec): Move window via parent (75 kids)
15000000 reps @ 0.0006 msec (1760000.0/sec): Move window via parent (75 kids)
15000000 reps @ 0.0006 msec (1760000.0/sec): Move window via parent (75 kids)
75000000 trep @ 0.0006 msec (1760000.0/sec): Move window via parent (75 kids)
20000000 reps @ 0.0004 msec (2240000.0/sec): Move window via parent (100 kids)
20000000 reps @ 0.0004 msec (2230000.0/sec): Move window via parent (100 kids)
20000000 reps @ 0.0004 msec (2230000.0/sec): Move window via parent (100 kids)
20000000 reps @ 0.0005 msec (2180000.0/sec): Move window via parent (100 kids)
20000000 reps @ 0.0004 msec (2220000.0/sec): Move window via parent (100 kids)
100000000 trep @ 0.0005 msec (2220000.0/sec): Move window via parent (100 kids)
20000000 reps @ 0.0003 msec (3790000.0/sec): Move window via parent (200 kids)
20000000 reps @ 0.0003 msec (3850000.0/sec): Move window via parent (200 kids)
20000000 reps @ 0.0003 msec (3830000.0/sec): Move window via parent (200 kids)
20000000 reps @ 0.0003 msec (3780000.0/sec): Move window via parent (200 kids)
20000000 reps @ 0.0003 msec (3680000.0/sec): Move window via parent (200 kids)
100000000 trep @ 0.0003 msec (3790000.0/sec): Move window via parent (200 kids)
1200000 reps @ 0.0043 msec (230000.0/sec): Resize window (4 kids)
1200000 reps @ 0.0043 msec (230000.0/sec): Resize window (4 kids)
1200000 reps @ 0.0043 msec (232000.0/sec): Resize window (4 kids)
1200000 reps @ 0.0043 msec (230000.0/sec): Resize window (4 kids)
1200000 reps @ 0.0043 msec (231000.0/sec): Resize window (4 kids)
6000000 trep @ 0.0043 msec (231000.0/sec): Resize window (4 kids)
1120000 reps @ 0.0049 msec (204000.0/sec): Resize window (16 kids)
1120000 reps @ 0.0049 msec (205000.0/sec): Resize window (16 kids)
1120000 reps @ 0.0049 msec (205000.0/sec): Resize window (16 kids)
1120000 reps @ 0.0049 msec (204000.0/sec): Resize window (16 kids)
1120000 reps @ 0.0049 msec (205000.0/sec): Resize window (16 kids)
5600000 trep @ 0.0049 msec (205000.0/sec): Resize window (16 kids)
1000000 reps @ 0.0054 msec (187000.0/sec): Resize window (25 kids)
1000000 reps @ 0.0055 msec (182000.0/sec): Resize window (25 kids)
1000000 reps @ 0.0055 msec (183000.0/sec): Resize window (25 kids)
1000000 reps @ 0.0054 msec (187000.0/sec): Resize window (25 kids)
1000000 reps @ 0.0054 msec (186000.0/sec): Resize window (25 kids)
5000000 trep @ 0.0054 msec (185000.0/sec): Resize window (25 kids)
1000000 reps @ 0.0064 msec (157000.0/sec): Resize window (50 kids)
1000000 reps @ 0.0063 msec (159000.0/sec): Resize window (50 kids)
1000000 reps @ 0.0063 msec (159000.0/sec): Resize window (50 kids)
1000000 reps @ 0.0063 msec (158000.0/sec): Resize window (50 kids)
1000000 reps @ 0.0063 msec (160000.0/sec): Resize window (50 kids)
5000000 trep @ 0.0063 msec (158000.0/sec): Resize window (50 kids)
750000 reps @ 0.0069 msec (144000.0/sec): Resize window (75 kids)
750000 reps @ 0.0070 msec (144000.0/sec): Resize window (75 kids)
750000 reps @ 0.0069 msec (145000.0/sec): Resize window (75 kids)
750000 reps @ 0.0070 msec (143000.0/sec): Resize window (75 kids)
750000 reps @ 0.0070 msec (142000.0/sec): Resize window (75 kids)
3750000 trep @ 0.0070 msec (144000.0/sec): Resize window (75 kids)
700000 reps @ 0.0078 msec (128000.0/sec): Resize window (100 kids)
700000 reps @ 0.0078 msec (128000.0/sec): Resize window (100 kids)
700000 reps @ 0.0077 msec (129000.0/sec): Resize window (100 kids)
700000 reps @ 0.0077 msec (130000.0/sec): Resize window (100 kids)
700000 reps @ 0.0077 msec (130000.0/sec): Resize window (100 kids)
3500000 trep @ 0.0077 msec (129000.0/sec): Resize window (100 kids)
600000 reps @ 0.0099 msec (101000.0/sec): Resize window (200 kids)
600000 reps @ 0.0099 msec (101000.0/sec): Resize window (200 kids)
600000 reps @ 0.0101 msec ( 98500.0/sec): Resize window (200 kids)
600000 reps @ 0.0099 msec (101000.0/sec): Resize window (200 kids)
600000 reps @ 0.0098 msec (102000.0/sec): Resize window (200 kids)
3000000 trep @ 0.0099 msec (101000.0/sec): Resize window (200 kids)
80000000 reps @ 0.0001 msec (8250000.0/sec): Resize unmapped window (4 kids)
80000000 reps @ 0.0001 msec (8240000.0/sec): Resize unmapped window (4 kids)
80000000 reps @ 0.0001 msec (8240000.0/sec): Resize unmapped window (4 kids)
80000000 reps @ 0.0001 msec (8250000.0/sec): Resize unmapped window (4 kids)
80000000 reps @ 0.0001 msec (8290000.0/sec): Resize unmapped window (4 kids)
400000000 trep @ 0.0001 msec (8250000.0/sec): Resize unmapped window (4 kids)
48000000 reps @ 0.0001 msec (8260000.0/sec): Resize unmapped window (16 kids)
48000000 reps @ 0.0001 msec (8260000.0/sec): Resize unmapped window (16 kids)
48000000 reps @ 0.0001 msec (8270000.0/sec): Resize unmapped window (16 kids)
48000000 reps @ 0.0001 msec (8260000.0/sec): Resize unmapped window (16 kids)
48000000 reps @ 0.0001 msec (8260000.0/sec): Resize unmapped window (16 kids)
240000000 trep @ 0.0001 msec (8260000.0/sec): Resize unmapped window (16 kids)
50000000 reps @ 0.0001 msec (8280000.0/sec): Resize unmapped window (25 kids)
50000000 reps @ 0.0001 msec (8260000.0/sec): Resize unmapped window (25 kids)
50000000 reps @ 0.0001 msec (8250000.0/sec): Resize unmapped window (25 kids)
50000000 reps @ 0.0001 msec (8250000.0/sec): Resize unmapped window (25 kids)
50000000 reps @ 0.0001 msec (8220000.0/sec): Resize unmapped window (25 kids)
250000000 trep @ 0.0001 msec (8250000.0/sec): Resize unmapped window (25 kids)
45000000 reps @ 0.0001 msec (8150000.0/sec): Resize unmapped window (50 kids)
45000000 reps @ 0.0001 msec (8180000.0/sec): Resize unmapped window (50 kids)
45000000 reps @ 0.0001 msec (8210000.0/sec): Resize unmapped window (50 kids)
45000000 reps @ 0.0001 msec (8200000.0/sec): Resize unmapped window (50 kids)
45000000 reps @ 0.0001 msec (8170000.0/sec): Resize unmapped window (50 kids)
225000000 trep @ 0.0001 msec (8180000.0/sec): Resize unmapped window (50 kids)
45000000 reps @ 0.0001 msec (8170000.0/sec): Resize unmapped window (75 kids)
45000000 reps @ 0.0001 msec (8220000.0/sec): Resize unmapped window (75 kids)
45000000 reps @ 0.0001 msec (8180000.0/sec): Resize unmapped window (75 kids)
45000000 reps @ 0.0001 msec (8130000.0/sec): Resize unmapped window (75 kids)
45000000 reps @ 0.0001 msec (8170000.0/sec): Resize unmapped window (75 kids)
225000000 trep @ 0.0001 msec (8170000.0/sec): Resize unmapped window (75 kids)
50000000 reps @ 0.0001 msec (8180000.0/sec): Resize unmapped window (100 kids)
50000000 reps @ 0.0001 msec (8130000.0/sec): Resize unmapped window (100 kids)
50000000 reps @ 0.0001 msec (8200000.0/sec): Resize unmapped window (100 kids)
50000000 reps @ 0.0001 msec (8180000.0/sec): Resize unmapped window (100 kids)
50000000 reps @ 0.0001 msec (8200000.0/sec): Resize unmapped window (100 kids)
250000000 trep @ 0.0001 msec (8180000.0/sec): Resize unmapped window (100 kids)
60000000 reps @ 0.0001 msec (8180000.0/sec): Resize unmapped window (200 kids)
60000000 reps @ 0.0001 msec (8240000.0/sec): Resize unmapped window (200 kids)
60000000 reps @ 0.0001 msec (8280000.0/sec): Resize unmapped window (200 kids)
60000000 reps @ 0.0001 msec (8280000.0/sec): Resize unmapped window (200 kids)
60000000 reps @ 0.0001 msec (8230000.0/sec): Resize unmapped window (200 kids)
300000000 trep @ 0.0001 msec (8240000.0/sec): Resize unmapped window (200 kids)
1600000 reps @ 0.0035 msec (283000.0/sec): Circulate window (4 kids)
1600000 reps @ 0.0036 msec (280000.0/sec): Circulate window (4 kids)
1600000 reps @ 0.0036 msec (281000.0/sec): Circulate window (4 kids)
1600000 reps @ 0.0035 msec (286000.0/sec): Circulate window (4 kids)
1600000 reps @ 0.0035 msec (282000.0/sec): Circulate window (4 kids)
8000000 trep @ 0.0035 msec (282000.0/sec): Circulate window (4 kids)
1120000 reps @ 0.0044 msec (230000.0/sec): Circulate window (16 kids)
1120000 reps @ 0.0045 msec (224000.0/sec): Circulate window (16 kids)
1120000 reps @ 0.0045 msec (224000.0/sec): Circulate window (16 kids)
1120000 reps @ 0.0044 msec (229000.0/sec): Circulate window (16 kids)
1120000 reps @ 0.0044 msec (229000.0/sec): Circulate window (16 kids)
5600000 trep @ 0.0044 msec (227000.0/sec): Circulate window (16 kids)
1250000 reps @ 0.0046 msec (217000.0/sec): Circulate window (25 kids)
1250000 reps @ 0.0047 msec (213000.0/sec): Circulate window (25 kids)
1250000 reps @ 0.0047 msec (212000.0/sec): Circulate window (25 kids)
1250000 reps @ 0.0046 msec (218000.0/sec): Circulate window (25 kids)
1250000 reps @ 0.0046 msec (218000.0/sec): Circulate window (25 kids)
6250000 trep @ 0.0046 msec (216000.0/sec): Circulate window (25 kids)
1000000 reps @ 0.0052 msec (192000.0/sec): Circulate window (50 kids)
1000000 reps @ 0.0052 msec (194000.0/sec): Circulate window (50 kids)
1000000 reps @ 0.0051 msec (197000.0/sec): Circulate window (50 kids)
1000000 reps @ 0.0051 msec (197000.0/sec): Circulate window (50 kids)
1000000 reps @ 0.0052 msec (192000.0/sec): Circulate window (50 kids)
5000000 trep @ 0.0051 msec (194000.0/sec): Circulate window (50 kids)
1500000 reps @ 0.0054 msec (184000.0/sec): Circulate window (75 kids)
1500000 reps @ 0.0055 msec (183000.0/sec): Circulate window (75 kids)
1500000 reps @ 0.0054 msec (185000.0/sec): Circulate window (75 kids)
1500000 reps @ 0.0056 msec (180000.0/sec): Circulate window (75 kids)
1500000 reps @ 0.0053 msec (187000.0/sec): Circulate window (75 kids)
7500000 trep @ 0.0054 msec (184000.0/sec): Circulate window (75 kids)
900000 reps @ 0.0058 msec (172000.0/sec): Circulate window (100 kids)
900000 reps @ 0.0059 msec (170000.0/sec): Circulate window (100 kids)
900000 reps @ 0.0059 msec (169000.0/sec): Circulate window (100 kids)
900000 reps @ 0.0059 msec (169000.0/sec): Circulate window (100 kids)
900000 reps @ 0.0056 msec (178000.0/sec): Circulate window (100 kids)
4500000 trep @ 0.0058 msec (171000.0/sec): Circulate window (100 kids)
800000 reps @ 0.0075 msec (133000.0/sec): Circulate window (200 kids)
800000 reps @ 0.0075 msec (134000.0/sec): Circulate window (200 kids)
800000 reps @ 0.0075 msec (132000.0/sec): Circulate window (200 kids)
800000 reps @ 0.0077 msec (130000.0/sec): Circulate window (200 kids)
800000 reps @ 0.0076 msec (131000.0/sec): Circulate window (200 kids)
4000000 trep @ 0.0076 msec (132000.0/sec): Circulate window (200 kids)
120000000 reps @ 0.0001 msec (18900000.0/sec): Circulate Unmapped window (4 kids)
120000000 reps @ 0.0001 msec (19200000.0/sec): Circulate Unmapped window (4 kids)
120000000 reps @ 0.0001 msec (19300000.0/sec): Circulate Unmapped window (4 kids)
120000000 reps @ 0.0001 msec (19200000.0/sec): Circulate Unmapped window (4 kids)
120000000 reps @ 0.0001 msec (19200000.0/sec): Circulate Unmapped window (4 kids)
600000000 trep @ 0.0001 msec (19200000.0/sec): Circulate Unmapped window (4 kids)
96000000 reps @ 0.0001 msec (17900000.0/sec): Circulate Unmapped window (16 kids)
96000000 reps @ 0.0001 msec (18000000.0/sec): Circulate Unmapped window (16 kids)
96000000 reps @ 0.0001 msec (17900000.0/sec): Circulate Unmapped window (16 kids)
96000000 reps @ 0.0001 msec (17900000.0/sec): Circulate Unmapped window (16 kids)
96000000 reps @ 0.0001 msec (18000000.0/sec): Circulate Unmapped window (16 kids)
480000000 trep @ 0.0001 msec (17900000.0/sec): Circulate Unmapped window (16 kids)
100000000 reps @ 0.0001 msec (15600000.0/sec): Circulate Unmapped window (25 kids)
100000000 reps @ 0.0001 msec (15600000.0/sec): Circulate Unmapped window (25 kids)
100000000 reps @ 0.0001 msec (15500000.0/sec): Circulate Unmapped window (25 kids)
100000000 reps @ 0.0001 msec (14900000.0/sec): Circulate Unmapped window (25 kids)
100000000 reps @ 0.0001 msec (15300000.0/sec): Circulate Unmapped window (25 kids)
500000000 trep @ 0.0001 msec (15400000.0/sec): Circulate Unmapped window (25 kids)
50000000 reps @ 0.0001 msec (9260000.0/sec): Circulate Unmapped window (50 kids)
50000000 reps @ 0.0001 msec (9290000.0/sec): Circulate Unmapped window (50 kids)
50000000 reps @ 0.0001 msec (9320000.0/sec): Circulate Unmapped window (50 kids)
50000000 reps @ 0.0001 msec (9280000.0/sec): Circulate Unmapped window (50 kids)
50000000 reps @ 0.0001 msec (9280000.0/sec): Circulate Unmapped window (50 kids)
250000000 trep @ 0.0001 msec (9290000.0/sec): Circulate Unmapped window (50 kids)
37500000 reps @ 0.0001 msec (7280000.0/sec): Circulate Unmapped window (75 kids)
37500000 reps @ 0.0001 msec (7290000.0/sec): Circulate Unmapped window (75 kids)
37500000 reps @ 0.0001 msec (7280000.0/sec): Circulate Unmapped window (75 kids)
37500000 reps @ 0.0001 msec (7290000.0/sec): Circulate Unmapped window (75 kids)
37500000 reps @ 0.0001 msec (7270000.0/sec): Circulate Unmapped window (75 kids)
187500000 trep @ 0.0001 msec (7280000.0/sec): Circulate Unmapped window (75 kids)
40000000 reps @ 0.0002 msec (6070000.0/sec): Circulate Unmapped window (100 kids)
40000000 reps @ 0.0002 msec (6070000.0/sec): Circulate Unmapped window (100 kids)
40000000 reps @ 0.0002 msec (6060000.0/sec): Circulate Unmapped window (100 kids)
40000000 reps @ 0.0002 msec (6070000.0/sec): Circulate Unmapped window (100 kids)
40000000 reps @ 0.0002 msec (6070000.0/sec): Circulate Unmapped window (100 kids)
200000000 trep @ 0.0002 msec (6070000.0/sec): Circulate Unmapped window (100 kids)
18000000 reps @ 0.0003 msec (3430000.0/sec): Circulate Unmapped window (200 kids)
18000000 reps @ 0.0003 msec (3430000.0/sec): Circulate Unmapped window (200 kids)
18000000 reps @ 0.0003 msec (3430000.0/sec): Circulate Unmapped window (200 kids)
18000000 reps @ 0.0003 msec (3420000.0/sec): Circulate Unmapped window (200 kids)
18000000 reps @ 0.0003 msec (3410000.0/sec): Circulate Unmapped window (200 kids)
90000000 trep @ 0.0003 msec (3420000.0/sec): Circulate Unmapped window (200 kids)
[-- Attachment #3: no-front-buffer-rendering.txt --]
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x11perf - X11 performance program, version 1.2
The X.Org Foundation server version 12005000 on :0.0
from stark01
Wed Aug 25 15:22:21 2021
Sync time adjustment is 0.0549 msecs.
900000000 reps @ 0.0000 msec (159000000.0/sec): Dot
900000000 reps @ 0.0000 msec (156000000.0/sec): Dot
900000000 reps @ 0.0000 msec (157000000.0/sec): Dot
900000000 reps @ 0.0000 msec (152000000.0/sec): Dot
900000000 reps @ 0.0000 msec (157000000.0/sec): Dot
4500000000 trep @ 0.0000 msec (156000000.0/sec): Dot
200000 reps @ 0.0302 msec ( 33100.0/sec): 500x500 rectangle
200000 reps @ 0.0302 msec ( 33100.0/sec): 500x500 rectangle
200000 reps @ 0.0302 msec ( 33100.0/sec): 500x500 rectangle
200000 reps @ 0.0302 msec ( 33100.0/sec): 500x500 rectangle
200000 reps @ 0.0302 msec ( 33100.0/sec): 500x500 rectangle
1000000 trep @ 0.0302 msec ( 33100.0/sec): 500x500 rectangle
70000 reps @ 0.0726 msec ( 13800.0/sec): 500x500 stippled rectangle (8x8 stipple)
70000 reps @ 0.0726 msec ( 13800.0/sec): 500x500 stippled rectangle (8x8 stipple)
70000 reps @ 0.0726 msec ( 13800.0/sec): 500x500 stippled rectangle (8x8 stipple)
70000 reps @ 0.0724 msec ( 13800.0/sec): 500x500 stippled rectangle (8x8 stipple)
70000 reps @ 0.0727 msec ( 13800.0/sec): 500x500 stippled rectangle (8x8 stipple)
350000 trep @ 0.0726 msec ( 13800.0/sec): 500x500 stippled rectangle (8x8 stipple)
200000 reps @ 0.0294 msec ( 34000.0/sec): 500x500 opaque stippled rectangle (8x8 stipple)
200000 reps @ 0.0294 msec ( 34000.0/sec): 500x500 opaque stippled rectangle (8x8 stipple)
200000 reps @ 0.0294 msec ( 34000.0/sec): 500x500 opaque stippled rectangle (8x8 stipple)
200000 reps @ 0.0294 msec ( 34000.0/sec): 500x500 opaque stippled rectangle (8x8 stipple)
200000 reps @ 0.0294 msec ( 34000.0/sec): 500x500 opaque stippled rectangle (8x8 stipple)
1000000 trep @ 0.0294 msec ( 34000.0/sec): 500x500 opaque stippled rectangle (8x8 stipple)
200000 reps @ 0.0295 msec ( 33900.0/sec): 500x500 tiled rectangle (4x4 tile)
200000 reps @ 0.0295 msec ( 33900.0/sec): 500x500 tiled rectangle (4x4 tile)
200000 reps @ 0.0296 msec ( 33800.0/sec): 500x500 tiled rectangle (4x4 tile)
200000 reps @ 0.0295 msec ( 33900.0/sec): 500x500 tiled rectangle (4x4 tile)
200000 reps @ 0.0295 msec ( 33900.0/sec): 500x500 tiled rectangle (4x4 tile)
1000000 trep @ 0.0295 msec ( 33900.0/sec): 500x500 tiled rectangle (4x4 tile)
80000 reps @ 0.0702 msec ( 14200.0/sec): 500x500 stippled rectangle (17x15 stipple)
80000 reps @ 0.0697 msec ( 14300.0/sec): 500x500 stippled rectangle (17x15 stipple)
80000 reps @ 0.0699 msec ( 14300.0/sec): 500x500 stippled rectangle (17x15 stipple)
80000 reps @ 0.0699 msec ( 14300.0/sec): 500x500 stippled rectangle (17x15 stipple)
80000 reps @ 0.0701 msec ( 14300.0/sec): 500x500 stippled rectangle (17x15 stipple)
400000 trep @ 0.0700 msec ( 14300.0/sec): 500x500 stippled rectangle (17x15 stipple)
200000 reps @ 0.0294 msec ( 34000.0/sec): 500x500 opaque stippled rectangle (17x15 stipple)
200000 reps @ 0.0294 msec ( 34000.0/sec): 500x500 opaque stippled rectangle (17x15 stipple)
200000 reps @ 0.0294 msec ( 34000.0/sec): 500x500 opaque stippled rectangle (17x15 stipple)
200000 reps @ 0.0294 msec ( 34000.0/sec): 500x500 opaque stippled rectangle (17x15 stipple)
200000 reps @ 0.0294 msec ( 34000.0/sec): 500x500 opaque stippled rectangle (17x15 stipple)
1000000 trep @ 0.0294 msec ( 34000.0/sec): 500x500 opaque stippled rectangle (17x15 stipple)
200000 reps @ 0.0297 msec ( 33700.0/sec): 500x500 tiled rectangle (17x15 tile)
200000 reps @ 0.0296 msec ( 33800.0/sec): 500x500 tiled rectangle (17x15 tile)
200000 reps @ 0.0296 msec ( 33800.0/sec): 500x500 tiled rectangle (17x15 tile)
200000 reps @ 0.0296 msec ( 33800.0/sec): 500x500 tiled rectangle (17x15 tile)
200000 reps @ 0.0297 msec ( 33700.0/sec): 500x500 tiled rectangle (17x15 tile)
1000000 trep @ 0.0296 msec ( 33800.0/sec): 500x500 tiled rectangle (17x15 tile)
200000 reps @ 0.0378 msec ( 26400.0/sec): 500x500 stippled rectangle (161x145 stipple)
200000 reps @ 0.0379 msec ( 26400.0/sec): 500x500 stippled rectangle (161x145 stipple)
200000 reps @ 0.0379 msec ( 26400.0/sec): 500x500 stippled rectangle (161x145 stipple)
200000 reps @ 0.0378 msec ( 26500.0/sec): 500x500 stippled rectangle (161x145 stipple)
200000 reps @ 0.0379 msec ( 26400.0/sec): 500x500 stippled rectangle (161x145 stipple)
1000000 trep @ 0.0379 msec ( 26400.0/sec): 500x500 stippled rectangle (161x145 stipple)
200000 reps @ 0.0295 msec ( 33900.0/sec): 500x500 opaque stippled rectangle (161x145 stipple)
200000 reps @ 0.0294 msec ( 34000.0/sec): 500x500 opaque stippled rectangle (161x145 stipple)
200000 reps @ 0.0294 msec ( 34000.0/sec): 500x500 opaque stippled rectangle (161x145 stipple)
200000 reps @ 0.0294 msec ( 34000.0/sec): 500x500 opaque stippled rectangle (161x145 stipple)
200000 reps @ 0.0295 msec ( 33900.0/sec): 500x500 opaque stippled rectangle (161x145 stipple)
1000000 trep @ 0.0294 msec ( 34000.0/sec): 500x500 opaque stippled rectangle (161x145 stipple)
200000 reps @ 0.0300 msec ( 33400.0/sec): 500x500 tiled rectangle (161x145 tile)
200000 reps @ 0.0300 msec ( 33400.0/sec): 500x500 tiled rectangle (161x145 tile)
200000 reps @ 0.0300 msec ( 33400.0/sec): 500x500 tiled rectangle (161x145 tile)
200000 reps @ 0.0300 msec ( 33300.0/sec): 500x500 tiled rectangle (161x145 tile)
200000 reps @ 0.0300 msec ( 33400.0/sec): 500x500 tiled rectangle (161x145 tile)
1000000 trep @ 0.0300 msec ( 33400.0/sec): 500x500 tiled rectangle (161x145 tile)
200000 reps @ 0.0299 msec ( 33400.0/sec): 500x500 tiled rectangle (216x208 tile)
200000 reps @ 0.0300 msec ( 33400.0/sec): 500x500 tiled rectangle (216x208 tile)
200000 reps @ 0.0299 msec ( 33400.0/sec): 500x500 tiled rectangle (216x208 tile)
200000 reps @ 0.0300 msec ( 33400.0/sec): 500x500 tiled rectangle (216x208 tile)
200000 reps @ 0.0299 msec ( 33500.0/sec): 500x500 tiled rectangle (216x208 tile)
1000000 trep @ 0.0299 msec ( 33400.0/sec): 500x500 tiled rectangle (216x208 tile)
20000000 reps @ 0.0003 msec (3820000.0/sec): 500-pixel line segment
20000000 reps @ 0.0003 msec (3810000.0/sec): 500-pixel line segment
20000000 reps @ 0.0003 msec (3760000.0/sec): 500-pixel line segment
20000000 reps @ 0.0003 msec (3820000.0/sec): 500-pixel line segment
20000000 reps @ 0.0003 msec (3820000.0/sec): 500-pixel line segment
100000000 trep @ 0.0003 msec (3810000.0/sec): 500-pixel line segment
90000000 reps @ 0.0001 msec (16500000.0/sec): 500-pixel horizontal line segment
90000000 reps @ 0.0001 msec (16500000.0/sec): 500-pixel horizontal line segment
90000000 reps @ 0.0001 msec (16500000.0/sec): 500-pixel horizontal line segment
90000000 reps @ 0.0001 msec (16500000.0/sec): 500-pixel horizontal line segment
90000000 reps @ 0.0001 msec (16500000.0/sec): 500-pixel horizontal line segment
450000000 trep @ 0.0001 msec (16500000.0/sec): 500-pixel horizontal line segment
80000000 reps @ 0.0001 msec (15800000.0/sec): 500-pixel vertical line segment
80000000 reps @ 0.0001 msec (15500000.0/sec): 500-pixel vertical line segment
80000000 reps @ 0.0001 msec (15700000.0/sec): 500-pixel vertical line segment
80000000 reps @ 0.0001 msec (15700000.0/sec): 500-pixel vertical line segment
80000000 reps @ 0.0001 msec (15700000.0/sec): 500-pixel vertical line segment
400000000 trep @ 0.0001 msec (15700000.0/sec): 500-pixel vertical line segment
1000000 reps @ 0.0083 msec (120000.0/sec): 500x50 wide horizontal line segment
1000000 reps @ 0.0084 msec (119000.0/sec): 500x50 wide horizontal line segment
1000000 reps @ 0.0083 msec (121000.0/sec): 500x50 wide horizontal line segment
1000000 reps @ 0.0083 msec (120000.0/sec): 500x50 wide horizontal line segment
1000000 reps @ 0.0083 msec (121000.0/sec): 500x50 wide horizontal line segment
5000000 trep @ 0.0083 msec (120000.0/sec): 500x50 wide horizontal line segment
1000000 reps @ 0.0084 msec (120000.0/sec): 500x50 wide vertical line segment
1000000 reps @ 0.0084 msec (120000.0/sec): 500x50 wide vertical line segment
1000000 reps @ 0.0084 msec (119000.0/sec): 500x50 wide vertical line segment
1000000 reps @ 0.0083 msec (120000.0/sec): 500x50 wide vertical line segment
1000000 reps @ 0.0083 msec (120000.0/sec): 500x50 wide vertical line segment
5000000 trep @ 0.0084 msec (120000.0/sec): 500x50 wide vertical line segment
30000000 reps @ 0.0002 msec (5830000.0/sec): 500-pixel line
30000000 reps @ 0.0002 msec (5820000.0/sec): 500-pixel line
30000000 reps @ 0.0002 msec (5840000.0/sec): 500-pixel line
30000000 reps @ 0.0002 msec (5820000.0/sec): 500-pixel line
30000000 reps @ 0.0002 msec (5800000.0/sec): 500-pixel line
150000000 trep @ 0.0002 msec (5820000.0/sec): 500-pixel line
1000000 reps @ 0.0053 msec (189000.0/sec): 500x50 wide line
1000000 reps @ 0.0053 msec (188000.0/sec): 500x50 wide line
1000000 reps @ 0.0053 msec (188000.0/sec): 500x50 wide line
1000000 reps @ 0.0053 msec (189000.0/sec): 500x50 wide line
1000000 reps @ 0.0053 msec (189000.0/sec): 500x50 wide line
5000000 trep @ 0.0053 msec (189000.0/sec): 500x50 wide line
3000000 reps @ 0.0019 msec (536000.0/sec): 500x500 rectangle outline
3000000 reps @ 0.0019 msec (528000.0/sec): 500x500 rectangle outline
3000000 reps @ 0.0019 msec (528000.0/sec): 500x500 rectangle outline
3000000 reps @ 0.0019 msec (529000.0/sec): 500x500 rectangle outline
3000000 reps @ 0.0019 msec (537000.0/sec): 500x500 rectangle outline
15000000 trep @ 0.0019 msec (532000.0/sec): 500x500 rectangle outline
300000 reps @ 0.0211 msec ( 47400.0/sec): 500x500 wide rectangle outline
300000 reps @ 0.0210 msec ( 47600.0/sec): 500x500 wide rectangle outline
300000 reps @ 0.0210 msec ( 47600.0/sec): 500x500 wide rectangle outline
300000 reps @ 0.0211 msec ( 47500.0/sec): 500x500 wide rectangle outline
300000 reps @ 0.0210 msec ( 47700.0/sec): 500x500 wide rectangle outline
1500000 trep @ 0.0210 msec ( 47500.0/sec): 500x500 wide rectangle outline
2000000 reps @ 0.0029 msec (346000.0/sec): 500-pixel circle
2000000 reps @ 0.0029 msec (346000.0/sec): 500-pixel circle
2000000 reps @ 0.0029 msec (347000.0/sec): 500-pixel circle
2000000 reps @ 0.0029 msec (347000.0/sec): 500-pixel circle
2000000 reps @ 0.0029 msec (347000.0/sec): 500-pixel circle
10000000 trep @ 0.0029 msec (346000.0/sec): 500-pixel circle
500000 reps @ 0.0151 msec ( 66200.0/sec): 500-pixel wide circle
500000 reps @ 0.0151 msec ( 66200.0/sec): 500-pixel wide circle
500000 reps @ 0.0151 msec ( 66400.0/sec): 500-pixel wide circle
500000 reps @ 0.0150 msec ( 66600.0/sec): 500-pixel wide circle
500000 reps @ 0.0151 msec ( 66100.0/sec): 500-pixel wide circle
2500000 trep @ 0.0151 msec ( 66300.0/sec): 500-pixel wide circle
200000 reps @ 0.0266 msec ( 37600.0/sec): 500-pixel solid circle
200000 reps @ 0.0273 msec ( 36600.0/sec): 500-pixel solid circle
200000 reps @ 0.0273 msec ( 36600.0/sec): 500-pixel solid circle
200000 reps @ 0.0274 msec ( 36500.0/sec): 500-pixel solid circle
200000 reps @ 0.0266 msec ( 37600.0/sec): 500-pixel solid circle
1000000 trep @ 0.0271 msec ( 37000.0/sec): 500-pixel solid circle
3000000 reps @ 0.0023 msec (427000.0/sec): 500-pixel ellipse
3000000 reps @ 0.0023 msec (427000.0/sec): 500-pixel ellipse
3000000 reps @ 0.0023 msec (427000.0/sec): 500-pixel ellipse
3000000 reps @ 0.0023 msec (427000.0/sec): 500-pixel ellipse
3000000 reps @ 0.0023 msec (427000.0/sec): 500-pixel ellipse
15000000 trep @ 0.0023 msec (427000.0/sec): 500-pixel ellipse
400000 reps @ 0.0184 msec ( 54300.0/sec): 500-pixel wide ellipse
400000 reps @ 0.0189 msec ( 53000.0/sec): 500-pixel wide ellipse
400000 reps @ 0.0187 msec ( 53500.0/sec): 500-pixel wide ellipse
400000 reps @ 0.0189 msec ( 52900.0/sec): 500-pixel wide ellipse
400000 reps @ 0.0185 msec ( 54100.0/sec): 500-pixel wide ellipse
2000000 trep @ 0.0187 msec ( 53600.0/sec): 500-pixel wide ellipse
400000 reps @ 0.0136 msec ( 73700.0/sec): 500-pixel filled ellipse
400000 reps @ 0.0140 msec ( 71400.0/sec): 500-pixel filled ellipse
400000 reps @ 0.0140 msec ( 71600.0/sec): 500-pixel filled ellipse
400000 reps @ 0.0136 msec ( 73700.0/sec): 500-pixel filled ellipse
400000 reps @ 0.0137 msec ( 73200.0/sec): 500-pixel filled ellipse
2000000 trep @ 0.0138 msec ( 72700.0/sec): 500-pixel filled ellipse
600000 reps @ 0.0123 msec ( 81000.0/sec): Fill 300x300 trapezoid
600000 reps @ 0.0124 msec ( 81000.0/sec): Fill 300x300 trapezoid
600000 reps @ 0.0124 msec ( 81000.0/sec): Fill 300x300 trapezoid
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 trapezoid
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 trapezoid
3000000 trep @ 0.0124 msec ( 80900.0/sec): Fill 300x300 trapezoid
200000 reps @ 0.0259 msec ( 38600.0/sec): Fill 300x300 stippled trapezoid (8x8 stipple)
200000 reps @ 0.0256 msec ( 39100.0/sec): Fill 300x300 stippled trapezoid (8x8 stipple)
200000 reps @ 0.0257 msec ( 38900.0/sec): Fill 300x300 stippled trapezoid (8x8 stipple)
200000 reps @ 0.0257 msec ( 38900.0/sec): Fill 300x300 stippled trapezoid (8x8 stipple)
200000 reps @ 0.0258 msec ( 38700.0/sec): Fill 300x300 stippled trapezoid (8x8 stipple)
1000000 trep @ 0.0257 msec ( 38800.0/sec): Fill 300x300 stippled trapezoid (8x8 stipple)
600000 reps @ 0.0124 msec ( 80700.0/sec): Fill 300x300 opaque stippled trapezoid (8x8 stipple)
600000 reps @ 0.0124 msec ( 80700.0/sec): Fill 300x300 opaque stippled trapezoid (8x8 stipple)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 opaque stippled trapezoid (8x8 stipple)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 opaque stippled trapezoid (8x8 stipple)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 opaque stippled trapezoid (8x8 stipple)
3000000 trep @ 0.0124 msec ( 80800.0/sec): Fill 300x300 opaque stippled trapezoid (8x8 stipple)
600000 reps @ 0.0123 msec ( 81000.0/sec): Fill 300x300 tiled trapezoid (4x4 tile)
600000 reps @ 0.0123 msec ( 81000.0/sec): Fill 300x300 tiled trapezoid (4x4 tile)
600000 reps @ 0.0123 msec ( 81100.0/sec): Fill 300x300 tiled trapezoid (4x4 tile)
600000 reps @ 0.0123 msec ( 81000.0/sec): Fill 300x300 tiled trapezoid (4x4 tile)
600000 reps @ 0.0123 msec ( 81000.0/sec): Fill 300x300 tiled trapezoid (4x4 tile)
3000000 trep @ 0.0123 msec ( 81000.0/sec): Fill 300x300 tiled trapezoid (4x4 tile)
400000 reps @ 0.0245 msec ( 40800.0/sec): Fill 300x300 stippled trapezoid (17x15 stipple)
400000 reps @ 0.0246 msec ( 40700.0/sec): Fill 300x300 stippled trapezoid (17x15 stipple)
400000 reps @ 0.0246 msec ( 40700.0/sec): Fill 300x300 stippled trapezoid (17x15 stipple)
400000 reps @ 0.0247 msec ( 40500.0/sec): Fill 300x300 stippled trapezoid (17x15 stipple)
400000 reps @ 0.0247 msec ( 40500.0/sec): Fill 300x300 stippled trapezoid (17x15 stipple)
2000000 trep @ 0.0246 msec ( 40600.0/sec): Fill 300x300 stippled trapezoid (17x15 stipple)
600000 reps @ 0.0124 msec ( 80700.0/sec): Fill 300x300 opaque stippled trapezoid (17x15 stipple)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 opaque stippled trapezoid (17x15 stipple)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 opaque stippled trapezoid (17x15 stipple)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 opaque stippled trapezoid (17x15 stipple)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 opaque stippled trapezoid (17x15 stipple)
3000000 trep @ 0.0124 msec ( 80800.0/sec): Fill 300x300 opaque stippled trapezoid (17x15 stipple)
600000 reps @ 0.0123 msec ( 81000.0/sec): Fill 300x300 tiled trapezoid (17x15 tile)
600000 reps @ 0.0123 msec ( 81000.0/sec): Fill 300x300 tiled trapezoid (17x15 tile)
600000 reps @ 0.0123 msec ( 81000.0/sec): Fill 300x300 tiled trapezoid (17x15 tile)
600000 reps @ 0.0124 msec ( 81000.0/sec): Fill 300x300 tiled trapezoid (17x15 tile)
600000 reps @ 0.0124 msec ( 81000.0/sec): Fill 300x300 tiled trapezoid (17x15 tile)
3000000 trep @ 0.0123 msec ( 81000.0/sec): Fill 300x300 tiled trapezoid (17x15 tile)
400000 reps @ 0.0135 msec ( 74100.0/sec): Fill 300x300 stippled trapezoid (161x145 stipple)
400000 reps @ 0.0136 msec ( 73500.0/sec): Fill 300x300 stippled trapezoid (161x145 stipple)
400000 reps @ 0.0135 msec ( 74000.0/sec): Fill 300x300 stippled trapezoid (161x145 stipple)
400000 reps @ 0.0136 msec ( 73600.0/sec): Fill 300x300 stippled trapezoid (161x145 stipple)
400000 reps @ 0.0135 msec ( 74000.0/sec): Fill 300x300 stippled trapezoid (161x145 stipple)
2000000 trep @ 0.0135 msec ( 73900.0/sec): Fill 300x300 stippled trapezoid (161x145 stipple)
600000 reps @ 0.0124 msec ( 80700.0/sec): Fill 300x300 opaque stippled trapezoid (161x145 stipple)
600000 reps @ 0.0124 msec ( 80700.0/sec): Fill 300x300 opaque stippled trapezoid (161x145 stipple)
600000 reps @ 0.0124 msec ( 80700.0/sec): Fill 300x300 opaque stippled trapezoid (161x145 stipple)
600000 reps @ 0.0124 msec ( 80700.0/sec): Fill 300x300 opaque stippled trapezoid (161x145 stipple)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 opaque stippled trapezoid (161x145 stipple)
3000000 trep @ 0.0124 msec ( 80700.0/sec): Fill 300x300 opaque stippled trapezoid (161x145 stipple)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 tiled trapezoid (161x145 tile)
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 tiled trapezoid (161x145 tile)
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 tiled trapezoid (161x145 tile)
600000 reps @ 0.0124 msec ( 80900.0/sec): Fill 300x300 tiled trapezoid (161x145 tile)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 tiled trapezoid (161x145 tile)
3000000 trep @ 0.0124 msec ( 80900.0/sec): Fill 300x300 tiled trapezoid (161x145 tile)
600000 reps @ 0.0124 msec ( 80700.0/sec): Fill 300x300 tiled trapezoid (216x208 tile)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 tiled trapezoid (216x208 tile)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 tiled trapezoid (216x208 tile)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 tiled trapezoid (216x208 tile)
600000 reps @ 0.0124 msec ( 80800.0/sec): Fill 300x300 tiled trapezoid (216x208 tile)
3000000 trep @ 0.0124 msec ( 80800.0/sec): Fill 300x300 tiled trapezoid (216x208 tile)
300000 reps @ 0.0248 msec ( 40300.0/sec): Fill 300x300 aa trap
300000 reps @ 0.0247 msec ( 40600.0/sec): Fill 300x300 aa trap
300000 reps @ 0.0245 msec ( 40800.0/sec): Fill 300x300 aa trap
300000 reps @ 0.0245 msec ( 40900.0/sec): Fill 300x300 aa trap
300000 reps @ 0.0243 msec ( 41100.0/sec): Fill 300x300 aa trap
1500000 trep @ 0.0245 msec ( 40700.0/sec): Fill 300x300 aa trap
300000 reps @ 0.0247 msec ( 40500.0/sec): Fill 300x300 aa trap with 4 bit alpha
300000 reps @ 0.0246 msec ( 40700.0/sec): Fill 300x300 aa trap with 4 bit alpha
300000 reps @ 0.0250 msec ( 40000.0/sec): Fill 300x300 aa trap with 4 bit alpha
300000 reps @ 0.0247 msec ( 40500.0/sec): Fill 300x300 aa trap with 4 bit alpha
300000 reps @ 0.0246 msec ( 40700.0/sec): Fill 300x300 aa trap with 4 bit alpha
1500000 trep @ 0.0247 msec ( 40500.0/sec): Fill 300x300 aa trap with 4 bit alpha
2000000 reps @ 0.0029 msec (346000.0/sec): Fill 300x300 aa trap with 1 bit alpha
2000000 reps @ 0.0030 msec (332000.0/sec): Fill 300x300 aa trap with 1 bit alpha
2000000 reps @ 0.0029 msec (340000.0/sec): Fill 300x300 aa trap with 1 bit alpha
2000000 reps @ 0.0031 msec (327000.0/sec): Fill 300x300 aa trap with 1 bit alpha
2000000 reps @ 0.0032 msec (313000.0/sec): Fill 300x300 aa trap with 1 bit alpha
10000000 trep @ 0.0030 msec (331000.0/sec): Fill 300x300 aa trap with 1 bit alpha
300000 reps @ 0.0215 msec ( 46600.0/sec): Fill 2x300 aa trap
300000 reps @ 0.0215 msec ( 46400.0/sec): Fill 2x300 aa trap
300000 reps @ 0.0215 msec ( 46600.0/sec): Fill 2x300 aa trap
300000 reps @ 0.0215 msec ( 46600.0/sec): Fill 2x300 aa trap
300000 reps @ 0.0215 msec ( 46500.0/sec): Fill 2x300 aa trap
1500000 trep @ 0.0215 msec ( 46500.0/sec): Fill 2x300 aa trap
20000 reps @ 0.2978 msec ( 3360.0/sec): Fill 300x300 aa trapezoid
20000 reps @ 0.2977 msec ( 3360.0/sec): Fill 300x300 aa trapezoid
20000 reps @ 0.2976 msec ( 3360.0/sec): Fill 300x300 aa trapezoid
20000 reps @ 0.2978 msec ( 3360.0/sec): Fill 300x300 aa trapezoid
20000 reps @ 0.2975 msec ( 3360.0/sec): Fill 300x300 aa trapezoid
100000 trep @ 0.2977 msec ( 3360.0/sec): Fill 300x300 aa trapezoid
300000 reps @ 0.0238 msec ( 42100.0/sec): Fill 300x300 aa pre-added trapezoid
300000 reps @ 0.0244 msec ( 40900.0/sec): Fill 300x300 aa pre-added trapezoid
300000 reps @ 0.0244 msec ( 41100.0/sec): Fill 300x300 aa pre-added trapezoid
300000 reps @ 0.0244 msec ( 41000.0/sec): Fill 300x300 aa pre-added trapezoid
300000 reps @ 0.0246 msec ( 40700.0/sec): Fill 300x300 aa pre-added trapezoid
1500000 trep @ 0.0243 msec ( 41200.0/sec): Fill 300x300 aa pre-added trapezoid
160000000 reps @ 0.0000 msec (30400000.0/sec): Char in 80-char line (6x13)
160000000 reps @ 0.0000 msec (30300000.0/sec): Char in 80-char line (6x13)
160000000 reps @ 0.0000 msec (30600000.0/sec): Char in 80-char line (6x13)
160000000 reps @ 0.0000 msec (30300000.0/sec): Char in 80-char line (6x13)
160000000 reps @ 0.0000 msec (30500000.0/sec): Char in 80-char line (6x13)
800000000 trep @ 0.0000 msec (30500000.0/sec): Char in 80-char line (6x13)
144000000 reps @ 0.0000 msec (27600000.0/sec): Char in 70-char line (8x13)
144000000 reps @ 0.0000 msec (27400000.0/sec): Char in 70-char line (8x13)
144000000 reps @ 0.0000 msec (27800000.0/sec): Char in 70-char line (8x13)
144000000 reps @ 0.0000 msec (27400000.0/sec): Char in 70-char line (8x13)
144000000 reps @ 0.0000 msec (27700000.0/sec): Char in 70-char line (8x13)
720000000 trep @ 0.0000 msec (27600000.0/sec): Char in 70-char line (8x13)
120000000 reps @ 0.0000 msec (24100000.0/sec): Char in 60-char line (9x15)
120000000 reps @ 0.0000 msec (23900000.0/sec): Char in 60-char line (9x15)
120000000 reps @ 0.0000 msec (23600000.0/sec): Char in 60-char line (9x15)
120000000 reps @ 0.0000 msec (24000000.0/sec): Char in 60-char line (9x15)
120000000 reps @ 0.0000 msec (23700000.0/sec): Char in 60-char line (9x15)
600000000 trep @ 0.0000 msec (23900000.0/sec): Char in 60-char line (9x15)
80000000 reps @ 0.0001 msec (15300000.0/sec): Char16 in 40-char line (k14)
80000000 reps @ 0.0001 msec (15400000.0/sec): Char16 in 40-char line (k14)
80000000 reps @ 0.0001 msec (15300000.0/sec): Char16 in 40-char line (k14)
80000000 reps @ 0.0001 msec (15400000.0/sec): Char16 in 40-char line (k14)
80000000 reps @ 0.0001 msec (15300000.0/sec): Char16 in 40-char line (k14)
400000000 trep @ 0.0001 msec (15300000.0/sec): Char16 in 40-char line (k14)
46000000 reps @ 0.0002 msec (6470000.0/sec): Char16 in 23-char line (k24)
46000000 reps @ 0.0002 msec (6460000.0/sec): Char16 in 23-char line (k24)
46000000 reps @ 0.0002 msec (6420000.0/sec): Char16 in 23-char line (k24)
46000000 reps @ 0.0002 msec (6470000.0/sec): Char16 in 23-char line (k24)
46000000 reps @ 0.0002 msec (6480000.0/sec): Char16 in 23-char line (k24)
230000000 trep @ 0.0002 msec (6460000.0/sec): Char16 in 23-char line (k24)
Could not load font '-adobe-times-medium-r-normal--10-100-75-75-p-54-iso8859-1', benchmark omitted
Could not load font '-adobe-times-medium-r-normal--24-240-75-75-p-124-iso8859-1', benchmark omitted
Could not load font '-adobe-times-medium-r-normal--10-100-75-75-p-54-iso8859-1', benchmark omitted
16800000 reps @ 0.0003 msec (3200000.0/sec): Char16 in 7/14/7 line (k14, k24)
16800000 reps @ 0.0003 msec (3250000.0/sec): Char16 in 7/14/7 line (k14, k24)
16800000 reps @ 0.0003 msec (3240000.0/sec): Char16 in 7/14/7 line (k14, k24)
16800000 reps @ 0.0003 msec (3240000.0/sec): Char16 in 7/14/7 line (k14, k24)
16800000 reps @ 0.0003 msec (3230000.0/sec): Char16 in 7/14/7 line (k14, k24)
84000000 trep @ 0.0003 msec (3230000.0/sec): Char16 in 7/14/7 line (k14, k24)
160000000 reps @ 0.0000 msec (30300000.0/sec): Char in 80-char image line (6x13)
160000000 reps @ 0.0000 msec (30100000.0/sec): Char in 80-char image line (6x13)
160000000 reps @ 0.0000 msec (30100000.0/sec): Char in 80-char image line (6x13)
160000000 reps @ 0.0000 msec (30300000.0/sec): Char in 80-char image line (6x13)
160000000 reps @ 0.0000 msec (30300000.0/sec): Char in 80-char image line (6x13)
800000000 trep @ 0.0000 msec (30200000.0/sec): Char in 80-char image line (6x13)
144000000 reps @ 0.0000 msec (27700000.0/sec): Char in 70-char image line (8x13)
144000000 reps @ 0.0000 msec (27500000.0/sec): Char in 70-char image line (8x13)
144000000 reps @ 0.0000 msec (27400000.0/sec): Char in 70-char image line (8x13)
144000000 reps @ 0.0000 msec (27100000.0/sec): Char in 70-char image line (8x13)
144000000 reps @ 0.0000 msec (27500000.0/sec): Char in 70-char image line (8x13)
720000000 trep @ 0.0000 msec (27400000.0/sec): Char in 70-char image line (8x13)
120000000 reps @ 0.0000 msec (23700000.0/sec): Char in 60-char image line (9x15)
120000000 reps @ 0.0000 msec (23600000.0/sec): Char in 60-char image line (9x15)
120000000 reps @ 0.0000 msec (23400000.0/sec): Char in 60-char image line (9x15)
120000000 reps @ 0.0000 msec (23500000.0/sec): Char in 60-char image line (9x15)
120000000 reps @ 0.0000 msec (23400000.0/sec): Char in 60-char image line (9x15)
600000000 trep @ 0.0000 msec (23500000.0/sec): Char in 60-char image line (9x15)
80000000 reps @ 0.0001 msec (15800000.0/sec): Char16 in 40-char image line (k14)
80000000 reps @ 0.0001 msec (15600000.0/sec): Char16 in 40-char image line (k14)
80000000 reps @ 0.0001 msec (15600000.0/sec): Char16 in 40-char image line (k14)
80000000 reps @ 0.0001 msec (15600000.0/sec): Char16 in 40-char image line (k14)
80000000 reps @ 0.0001 msec (15600000.0/sec): Char16 in 40-char image line (k14)
400000000 trep @ 0.0001 msec (15600000.0/sec): Char16 in 40-char image line (k14)
69000000 reps @ 0.0001 msec (9360000.0/sec): Char16 in 23-char image line (k24)
69000000 reps @ 0.0001 msec (9290000.0/sec): Char16 in 23-char image line (k24)
69000000 reps @ 0.0001 msec (9180000.0/sec): Char16 in 23-char image line (k24)
69000000 reps @ 0.0001 msec (9240000.0/sec): Char16 in 23-char image line (k24)
69000000 reps @ 0.0001 msec (9260000.0/sec): Char16 in 23-char image line (k24)
345000000 trep @ 0.0001 msec (9260000.0/sec): Char16 in 23-char image line (k24)
Could not load font '-adobe-times-medium-r-normal--10-100-75-75-p-54-iso8859-1', benchmark omitted
Could not load font '-adobe-times-medium-r-normal--24-240-75-75-p-124-iso8859-1', benchmark omitted
160000000 reps @ 0.0001 msec (17100000.0/sec): Char in 80-char aa line (Charter 10)
160000000 reps @ 0.0001 msec (17100000.0/sec): Char in 80-char aa line (Charter 10)
160000000 reps @ 0.0001 msec (17100000.0/sec): Char in 80-char aa line (Charter 10)
160000000 reps @ 0.0001 msec (17100000.0/sec): Char in 80-char aa line (Charter 10)
160000000 reps @ 0.0001 msec (17400000.0/sec): Char in 80-char aa line (Charter 10)
800000000 trep @ 0.0001 msec (17200000.0/sec): Char in 80-char aa line (Charter 10)
64000000 reps @ 0.0001 msec (7930000.0/sec): Char in 30-char aa line (Charter 24)
64000000 reps @ 0.0001 msec (7850000.0/sec): Char in 30-char aa line (Charter 24)
64000000 reps @ 0.0001 msec (7820000.0/sec): Char in 30-char aa line (Charter 24)
64000000 reps @ 0.0001 msec (7870000.0/sec): Char in 30-char aa line (Charter 24)
64000000 reps @ 0.0001 msec (7920000.0/sec): Char in 30-char aa line (Charter 24)
320000000 trep @ 0.0001 msec (7880000.0/sec): Char in 30-char aa line (Charter 24)
160000000 reps @ 0.0001 msec (17100000.0/sec): Char in 80-char aa line (Courier 12)
160000000 reps @ 0.0001 msec (17200000.0/sec): Char in 80-char aa line (Courier 12)
160000000 reps @ 0.0001 msec (17000000.0/sec): Char in 80-char aa line (Courier 12)
160000000 reps @ 0.0001 msec (17100000.0/sec): Char in 80-char aa line (Courier 12)
160000000 reps @ 0.0001 msec (17000000.0/sec): Char in 80-char aa line (Courier 12)
800000000 trep @ 0.0001 msec (17100000.0/sec): Char in 80-char aa line (Courier 12)
160000000 reps @ 0.0001 msec (17200000.0/sec): Char in 80-char a line (Charter 10)
160000000 reps @ 0.0001 msec (17200000.0/sec): Char in 80-char a line (Charter 10)
160000000 reps @ 0.0001 msec (17100000.0/sec): Char in 80-char a line (Charter 10)
160000000 reps @ 0.0001 msec (17000000.0/sec): Char in 80-char a line (Charter 10)
160000000 reps @ 0.0001 msec (17000000.0/sec): Char in 80-char a line (Charter 10)
800000000 trep @ 0.0001 msec (17100000.0/sec): Char in 80-char a line (Charter 10)
64000000 reps @ 0.0001 msec (7880000.0/sec): Char in 30-char a line (Charter 24)
64000000 reps @ 0.0001 msec (7790000.0/sec): Char in 30-char a line (Charter 24)
64000000 reps @ 0.0001 msec (7830000.0/sec): Char in 30-char a line (Charter 24)
64000000 reps @ 0.0001 msec (7890000.0/sec): Char in 30-char a line (Charter 24)
64000000 reps @ 0.0001 msec (7790000.0/sec): Char in 30-char a line (Charter 24)
320000000 trep @ 0.0001 msec (7840000.0/sec): Char in 30-char a line (Charter 24)
160000000 reps @ 0.0001 msec (17000000.0/sec): Char in 80-char a line (Courier 12)
160000000 reps @ 0.0001 msec (17400000.0/sec): Char in 80-char a line (Courier 12)
160000000 reps @ 0.0001 msec (17300000.0/sec): Char in 80-char a line (Courier 12)
160000000 reps @ 0.0001 msec (17100000.0/sec): Char in 80-char a line (Courier 12)
160000000 reps @ 0.0001 msec (17200000.0/sec): Char in 80-char a line (Courier 12)
800000000 trep @ 0.0001 msec (17200000.0/sec): Char in 80-char a line (Courier 12)
160000000 reps @ 0.0000 msec (23200000.0/sec): Char in 80-char rgb line (Charter 10)
160000000 reps @ 0.0000 msec (23400000.0/sec): Char in 80-char rgb line (Charter 10)
160000000 reps @ 0.0000 msec (23600000.0/sec): Char in 80-char rgb line (Charter 10)
160000000 reps @ 0.0000 msec (23500000.0/sec): Char in 80-char rgb line (Charter 10)
160000000 reps @ 0.0000 msec (23400000.0/sec): Char in 80-char rgb line (Charter 10)
800000000 trep @ 0.0000 msec (23400000.0/sec): Char in 80-char rgb line (Charter 10)
64000000 reps @ 0.0001 msec (11300000.0/sec): Char in 30-char rgb line (Charter 24)
64000000 reps @ 0.0001 msec (11300000.0/sec): Char in 30-char rgb line (Charter 24)
64000000 reps @ 0.0001 msec (11300000.0/sec): Char in 30-char rgb line (Charter 24)
64000000 reps @ 0.0001 msec (11500000.0/sec): Char in 30-char rgb line (Charter 24)
64000000 reps @ 0.0001 msec (11300000.0/sec): Char in 30-char rgb line (Charter 24)
320000000 trep @ 0.0001 msec (11400000.0/sec): Char in 30-char rgb line (Charter 24)
160000000 reps @ 0.0000 msec (22300000.0/sec): Char in 80-char rgb line (Courier 12)
160000000 reps @ 0.0000 msec (22100000.0/sec): Char in 80-char rgb line (Courier 12)
160000000 reps @ 0.0000 msec (22500000.0/sec): Char in 80-char rgb line (Courier 12)
160000000 reps @ 0.0000 msec (22700000.0/sec): Char in 80-char rgb line (Courier 12)
160000000 reps @ 0.0000 msec (22700000.0/sec): Char in 80-char rgb line (Courier 12)
800000000 trep @ 0.0000 msec (22500000.0/sec): Char in 80-char rgb line (Courier 12)
Could not load font 'charter:antialias=true:render=false:rgba=0:pixelsize=10', benchmark omitted
Could not load font 'charter:antialias=true:render=false:rgba=0:pixelsize=24', benchmark omitted
Could not load font 'courier:antialias=true:render=false:rgba=0:pixelsize=12', benchmark omitted
Could not load font 'charter:antialias=false:render=false:rgba=0:pixelsize=10', benchmark omitted
Could not load font 'charter:antialias=false:render=false:rgba=0:pixelsize=24', benchmark omitted
Could not load font 'courier:antialias=false:render=false:rgba=0:pixelsize=12', benchmark omitted
Could not load font 'charter:antialias=true:render=false:rgba=rgb:pixelsize=10', benchmark omitted
Could not load font 'charter:antialias=true:render=false:rgba=rgb:pixelsize=24', benchmark omitted
Could not load font 'courier:antialias=true:render=false:rgba=rgb:pixelsize=12', benchmark omitted
60000 reps @ 0.0949 msec ( 10500.0/sec): Scroll 500x500 pixels
60000 reps @ 0.0938 msec ( 10700.0/sec): Scroll 500x500 pixels
60000 reps @ 0.0925 msec ( 10800.0/sec): Scroll 500x500 pixels
60000 reps @ 0.0918 msec ( 10900.0/sec): Scroll 500x500 pixels
60000 reps @ 0.0919 msec ( 10900.0/sec): Scroll 500x500 pixels
300000 trep @ 0.0930 msec ( 10800.0/sec): Scroll 500x500 pixels
80000 reps @ 0.0886 msec ( 11300.0/sec): Copy 500x500 from window to window
80000 reps @ 0.0886 msec ( 11300.0/sec): Copy 500x500 from window to window
80000 reps @ 0.0883 msec ( 11300.0/sec): Copy 500x500 from window to window
80000 reps @ 0.0881 msec ( 11300.0/sec): Copy 500x500 from window to window
80000 reps @ 0.0883 msec ( 11300.0/sec): Copy 500x500 from window to window
400000 trep @ 0.0884 msec ( 11300.0/sec): Copy 500x500 from window to window
160000 reps @ 0.0324 msec ( 30900.0/sec): Copy 500x500 from pixmap to window
160000 reps @ 0.0323 msec ( 30900.0/sec): Copy 500x500 from pixmap to window
160000 reps @ 0.0323 msec ( 30900.0/sec): Copy 500x500 from pixmap to window
160000 reps @ 0.0324 msec ( 30900.0/sec): Copy 500x500 from pixmap to window
160000 reps @ 0.0323 msec ( 30900.0/sec): Copy 500x500 from pixmap to window
800000 trep @ 0.0323 msec ( 30900.0/sec): Copy 500x500 from pixmap to window
160000 reps @ 0.0386 msec ( 25900.0/sec): Copy 500x500 from window to pixmap
160000 reps @ 0.0386 msec ( 25900.0/sec): Copy 500x500 from window to pixmap
160000 reps @ 0.0386 msec ( 25900.0/sec): Copy 500x500 from window to pixmap
160000 reps @ 0.0386 msec ( 25900.0/sec): Copy 500x500 from window to pixmap
160000 reps @ 0.0386 msec ( 25900.0/sec): Copy 500x500 from window to pixmap
800000 trep @ 0.0386 msec ( 25900.0/sec): Copy 500x500 from window to pixmap
80000 reps @ 0.0633 msec ( 15800.0/sec): Copy 500x500 from pixmap to pixmap
80000 reps @ 0.0635 msec ( 15800.0/sec): Copy 500x500 from pixmap to pixmap
80000 reps @ 0.0638 msec ( 15700.0/sec): Copy 500x500 from pixmap to pixmap
80000 reps @ 0.0643 msec ( 15500.0/sec): Copy 500x500 from pixmap to pixmap
80000 reps @ 0.0653 msec ( 15300.0/sec): Copy 500x500 from pixmap to pixmap
400000 trep @ 0.0640 msec ( 15600.0/sec): Copy 500x500 from pixmap to pixmap
12000 reps @ 0.3977 msec ( 2510.0/sec): Copy 500x500 1-bit deep plane
12000 reps @ 0.3799 msec ( 2630.0/sec): Copy 500x500 1-bit deep plane
12000 reps @ 0.3826 msec ( 2610.0/sec): Copy 500x500 1-bit deep plane
12000 reps @ 0.3792 msec ( 2640.0/sec): Copy 500x500 1-bit deep plane
12000 reps @ 0.3797 msec ( 2630.0/sec): Copy 500x500 1-bit deep plane
60000 trep @ 0.3838 msec ( 2610.0/sec): Copy 500x500 1-bit deep plane
160000 reps @ 0.0322 msec ( 31100.0/sec): Copy 500x500 n-bit deep plane
160000 reps @ 0.0322 msec ( 31100.0/sec): Copy 500x500 n-bit deep plane
160000 reps @ 0.0322 msec ( 31100.0/sec): Copy 500x500 n-bit deep plane
160000 reps @ 0.0322 msec ( 31100.0/sec): Copy 500x500 n-bit deep plane
160000 reps @ 0.0322 msec ( 31000.0/sec): Copy 500x500 n-bit deep plane
800000 trep @ 0.0322 msec ( 31100.0/sec): Copy 500x500 n-bit deep plane
12000 reps @ 0.5797 msec ( 1720.0/sec): PutImage 500x500 square
12000 reps @ 0.5912 msec ( 1690.0/sec): PutImage 500x500 square
12000 reps @ 0.5852 msec ( 1710.0/sec): PutImage 500x500 square
12000 reps @ 0.5863 msec ( 1710.0/sec): PutImage 500x500 square
12000 reps @ 0.5853 msec ( 1710.0/sec): PutImage 500x500 square
60000 trep @ 0.5856 msec ( 1710.0/sec): PutImage 500x500 square
800 reps @ 9.3424 msec ( 107.0/sec): PutImage XY 500x500 square
800 reps @ 9.3531 msec ( 107.0/sec): PutImage XY 500x500 square
800 reps @ 9.4013 msec ( 106.0/sec): PutImage XY 500x500 square
800 reps @ 9.4017 msec ( 106.0/sec): PutImage XY 500x500 square
800 reps @ 9.3881 msec ( 107.0/sec): PutImage XY 500x500 square
4000 trep @ 9.3773 msec ( 107.0/sec): PutImage XY 500x500 square
32000 reps @ 0.1625 msec ( 6150.0/sec): ShmPutImage 500x500 square
32000 reps @ 0.1661 msec ( 6020.0/sec): ShmPutImage 500x500 square
32000 reps @ 0.1674 msec ( 5970.0/sec): ShmPutImage 500x500 square
32000 reps @ 0.1667 msec ( 6000.0/sec): ShmPutImage 500x500 square
32000 reps @ 0.1631 msec ( 6130.0/sec): ShmPutImage 500x500 square
160000 trep @ 0.1652 msec ( 6060.0/sec): ShmPutImage 500x500 square
800 reps @ 7.4042 msec ( 135.0/sec): ShmPutImage XY 500x500 square
800 reps @ 7.4317 msec ( 135.0/sec): ShmPutImage XY 500x500 square
800 reps @ 7.3998 msec ( 135.0/sec): ShmPutImage XY 500x500 square
800 reps @ 7.4415 msec ( 134.0/sec): ShmPutImage XY 500x500 square
800 reps @ 7.4072 msec ( 135.0/sec): ShmPutImage XY 500x500 square
4000 trep @ 7.4169 msec ( 135.0/sec): ShmPutImage XY 500x500 square
80000 reps @ 0.0868 msec ( 11500.0/sec): ShmGetImage 500x500 square
80000 reps @ 0.0875 msec ( 11400.0/sec): ShmGetImage 500x500 square
80000 reps @ 0.0886 msec ( 11300.0/sec): ShmGetImage 500x500 square
80000 reps @ 0.0884 msec ( 11300.0/sec): ShmGetImage 500x500 square
80000 reps @ 0.0872 msec ( 11500.0/sec): ShmGetImage 500x500 square
400000 trep @ 0.0877 msec ( 11400.0/sec): ShmGetImage 500x500 square
320 reps @ 17.4602 msec ( 57.3/sec): ShmGetImage XY 500x500 square
320 reps @ 17.6852 msec ( 56.5/sec): ShmGetImage XY 500x500 square
320 reps @ 17.6235 msec ( 56.7/sec): ShmGetImage XY 500x500 square
320 reps @ 17.7961 msec ( 56.2/sec): ShmGetImage XY 500x500 square
320 reps @ 17.6269 msec ( 56.7/sec): ShmGetImage XY 500x500 square
1600 trep @ 17.6384 msec ( 56.7/sec): ShmGetImage XY 500x500 square
12000 reps @ 0.5246 msec ( 1910.0/sec): GetImage 500x500 square
12000 reps @ 0.5250 msec ( 1900.0/sec): GetImage 500x500 square
12000 reps @ 0.5204 msec ( 1920.0/sec): GetImage 500x500 square
12000 reps @ 0.5215 msec ( 1920.0/sec): GetImage 500x500 square
12000 reps @ 0.5221 msec ( 1920.0/sec): GetImage 500x500 square
60000 trep @ 0.5227 msec ( 1910.0/sec): GetImage 500x500 square
320 reps @ 16.9859 msec ( 58.9/sec): GetImage XY 500x500 square
320 reps @ 17.2835 msec ( 57.9/sec): GetImage XY 500x500 square
320 reps @ 17.4346 msec ( 57.4/sec): GetImage XY 500x500 square
320 reps @ 17.1519 msec ( 58.3/sec): GetImage XY 500x500 square
320 reps @ 17.1147 msec ( 58.4/sec): GetImage XY 500x500 square
1600 trep @ 17.1941 msec ( 58.2/sec): GetImage XY 500x500 square
80000 reps @ 0.0918 msec ( 10900.0/sec): Composite 500x500 from window to window
80000 reps @ 0.0902 msec ( 11100.0/sec): Composite 500x500 from window to window
80000 reps @ 0.0891 msec ( 11200.0/sec): Composite 500x500 from window to window
80000 reps @ 0.0887 msec ( 11300.0/sec): Composite 500x500 from window to window
80000 reps @ 0.0885 msec ( 11300.0/sec): Composite 500x500 from window to window
400000 trep @ 0.0896 msec ( 11200.0/sec): Composite 500x500 from window to window
160000 reps @ 0.0324 msec ( 30900.0/sec): Composite 500x500 from pixmap to window
160000 reps @ 0.0323 msec ( 30900.0/sec): Composite 500x500 from pixmap to window
160000 reps @ 0.0324 msec ( 30900.0/sec): Composite 500x500 from pixmap to window
160000 reps @ 0.0324 msec ( 30900.0/sec): Composite 500x500 from pixmap to window
160000 reps @ 0.0324 msec ( 30900.0/sec): Composite 500x500 from pixmap to window
800000 trep @ 0.0324 msec ( 30900.0/sec): Composite 500x500 from pixmap to window
160000 reps @ 0.0320 msec ( 31200.0/sec): Scale 250x250 from pixmap to 500x500 window
160000 reps @ 0.0320 msec ( 31200.0/sec): Scale 250x250 from pixmap to 500x500 window
160000 reps @ 0.0321 msec ( 31200.0/sec): Scale 250x250 from pixmap to 500x500 window
160000 reps @ 0.0321 msec ( 31200.0/sec): Scale 250x250 from pixmap to 500x500 window
160000 reps @ 0.0321 msec ( 31200.0/sec): Scale 250x250 from pixmap to 500x500 window
800000 trep @ 0.0321 msec ( 31200.0/sec): Scale 250x250 from pixmap to 500x500 window
800000 reps @ 0.0083 msec (121000.0/sec): Scale 500x500 from pixmap to 250x250 window
800000 reps @ 0.0083 msec (121000.0/sec): Scale 500x500 from pixmap to 250x250 window
800000 reps @ 0.0083 msec (121000.0/sec): Scale 500x500 from pixmap to 250x250 window
800000 reps @ 0.0083 msec (121000.0/sec): Scale 500x500 from pixmap to 250x250 window
800000 reps @ 0.0083 msec (121000.0/sec): Scale 500x500 from pixmap to 250x250 window
4000000 trep @ 0.0083 msec (121000.0/sec): Scale 500x500 from pixmap to 250x250 window
600000000 reps @ 0.0000 msec (97000000.0/sec): X protocol NoOperation
600000000 reps @ 0.0000 msec (96300000.0/sec): X protocol NoOperation
600000000 reps @ 0.0000 msec (95600000.0/sec): X protocol NoOperation
600000000 reps @ 0.0000 msec (98500000.0/sec): X protocol NoOperation
600000000 reps @ 0.0000 msec (96100000.0/sec): X protocol NoOperation
3000000000 trep @ 0.0000 msec (96700000.0/sec): X protocol NoOperation
200000 reps @ 0.0393 msec ( 25400.0/sec): QueryPointer
200000 reps @ 0.0391 msec ( 25600.0/sec): QueryPointer
200000 reps @ 0.0394 msec ( 25400.0/sec): QueryPointer
200000 reps @ 0.0390 msec ( 25700.0/sec): QueryPointer
200000 reps @ 0.0388 msec ( 25800.0/sec): QueryPointer
1000000 trep @ 0.0391 msec ( 25600.0/sec): QueryPointer
200000 reps @ 0.0450 msec ( 22200.0/sec): GetProperty
200000 reps @ 0.0452 msec ( 22100.0/sec): GetProperty
200000 reps @ 0.0453 msec ( 22100.0/sec): GetProperty
200000 reps @ 0.0452 msec ( 22100.0/sec): GetProperty
200000 reps @ 0.0459 msec ( 21800.0/sec): GetProperty
1000000 trep @ 0.0453 msec ( 22100.0/sec): GetProperty
3200000 reps @ 0.0017 msec (586000.0/sec): Change graphics context
3200000 reps @ 0.0017 msec (588000.0/sec): Change graphics context
3200000 reps @ 0.0017 msec (588000.0/sec): Change graphics context
3200000 reps @ 0.0017 msec (584000.0/sec): Change graphics context
3200000 reps @ 0.0017 msec (584000.0/sec): Change graphics context
16000000 trep @ 0.0017 msec (586000.0/sec): Change graphics context
2400 reps @ 0.0044 msec (228000.0/sec): Create and map subwindows (4 kids)
2400 reps @ 0.0061 msec (163000.0/sec): Create and map subwindows (4 kids)
2400 reps @ 0.0050 msec (201000.0/sec): Create and map subwindows (4 kids)
2400 reps @ 0.0055 msec (181000.0/sec): Create and map subwindows (4 kids)
2400 reps @ 0.0053 msec (189000.0/sec): Create and map subwindows (4 kids)
12000 trep @ 0.0053 msec (190000.0/sec): Create and map subwindows (4 kids)
2400 reps @ 0.0023 msec (439000.0/sec): Create and map subwindows (16 kids)
2400 reps @ 0.0053 msec (190000.0/sec): Create and map subwindows (16 kids)
2400 reps @ 0.0058 msec (173000.0/sec): Create and map subwindows (16 kids)
2400 reps @ 0.0052 msec (193000.0/sec): Create and map subwindows (16 kids)
2400 reps @ 0.0053 msec (190000.0/sec): Create and map subwindows (16 kids)
12000 trep @ 0.0047 msec (211000.0/sec): Create and map subwindows (16 kids)
2500 reps @ 0.0025 msec (396000.0/sec): Create and map subwindows (25 kids)
2500 reps @ 0.0068 msec (148000.0/sec): Create and map subwindows (25 kids)
2500 reps @ 0.0039 msec (254000.0/sec): Create and map subwindows (25 kids)
2500 reps @ 0.0064 msec (157000.0/sec): Create and map subwindows (25 kids)
2500 reps @ 0.0076 msec (132000.0/sec): Create and map subwindows (25 kids)
12500 trep @ 0.0054 msec (184000.0/sec): Create and map subwindows (25 kids)
2500 reps @ 0.0027 msec (364000.0/sec): Create and map subwindows (50 kids)
2500 reps @ 0.0050 msec (200000.0/sec): Create and map subwindows (50 kids)
2500 reps @ 0.0060 msec (166000.0/sec): Create and map subwindows (50 kids)
2500 reps @ 0.0078 msec (129000.0/sec): Create and map subwindows (50 kids)
2500 reps @ 0.0057 msec (175000.0/sec): Create and map subwindows (50 kids)
12500 trep @ 0.0055 msec (183000.0/sec): Create and map subwindows (50 kids)
2400 reps @ 0.0049 msec (202000.0/sec): Create and map subwindows (75 kids)
2400 reps @ 0.0054 msec (184000.0/sec): Create and map subwindows (75 kids)
2400 reps @ 0.0055 msec (182000.0/sec): Create and map subwindows (75 kids)
2400 reps @ 0.0054 msec (186000.0/sec): Create and map subwindows (75 kids)
2400 reps @ 0.0057 msec (177000.0/sec): Create and map subwindows (75 kids)
12000 trep @ 0.0054 msec (186000.0/sec): Create and map subwindows (75 kids)
2400 reps @ 0.0071 msec (140000.0/sec): Create and map subwindows (100 kids)
2400 reps @ 0.0036 msec (276000.0/sec): Create and map subwindows (100 kids)
2400 reps @ 0.0050 msec (201000.0/sec): Create and map subwindows (100 kids)
2400 reps @ 0.0063 msec (158000.0/sec): Create and map subwindows (100 kids)
2400 reps @ 0.0079 msec (126000.0/sec): Create and map subwindows (100 kids)
12000 trep @ 0.0060 msec (167000.0/sec): Create and map subwindows (100 kids)
2400 reps @ 0.0029 msec (342000.0/sec): Create and map subwindows (200 kids)
2400 reps @ 0.0062 msec (161000.0/sec): Create and map subwindows (200 kids)
2400 reps @ 0.0060 msec (168000.0/sec): Create and map subwindows (200 kids)
2400 reps @ 0.0078 msec (128000.0/sec): Create and map subwindows (200 kids)
2400 reps @ 0.0064 msec (156000.0/sec): Create and map subwindows (200 kids)
12000 trep @ 0.0059 msec (171000.0/sec): Create and map subwindows (200 kids)
2400 reps @ 0.0006 msec (1580000.0/sec): Create unmapped window (4 kids)
2400 reps @ 0.0011 msec (896000.0/sec): Create unmapped window (4 kids)
2400 reps @ 0.0014 msec (722000.0/sec): Create unmapped window (4 kids)
2400 reps @ 0.0013 msec (750000.0/sec): Create unmapped window (4 kids)
2400 reps @ 0.0016 msec (632000.0/sec): Create unmapped window (4 kids)
12000 trep @ 0.0012 msec (827000.0/sec): Create unmapped window (4 kids)
2400 reps @ 0.0004 msec (2240000.0/sec): Create unmapped window (16 kids)
2400 reps @ 0.0013 msec (753000.0/sec): Create unmapped window (16 kids)
2400 reps @ 0.0012 msec (804000.0/sec): Create unmapped window (16 kids)
2400 reps @ 0.0016 msec (635000.0/sec): Create unmapped window (16 kids)
2400 reps @ 0.0014 msec (714000.0/sec): Create unmapped window (16 kids)
12000 trep @ 0.0012 msec (834000.0/sec): Create unmapped window (16 kids)
2500 reps @ 0.0012 msec (813000.0/sec): Create unmapped window (25 kids)
2500 reps @ 0.0012 msec (807000.0/sec): Create unmapped window (25 kids)
2500 reps @ 0.0012 msec (825000.0/sec): Create unmapped window (25 kids)
2500 reps @ 0.0013 msec (761000.0/sec): Create unmapped window (25 kids)
2500 reps @ 0.0012 msec (819000.0/sec): Create unmapped window (25 kids)
12500 trep @ 0.0012 msec (804000.0/sec): Create unmapped window (25 kids)
2500 reps @ 0.0011 msec (924000.0/sec): Create unmapped window (50 kids)
2500 reps @ 0.0013 msec (789000.0/sec): Create unmapped window (50 kids)
2500 reps @ 0.0013 msec (800000.0/sec): Create unmapped window (50 kids)
2500 reps @ 0.0013 msec (773000.0/sec): Create unmapped window (50 kids)
2500 reps @ 0.0013 msec (781000.0/sec): Create unmapped window (50 kids)
12500 trep @ 0.0012 msec (810000.0/sec): Create unmapped window (50 kids)
2400 reps @ 0.0013 msec (791000.0/sec): Create unmapped window (75 kids)
2400 reps @ 0.0012 msec (802000.0/sec): Create unmapped window (75 kids)
2400 reps @ 0.0012 msec (821000.0/sec): Create unmapped window (75 kids)
2400 reps @ 0.0013 msec (748000.0/sec): Create unmapped window (75 kids)
2400 reps @ 0.0012 msec (816000.0/sec): Create unmapped window (75 kids)
12000 trep @ 0.0013 msec (795000.0/sec): Create unmapped window (75 kids)
2400 reps @ 0.0010 msec (1010000.0/sec): Create unmapped window (100 kids)
2400 reps @ 0.0012 msec (826000.0/sec): Create unmapped window (100 kids)
2400 reps @ 0.0012 msec (824000.0/sec): Create unmapped window (100 kids)
2400 reps @ 0.0013 msec (746000.0/sec): Create unmapped window (100 kids)
2400 reps @ 0.0012 msec (854000.0/sec): Create unmapped window (100 kids)
12000 trep @ 0.0012 msec (844000.0/sec): Create unmapped window (100 kids)
2400 reps @ 0.0015 msec (681000.0/sec): Create unmapped window (200 kids)
2400 reps @ 0.0013 msec (754000.0/sec): Create unmapped window (200 kids)
2400 reps @ 0.0012 msec (836000.0/sec): Create unmapped window (200 kids)
2400 reps @ 0.0015 msec (670000.0/sec): Create unmapped window (200 kids)
2400 reps @ 0.0014 msec (709000.0/sec): Create unmapped window (200 kids)
12000 trep @ 0.0014 msec (725000.0/sec): Create unmapped window (200 kids)
2400 reps @ 0.0064 msec (157000.0/sec): Map window via parent (4 kids)
2400 reps @ 0.0076 msec (131000.0/sec): Map window via parent (4 kids)
2400 reps @ 0.0092 msec (109000.0/sec): Map window via parent (4 kids)
2400 reps @ 0.0038 msec (266000.0/sec): Map window via parent (4 kids)
2400 reps @ 0.0053 msec (187000.0/sec): Map window via parent (4 kids)
12000 trep @ 0.0064 msec (155000.0/sec): Map window via parent (4 kids)
2400 reps @ 0.0028 msec (358000.0/sec): Map window via parent (16 kids)
2400 reps @ 0.0051 msec (197000.0/sec): Map window via parent (16 kids)
2400 reps @ 0.0054 msec (185000.0/sec): Map window via parent (16 kids)
2400 reps @ 0.0086 msec (116000.0/sec): Map window via parent (16 kids)
2400 reps @ 0.0065 msec (153000.0/sec): Map window via parent (16 kids)
12000 trep @ 0.0057 msec (176000.0/sec): Map window via parent (16 kids)
2500 reps @ 0.0038 msec (261000.0/sec): Map window via parent (25 kids)
2500 reps @ 0.0054 msec (187000.0/sec): Map window via parent (25 kids)
2500 reps @ 0.0073 msec (136000.0/sec): Map window via parent (25 kids)
2500 reps @ 0.0065 msec (153000.0/sec): Map window via parent (25 kids)
2500 reps @ 0.0042 msec (237000.0/sec): Map window via parent (25 kids)
12500 trep @ 0.0055 msec (183000.0/sec): Map window via parent (25 kids)
2500 reps @ 0.0038 msec (262000.0/sec): Map window via parent (50 kids)
2500 reps @ 0.0028 msec (361000.0/sec): Map window via parent (50 kids)
2500 reps @ 0.0051 msec (197000.0/sec): Map window via parent (50 kids)
2500 reps @ 0.0054 msec (186000.0/sec): Map window via parent (50 kids)
2500 reps @ 0.0071 msec (141000.0/sec): Map window via parent (50 kids)
12500 trep @ 0.0048 msec (207000.0/sec): Map window via parent (50 kids)
2400 reps @ 0.0029 msec (341000.0/sec): Map window via parent (75 kids)
2400 reps @ 0.0053 msec (188000.0/sec): Map window via parent (75 kids)
2400 reps @ 0.0055 msec (181000.0/sec): Map window via parent (75 kids)
2400 reps @ 0.0075 msec (134000.0/sec): Map window via parent (75 kids)
2400 reps @ 0.0068 msec (146000.0/sec): Map window via parent (75 kids)
12000 trep @ 0.0056 msec (178000.0/sec): Map window via parent (75 kids)
2400 reps @ 0.0050 msec (200000.0/sec): Map window via parent (100 kids)
2400 reps @ 0.0088 msec (113000.0/sec): Map window via parent (100 kids)
2400 reps @ 0.0064 msec (155000.0/sec): Map window via parent (100 kids)
2400 reps @ 0.0048 msec (209000.0/sec): Map window via parent (100 kids)
2400 reps @ 0.0055 msec (182000.0/sec): Map window via parent (100 kids)
12000 trep @ 0.0061 msec (164000.0/sec): Map window via parent (100 kids)
2400 reps @ 0.0028 msec (354000.0/sec): Map window via parent (200 kids)
2400 reps @ 0.0055 msec (182000.0/sec): Map window via parent (200 kids)
2400 reps @ 0.0056 msec (179000.0/sec): Map window via parent (200 kids)
2400 reps @ 0.0076 msec (131000.0/sec): Map window via parent (200 kids)
2400 reps @ 0.0079 msec (126000.0/sec): Map window via parent (200 kids)
12000 trep @ 0.0059 msec (170000.0/sec): Map window via parent (200 kids)
2400 reps @ 0.0010 msec (985000.0/sec): Unmap window via parent (4 kids)
2400 reps @ 0.0019 msec (538000.0/sec): Unmap window via parent (4 kids)
2400 reps @ 0.0019 msec (533000.0/sec): Unmap window via parent (4 kids)
2400 reps @ 0.0023 msec (435000.0/sec): Unmap window via parent (4 kids)
2400 reps @ 0.0022 msec (463000.0/sec): Unmap window via parent (4 kids)
12000 trep @ 0.0018 msec (543000.0/sec): Unmap window via parent (4 kids)
2400 reps @ 0.0006 msec (1600000.0/sec): Unmap window via parent (16 kids)
2400 reps @ 0.0011 msec (902000.0/sec): Unmap window via parent (16 kids)
2400 reps @ 0.0019 msec (530000.0/sec): Unmap window via parent (16 kids)
2400 reps @ 0.0018 msec (547000.0/sec): Unmap window via parent (16 kids)
2400 reps @ 0.0005 msec (1840000.0/sec): Unmap window via parent (16 kids)
12000 trep @ 0.0012 msec (835000.0/sec): Unmap window via parent (16 kids)
2500 reps @ 0.0005 msec (1900000.0/sec): Unmap window via parent (25 kids)
2500 reps @ 0.0012 msec (829000.0/sec): Unmap window via parent (25 kids)
2500 reps @ 0.0014 msec (722000.0/sec): Unmap window via parent (25 kids)
2500 reps @ 0.0016 msec (634000.0/sec): Unmap window via parent (25 kids)
2500 reps @ 0.0006 msec (1720000.0/sec): Unmap window via parent (25 kids)
12500 trep @ 0.0011 msec (948000.0/sec): Unmap window via parent (25 kids)
2500 reps @ 0.0009 msec (1070000.0/sec): Unmap window via parent (50 kids)
2500 reps @ 0.0005 msec (2080000.0/sec): Unmap window via parent (50 kids)
2500 reps @ 0.0011 msec (940000.0/sec): Unmap window via parent (50 kids)
2500 reps @ 0.0012 msec (834000.0/sec): Unmap window via parent (50 kids)
2500 reps @ 0.0017 msec (599000.0/sec): Unmap window via parent (50 kids)
12500 trep @ 0.0011 msec (936000.0/sec): Unmap window via parent (50 kids)
2400 reps @ 0.0006 msec (1630000.0/sec): Unmap window via parent (75 kids)
2400 reps @ 0.0005 msec (1950000.0/sec): Unmap window via parent (75 kids)
2400 reps @ 0.0010 msec (978000.0/sec): Unmap window via parent (75 kids)
2400 reps @ 0.0010 msec (1030000.0/sec): Unmap window via parent (75 kids)
2400 reps @ 0.0009 msec (1090000.0/sec): Unmap window via parent (75 kids)
12000 trep @ 0.0008 msec (1240000.0/sec): Unmap window via parent (75 kids)
2400 reps @ 0.0004 msec (2510000.0/sec): Unmap window via parent (100 kids)
2400 reps @ 0.0009 msec (1160000.0/sec): Unmap window via parent (100 kids)
2400 reps @ 0.0013 msec (750000.0/sec): Unmap window via parent (100 kids)
2400 reps @ 0.0012 msec (826000.0/sec): Unmap window via parent (100 kids)
2400 reps @ 0.0010 msec (1010000.0/sec): Unmap window via parent (100 kids)
12000 trep @ 0.0010 msec (1040000.0/sec): Unmap window via parent (100 kids)
2400 reps @ 0.0012 msec (846000.0/sec): Unmap window via parent (200 kids)
2400 reps @ 0.0014 msec (736000.0/sec): Unmap window via parent (200 kids)
2400 reps @ 0.0011 msec (937000.0/sec): Unmap window via parent (200 kids)
2400 reps @ 0.0004 msec (2250000.0/sec): Unmap window via parent (200 kids)
2400 reps @ 0.0012 msec (845000.0/sec): Unmap window via parent (200 kids)
12000 trep @ 0.0010 msec (955000.0/sec): Unmap window via parent (200 kids)
2400 reps @ 0.0014 msec (728000.0/sec): Destroy window via parent (4 kids)
2400 reps @ 0.0019 msec (536000.0/sec): Destroy window via parent (4 kids)
2400 reps @ 0.0021 msec (480000.0/sec): Destroy window via parent (4 kids)
2400 reps @ 0.0025 msec (407000.0/sec): Destroy window via parent (4 kids)
2400 reps @ 0.0020 msec (495000.0/sec): Destroy window via parent (4 kids)
12000 trep @ 0.0020 msec (510000.0/sec): Destroy window via parent (4 kids)
2400 reps @ 0.0013 msec (790000.0/sec): Destroy window via parent (16 kids)
2400 reps @ 0.0017 msec (573000.0/sec): Destroy window via parent (16 kids)
2400 reps @ 0.0037 msec (269000.0/sec): Destroy window via parent (16 kids)
2400 reps @ 0.0024 msec (418000.0/sec): Destroy window via parent (16 kids)
2400 reps @ 0.0018 msec (551000.0/sec): Destroy window via parent (16 kids)
12000 trep @ 0.0022 msec (457000.0/sec): Destroy window via parent (16 kids)
2500 reps @ 0.0007 msec (1460000.0/sec): Destroy window via parent (25 kids)
2500 reps @ 0.0013 msec (766000.0/sec): Destroy window via parent (25 kids)
2500 reps @ 0.0018 msec (549000.0/sec): Destroy window via parent (25 kids)
2500 reps @ 0.0008 msec (1320000.0/sec): Destroy window via parent (25 kids)
2500 reps @ 0.0015 msec (665000.0/sec): Destroy window via parent (25 kids)
12500 trep @ 0.0012 msec (823000.0/sec): Destroy window via parent (25 kids)
2500 reps @ 0.0007 msec (1440000.0/sec): Destroy window via parent (50 kids)
2500 reps @ 0.0012 msec (830000.0/sec): Destroy window via parent (50 kids)
2500 reps @ 0.0019 msec (536000.0/sec): Destroy window via parent (50 kids)
2500 reps @ 0.0016 msec (644000.0/sec): Destroy window via parent (50 kids)
2500 reps @ 0.0015 msec (683000.0/sec): Destroy window via parent (50 kids)
12500 trep @ 0.0014 msec (737000.0/sec): Destroy window via parent (50 kids)
2400 reps @ 0.0006 msec (1800000.0/sec): Destroy window via parent (75 kids)
2400 reps @ 0.0012 msec (837000.0/sec): Destroy window via parent (75 kids)
2400 reps @ 0.0016 msec (610000.0/sec): Destroy window via parent (75 kids)
2400 reps @ 0.0015 msec (648000.0/sec): Destroy window via parent (75 kids)
2400 reps @ 0.0016 msec (609000.0/sec): Destroy window via parent (75 kids)
12000 trep @ 0.0013 msec (760000.0/sec): Destroy window via parent (75 kids)
2400 reps @ 0.0007 msec (1350000.0/sec): Destroy window via parent (100 kids)
2400 reps @ 0.0015 msec (685000.0/sec): Destroy window via parent (100 kids)
2400 reps @ 0.0014 msec (694000.0/sec): Destroy window via parent (100 kids)
2400 reps @ 0.0015 msec (647000.0/sec): Destroy window via parent (100 kids)
2400 reps @ 0.0011 msec (894000.0/sec): Destroy window via parent (100 kids)
12000 trep @ 0.0013 msec (793000.0/sec): Destroy window via parent (100 kids)
2400 reps @ 0.0010 msec (965000.0/sec): Destroy window via parent (200 kids)
2400 reps @ 0.0007 msec (1510000.0/sec): Destroy window via parent (200 kids)
2400 reps @ 0.0015 msec (661000.0/sec): Destroy window via parent (200 kids)
2400 reps @ 0.0016 msec (632000.0/sec): Destroy window via parent (200 kids)
2400 reps @ 0.0006 msec (1780000.0/sec): Destroy window via parent (200 kids)
12000 trep @ 0.0011 msec (934000.0/sec): Destroy window via parent (200 kids)
1600000 reps @ 0.0040 msec (250000.0/sec): Hide/expose window via popup (4 kids)
1600000 reps @ 0.0040 msec (251000.0/sec): Hide/expose window via popup (4 kids)
1600000 reps @ 0.0040 msec (252000.0/sec): Hide/expose window via popup (4 kids)
1600000 reps @ 0.0040 msec (252000.0/sec): Hide/expose window via popup (4 kids)
1600000 reps @ 0.0040 msec (252000.0/sec): Hide/expose window via popup (4 kids)
8000000 trep @ 0.0040 msec (252000.0/sec): Hide/expose window via popup (4 kids)
3200000 reps @ 0.0027 msec (370000.0/sec): Hide/expose window via popup (16 kids)
3200000 reps @ 0.0027 msec (371000.0/sec): Hide/expose window via popup (16 kids)
3200000 reps @ 0.0027 msec (368000.0/sec): Hide/expose window via popup (16 kids)
3200000 reps @ 0.0027 msec (371000.0/sec): Hide/expose window via popup (16 kids)
3200000 reps @ 0.0027 msec (370000.0/sec): Hide/expose window via popup (16 kids)
16000000 trep @ 0.0027 msec (370000.0/sec): Hide/expose window via popup (16 kids)
2000000 reps @ 0.0026 msec (388000.0/sec): Hide/expose window via popup (25 kids)
2000000 reps @ 0.0026 msec (390000.0/sec): Hide/expose window via popup (25 kids)
2000000 reps @ 0.0026 msec (389000.0/sec): Hide/expose window via popup (25 kids)
2000000 reps @ 0.0026 msec (389000.0/sec): Hide/expose window via popup (25 kids)
2000000 reps @ 0.0026 msec (388000.0/sec): Hide/expose window via popup (25 kids)
10000000 trep @ 0.0026 msec (389000.0/sec): Hide/expose window via popup (25 kids)
2000000 reps @ 0.0024 msec (409000.0/sec): Hide/expose window via popup (50 kids)
2000000 reps @ 0.0025 msec (406000.0/sec): Hide/expose window via popup (50 kids)
2000000 reps @ 0.0025 msec (406000.0/sec): Hide/expose window via popup (50 kids)
2000000 reps @ 0.0025 msec (405000.0/sec): Hide/expose window via popup (50 kids)
2000000 reps @ 0.0025 msec (408000.0/sec): Hide/expose window via popup (50 kids)
10000000 trep @ 0.0025 msec (407000.0/sec): Hide/expose window via popup (50 kids)
2250000 reps @ 0.0024 msec (413000.0/sec): Hide/expose window via popup (75 kids)
2250000 reps @ 0.0024 msec (410000.0/sec): Hide/expose window via popup (75 kids)
2250000 reps @ 0.0024 msec (411000.0/sec): Hide/expose window via popup (75 kids)
2250000 reps @ 0.0024 msec (414000.0/sec): Hide/expose window via popup (75 kids)
2250000 reps @ 0.0024 msec (412000.0/sec): Hide/expose window via popup (75 kids)
11250000 trep @ 0.0024 msec (412000.0/sec): Hide/expose window via popup (75 kids)
3000000 reps @ 0.0024 msec (417000.0/sec): Hide/expose window via popup (100 kids)
3000000 reps @ 0.0024 msec (415000.0/sec): Hide/expose window via popup (100 kids)
3000000 reps @ 0.0024 msec (416000.0/sec): Hide/expose window via popup (100 kids)
3000000 reps @ 0.0024 msec (414000.0/sec): Hide/expose window via popup (100 kids)
3000000 reps @ 0.0024 msec (418000.0/sec): Hide/expose window via popup (100 kids)
15000000 trep @ 0.0024 msec (416000.0/sec): Hide/expose window via popup (100 kids)
4000000 reps @ 0.0024 msec (420000.0/sec): Hide/expose window via popup (200 kids)
4000000 reps @ 0.0024 msec (419000.0/sec): Hide/expose window via popup (200 kids)
4000000 reps @ 0.0024 msec (419000.0/sec): Hide/expose window via popup (200 kids)
4000000 reps @ 0.0024 msec (421000.0/sec): Hide/expose window via popup (200 kids)
4000000 reps @ 0.0024 msec (421000.0/sec): Hide/expose window via popup (200 kids)
20000000 trep @ 0.0024 msec (420000.0/sec): Hide/expose window via popup (200 kids)
160000 reps @ 0.0397 msec ( 25200.0/sec): Move window (4 kids)
160000 reps @ 0.0394 msec ( 25400.0/sec): Move window (4 kids)
160000 reps @ 0.0397 msec ( 25200.0/sec): Move window (4 kids)
160000 reps @ 0.0399 msec ( 25100.0/sec): Move window (4 kids)
160000 reps @ 0.0406 msec ( 24600.0/sec): Move window (4 kids)
800000 trep @ 0.0398 msec ( 25100.0/sec): Move window (4 kids)
144000 reps @ 0.0373 msec ( 26800.0/sec): Move window (16 kids)
144000 reps @ 0.0376 msec ( 26600.0/sec): Move window (16 kids)
144000 reps @ 0.0376 msec ( 26600.0/sec): Move window (16 kids)
144000 reps @ 0.0373 msec ( 26800.0/sec): Move window (16 kids)
144000 reps @ 0.0388 msec ( 25800.0/sec): Move window (16 kids)
720000 trep @ 0.0377 msec ( 26500.0/sec): Move window (16 kids)
150000 reps @ 0.0375 msec ( 26700.0/sec): Move window (25 kids)
150000 reps @ 0.0374 msec ( 26700.0/sec): Move window (25 kids)
150000 reps @ 0.0374 msec ( 26700.0/sec): Move window (25 kids)
150000 reps @ 0.0376 msec ( 26600.0/sec): Move window (25 kids)
150000 reps @ 0.0374 msec ( 26800.0/sec): Move window (25 kids)
750000 trep @ 0.0375 msec ( 26700.0/sec): Move window (25 kids)
150000 reps @ 0.0371 msec ( 26900.0/sec): Move window (50 kids)
150000 reps @ 0.0373 msec ( 26800.0/sec): Move window (50 kids)
150000 reps @ 0.0377 msec ( 26600.0/sec): Move window (50 kids)
150000 reps @ 0.0373 msec ( 26800.0/sec): Move window (50 kids)
150000 reps @ 0.0373 msec ( 26800.0/sec): Move window (50 kids)
750000 trep @ 0.0373 msec ( 26800.0/sec): Move window (50 kids)
150000 reps @ 0.0381 msec ( 26200.0/sec): Move window (75 kids)
150000 reps @ 0.0383 msec ( 26100.0/sec): Move window (75 kids)
150000 reps @ 0.0381 msec ( 26200.0/sec): Move window (75 kids)
150000 reps @ 0.0380 msec ( 26300.0/sec): Move window (75 kids)
150000 reps @ 0.0383 msec ( 26100.0/sec): Move window (75 kids)
750000 trep @ 0.0382 msec ( 26200.0/sec): Move window (75 kids)
200000 reps @ 0.0391 msec ( 25600.0/sec): Move window (100 kids)
200000 reps @ 0.0386 msec ( 25900.0/sec): Move window (100 kids)
200000 reps @ 0.0388 msec ( 25800.0/sec): Move window (100 kids)
200000 reps @ 0.0387 msec ( 25900.0/sec): Move window (100 kids)
200000 reps @ 0.0387 msec ( 25800.0/sec): Move window (100 kids)
1000000 trep @ 0.0388 msec ( 25800.0/sec): Move window (100 kids)
140000 reps @ 0.0414 msec ( 24200.0/sec): Move window (200 kids)
140000 reps @ 0.0416 msec ( 24000.0/sec): Move window (200 kids)
140000 reps @ 0.0414 msec ( 24100.0/sec): Move window (200 kids)
140000 reps @ 0.0415 msec ( 24100.0/sec): Move window (200 kids)
140000 reps @ 0.0414 msec ( 24100.0/sec): Move window (200 kids)
700000 trep @ 0.0415 msec ( 24100.0/sec): Move window (200 kids)
80000000 reps @ 0.0001 msec (8250000.0/sec): Moved unmapped window (4 kids)
80000000 reps @ 0.0001 msec (8260000.0/sec): Moved unmapped window (4 kids)
80000000 reps @ 0.0001 msec (8060000.0/sec): Moved unmapped window (4 kids)
80000000 reps @ 0.0001 msec (8170000.0/sec): Moved unmapped window (4 kids)
80000000 reps @ 0.0001 msec (8310000.0/sec): Moved unmapped window (4 kids)
400000000 trep @ 0.0001 msec (8210000.0/sec): Moved unmapped window (4 kids)
48000000 reps @ 0.0001 msec (8380000.0/sec): Moved unmapped window (16 kids)
48000000 reps @ 0.0001 msec (8330000.0/sec): Moved unmapped window (16 kids)
48000000 reps @ 0.0001 msec (8280000.0/sec): Moved unmapped window (16 kids)
48000000 reps @ 0.0001 msec (8330000.0/sec): Moved unmapped window (16 kids)
48000000 reps @ 0.0001 msec (8300000.0/sec): Moved unmapped window (16 kids)
240000000 trep @ 0.0001 msec (8320000.0/sec): Moved unmapped window (16 kids)
50000000 reps @ 0.0001 msec (8290000.0/sec): Moved unmapped window (25 kids)
50000000 reps @ 0.0001 msec (8270000.0/sec): Moved unmapped window (25 kids)
50000000 reps @ 0.0001 msec (8300000.0/sec): Moved unmapped window (25 kids)
50000000 reps @ 0.0001 msec (8200000.0/sec): Moved unmapped window (25 kids)
50000000 reps @ 0.0001 msec (8320000.0/sec): Moved unmapped window (25 kids)
250000000 trep @ 0.0001 msec (8280000.0/sec): Moved unmapped window (25 kids)
45000000 reps @ 0.0001 msec (8260000.0/sec): Moved unmapped window (50 kids)
45000000 reps @ 0.0001 msec (8310000.0/sec): Moved unmapped window (50 kids)
45000000 reps @ 0.0001 msec (8330000.0/sec): Moved unmapped window (50 kids)
45000000 reps @ 0.0001 msec (8330000.0/sec): Moved unmapped window (50 kids)
45000000 reps @ 0.0001 msec (8330000.0/sec): Moved unmapped window (50 kids)
225000000 trep @ 0.0001 msec (8310000.0/sec): Moved unmapped window (50 kids)
45000000 reps @ 0.0001 msec (8280000.0/sec): Moved unmapped window (75 kids)
45000000 reps @ 0.0001 msec (8360000.0/sec): Moved unmapped window (75 kids)
45000000 reps @ 0.0001 msec (8270000.0/sec): Moved unmapped window (75 kids)
45000000 reps @ 0.0001 msec (8250000.0/sec): Moved unmapped window (75 kids)
45000000 reps @ 0.0001 msec (8300000.0/sec): Moved unmapped window (75 kids)
225000000 trep @ 0.0001 msec (8290000.0/sec): Moved unmapped window (75 kids)
50000000 reps @ 0.0001 msec (7990000.0/sec): Moved unmapped window (100 kids)
50000000 reps @ 0.0001 msec (8250000.0/sec): Moved unmapped window (100 kids)
50000000 reps @ 0.0001 msec (7540000.0/sec): Moved unmapped window (100 kids)
50000000 reps @ 0.0001 msec (8020000.0/sec): Moved unmapped window (100 kids)
50000000 reps @ 0.0001 msec (8250000.0/sec): Moved unmapped window (100 kids)
250000000 trep @ 0.0001 msec (8000000.0/sec): Moved unmapped window (100 kids)
60000000 reps @ 0.0001 msec (8270000.0/sec): Moved unmapped window (200 kids)
60000000 reps @ 0.0001 msec (8270000.0/sec): Moved unmapped window (200 kids)
60000000 reps @ 0.0001 msec (7870000.0/sec): Moved unmapped window (200 kids)
60000000 reps @ 0.0001 msec (8220000.0/sec): Moved unmapped window (200 kids)
60000000 reps @ 0.0001 msec (8310000.0/sec): Moved unmapped window (200 kids)
300000000 trep @ 0.0001 msec (8190000.0/sec): Moved unmapped window (200 kids)
800000 reps @ 0.0098 msec (102000.0/sec): Move window via parent (4 kids)
800000 reps @ 0.0100 msec ( 99600.0/sec): Move window via parent (4 kids)
800000 reps @ 0.0100 msec (100000.0/sec): Move window via parent (4 kids)
800000 reps @ 0.0097 msec (103000.0/sec): Move window via parent (4 kids)
800000 reps @ 0.0097 msec (103000.0/sec): Move window via parent (4 kids)
4000000 trep @ 0.0099 msec (101000.0/sec): Move window via parent (4 kids)
3200000 reps @ 0.0025 msec (404000.0/sec): Move window via parent (16 kids)
3200000 reps @ 0.0025 msec (406000.0/sec): Move window via parent (16 kids)
3200000 reps @ 0.0025 msec (401000.0/sec): Move window via parent (16 kids)
3200000 reps @ 0.0024 msec (409000.0/sec): Move window via parent (16 kids)
3200000 reps @ 0.0025 msec (408000.0/sec): Move window via parent (16 kids)
16000000 trep @ 0.0025 msec (406000.0/sec): Move window via parent (16 kids)
5000000 reps @ 0.0016 msec (636000.0/sec): Move window via parent (25 kids)
5000000 reps @ 0.0016 msec (641000.0/sec): Move window via parent (25 kids)
5000000 reps @ 0.0015 msec (646000.0/sec): Move window via parent (25 kids)
5000000 reps @ 0.0015 msec (646000.0/sec): Move window via parent (25 kids)
5000000 reps @ 0.0016 msec (643000.0/sec): Move window via parent (25 kids)
25000000 trep @ 0.0016 msec (642000.0/sec): Move window via parent (25 kids)
10000000 reps @ 0.0008 msec (1210000.0/sec): Move window via parent (50 kids)
10000000 reps @ 0.0008 msec (1210000.0/sec): Move window via parent (50 kids)
10000000 reps @ 0.0008 msec (1210000.0/sec): Move window via parent (50 kids)
10000000 reps @ 0.0008 msec (1220000.0/sec): Move window via parent (50 kids)
10000000 reps @ 0.0008 msec (1210000.0/sec): Move window via parent (50 kids)
50000000 trep @ 0.0008 msec (1210000.0/sec): Move window via parent (50 kids)
15000000 reps @ 0.0006 msec (1750000.0/sec): Move window via parent (75 kids)
15000000 reps @ 0.0006 msec (1740000.0/sec): Move window via parent (75 kids)
15000000 reps @ 0.0006 msec (1730000.0/sec): Move window via parent (75 kids)
15000000 reps @ 0.0006 msec (1740000.0/sec): Move window via parent (75 kids)
15000000 reps @ 0.0006 msec (1720000.0/sec): Move window via parent (75 kids)
75000000 trep @ 0.0006 msec (1730000.0/sec): Move window via parent (75 kids)
20000000 reps @ 0.0005 msec (2210000.0/sec): Move window via parent (100 kids)
20000000 reps @ 0.0005 msec (2210000.0/sec): Move window via parent (100 kids)
20000000 reps @ 0.0005 msec (2220000.0/sec): Move window via parent (100 kids)
20000000 reps @ 0.0004 msec (2220000.0/sec): Move window via parent (100 kids)
20000000 reps @ 0.0005 msec (2210000.0/sec): Move window via parent (100 kids)
100000000 trep @ 0.0005 msec (2210000.0/sec): Move window via parent (100 kids)
20000000 reps @ 0.0003 msec (3790000.0/sec): Move window via parent (200 kids)
20000000 reps @ 0.0003 msec (3790000.0/sec): Move window via parent (200 kids)
20000000 reps @ 0.0003 msec (3760000.0/sec): Move window via parent (200 kids)
20000000 reps @ 0.0003 msec (3740000.0/sec): Move window via parent (200 kids)
20000000 reps @ 0.0003 msec (3770000.0/sec): Move window via parent (200 kids)
100000000 trep @ 0.0003 msec (3770000.0/sec): Move window via parent (200 kids)
1200000 reps @ 0.0044 msec (226000.0/sec): Resize window (4 kids)
1200000 reps @ 0.0044 msec (226000.0/sec): Resize window (4 kids)
1200000 reps @ 0.0044 msec (228000.0/sec): Resize window (4 kids)
1200000 reps @ 0.0044 msec (226000.0/sec): Resize window (4 kids)
1200000 reps @ 0.0044 msec (227000.0/sec): Resize window (4 kids)
6000000 trep @ 0.0044 msec (227000.0/sec): Resize window (4 kids)
1120000 reps @ 0.0050 msec (200000.0/sec): Resize window (16 kids)
1120000 reps @ 0.0051 msec (198000.0/sec): Resize window (16 kids)
1120000 reps @ 0.0050 msec (199000.0/sec): Resize window (16 kids)
1120000 reps @ 0.0050 msec (200000.0/sec): Resize window (16 kids)
1120000 reps @ 0.0051 msec (195000.0/sec): Resize window (16 kids)
5600000 trep @ 0.0050 msec (198000.0/sec): Resize window (16 kids)
1000000 reps @ 0.0054 msec (184000.0/sec): Resize window (25 kids)
1000000 reps @ 0.0054 msec (185000.0/sec): Resize window (25 kids)
1000000 reps @ 0.0054 msec (185000.0/sec): Resize window (25 kids)
1000000 reps @ 0.0056 msec (179000.0/sec): Resize window (25 kids)
1000000 reps @ 0.0056 msec (179000.0/sec): Resize window (25 kids)
5000000 trep @ 0.0055 msec (182000.0/sec): Resize window (25 kids)
1000000 reps @ 0.0066 msec (151000.0/sec): Resize window (50 kids)
1000000 reps @ 0.0066 msec (151000.0/sec): Resize window (50 kids)
1000000 reps @ 0.0065 msec (154000.0/sec): Resize window (50 kids)
1000000 reps @ 0.0065 msec (154000.0/sec): Resize window (50 kids)
1000000 reps @ 0.0065 msec (154000.0/sec): Resize window (50 kids)
5000000 trep @ 0.0065 msec (153000.0/sec): Resize window (50 kids)
750000 reps @ 0.0071 msec (141000.0/sec): Resize window (75 kids)
750000 reps @ 0.0072 msec (140000.0/sec): Resize window (75 kids)
750000 reps @ 0.0072 msec (139000.0/sec): Resize window (75 kids)
750000 reps @ 0.0073 msec (137000.0/sec): Resize window (75 kids)
750000 reps @ 0.0071 msec (140000.0/sec): Resize window (75 kids)
3750000 trep @ 0.0072 msec (139000.0/sec): Resize window (75 kids)
700000 reps @ 0.0080 msec (125000.0/sec): Resize window (100 kids)
700000 reps @ 0.0078 msec (127000.0/sec): Resize window (100 kids)
700000 reps @ 0.0080 msec (124000.0/sec): Resize window (100 kids)
700000 reps @ 0.0079 msec (127000.0/sec): Resize window (100 kids)
700000 reps @ 0.0078 msec (128000.0/sec): Resize window (100 kids)
3500000 trep @ 0.0079 msec (126000.0/sec): Resize window (100 kids)
600000 reps @ 0.0102 msec ( 98500.0/sec): Resize window (200 kids)
600000 reps @ 0.0102 msec ( 97800.0/sec): Resize window (200 kids)
600000 reps @ 0.0101 msec ( 99500.0/sec): Resize window (200 kids)
600000 reps @ 0.0103 msec ( 97300.0/sec): Resize window (200 kids)
600000 reps @ 0.0102 msec ( 97700.0/sec): Resize window (200 kids)
3000000 trep @ 0.0102 msec ( 98100.0/sec): Resize window (200 kids)
40000000 reps @ 0.0001 msec (7860000.0/sec): Resize unmapped window (4 kids)
40000000 reps @ 0.0001 msec (7900000.0/sec): Resize unmapped window (4 kids)
40000000 reps @ 0.0001 msec (7500000.0/sec): Resize unmapped window (4 kids)
40000000 reps @ 0.0001 msec (7880000.0/sec): Resize unmapped window (4 kids)
40000000 reps @ 0.0001 msec (7860000.0/sec): Resize unmapped window (4 kids)
200000000 trep @ 0.0001 msec (7800000.0/sec): Resize unmapped window (4 kids)
48000000 reps @ 0.0001 msec (7890000.0/sec): Resize unmapped window (16 kids)
48000000 reps @ 0.0001 msec (7900000.0/sec): Resize unmapped window (16 kids)
48000000 reps @ 0.0001 msec (7910000.0/sec): Resize unmapped window (16 kids)
48000000 reps @ 0.0001 msec (7490000.0/sec): Resize unmapped window (16 kids)
48000000 reps @ 0.0001 msec (7910000.0/sec): Resize unmapped window (16 kids)
240000000 trep @ 0.0001 msec (7820000.0/sec): Resize unmapped window (16 kids)
50000000 reps @ 0.0001 msec (7660000.0/sec): Resize unmapped window (25 kids)
50000000 reps @ 0.0001 msec (7930000.0/sec): Resize unmapped window (25 kids)
50000000 reps @ 0.0001 msec (7960000.0/sec): Resize unmapped window (25 kids)
50000000 reps @ 0.0001 msec (7910000.0/sec): Resize unmapped window (25 kids)
50000000 reps @ 0.0001 msec (7850000.0/sec): Resize unmapped window (25 kids)
250000000 trep @ 0.0001 msec (7860000.0/sec): Resize unmapped window (25 kids)
40000000 reps @ 0.0001 msec (7820000.0/sec): Resize unmapped window (50 kids)
40000000 reps @ 0.0001 msec (7940000.0/sec): Resize unmapped window (50 kids)
40000000 reps @ 0.0001 msec (7150000.0/sec): Resize unmapped window (50 kids)
40000000 reps @ 0.0001 msec (7620000.0/sec): Resize unmapped window (50 kids)
40000000 reps @ 0.0001 msec (7880000.0/sec): Resize unmapped window (50 kids)
200000000 trep @ 0.0001 msec (7670000.0/sec): Resize unmapped window (50 kids)
45000000 reps @ 0.0001 msec (7950000.0/sec): Resize unmapped window (75 kids)
45000000 reps @ 0.0001 msec (7940000.0/sec): Resize unmapped window (75 kids)
45000000 reps @ 0.0001 msec (7780000.0/sec): Resize unmapped window (75 kids)
45000000 reps @ 0.0001 msec (7890000.0/sec): Resize unmapped window (75 kids)
45000000 reps @ 0.0001 msec (7910000.0/sec): Resize unmapped window (75 kids)
225000000 trep @ 0.0001 msec (7890000.0/sec): Resize unmapped window (75 kids)
40000000 reps @ 0.0001 msec (7890000.0/sec): Resize unmapped window (100 kids)
40000000 reps @ 0.0001 msec (7980000.0/sec): Resize unmapped window (100 kids)
40000000 reps @ 0.0001 msec (7960000.0/sec): Resize unmapped window (100 kids)
40000000 reps @ 0.0001 msec (7940000.0/sec): Resize unmapped window (100 kids)
40000000 reps @ 0.0001 msec (7950000.0/sec): Resize unmapped window (100 kids)
200000000 trep @ 0.0001 msec (7950000.0/sec): Resize unmapped window (100 kids)
40000000 reps @ 0.0001 msec (7920000.0/sec): Resize unmapped window (200 kids)
40000000 reps @ 0.0001 msec (7920000.0/sec): Resize unmapped window (200 kids)
40000000 reps @ 0.0001 msec (7150000.0/sec): Resize unmapped window (200 kids)
40000000 reps @ 0.0001 msec (7230000.0/sec): Resize unmapped window (200 kids)
40000000 reps @ 0.0001 msec (7280000.0/sec): Resize unmapped window (200 kids)
200000000 trep @ 0.0001 msec (7480000.0/sec): Resize unmapped window (200 kids)
1600000 reps @ 0.0036 msec (276000.0/sec): Circulate window (4 kids)
1600000 reps @ 0.0036 msec (278000.0/sec): Circulate window (4 kids)
1600000 reps @ 0.0036 msec (277000.0/sec): Circulate window (4 kids)
1600000 reps @ 0.0037 msec (272000.0/sec): Circulate window (4 kids)
1600000 reps @ 0.0037 msec (270000.0/sec): Circulate window (4 kids)
8000000 trep @ 0.0036 msec (275000.0/sec): Circulate window (4 kids)
1280000 reps @ 0.0044 msec (228000.0/sec): Circulate window (16 kids)
1280000 reps @ 0.0044 msec (225000.0/sec): Circulate window (16 kids)
1280000 reps @ 0.0045 msec (224000.0/sec): Circulate window (16 kids)
1280000 reps @ 0.0044 msec (228000.0/sec): Circulate window (16 kids)
1280000 reps @ 0.0044 msec (229000.0/sec): Circulate window (16 kids)
6400000 trep @ 0.0044 msec (227000.0/sec): Circulate window (16 kids)
1250000 reps @ 0.0048 msec (211000.0/sec): Circulate window (25 kids)
1250000 reps @ 0.0047 msec (212000.0/sec): Circulate window (25 kids)
1250000 reps @ 0.0047 msec (214000.0/sec): Circulate window (25 kids)
1250000 reps @ 0.0046 msec (216000.0/sec): Circulate window (25 kids)
1250000 reps @ 0.0046 msec (217000.0/sec): Circulate window (25 kids)
6250000 trep @ 0.0047 msec (214000.0/sec): Circulate window (25 kids)
1000000 reps @ 0.0050 msec (198000.0/sec): Circulate window (50 kids)
1000000 reps @ 0.0051 msec (198000.0/sec): Circulate window (50 kids)
1000000 reps @ 0.0050 msec (199000.0/sec): Circulate window (50 kids)
1000000 reps @ 0.0051 msec (198000.0/sec): Circulate window (50 kids)
1000000 reps @ 0.0050 msec (201000.0/sec): Circulate window (50 kids)
5000000 trep @ 0.0050 msec (199000.0/sec): Circulate window (50 kids)
1500000 reps @ 0.0056 msec (177000.0/sec): Circulate window (75 kids)
1500000 reps @ 0.0055 msec (182000.0/sec): Circulate window (75 kids)
1500000 reps @ 0.0057 msec (177000.0/sec): Circulate window (75 kids)
1500000 reps @ 0.0056 msec (179000.0/sec): Circulate window (75 kids)
1500000 reps @ 0.0054 msec (184000.0/sec): Circulate window (75 kids)
7500000 trep @ 0.0056 msec (180000.0/sec): Circulate window (75 kids)
900000 reps @ 0.0059 msec (168000.0/sec): Circulate window (100 kids)
900000 reps @ 0.0058 msec (172000.0/sec): Circulate window (100 kids)
900000 reps @ 0.0059 msec (170000.0/sec): Circulate window (100 kids)
900000 reps @ 0.0059 msec (170000.0/sec): Circulate window (100 kids)
900000 reps @ 0.0058 msec (172000.0/sec): Circulate window (100 kids)
4500000 trep @ 0.0059 msec (171000.0/sec): Circulate window (100 kids)
800000 reps @ 0.0075 msec (133000.0/sec): Circulate window (200 kids)
800000 reps @ 0.0077 msec (130000.0/sec): Circulate window (200 kids)
800000 reps @ 0.0075 msec (133000.0/sec): Circulate window (200 kids)
800000 reps @ 0.0075 msec (133000.0/sec): Circulate window (200 kids)
800000 reps @ 0.0076 msec (131000.0/sec): Circulate window (200 kids)
4000000 trep @ 0.0076 msec (132000.0/sec): Circulate window (200 kids)
120000000 reps @ 0.0001 msec (19000000.0/sec): Circulate Unmapped window (4 kids)
120000000 reps @ 0.0001 msec (19000000.0/sec): Circulate Unmapped window (4 kids)
120000000 reps @ 0.0001 msec (18800000.0/sec): Circulate Unmapped window (4 kids)
120000000 reps @ 0.0001 msec (19000000.0/sec): Circulate Unmapped window (4 kids)
120000000 reps @ 0.0001 msec (18900000.0/sec): Circulate Unmapped window (4 kids)
600000000 trep @ 0.0001 msec (18900000.0/sec): Circulate Unmapped window (4 kids)
96000000 reps @ 0.0001 msec (17900000.0/sec): Circulate Unmapped window (16 kids)
96000000 reps @ 0.0001 msec (18000000.0/sec): Circulate Unmapped window (16 kids)
96000000 reps @ 0.0001 msec (18000000.0/sec): Circulate Unmapped window (16 kids)
96000000 reps @ 0.0001 msec (18000000.0/sec): Circulate Unmapped window (16 kids)
96000000 reps @ 0.0001 msec (18100000.0/sec): Circulate Unmapped window (16 kids)
480000000 trep @ 0.0001 msec (18000000.0/sec): Circulate Unmapped window (16 kids)
100000000 reps @ 0.0001 msec (15200000.0/sec): Circulate Unmapped window (25 kids)
100000000 reps @ 0.0001 msec (15400000.0/sec): Circulate Unmapped window (25 kids)
100000000 reps @ 0.0001 msec (15500000.0/sec): Circulate Unmapped window (25 kids)
100000000 reps @ 0.0001 msec (15400000.0/sec): Circulate Unmapped window (25 kids)
100000000 reps @ 0.0001 msec (15400000.0/sec): Circulate Unmapped window (25 kids)
500000000 trep @ 0.0001 msec (15400000.0/sec): Circulate Unmapped window (25 kids)
50000000 reps @ 0.0001 msec (9330000.0/sec): Circulate Unmapped window (50 kids)
50000000 reps @ 0.0001 msec (9320000.0/sec): Circulate Unmapped window (50 kids)
50000000 reps @ 0.0001 msec (9330000.0/sec): Circulate Unmapped window (50 kids)
50000000 reps @ 0.0001 msec (9300000.0/sec): Circulate Unmapped window (50 kids)
50000000 reps @ 0.0001 msec (9260000.0/sec): Circulate Unmapped window (50 kids)
250000000 trep @ 0.0001 msec (9310000.0/sec): Circulate Unmapped window (50 kids)
37500000 reps @ 0.0001 msec (7280000.0/sec): Circulate Unmapped window (75 kids)
37500000 reps @ 0.0001 msec (7260000.0/sec): Circulate Unmapped window (75 kids)
37500000 reps @ 0.0001 msec (7280000.0/sec): Circulate Unmapped window (75 kids)
37500000 reps @ 0.0001 msec (7280000.0/sec): Circulate Unmapped window (75 kids)
37500000 reps @ 0.0001 msec (7280000.0/sec): Circulate Unmapped window (75 kids)
187500000 trep @ 0.0001 msec (7280000.0/sec): Circulate Unmapped window (75 kids)
30000000 reps @ 0.0002 msec (6040000.0/sec): Circulate Unmapped window (100 kids)
30000000 reps @ 0.0002 msec (6040000.0/sec): Circulate Unmapped window (100 kids)
30000000 reps @ 0.0002 msec (6050000.0/sec): Circulate Unmapped window (100 kids)
30000000 reps @ 0.0002 msec (6050000.0/sec): Circulate Unmapped window (100 kids)
30000000 reps @ 0.0002 msec (6050000.0/sec): Circulate Unmapped window (100 kids)
150000000 trep @ 0.0002 msec (6050000.0/sec): Circulate Unmapped window (100 kids)
18000000 reps @ 0.0003 msec (3350000.0/sec): Circulate Unmapped window (200 kids)
18000000 reps @ 0.0003 msec (3340000.0/sec): Circulate Unmapped window (200 kids)
18000000 reps @ 0.0003 msec (3340000.0/sec): Circulate Unmapped window (200 kids)
18000000 reps @ 0.0003 msec (3340000.0/sec): Circulate Unmapped window (200 kids)
18000000 reps @ 0.0003 msec (3350000.0/sec): Circulate Unmapped window (200 kids)
90000000 trep @ 0.0003 msec (3350000.0/sec): Circulate Unmapped window (200 kids)
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 7/8] drm/i915/display/skl+: Drop frontbuffer rendering support
2021-08-18 0:42 ` [Intel-gfx] [PATCH 7/8] drm/i915/display/skl+: Drop frontbuffer rendering support José Roberto de Souza
2021-08-18 14:55 ` Ville Syrjälä
@ 2021-08-24 7:21 ` Daniel Vetter
1 sibling, 0 replies; 22+ messages in thread
From: Daniel Vetter @ 2021-08-24 7:21 UTC (permalink / raw)
To: José Roberto de Souza
Cc: intel-gfx, Gwan-gyeong Mun, Ville Syrjälä,
Jani Nikula, Rodrigo Vivi
On Wed, Aug 18, 2021 at 2:37 AM José Roberto de Souza
<jose.souza@intel.com> wrote:
>
> By now all the userspace applications should have migrated to atomic
> or at least be calling DRM_IOCTL_MODE_DIRTYFB.
>
> With that we can kill frontbuffer rendering support in i915 for
> modern platforms.
>
> So here converting legacy APIs into atomic commits so it can be
> properly handled by driver i915.
>
> Several IGT tests will fail with this changes, because some tests
> were stressing those frontbuffer rendering scenarios that no userspace
> should be using by now, fixes to IGT should be sent soon.
>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Patch looks good in overall direction, but there's more
intel_frontbuffer.c functions to disable, none of the tracking of the
tracking bits should ever be set, maybe even throw some WARN_ON in the
code.
-Daniel
> ---
> drivers/gpu/drm/i915/display/intel_cursor.c | 6 ++----
> drivers/gpu/drm/i915/display/intel_display.c | 7 ++++++-
> drivers/gpu/drm/i915/display/intel_frontbuffer.c | 6 ++++++
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> 4 files changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index c7618fef01439..5aa996c3b7980 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -617,6 +617,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
> u32 src_w, u32 src_h,
> struct drm_modeset_acquire_ctx *ctx)
> {
> + struct drm_i915_private *i915 = to_i915(_crtc->dev);
> struct intel_plane *plane = to_intel_plane(_plane);
> struct intel_crtc *crtc = to_intel_crtc(_crtc);
> struct intel_plane_state *old_plane_state =
> @@ -633,12 +634,9 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
> * PSR2 selective fetch also requires the slow path as
> * PSR2 plane and transcoder registers can only be updated during
> * vblank.
> - *
> - * FIXME bigjoiner fastpath would be good
> */
> if (!crtc_state->hw.active || intel_crtc_needs_modeset(crtc_state) ||
> - crtc_state->update_pipe || crtc_state->bigjoiner ||
> - crtc_state->enable_psr2_sel_fetch)
> + crtc_state->update_pipe || !HAS_FRONTBUFFER_RENDERING(i915))
> goto slow;
>
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e55c9e2cb254a..f700544454ad5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11744,10 +11744,15 @@ static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
> unsigned num_clips)
> {
> struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> + struct drm_i915_private *i915 = to_i915(obj->base.dev);
>
> i915_gem_object_flush_if_display(obj);
> - intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
>
> + if (!HAS_FRONTBUFFER_RENDERING(i915))
> + return drm_atomic_helper_dirtyfb(fb, file, flags, color, clips,
> + num_clips);
> +
> + intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
> index e4834d84ce5e3..6be2f767a203c 100644
> --- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
> +++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
> @@ -91,6 +91,9 @@ static void frontbuffer_flush(struct drm_i915_private *i915,
>
> trace_intel_frontbuffer_flush(frontbuffer_bits, origin);
>
> + if (!HAS_FRONTBUFFER_RENDERING(i915))
> + return;
> +
> might_sleep();
> intel_edp_drrs_flush(i915, frontbuffer_bits);
> intel_psr_flush(i915, frontbuffer_bits, origin);
> @@ -179,6 +182,9 @@ void __intel_fb_invalidate(struct intel_frontbuffer *front,
>
> trace_intel_frontbuffer_invalidate(frontbuffer_bits, origin);
>
> + if (!HAS_FRONTBUFFER_RENDERING(i915))
> + return;
> +
> might_sleep();
> intel_psr_invalidate(i915, frontbuffer_bits, origin);
> intel_edp_drrs_invalidate(i915, frontbuffer_bits);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1ea27c4e94a6d..fe1dc8b7871a0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1719,6 +1719,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_VRR(i915) (GRAPHICS_VER(i915) >= 12)
>
> +#define HAS_FRONTBUFFER_RENDERING(i915) (GRAPHICS_VER(i915) < 9)
> +
> /* Only valid when HAS_DISPLAY() is true */
> #define INTEL_DISPLAY_ENABLED(dev_priv) \
> (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
> --
> 2.32.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH 8/8] drm/i915/display: Drop PSR frontbuffer rendering support
2021-08-18 0:42 [Intel-gfx] [PATCH 0/8] Drop frontbuffer rendering support from Skylake and newer José Roberto de Souza
` (6 preceding siblings ...)
2021-08-18 0:42 ` [Intel-gfx] [PATCH 7/8] drm/i915/display/skl+: Drop frontbuffer rendering support José Roberto de Souza
@ 2021-08-18 0:42 ` José Roberto de Souza
2021-08-18 1:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Drop frontbuffer rendering support from Skylake and newer Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: José Roberto de Souza @ 2021-08-18 0:42 UTC (permalink / raw)
To: intel-gfx; +Cc: Gwan-gyeong Mun, José Roberto de Souza
After commit "drm/i915/display/skl+: Drop frontbuffer rendering
support" frontbuffer rendering is not supported for display 9 and
newer and as PSR is only supported by default in display 9 and newer
we can now drop all frontbuffer rendering support for PSR code.
Some DC3CO code was commented with a macro, because the function
caller is being dropped. As DC3CO is already disabled by default
because it requires changes in its sequences
Two DC3CO functions lost their callers while dropping frontbuffer
rendering but as DC3CO is already disabled by default because it
requires fixes, will leave this task to whoever will fix DC3CO.
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 2 -
.../drm/i915/display/intel_display_types.h | 2 -
.../gpu/drm/i915/display/intel_frontbuffer.c | 2 -
drivers/gpu/drm/i915/display/intel_psr.c | 186 ++----------------
drivers/gpu/drm/i915/display/intel_psr.h | 8 +-
5 files changed, 18 insertions(+), 182 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index b136a0fc0963b..64a03ae56d6fe 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -374,8 +374,6 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
enableddisabled(enabled), val);
psr_source_status(intel_dp, m);
- seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
- psr->busy_frontbuffer_bits);
/*
* SKL+ Perf counter is reset to 0 everytime DC state is entered
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6beeeeba1bed2..a6b08032917a7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1512,7 +1512,6 @@ struct intel_psr {
enum transcoder transcoder;
bool active;
struct work_struct work;
- unsigned int busy_frontbuffer_bits;
bool sink_psr2_support;
bool link_standby;
bool colorimetry_support;
@@ -1523,7 +1522,6 @@ struct intel_psr {
ktime_t last_entry_attempt;
ktime_t last_exit;
bool sink_not_reliable;
- bool irq_aux_error;
u16 su_w_granularity;
u16 su_y_granularity;
u32 dc3co_exitline;
diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
index 6be2f767a203c..784aa423b84bf 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
@@ -96,7 +96,6 @@ static void frontbuffer_flush(struct drm_i915_private *i915,
might_sleep();
intel_edp_drrs_flush(i915, frontbuffer_bits);
- intel_psr_flush(i915, frontbuffer_bits, origin);
intel_fbc_flush(i915, frontbuffer_bits, origin);
}
@@ -186,7 +185,6 @@ void __intel_fb_invalidate(struct intel_frontbuffer *front,
return;
might_sleep();
- intel_psr_invalidate(i915, frontbuffer_bits, origin);
intel_edp_drrs_invalidate(i915, frontbuffer_bits);
intel_fbc_invalidate(i915, frontbuffer_bits, origin);
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 3f6fb7d67f84d..8c9bd5846a8d0 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -224,15 +224,12 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n",
transcoder_name(cpu_transcoder));
- intel_dp->psr.irq_aux_error = true;
-
/*
* If this interruption is not masked it will keep
* interrupting so fast that it prevents the scheduled
* work to run.
* Also after a PSR error, we don't want to arm PSR
* again so we don't care about unmask the interruption
- * or unset irq_aux_error.
*/
val = intel_de_read(dev_priv, imr_reg);
val |= EDP_PSR_ERROR(trans_shift);
@@ -614,14 +611,6 @@ static void psr2_program_idle_frames(struct intel_dp *intel_dp,
intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
}
-static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- psr2_program_idle_frames(intel_dp, 0);
- intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO);
-}
-
static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1177,7 +1166,6 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
- intel_dp->psr.busy_frontbuffer_bits = 0;
intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
/* DC5/DC6 requires at least 6 idle frames */
@@ -1784,36 +1772,6 @@ void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
}
}
-static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- i915_reg_t reg;
- u32 mask;
- int err;
-
- if (!intel_dp->psr.enabled)
- return false;
-
- if (intel_dp->psr.psr2_enabled) {
- reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
- mask = EDP_PSR2_STATUS_STATE_MASK;
- } else {
- reg = EDP_PSR_STATUS(intel_dp->psr.transcoder);
- mask = EDP_PSR_STATUS_STATE_MASK;
- }
-
- mutex_unlock(&intel_dp->psr.lock);
-
- err = intel_de_wait_for_clear(dev_priv, reg, mask, 50);
- if (err)
- drm_err(&dev_priv->drm,
- "Timed out waiting for PSR Idle for re-enable\n");
-
- /* After the unlocked wait, verify that PSR is still wanted! */
- mutex_lock(&intel_dp->psr.lock);
- return err == 0 && intel_dp->psr.enabled;
-}
-
static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
{
struct drm_connector_list_iter conn_iter;
@@ -1912,16 +1870,6 @@ int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val)
return ret;
}
-static void intel_psr_handle_irq(struct intel_dp *intel_dp)
-{
- struct intel_psr *psr = &intel_dp->psr;
-
- intel_psr_disable_locked(intel_dp);
- psr->sink_not_reliable = true;
- /* let's make sure that sink is awaken */
- drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
-}
-
static void intel_psr_work(struct work_struct *work)
{
struct intel_dp *intel_dp =
@@ -1929,75 +1877,30 @@ static void intel_psr_work(struct work_struct *work)
mutex_lock(&intel_dp->psr.lock);
- if (!intel_dp->psr.enabled)
- goto unlock;
-
- if (READ_ONCE(intel_dp->psr.irq_aux_error))
- intel_psr_handle_irq(intel_dp);
-
- /*
- * We have to make sure PSR is ready for re-enable
- * otherwise it keeps disabled until next full enable/disable cycle.
- * PSR might take some time to get fully disabled
- * and be ready for re-enable.
- */
- if (!__psr_wait_for_idle_locked(intel_dp))
- goto unlock;
-
- /*
- * The delayed work can race with an invalidate hence we need to
- * recheck. Since psr_flush first clears this and then reschedules we
- * won't ever miss a flush when bailing out here.
- */
- if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active)
- goto unlock;
+ /* Handling PSR error interruption */
+ intel_psr_disable_locked(intel_dp);
+ intel_dp->psr.sink_not_reliable = true;
+ /* let's make sure that sink is awaken */
+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
- intel_psr_activate(intel_dp);
-unlock:
mutex_unlock(&intel_dp->psr.lock);
}
-/**
- * intel_psr_invalidate - Invalidade PSR
- * @dev_priv: i915 device
- * @frontbuffer_bits: frontbuffer plane tracking bits
- * @origin: which operation caused the invalidate
- *
- * Since the hardware frontbuffer tracking has gaps we need to integrate
- * with the software frontbuffer tracking. This function gets called every
- * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
- * disabled if the frontbuffer mask contains a buffer relevant to PSR.
- *
- * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
+/*
+ * TODO: Functions below lost their callers to a refactor but as DC3CO is
+ * already disabled by default because it requires fixes, will leave this task
+ * to whoever will fix DC3CO.
*/
-void intel_psr_invalidate(struct drm_i915_private *dev_priv,
- unsigned frontbuffer_bits, enum fb_op_origin origin)
-{
- struct intel_encoder *encoder;
-
- if (origin == ORIGIN_FLIP)
- return;
-
- for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
- unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
- mutex_lock(&intel_dp->psr.lock);
- if (!intel_dp->psr.enabled) {
- mutex_unlock(&intel_dp->psr.lock);
- continue;
- }
-
- pipe_frontbuffer_bits &=
- INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
- intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits;
+#if 0
- if (pipe_frontbuffer_bits)
- intel_psr_exit(intel_dp);
+static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- mutex_unlock(&intel_dp->psr.lock);
- }
+ psr2_program_idle_frames(intel_dp, 0);
+ intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO);
}
+
/*
* When we will be completely rely on PSR2 S/W tracking in future,
* intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
@@ -2032,62 +1935,7 @@ tgl_dc3co_flush(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
mutex_unlock(&intel_dp->psr.lock);
}
-/**
- * intel_psr_flush - Flush PSR
- * @dev_priv: i915 device
- * @frontbuffer_bits: frontbuffer plane tracking bits
- * @origin: which operation caused the flush
- *
- * Since the hardware frontbuffer tracking has gaps we need to integrate
- * with the software frontbuffer tracking. This function gets called every
- * time frontbuffer rendering has completed and flushed out to memory. PSR
- * can be enabled again if no other frontbuffer relevant to PSR is dirty.
- *
- * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
- */
-void intel_psr_flush(struct drm_i915_private *dev_priv,
- unsigned frontbuffer_bits, enum fb_op_origin origin)
-{
- struct intel_encoder *encoder;
-
- for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
- unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
- if (origin == ORIGIN_FLIP) {
- tgl_dc3co_flush(intel_dp, frontbuffer_bits, origin);
- continue;
- }
-
- mutex_lock(&intel_dp->psr.lock);
- if (!intel_dp->psr.enabled) {
- mutex_unlock(&intel_dp->psr.lock);
- continue;
- }
-
- pipe_frontbuffer_bits &=
- INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
- intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits;
-
- /*
- * If the PSR is paused by an explicit intel_psr_paused() call,
- * we have to ensure that the PSR is not activated until
- * intel_psr_resume() is called.
- */
- if (intel_dp->psr.paused) {
- mutex_unlock(&intel_dp->psr.lock);
- continue;
- }
-
- /* By definition flush = invalidate + flush */
- if (pipe_frontbuffer_bits)
- psr_force_hw_tracking_exit(intel_dp);
-
- if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)
- schedule_work(&intel_dp->psr.work);
- mutex_unlock(&intel_dp->psr.lock);
- }
-}
+#endif
/**
* intel_psr_init - Init basic PSR work and mutex.
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 641521b101c82..58e2e5c2b81ef 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -6,7 +6,7 @@
#ifndef __INTEL_PSR_H__
#define __INTEL_PSR_H__
-#include "intel_frontbuffer.h"
+#include <linux/types.h>
struct drm_connector;
struct drm_connector_state;
@@ -29,12 +29,6 @@ void intel_psr_update(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
int intel_psr_debug_set(struct intel_dp *intel_dp, u64 value);
-void intel_psr_invalidate(struct drm_i915_private *dev_priv,
- unsigned frontbuffer_bits,
- enum fb_op_origin origin);
-void intel_psr_flush(struct drm_i915_private *dev_priv,
- unsigned frontbuffer_bits,
- enum fb_op_origin origin);
void intel_psr_init(struct intel_dp *intel_dp);
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state);
--
2.32.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Drop frontbuffer rendering support from Skylake and newer
2021-08-18 0:42 [Intel-gfx] [PATCH 0/8] Drop frontbuffer rendering support from Skylake and newer José Roberto de Souza
` (7 preceding siblings ...)
2021-08-18 0:42 ` [Intel-gfx] [PATCH 8/8] drm/i915/display: Drop PSR " José Roberto de Souza
@ 2021-08-18 1:12 ` Patchwork
2021-08-18 1:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-18 1:45 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
10 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2021-08-18 1:12 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: Drop frontbuffer rendering support from Skylake and newer
URL : https://patchwork.freedesktop.org/series/93769/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c4bc916870ba drm/damage_helper: Fix handling of cursor dirty buffers
1080e192fe73 drm/i915/display: Drop PSR support from HSW and BDW
-:267: WARNING:LONG_LINE_COMMENT: line length of 113 exceeds 100 columns
#267: FILE: drivers/gpu/drm/i915/i915_reg.h:4563:
+#define EDP_PSR_AUX_DATA(tran, i) _MMIO(_TRANS2(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */
total: 0 errors, 1 warnings, 0 checks, 240 lines checked
6d37b8b938ac drm/i915/display: Move DRRS code its own file
-:604: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#604:
new file mode 100644
-:725: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!intel_dp"
#725: FILE: drivers/gpu/drm/i915/display/intel_drrs.c:117:
+ if (intel_dp == NULL) {
-:934: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#934: FILE: drivers/gpu/drm/i915/display/intel_drrs.c:326:
+ drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
-:980: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#980: FILE: drivers/gpu/drm/i915/display/intel_drrs.c:372:
+ drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
-:1026: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#1026: FILE: drivers/gpu/drm/i915/display/intel_drrs.c:418:
+ drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
total: 0 errors, 4 warnings, 1 checks, 1071 lines checked
f8a34cf4d131 drm/i915/display: Some code improvements and code style fixes for DRRS
0be6fec2e58f drm/i915/display: Share code between intel_edp_drrs_flush and invalidate
d392eb08d84c drm/i915/display: Prepare DRRS for frontbuffer rendering drop
7abf1b3f8539 drm/i915/display/skl+: Drop frontbuffer rendering support
deb2e98252ec drm/i915/display: Drop PSR frontbuffer rendering support
-:250: WARNING:IF_0: Consider removing the code enclosed by this #if 0 and its #endif
#250: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1894:
+#if 0
total: 0 errors, 1 warnings, 0 checks, 298 lines checked
^ permalink raw reply [flat|nested] 22+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Drop frontbuffer rendering support from Skylake and newer
2021-08-18 0:42 [Intel-gfx] [PATCH 0/8] Drop frontbuffer rendering support from Skylake and newer José Roberto de Souza
` (8 preceding siblings ...)
2021-08-18 1:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Drop frontbuffer rendering support from Skylake and newer Patchwork
@ 2021-08-18 1:14 ` Patchwork
2021-08-18 1:45 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
10 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2021-08-18 1:14 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: Drop frontbuffer rendering support from Skylake and newer
URL : https://patchwork.freedesktop.org/series/93769/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
^ permalink raw reply [flat|nested] 22+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for Drop frontbuffer rendering support from Skylake and newer
2021-08-18 0:42 [Intel-gfx] [PATCH 0/8] Drop frontbuffer rendering support from Skylake and newer José Roberto de Souza
` (9 preceding siblings ...)
2021-08-18 1:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-08-18 1:45 ` Patchwork
10 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2021-08-18 1:45 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 13378 bytes --]
== Series Details ==
Series: Drop frontbuffer rendering support from Skylake and newer
URL : https://patchwork.freedesktop.org/series/93769/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10491 -> Patchwork_20841
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_20841 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20841, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20841:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-skl-guc: [PASS][1] -> [FAIL][2] +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-skl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-skl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-cfl-guc: [PASS][3] -> [FAIL][4] +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-cfl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-cfl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-icl-y: [PASS][5] -> [FAIL][6] +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-icl-y/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-icl-y/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-rkl-guc: [PASS][7] -> [FAIL][8] +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-rkl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-rkl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-skl-6700k2: [PASS][9] -> [FAIL][10] +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-skl-6700k2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-skl-6700k2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [PASS][11] -> [FAIL][12] +3 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- fi-cfl-8700k: [PASS][13] -> [FAIL][14] +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-cfl-8700k/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-cfl-8700k/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- fi-cfl-8109u: [PASS][15] -> [FAIL][16] +3 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-cfl-8109u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-cfl-8109u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- fi-glk-dsi: [PASS][17] -> [FAIL][18] +3 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-glk-dsi/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-glk-dsi/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- fi-kbl-soraka: NOTRUN -> [FAIL][19] +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-kbl-soraka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- fi-kbl-7500u: [PASS][20] -> [FAIL][21] +3 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-kbl-7500u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-kbl-7500u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- fi-bxt-dsi: [PASS][22] -> [FAIL][23] +3 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-bxt-dsi/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-bxt-dsi/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
- fi-tgl-1115g4: [PASS][24] -> [FAIL][25] +3 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- fi-cml-u2: [PASS][26] -> [FAIL][27] +3 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-cml-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-cml-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@coherency:
- {fi-jsl-1}: [PASS][28] -> [INCOMPLETE][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-jsl-1/igt@i915_selftest@live@coherency.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-jsl-1/igt@i915_selftest@live@coherency.html
* igt@i915_selftest@live@gt_heartbeat:
- {fi-jsl-1}: [PASS][30] -> [DMESG-FAIL][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-jsl-1/igt@i915_selftest@live@gt_heartbeat.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-jsl-1/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- {fi-ehl-2}: [PASS][32] -> [FAIL][33] +3 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-ehl-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-ehl-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- {fi-tgl-dsi}: [PASS][34] -> [FAIL][35] +3 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-tgl-dsi/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-tgl-dsi/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- {fi-jsl-1}: [PASS][36] -> [FAIL][37] +3 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-jsl-1/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-jsl-1/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
Known issues
------------
Here are the changes found in Patchwork_20841 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-gfx:
- fi-rkl-guc: NOTRUN -> [SKIP][38] ([fdo#109315]) +17 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-rkl-guc/igt@amdgpu/amd_basic@cs-gfx.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#2190])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_tiled_blits@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][40] ([fdo#109271]) +3 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-kbl-soraka/igt@gem_tiled_blits@basic.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][41] ([i915#1886] / [i915#2291])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +8 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#533])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- fi-rkl-guc: [DMESG-WARN][44] ([i915#3925]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-rkl-guc/igt@core_hotunplug@unbind-rebind.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-rkl-guc/igt@core_hotunplug@unbind-rebind.html
- fi-ilk-650: [DMESG-WARN][46] ([i915#164]) -> [PASS][47] +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-ilk-650/igt@core_hotunplug@unbind-rebind.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-ilk-650/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-soraka: [INCOMPLETE][48] ([i915#155]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-kbl-soraka/igt@gem_exec_suspend@basic-s0.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-kbl-soraka/igt@gem_exec_suspend@basic-s0.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [FAIL][50] ([i915#1888]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
* igt@i915_selftest@live@execlists:
- {fi-tgl-dsi}: [DMESG-FAIL][52] ([i915#1993]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10491/fi-tgl-dsi/igt@i915_selftest@live@execlists.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/fi-tgl-dsi/igt@i915_selftest@live@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#164]: https://gitlab.freedesktop.org/drm/intel/issues/164
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1993]: https://gitlab.freedesktop.org/drm/intel/issues/1993
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#3717]: https://gitlab.freedesktop.org/drm/intel/issues/3717
[i915#3925]: https://gitlab.freedesktop.org/drm/intel/issues/3925
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (36 -> 34)
------------------------------
Missing (2): fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_10491 -> Patchwork_20841
CI-20190529: 20190529
CI_DRM_10491: efa09f306ade4b8550404d7248ac743fc0cb2c7d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6177: f474644e7226dd319195ca03b3cde82ad10ac54c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20841: deb2e98252ece8cd9336dfa0e35223a0869a18c8 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
deb2e98252ec drm/i915/display: Drop PSR frontbuffer rendering support
7abf1b3f8539 drm/i915/display/skl+: Drop frontbuffer rendering support
d392eb08d84c drm/i915/display: Prepare DRRS for frontbuffer rendering drop
0be6fec2e58f drm/i915/display: Share code between intel_edp_drrs_flush and invalidate
f8a34cf4d131 drm/i915/display: Some code improvements and code style fixes for DRRS
6d37b8b938ac drm/i915/display: Move DRRS code its own file
1080e192fe73 drm/i915/display: Drop PSR support from HSW and BDW
c4bc916870ba drm/damage_helper: Fix handling of cursor dirty buffers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20841/index.html
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