[PATCH 00/18] Haswell eDP enablement v3

[PATCH 00/18] Haswell eDP enablement v3

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Hi

Here is the third version, which is the result of the discussions I had with
Daniel both on the mailing list and on IRC.

In my discussions with Daniel we were wondering about code that would or would
not be run on VGA (the only output that requires the PCH), so what I actually
did was an attempt to fix VGA and see what changes would really be needed on our
PCH code. After my investigation I partially fixed our VGA support (some modes
still didn't work) but it was enough to get a clear idea of what we would need
to do with the PCH/FDI code. The "partially fix VGA" series will come later.

So this new series contains 4 new patches at its beginning. These patches do
some small adjustments to consider the fact that we only have 1 PCH transcoder
on Haswell. This way we can avoid running PCH/FDI code on eDP, allowing us to
port even less code to use cpu_transcoder instead of pipe, possibly making
Daniel happier.

Comments? Reviews?

Thanks,
Paulo

Paulo Zanoni (18):
  drm/i915: fork a Haswell version of ironlake_crtc_{enable,disable}
  drm/i915: fix the checks inside Ironlake/Haswell crtc enable/disable
  drm/i915: simplify intel_crtc_driving_pch
  drm/i915: don't call Haswell PCH code when we can't or don't need
  drm/i915: add TRANSCODER_EDP
  drm/i915: convert PIPE_CLK_SEL to transcoder
  drm/i915: convert DDI_FUNC_CTL to transcoder
  drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state
  drm/i915: convert PIPECONF to use transcoder instead of pipe
  drm/i915: convert PIPE_MSA_MISC to transcoder
  drm/i915: convert CPU M/N timings to transcoder
  drm/i915: convert pipe timing definitions to transcoder
  drm/i915: implement workaround for VTOTAL when using TRANSCODER_EDP
  drm/i915: select the correct pipe when using TRANSCODER_EDP
  drm/i915: set the correct eDP aux channel clock divider on DDI
  drm/i915: set/unset the DDI eDP backlight
  drm/i915: turn the eDP DDI panel on/off
  drm/i915: enable DDI eDP

 drivers/gpu/drm/i915/i915_drv.h      |   8 +
 drivers/gpu/drm/i915/i915_irq.c      |  13 +-
 drivers/gpu/drm/i915/i915_reg.h      | 127 +++++++-------
 drivers/gpu/drm/i915/intel_ddi.c     | 183 ++++++++++++++------
 drivers/gpu/drm/i915/intel_display.c | 321 +++++++++++++++++++++++++++--------
 drivers/gpu/drm/i915/intel_dp.c      |  29 ++--
 drivers/gpu/drm/i915/intel_drv.h     |  19 ++-
 drivers/gpu/drm/i915/intel_sprite.c  |   4 +-
 8 files changed, 495 insertions(+), 209 deletions(-)

-- 
1.7.11.4

[PATCH 01/18] drm/i915: fork a Haswell version of ironlake_crtc_{enable, disable}

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

The way we enable and disable the PCH on Haswell changed considerably
since now we have only one PCH transcoder, so we can't keep the same
asserts and we also can't just unconditionally disable the PCH
transcoder for non-PCH outputs. So let's fork a Haswell version.

These new functions look exactly the same as the ironlake versions.
The next patches will introduce the differences.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 183 ++++++++++++++++++++++++++++++++++-
 1 file changed, 181 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0fb5542..eb4dba6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3283,6 +3283,99 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 	intel_wait_for_vblank(dev, intel_crtc->pipe);
 }
 
+static void haswell_crtc_enable(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct intel_encoder *encoder;
+	int pipe = intel_crtc->pipe;
+	int plane = intel_crtc->plane;
+	u32 temp;
+	bool is_pch_port;
+
+	WARN_ON(!crtc->enabled);
+
+	if (intel_crtc->active)
+		return;
+
+	intel_crtc->active = true;
+	intel_update_watermarks(dev);
+
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
+		temp = I915_READ(PCH_LVDS);
+		if ((temp & LVDS_PORT_EN) == 0)
+			I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
+	}
+
+	is_pch_port = intel_crtc_driving_pch(crtc);
+
+	if (is_pch_port) {
+		ironlake_fdi_pll_enable(intel_crtc);
+	} else {
+		assert_fdi_tx_disabled(dev_priv, pipe);
+		assert_fdi_rx_disabled(dev_priv, pipe);
+	}
+
+	for_each_encoder_on_crtc(dev, crtc, encoder)
+		if (encoder->pre_enable)
+			encoder->pre_enable(encoder);
+
+	if (IS_HASWELL(dev))
+		intel_ddi_enable_pipe_clock(intel_crtc);
+
+	/* Enable panel fitting for LVDS */
+	if (dev_priv->pch_pf_size &&
+	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
+		/* Force use of hard-coded filter coefficients
+		 * as some pre-programmed values are broken,
+		 * e.g. x201.
+		 */
+		I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
+		I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
+		I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
+	}
+
+	/*
+	 * On ILK+ LUT must be loaded before the pipe is running but with
+	 * clocks enabled
+	 */
+	intel_crtc_load_lut(crtc);
+
+	if (IS_HASWELL(dev)) {
+		intel_ddi_set_pipe_settings(crtc);
+		intel_ddi_enable_pipe_func(crtc);
+	}
+
+	intel_enable_pipe(dev_priv, pipe, is_pch_port);
+	intel_enable_plane(dev_priv, plane, pipe);
+
+	if (is_pch_port)
+		ironlake_pch_enable(crtc);
+
+	mutex_lock(&dev->struct_mutex);
+	intel_update_fbc(dev);
+	mutex_unlock(&dev->struct_mutex);
+
+	intel_crtc_update_cursor(crtc, true);
+
+	for_each_encoder_on_crtc(dev, crtc, encoder)
+		encoder->enable(encoder);
+
+	if (HAS_PCH_CPT(dev))
+		intel_cpt_verify_modeset(dev, intel_crtc->pipe);
+
+	/*
+	 * There seems to be a race in PCH platform hw (at least on some
+	 * outputs) where an enabled pipe still completes any pageflip right
+	 * away (as if the pipe is off) instead of waiting for vblank. As soon
+	 * as the first vblank happend, everything works as expected. Hence just
+	 * wait for one vblank before returning to avoid strange things
+	 * happening.
+	 */
+	intel_wait_for_vblank(dev, intel_crtc->pipe);
+}
+
 static void ironlake_crtc_disable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
@@ -3369,6 +3462,92 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 	mutex_unlock(&dev->struct_mutex);
 }
 
+static void haswell_crtc_disable(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct intel_encoder *encoder;
+	int pipe = intel_crtc->pipe;
+	int plane = intel_crtc->plane;
+	u32 reg, temp;
+
+
+	if (!intel_crtc->active)
+		return;
+
+	for_each_encoder_on_crtc(dev, crtc, encoder)
+		encoder->disable(encoder);
+
+	intel_crtc_wait_for_pending_flips(crtc);
+	drm_vblank_off(dev, pipe);
+	intel_crtc_update_cursor(crtc, false);
+
+	intel_disable_plane(dev_priv, plane, pipe);
+
+	if (dev_priv->cfb_plane == plane)
+		intel_disable_fbc(dev);
+
+	intel_disable_pipe(dev_priv, pipe);
+
+	if (IS_HASWELL(dev))
+		intel_ddi_disable_pipe_func(dev_priv, pipe);
+
+	/* Disable PF */
+	I915_WRITE(PF_CTL(pipe), 0);
+	I915_WRITE(PF_WIN_SZ(pipe), 0);
+
+	if (IS_HASWELL(dev))
+		intel_ddi_disable_pipe_clock(intel_crtc);
+
+	for_each_encoder_on_crtc(dev, crtc, encoder)
+		if (encoder->post_disable)
+			encoder->post_disable(encoder);
+
+	ironlake_fdi_disable(crtc);
+
+	intel_disable_transcoder(dev_priv, pipe);
+
+	if (HAS_PCH_CPT(dev)) {
+		/* disable TRANS_DP_CTL */
+		reg = TRANS_DP_CTL(pipe);
+		temp = I915_READ(reg);
+		temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
+		temp |= TRANS_DP_PORT_SEL_NONE;
+		I915_WRITE(reg, temp);
+
+		/* disable DPLL_SEL */
+		temp = I915_READ(PCH_DPLL_SEL);
+		switch (pipe) {
+		case 0:
+			temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
+			break;
+		case 1:
+			temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
+			break;
+		case 2:
+			/* C shares PLL A or B */
+			temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
+			break;
+		default:
+			BUG(); /* wtf */
+		}
+		I915_WRITE(PCH_DPLL_SEL, temp);
+	}
+
+	/* disable PCH DPLL */
+	intel_disable_pch_pll(intel_crtc);
+
+	ironlake_fdi_pll_disable(intel_crtc);
+
+	intel_crtc->active = false;
+	intel_update_watermarks(dev);
+
+	mutex_lock(&dev->struct_mutex);
+	intel_update_fbc(dev);
+	mutex_unlock(&dev->struct_mutex);
+}
+
 static void ironlake_crtc_off(struct drm_crtc *crtc)
 {
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -8109,8 +8288,8 @@ static void intel_init_display(struct drm_device *dev)
 	/* We always want a DPMS function */
 	if (IS_HASWELL(dev)) {
 		dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
-		dev_priv->display.crtc_enable = ironlake_crtc_enable;
-		dev_priv->display.crtc_disable = ironlake_crtc_disable;
+		dev_priv->display.crtc_enable = haswell_crtc_enable;
+		dev_priv->display.crtc_disable = haswell_crtc_disable;
 		dev_priv->display.off = haswell_crtc_off;
 		dev_priv->display.update_plane = ironlake_update_plane;
 	} else if (HAS_PCH_SPLIT(dev)) {
-- 
1.7.11.4

[PATCH 02/18] drm/i915: fix the checks inside Ironlake/Haswell crtc enable/disable

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

The last commit just forked the functions, this one removes Haswell
code from the Ironlake functions and removes Ironlake code from the
Haswell functions.

It is worth noticing that we are not considering CPT possible on
Haswell anymore. So far on Haswell enablement we kept trying to still
consider IBX/CPT as a possibility with a Haswell CPU, but this was
never tested, I really doubt it will work with the current code and we
don't really have plans to support it. Future patches will remove the
IBX/CPT code from other Haswell functions. Notice that we still have a
WARN on haswell_crtc_mode_set in case we detect non-LPT PCH.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 73 ++++--------------------------------
 1 file changed, 7 insertions(+), 66 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index eb4dba6..a90da35 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3228,9 +3228,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 		if (encoder->pre_enable)
 			encoder->pre_enable(encoder);
 
-	if (IS_HASWELL(dev))
-		intel_ddi_enable_pipe_clock(intel_crtc);
-
 	/* Enable panel fitting for LVDS */
 	if (dev_priv->pch_pf_size &&
 	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
@@ -3249,11 +3246,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 	 */
 	intel_crtc_load_lut(crtc);
 
-	if (IS_HASWELL(dev)) {
-		intel_ddi_set_pipe_settings(crtc);
-		intel_ddi_enable_pipe_func(crtc);
-	}
-
 	intel_enable_pipe(dev_priv, pipe, is_pch_port);
 	intel_enable_plane(dev_priv, plane, pipe);
 
@@ -3291,7 +3283,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
-	u32 temp;
 	bool is_pch_port;
 
 	WARN_ON(!crtc->enabled);
@@ -3302,12 +3293,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	intel_crtc->active = true;
 	intel_update_watermarks(dev);
 
-	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
-		temp = I915_READ(PCH_LVDS);
-		if ((temp & LVDS_PORT_EN) == 0)
-			I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
-	}
-
 	is_pch_port = intel_crtc_driving_pch(crtc);
 
 	if (is_pch_port) {
@@ -3321,12 +3306,10 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 		if (encoder->pre_enable)
 			encoder->pre_enable(encoder);
 
-	if (IS_HASWELL(dev))
-		intel_ddi_enable_pipe_clock(intel_crtc);
+	intel_ddi_enable_pipe_clock(intel_crtc);
 
-	/* Enable panel fitting for LVDS */
-	if (dev_priv->pch_pf_size &&
-	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
+	/* Enable panel fitting for eDP */
+	if (dev_priv->pch_pf_size && HAS_eDP) {
 		/* Force use of hard-coded filter coefficients
 		 * as some pre-programmed values are broken,
 		 * e.g. x201.
@@ -3342,10 +3325,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	 */
 	intel_crtc_load_lut(crtc);
 
-	if (IS_HASWELL(dev)) {
-		intel_ddi_set_pipe_settings(crtc);
-		intel_ddi_enable_pipe_func(crtc);
-	}
+	intel_ddi_set_pipe_settings(crtc);
+	intel_ddi_enable_pipe_func(crtc);
 
 	intel_enable_pipe(dev_priv, pipe, is_pch_port);
 	intel_enable_plane(dev_priv, plane, pipe);
@@ -3362,9 +3343,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		encoder->enable(encoder);
 
-	if (HAS_PCH_CPT(dev))
-		intel_cpt_verify_modeset(dev, intel_crtc->pipe);
-
 	/*
 	 * There seems to be a race in PCH platform hw (at least on some
 	 * outputs) where an enabled pipe still completes any pageflip right
@@ -3404,16 +3382,10 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 
 	intel_disable_pipe(dev_priv, pipe);
 
-	if (IS_HASWELL(dev))
-		intel_ddi_disable_pipe_func(dev_priv, pipe);
-
 	/* Disable PF */
 	I915_WRITE(PF_CTL(pipe), 0);
 	I915_WRITE(PF_WIN_SZ(pipe), 0);
 
-	if (IS_HASWELL(dev))
-		intel_ddi_disable_pipe_clock(intel_crtc);
-
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->post_disable)
 			encoder->post_disable(encoder);
@@ -3470,8 +3442,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
-	u32 reg, temp;
-
 
 	if (!intel_crtc->active)
 		return;
@@ -3490,15 +3460,13 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 
 	intel_disable_pipe(dev_priv, pipe);
 
-	if (IS_HASWELL(dev))
-		intel_ddi_disable_pipe_func(dev_priv, pipe);
+	intel_ddi_disable_pipe_func(dev_priv, pipe);
 
 	/* Disable PF */
 	I915_WRITE(PF_CTL(pipe), 0);
 	I915_WRITE(PF_WIN_SZ(pipe), 0);
 
-	if (IS_HASWELL(dev))
-		intel_ddi_disable_pipe_clock(intel_crtc);
+	intel_ddi_disable_pipe_clock(intel_crtc);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->post_disable)
@@ -3508,33 +3476,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 
 	intel_disable_transcoder(dev_priv, pipe);
 
-	if (HAS_PCH_CPT(dev)) {
-		/* disable TRANS_DP_CTL */
-		reg = TRANS_DP_CTL(pipe);
-		temp = I915_READ(reg);
-		temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
-		temp |= TRANS_DP_PORT_SEL_NONE;
-		I915_WRITE(reg, temp);
-
-		/* disable DPLL_SEL */
-		temp = I915_READ(PCH_DPLL_SEL);
-		switch (pipe) {
-		case 0:
-			temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
-			break;
-		case 1:
-			temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
-			break;
-		case 2:
-			/* C shares PLL A or B */
-			temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
-			break;
-		default:
-			BUG(); /* wtf */
-		}
-		I915_WRITE(PCH_DPLL_SEL, temp);
-	}
-
 	/* disable PCH DPLL */
 	intel_disable_pch_pll(intel_crtc);
 
-- 
1.7.11.4

[PATCH 03/18] drm/i915: simplify intel_crtc_driving_pch

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

By forking Ironlake and Haswell functions. The only callers are
{ironlake,haswell}_crtc_enable anyway, and this way we won't need to
add other checks on the Haswell version for the next gens.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 31 +++++++++++--------------------
 1 file changed, 11 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a90da35..0c4e9c5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2849,7 +2849,7 @@ static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
 	mutex_unlock(&dev->struct_mutex);
 }
 
-static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
+static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct intel_encoder *intel_encoder;
@@ -2859,23 +2859,6 @@ static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
 	 * must be driven by its own crtc; no sharing is possible.
 	 */
 	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
-
-		/* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
-		 * CPU handles all others */
-		if (IS_HASWELL(dev)) {
-			/* It is still unclear how this will work on PPT, so throw up a warning */
-			WARN_ON(!HAS_PCH_LPT(dev));
-
-			if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
-				DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
-				return true;
-			} else {
-				DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
-					      intel_encoder->type);
-				return false;
-			}
-		}
-
 		switch (intel_encoder->type) {
 		case INTEL_OUTPUT_EDP:
 			if (!intel_encoder_is_pch_edp(&intel_encoder->base))
@@ -2887,6 +2870,14 @@ static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
 	return true;
 }
 
+static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
+{
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
+		return true;
+	else
+		return false;
+}
+
 /* Program iCLKIP clock to the desired frequency */
 static void lpt_program_iclkip(struct drm_crtc *crtc)
 {
@@ -3215,7 +3206,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 			I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
 	}
 
-	is_pch_port = intel_crtc_driving_pch(crtc);
+	is_pch_port = ironlake_crtc_driving_pch(crtc);
 
 	if (is_pch_port) {
 		ironlake_fdi_pll_enable(intel_crtc);
@@ -3293,7 +3284,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	intel_crtc->active = true;
 	intel_update_watermarks(dev);
 
-	is_pch_port = intel_crtc_driving_pch(crtc);
+	is_pch_port = haswell_crtc_driving_pch(crtc);
 
 	if (is_pch_port) {
 		ironlake_fdi_pll_enable(intel_crtc);
-- 
1.7.11.4

[PATCH 04/18] drm/i915: don't call Haswell PCH code when we can't or don't need

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

On Ironlake we have one PCH transcoder and FDI per pipe, so we know
that if ironlake_crtc_driving_pch returns false we can disable the PCH
transcoder and we also know that when we disable the crtc we can also
disable the PCH transcoder.

On Haswell there is only 1 PCH transcoder and FDI and they can be used
by any CRTC. So if for one specific crtc haswell_crtc_driving_pch
returns false we can't assert anything about the state of the PCH
transcoder or the FDI link without checking if any other CRTC is using
the PCH.

So on this commit remove the "assert_fdi_{t,r}x_disabled" form
haswell_crtc_enable and also only disable FDI and the PCH transcoder
if the port being disabled was actually a PCH port (we only have one
port using PCH: the VGA port).

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 23 ++++++++++-------------
 1 file changed, 10 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0c4e9c5..67c9472 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3286,12 +3286,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 
 	is_pch_port = haswell_crtc_driving_pch(crtc);
 
-	if (is_pch_port) {
+	if (is_pch_port)
 		ironlake_fdi_pll_enable(intel_crtc);
-	} else {
-		assert_fdi_tx_disabled(dev_priv, pipe);
-		assert_fdi_rx_disabled(dev_priv, pipe);
-	}
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->pre_enable)
@@ -3433,10 +3429,13 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
+	bool is_pch_port;
 
 	if (!intel_crtc->active)
 		return;
 
+	is_pch_port = haswell_crtc_driving_pch(crtc);
+
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		encoder->disable(encoder);
 
@@ -3463,14 +3462,12 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 		if (encoder->post_disable)
 			encoder->post_disable(encoder);
 
-	ironlake_fdi_disable(crtc);
-
-	intel_disable_transcoder(dev_priv, pipe);
-
-	/* disable PCH DPLL */
-	intel_disable_pch_pll(intel_crtc);
-
-	ironlake_fdi_pll_disable(intel_crtc);
+	if (is_pch_port) {
+		ironlake_fdi_disable(crtc);
+		intel_disable_transcoder(dev_priv, pipe);
+		intel_disable_pch_pll(intel_crtc);
+		ironlake_fdi_pll_disable(intel_crtc);
+	}
 
 	intel_crtc->active = false;
 	intel_update_watermarks(dev);
-- 
1.7.11.4

[PATCH 05/18] drm/i915: add TRANSCODER_EDP

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Before Haswell we used to have the CPU pipes and the PCH transcoders.
We had the same amount of pipes and transcoders, and there was a 1:1
mapping between them. After Haswell what we used to call CPU pipe was
split into CPU pipe and CPU transcoder. So now we have 3 CPU pipes (A,
B and C), 4 CPU transcoders (A, B, C and EDP) and 1 PCH transcoder
(only used for VGA).

For all the outputs except for EDP we have an 1:1 mapping on the CPU
pipes and CPU transcoders, so if you're using CPU pipe A you have to
use CPU transcoder A. When have an eDP ouput you have to use
transcoder EDP and you can attach this CPU transcoder to any of the 3
CPU pipes. When using VGA you need to select a pair of matching CPU
pipes/transcoders (A/A, B/B, C/C) and you also need to enable/use the
PCH transcoder.

For now we're just creating the cpu_transcoder definitions and setting
cpu_transcoder to TRANSCODER_EDP on DDI eDP code, but none of the
registers was ported to use transcoder instead of pipe. The goal is to
keep the code backwards-compatible since on all cases except when
using eDP we must have pipe == cpu_transcoder.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  8 ++++++++
 drivers/gpu/drm/i915/i915_reg.h      |  1 +
 drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h     |  4 ++++
 4 files changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 987af6f..2fcf284 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -58,6 +58,14 @@ enum pipe {
 };
 #define pipe_name(p) ((p) + 'A')
 
+enum transcoder {
+	TRANSCODER_A = 0,
+	TRANSCODER_B,
+	TRANSCODER_C,
+	TRANSCODER_EDP = 0xF,
+};
+#define transcoder_name(t) ((t) + 'A')
+
 enum plane {
 	PLANE_A = 0,
 	PLANE_B,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c7c4b96..598f83a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -26,6 +26,7 @@
 #define _I915_REG_H_
 
 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
+#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
 
 #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 67c9472..214ff5a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -937,6 +937,15 @@ intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 	return true;
 }
 
+enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
+					     enum pipe pipe)
+{
+	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+	return intel_crtc->cpu_transcoder;
+}
+
 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3485,6 +3494,9 @@ static void ironlake_crtc_off(struct drm_crtc *crtc)
 
 static void haswell_crtc_off(struct drm_crtc *crtc)
 {
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+	intel_crtc->cpu_transcoder = intel_crtc->pipe;
 	intel_ddi_put_crtc_pll(crtc);
 }
 
@@ -5361,6 +5373,11 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
 		num_connectors++;
 	}
 
+	if (is_cpu_edp)
+		intel_crtc->cpu_transcoder = TRANSCODER_EDP;
+	else
+		intel_crtc->cpu_transcoder = pipe;
+
 	/* We are not sure yet this won't happen. */
 	WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
 	     INTEL_PCH_TYPE(dev));
@@ -7897,6 +7914,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
 	/* Swap pipes & planes for FBC on pre-965 */
 	intel_crtc->pipe = pipe;
 	intel_crtc->plane = pipe;
+	intel_crtc->cpu_transcoder = pipe;
 	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
 		DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
 		intel_crtc->plane = !pipe;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c2e439b..14484ef 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -195,6 +195,7 @@ struct intel_crtc {
 	struct drm_crtc base;
 	enum pipe pipe;
 	enum plane plane;
+	enum transcoder cpu_transcoder;
 	u8 lut_r[256], lut_g[256], lut_b[256];
 	/*
 	 * Whether the crtc and the connected output pipeline is active. Implies
@@ -506,6 +507,9 @@ extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 						    struct drm_crtc *crtc);
 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 				struct drm_file *file_priv);
+extern enum transcoder
+intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
+			     enum pipe pipe);
 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 
-- 
1.7.11.4

[PATCH 06/18] drm/i915: convert PIPE_CLK_SEL to transcoder

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

This register appeared in Haswell. It does not have an EDP version
because the EDP transcoder is always tied to the DDIA clock. Notice
that if we call PIPE_CLK_SEL(pipe) when pipe is PIPE_A and transcoder
is TRANSCODER_EDP we might introduce a bug, that's why this is a
transcoder register even though it does not have an EDP version.

Even though Haswell names this register PIPE_CLK_SEL, it will be
renamed to TRANS_CLK_SEL in the future, so let's just start using the
real name that makes more sense and avoids misusage.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 14 +++++++-------
 drivers/gpu/drm/i915/intel_ddi.c | 10 ++++++++--
 2 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 598f83a..99cda88 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4543,13 +4543,13 @@
 #define  PORT_CLK_SEL_WRPLL2		(5<<29)
 #define  PORT_CLK_SEL_NONE		(7<<29)
 
-/* Pipe clock selection */
-#define PIPE_CLK_SEL_A			0x46140
-#define PIPE_CLK_SEL_B			0x46144
-#define PIPE_CLK_SEL(pipe) _PIPE(pipe, PIPE_CLK_SEL_A, PIPE_CLK_SEL_B)
-/* For each pipe, we need to select the corresponding port clock */
-#define  PIPE_CLK_SEL_DISABLED		(0x0<<29)
-#define  PIPE_CLK_SEL_PORT(x)		((x+1)<<29)
+/* Transcoder clock selection */
+#define TRANS_CLK_SEL_A			0x46140
+#define TRANS_CLK_SEL_B			0x46144
+#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
+/* For each transcoder, we need to select the corresponding port clock */
+#define  TRANS_CLK_SEL_DISABLED		(0x0<<29)
+#define  TRANS_CLK_SEL_PORT(x)		((x+1)<<29)
 
 #define _PIPEA_MSA_MISC			0x60410
 #define _PIPEB_MSA_MISC			0x61410
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 81cca48..f568862 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1095,15 +1095,21 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
 	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 	enum port port = intel_ddi_get_encoder_port(intel_encoder);
+	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 
-	I915_WRITE(PIPE_CLK_SEL(intel_crtc->pipe), PIPE_CLK_SEL_PORT(port));
+	if (cpu_transcoder != TRANSCODER_EDP)
+		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+			   TRANS_CLK_SEL_PORT(port));
 }
 
 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
 {
 	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
+	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 
-	I915_WRITE(PIPE_CLK_SEL(intel_crtc->pipe), PIPE_CLK_SEL_DISABLED);
+	if (cpu_transcoder != TRANSCODER_EDP)
+		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+			   TRANS_CLK_SEL_DISABLED);
 }
 
 void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
-- 
1.7.11.4

[PATCH 07/18] drm/i915: convert DDI_FUNC_CTL to transcoder

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Because there's one instance of the register per CPU transcoder and
not per CPU pipe. This is another register that appeared for the first
time on Haswell, and even though its Haswell name is
PIPE_DDI_FUNC_CTL, it will be renamed to TRANS_DDI_FUNC_CTL, so let's
just use the new naming scheme before it confuses more people.

Notice that there's a big improvement on intel_ddi_get_hw_state due to
the new TRANSCODER_EDP.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  59 ++++++++++----------
 drivers/gpu/drm/i915/intel_ddi.c     | 101 ++++++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_display.c |   9 ++--
 drivers/gpu/drm/i915/intel_drv.h     |   4 +-
 4 files changed, 104 insertions(+), 69 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 99cda88..2628524 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4399,34 +4399,39 @@
 #define HSW_PWR_WELL_CTL6			0x45414
 
 /* Per-pipe DDI Function Control */
-#define PIPE_DDI_FUNC_CTL_A		0x60400
-#define PIPE_DDI_FUNC_CTL_B		0x61400
-#define PIPE_DDI_FUNC_CTL_C		0x62400
-#define PIPE_DDI_FUNC_CTL_EDP		0x6F400
-#define DDI_FUNC_CTL(pipe) _PIPE(pipe, PIPE_DDI_FUNC_CTL_A, \
-				       PIPE_DDI_FUNC_CTL_B)
-#define  PIPE_DDI_FUNC_ENABLE		(1<<31)
+#define TRANS_DDI_FUNC_CTL_A		0x60400
+#define TRANS_DDI_FUNC_CTL_B		0x61400
+#define TRANS_DDI_FUNC_CTL_C		0x62400
+#define TRANS_DDI_FUNC_CTL_EDP		0x6F400
+#define DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \
+					     TRANS_DDI_FUNC_CTL_B)
+#define  TRANS_DDI_FUNC_ENABLE		(1<<31)
 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
-#define  PIPE_DDI_PORT_MASK		(7<<28)
-#define  PIPE_DDI_SELECT_PORT(x)	((x)<<28)
-#define  PIPE_DDI_PORT_NONE		(0<<28)
-#define  PIPE_DDI_MODE_SELECT_MASK	(7<<24)
-#define  PIPE_DDI_MODE_SELECT_HDMI	(0<<24)
-#define  PIPE_DDI_MODE_SELECT_DVI	(1<<24)
-#define  PIPE_DDI_MODE_SELECT_DP_SST	(2<<24)
-#define  PIPE_DDI_MODE_SELECT_DP_MST	(3<<24)
-#define  PIPE_DDI_MODE_SELECT_FDI	(4<<24)
-#define  PIPE_DDI_BPC_MASK		(7<<20)
-#define  PIPE_DDI_BPC_8			(0<<20)
-#define  PIPE_DDI_BPC_10		(1<<20)
-#define  PIPE_DDI_BPC_6			(2<<20)
-#define  PIPE_DDI_BPC_12		(3<<20)
-#define  PIPE_DDI_PVSYNC		(1<<17)
-#define  PIPE_DDI_PHSYNC		(1<<16)
-#define  PIPE_DDI_BFI_ENABLE		(1<<4)
-#define  PIPE_DDI_PORT_WIDTH_X1		(0<<1)
-#define  PIPE_DDI_PORT_WIDTH_X2		(1<<1)
-#define  PIPE_DDI_PORT_WIDTH_X4		(3<<1)
+#define  TRANS_DDI_PORT_MASK		(7<<28)
+#define  TRANS_DDI_SELECT_PORT(x)	((x)<<28)
+#define  TRANS_DDI_PORT_NONE		(0<<28)
+#define  TRANS_DDI_MODE_SELECT_MASK	(7<<24)
+#define  TRANS_DDI_MODE_SELECT_HDMI	(0<<24)
+#define  TRANS_DDI_MODE_SELECT_DVI	(1<<24)
+#define  TRANS_DDI_MODE_SELECT_DP_SST	(2<<24)
+#define  TRANS_DDI_MODE_SELECT_DP_MST	(3<<24)
+#define  TRANS_DDI_MODE_SELECT_FDI	(4<<24)
+#define  TRANS_DDI_BPC_MASK		(7<<20)
+#define  TRANS_DDI_BPC_8		(0<<20)
+#define  TRANS_DDI_BPC_10		(1<<20)
+#define  TRANS_DDI_BPC_6		(2<<20)
+#define  TRANS_DDI_BPC_12		(3<<20)
+#define  TRANS_DDI_PVSYNC		(1<<17)
+#define  TRANS_DDI_PHSYNC		(1<<16)
+#define  TRANS_DDI_EDP_INPUT_MASK	(7<<12)
+#define  TRANS_DDI_EDP_INPUT_A_ON	(0<<12)
+#define  TRANS_DDI_EDP_INPUT_A_ONOFF	(4<<12)
+#define  TRANS_DDI_EDP_INPUT_B_ONOFF	(5<<12)
+#define  TRANS_DDI_EDP_INPUT_C_ONOFF	(6<<12)
+#define  TRANS_DDI_BFI_ENABLE		(1<<4)
+#define  TRANS_DDI_PORT_WIDTH_X1	(0<<1)
+#define  TRANS_DDI_PORT_WIDTH_X2	(1<<1)
+#define  TRANS_DDI_PORT_WIDTH_X4	(3<<1)
 
 /* DisplayPort Transport Control */
 #define DP_TP_CTL_A			0x64040
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f568862..93e0374 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -924,68 +924,69 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
 	struct drm_encoder *encoder = &intel_encoder->base;
 	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 	enum pipe pipe = intel_crtc->pipe;
+	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 	int type = intel_encoder->type;
 	uint32_t temp;
 
-	/* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */
-	temp = PIPE_DDI_FUNC_ENABLE;
+	/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
+	temp = TRANS_DDI_FUNC_ENABLE;
 
 	switch (intel_crtc->bpp) {
 	case 18:
-		temp |= PIPE_DDI_BPC_6;
+		temp |= TRANS_DDI_BPC_6;
 		break;
 	case 24:
-		temp |= PIPE_DDI_BPC_8;
+		temp |= TRANS_DDI_BPC_8;
 		break;
 	case 30:
-		temp |= PIPE_DDI_BPC_10;
+		temp |= TRANS_DDI_BPC_10;
 		break;
 	case 36:
-		temp |= PIPE_DDI_BPC_12;
+		temp |= TRANS_DDI_BPC_12;
 		break;
 	default:
-		WARN(1, "%d bpp unsupported by pipe DDI function\n",
+		WARN(1, "%d bpp unsupported by transcoder DDI function\n",
 		     intel_crtc->bpp);
 	}
 
 	if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
-		temp |= PIPE_DDI_PVSYNC;
+		temp |= TRANS_DDI_PVSYNC;
 	if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
-		temp |= PIPE_DDI_PHSYNC;
+		temp |= TRANS_DDI_PHSYNC;
 
 	if (type == INTEL_OUTPUT_HDMI) {
 		struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 
 		if (intel_hdmi->has_hdmi_sink)
-			temp |= PIPE_DDI_MODE_SELECT_HDMI;
+			temp |= TRANS_DDI_MODE_SELECT_HDMI;
 		else
-			temp |= PIPE_DDI_MODE_SELECT_DVI;
+			temp |= TRANS_DDI_MODE_SELECT_DVI;
 
-		temp |= PIPE_DDI_SELECT_PORT(intel_hdmi->ddi_port);
+		temp |= TRANS_DDI_SELECT_PORT(intel_hdmi->ddi_port);
 
 	} else if (type == INTEL_OUTPUT_ANALOG) {
-		temp |= PIPE_DDI_MODE_SELECT_FDI;
-		temp |= PIPE_DDI_SELECT_PORT(PORT_E);
+		temp |= TRANS_DDI_MODE_SELECT_FDI;
+		temp |= TRANS_DDI_SELECT_PORT(PORT_E);
 
 	} else if (type == INTEL_OUTPUT_DISPLAYPORT ||
 		   type == INTEL_OUTPUT_EDP) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
-		temp |= PIPE_DDI_MODE_SELECT_DP_SST;
-		temp |= PIPE_DDI_SELECT_PORT(intel_dp->port);
+		temp |= TRANS_DDI_MODE_SELECT_DP_SST;
+		temp |= TRANS_DDI_SELECT_PORT(intel_dp->port);
 
 		switch (intel_dp->lane_count) {
 		case 1:
-			temp |= PIPE_DDI_PORT_WIDTH_X1;
+			temp |= TRANS_DDI_PORT_WIDTH_X1;
 			break;
 		case 2:
-			temp |= PIPE_DDI_PORT_WIDTH_X2;
+			temp |= TRANS_DDI_PORT_WIDTH_X2;
 			break;
 		case 4:
-			temp |= PIPE_DDI_PORT_WIDTH_X4;
+			temp |= TRANS_DDI_PORT_WIDTH_X4;
 			break;
 		default:
-			temp |= PIPE_DDI_PORT_WIDTH_X4;
+			temp |= TRANS_DDI_PORT_WIDTH_X4;
 			WARN(1, "Unsupported lane count %d\n",
 			     intel_dp->lane_count);
 		}
@@ -995,17 +996,17 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
 		     intel_encoder->type, pipe);
 	}
 
-	I915_WRITE(DDI_FUNC_CTL(pipe), temp);
+	I915_WRITE(DDI_FUNC_CTL(cpu_transcoder), temp);
 }
 
-void intel_ddi_disable_pipe_func(struct drm_i915_private *dev_priv,
-				 enum pipe pipe)
+void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
+				       enum transcoder cpu_transcoder)
 {
-	uint32_t reg = DDI_FUNC_CTL(pipe);
+	uint32_t reg = DDI_FUNC_CTL(cpu_transcoder);
 	uint32_t val = I915_READ(reg);
 
-	val &= ~(PIPE_DDI_FUNC_ENABLE | PIPE_DDI_PORT_MASK);
-	val |= PIPE_DDI_PORT_NONE;
+	val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
+	val |= TRANS_DDI_PORT_NONE;
 	I915_WRITE(reg, val);
 }
 
@@ -1023,13 +1024,32 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 	if (!(tmp & DDI_BUF_CTL_ENABLE))
 		return false;
 
-	for_each_pipe(i) {
-		tmp = I915_READ(DDI_FUNC_CTL(i));
+	if (port == PORT_A) {
+		tmp = I915_READ(DDI_FUNC_CTL(TRANSCODER_EDP));
 
-		if ((tmp & PIPE_DDI_PORT_MASK)
-		    == PIPE_DDI_SELECT_PORT(port)) {
-			*pipe = i;
-			return true;
+		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
+		case TRANS_DDI_EDP_INPUT_A_ON:
+		case TRANS_DDI_EDP_INPUT_A_ONOFF:
+			*pipe = PIPE_A;
+			break;
+		case TRANS_DDI_EDP_INPUT_B_ONOFF:
+			*pipe = PIPE_B;
+			break;
+		case TRANS_DDI_EDP_INPUT_C_ONOFF:
+			*pipe = PIPE_C;
+			break;
+		}
+
+		return true;
+	} else {
+		for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
+			tmp = I915_READ(DDI_FUNC_CTL(i));
+
+			if ((tmp & TRANS_DDI_PORT_MASK)
+			    == TRANS_DDI_SELECT_PORT(port)) {
+				*pipe = i;
+				return true;
+			}
 		}
 	}
 
@@ -1043,13 +1063,20 @@ static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
 {
 	uint32_t temp, ret;
 	enum port port;
+	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
+								      pipe);
 	int i;
 
-	temp = I915_READ(DDI_FUNC_CTL(pipe));
-	temp &= PIPE_DDI_PORT_MASK;
-	for (i = PORT_A; i <= PORT_E; i++)
-		if (temp == PIPE_DDI_SELECT_PORT(i))
-			port = i;
+	if (cpu_transcoder == TRANSCODER_EDP) {
+		port = PORT_A;
+	} else {
+		temp = I915_READ(DDI_FUNC_CTL(cpu_transcoder));
+		temp &= TRANS_DDI_PORT_MASK;
+
+		for (i = PORT_B; i <= PORT_E; i++)
+			if (temp == TRANS_DDI_SELECT_PORT(i))
+				port = i;
+	}
 
 	ret = I915_READ(PORT_CLK_SEL(port));
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 214ff5a..d63da7b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1122,12 +1122,14 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 	int reg;
 	u32 val;
 	bool cur_state;
+	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
+								      pipe);
 
 	if (IS_HASWELL(dev_priv->dev)) {
 		/* On Haswell, DDI is used instead of FDI_TX_CTL */
-		reg = DDI_FUNC_CTL(pipe);
+		reg = DDI_FUNC_CTL(cpu_transcoder);
 		val = I915_READ(reg);
-		cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
+		cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 	} else {
 		reg = FDI_TX_CTL(pipe);
 		val = I915_READ(reg);
@@ -3438,6 +3440,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
+	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 	bool is_pch_port;
 
 	if (!intel_crtc->active)
@@ -3459,7 +3462,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 
 	intel_disable_pipe(dev_priv, pipe);
 
-	intel_ddi_disable_pipe_func(dev_priv, pipe);
+	intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
 
 	/* Disable PF */
 	I915_WRITE(PF_CTL(pipe), 0);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 14484ef..65927d9 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -611,8 +611,8 @@ extern void intel_ddi_mode_set(struct drm_encoder *encoder,
 				struct drm_display_mode *adjusted_mode);
 extern void intel_ddi_pll_init(struct drm_device *dev);
 extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);
-extern void intel_ddi_disable_pipe_func(struct drm_i915_private *dev_priv,
-					enum pipe pipe);
+extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
+					      enum transcoder cpu_transcoder);
 extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
-- 
1.7.11.4

[PATCH 08/18] drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

We need to check if any of the pipes is using TRANSCODER_EDP.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d63da7b..2f546e8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8690,6 +8690,31 @@ void intel_modeset_setup_hw_state(struct drm_device *dev)
 	struct intel_encoder *encoder;
 	struct intel_connector *connector;
 
+	if (IS_HASWELL(dev)) {
+		tmp = I915_READ(DDI_FUNC_CTL(TRANSCODER_EDP));
+
+		if (tmp & TRANS_DDI_FUNC_ENABLE) {
+			switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
+			case TRANS_DDI_EDP_INPUT_A_ON:
+			case TRANS_DDI_EDP_INPUT_A_ONOFF:
+				pipe = PIPE_A;
+				break;
+			case TRANS_DDI_EDP_INPUT_B_ONOFF:
+				pipe = PIPE_B;
+				break;
+			case TRANS_DDI_EDP_INPUT_C_ONOFF:
+				pipe = PIPE_C;
+				break;
+			}
+
+			crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
+			crtc->cpu_transcoder = TRANSCODER_EDP;
+
+			DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
+				      pipe_name(pipe));
+		}
+	}
+
 	for_each_pipe(pipe) {
 		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 
-- 
1.7.11.4

[PATCH 09/18] drm/i915: convert PIPECONF to use transcoder instead of pipe

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Because the PIPECONF register is actually part of the CPU transcoder,
not the CPU pipe.

Ideally we would also rename PIPECONF to TRANSCONF to remind people
that they should use the transcoder instead of the pipe, but let's
keep it like this for now since most Gens still name it PIPECONF.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c      |  5 ++++-
 drivers/gpu/drm/i915/i915_reg.h      |  2 +-
 drivers/gpu/drm/i915/intel_display.c | 35 +++++++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_sprite.c  |  4 +++-
 4 files changed, 31 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9628508..6036d21 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -122,7 +122,10 @@ static int
 i915_pipe_enabled(struct drm_device *dev, int pipe)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-	return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
+	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
+								      pipe);
+
+	return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
 }
 
 /* Called from drm generic code, passed a 'crtc', which
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2628524..439ba3d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2721,7 +2721,7 @@
 #define   PIPE_12BPC				(3 << 5)
 
 #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
-#define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
+#define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF)
 #define PIPEDSL(pipe)  _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
 #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
 #define PIPEFRAMEPIXEL(pipe)  _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2f546e8..2d1f74c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1018,9 +1018,11 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
+								      pipe);
 
 	if (INTEL_INFO(dev)->gen >= 4) {
-		int reg = PIPECONF(pipe);
+		int reg = PIPECONF(cpu_transcoder);
 
 		/* Wait for the Pipe State to go off */
 		if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
@@ -1233,12 +1235,14 @@ void assert_pipe(struct drm_i915_private *dev_priv,
 	int reg;
 	u32 val;
 	bool cur_state;
+	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
+								      pipe);
 
 	/* if we need the pipe A quirk it must be always on */
 	if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
 		state = true;
 
-	reg = PIPECONF(pipe);
+	reg = PIPECONF(cpu_transcoder);
 	val = I915_READ(reg);
 	cur_state = !!(val & PIPECONF_ENABLE);
 	WARN(cur_state != state,
@@ -1756,6 +1760,8 @@ static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
 			      bool pch_port)
 {
+	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
+								      pipe);
 	int reg;
 	u32 val;
 
@@ -1775,7 +1781,7 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
 		/* FIXME: assert CPU port conditions for SNB+ */
 	}
 
-	reg = PIPECONF(pipe);
+	reg = PIPECONF(cpu_transcoder);
 	val = I915_READ(reg);
 	if (val & PIPECONF_ENABLE)
 		return;
@@ -1799,6 +1805,8 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
 			       enum pipe pipe)
 {
+	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
+								      pipe);
 	int reg;
 	u32 val;
 
@@ -1812,7 +1820,7 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
 	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
 		return;
 
-	reg = PIPECONF(pipe);
+	reg = PIPECONF(cpu_transcoder);
 	val = I915_READ(reg);
 	if ((val & PIPECONF_ENABLE) == 0)
 		return;
@@ -4898,10 +4906,10 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc,
 {
 	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	int pipe = intel_crtc->pipe;
+	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 	uint32_t val;
 
-	val = I915_READ(PIPECONF(pipe));
+	val = I915_READ(PIPECONF(cpu_transcoder));
 
 	val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
 	if (dither)
@@ -4913,8 +4921,8 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc,
 	else
 		val |= PIPECONF_PROGRESSIVE;
 
-	I915_WRITE(PIPECONF(pipe), val);
-	POSTING_READ(PIPECONF(pipe));
+	I915_WRITE(PIPECONF(cpu_transcoder), val);
+	POSTING_READ(PIPECONF(cpu_transcoder));
 }
 
 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
@@ -5388,7 +5396,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
 	WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
 	     num_connectors, pipe_name(pipe));
 
-	WARN_ON(I915_READ(PIPECONF(pipe)) &
+	WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
 		(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
 
 	WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
@@ -8562,7 +8570,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
 	u32 reg;
 
 	/* Clear any frame start delays used for debugging left by the BIOS */
-	reg = PIPECONF(crtc->pipe);
+	reg = PIPECONF(crtc->cpu_transcoder);
 	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
 
 	/* We need to sanitize the plane -> pipe mapping first because this will
@@ -8718,7 +8726,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev)
 	for_each_pipe(pipe) {
 		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 
-		tmp = I915_READ(PIPECONF(pipe));
+		tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
 		if (tmp & PIPECONF_ENABLE)
 			crtc->active = true;
 		else
@@ -8912,6 +8920,7 @@ intel_display_capture_error_state(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct intel_display_error_state *error;
+	enum transcoder cpu_transcoder;
 	int i;
 
 	error = kmalloc(sizeof(*error), GFP_ATOMIC);
@@ -8919,6 +8928,8 @@ intel_display_capture_error_state(struct drm_device *dev)
 		return NULL;
 
 	for_each_pipe(i) {
+		cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
+
 		error->cursor[i].control = I915_READ(CURCNTR(i));
 		error->cursor[i].position = I915_READ(CURPOS(i));
 		error->cursor[i].base = I915_READ(CURBASE(i));
@@ -8933,7 +8944,7 @@ intel_display_capture_error_state(struct drm_device *dev)
 			error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
 		}
 
-		error->pipe[i].conf = I915_READ(PIPECONF(i));
+		error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
 		error->pipe[i].source = I915_READ(PIPESRC(i));
 		error->pipe[i].htotal = I915_READ(HTOTAL(i));
 		error->pipe[i].hblank = I915_READ(HBLANK(i));
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 651b87f..0c2189e 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -423,6 +423,8 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	struct intel_framebuffer *intel_fb;
 	struct drm_i915_gem_object *obj, *old_obj;
 	int pipe = intel_plane->pipe;
+	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
+								      pipe);
 	int ret = 0;
 	int x = src_x >> 16, y = src_y >> 16;
 	int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay;
@@ -437,7 +439,7 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	src_h = src_h >> 16;
 
 	/* Pipe must be running... */
-	if (!(I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE))
+	if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE))
 		return -EINVAL;
 
 	if (crtc_x >= primary_w || crtc_y >= primary_h)
-- 
1.7.11.4

[PATCH 10/18] drm/i915: convert PIPE_MSA_MISC to transcoder

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Same as the other registers. This one also appeared on Haswell for the
first time, so that's why we are renaming it.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 19 ++++++++++---------
 drivers/gpu/drm/i915/intel_ddi.c | 18 +++++++++---------
 2 files changed, 19 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 439ba3d..6ec99e3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4556,15 +4556,16 @@
 #define  TRANS_CLK_SEL_DISABLED		(0x0<<29)
 #define  TRANS_CLK_SEL_PORT(x)		((x+1)<<29)
 
-#define _PIPEA_MSA_MISC			0x60410
-#define _PIPEB_MSA_MISC			0x61410
-#define PIPE_MSA_MISC(pipe) _PIPE(pipe, _PIPEA_MSA_MISC, _PIPEB_MSA_MISC)
-#define  PIPE_MSA_SYNC_CLK		(1<<0)
-#define  PIPE_MSA_6_BPC			(0<<5)
-#define  PIPE_MSA_8_BPC			(1<<5)
-#define  PIPE_MSA_10_BPC		(2<<5)
-#define  PIPE_MSA_12_BPC		(3<<5)
-#define  PIPE_MSA_16_BPC		(4<<5)
+#define _TRANSA_MSA_MISC		0x60410
+#define _TRANSB_MSA_MISC		0x61410
+#define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \
+					       _TRANSB_MSA_MISC)
+#define  TRANS_MSA_SYNC_CLK		(1<<0)
+#define  TRANS_MSA_6_BPC		(0<<5)
+#define  TRANS_MSA_8_BPC		(1<<5)
+#define  TRANS_MSA_10_BPC		(2<<5)
+#define  TRANS_MSA_12_BPC		(3<<5)
+#define  TRANS_MSA_16_BPC		(4<<5)
 
 /* LCPLL Control */
 #define LCPLL_CTL			0x130040
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 93e0374..3283f6f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -888,32 +888,32 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
 	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
-	enum pipe pipe = intel_crtc->pipe;
+	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 	int type = intel_encoder->type;
 	uint32_t temp;
 
 	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 
-		temp = PIPE_MSA_SYNC_CLK;
+		temp = TRANS_MSA_SYNC_CLK;
 		switch (intel_crtc->bpp) {
 		case 18:
-			temp |= PIPE_MSA_6_BPC;
+			temp |= TRANS_MSA_6_BPC;
 			break;
 		case 24:
-			temp |= PIPE_MSA_8_BPC;
+			temp |= TRANS_MSA_8_BPC;
 			break;
 		case 30:
-			temp |= PIPE_MSA_10_BPC;
+			temp |= TRANS_MSA_10_BPC;
 			break;
 		case 36:
-			temp |= PIPE_MSA_12_BPC;
+			temp |= TRANS_MSA_12_BPC;
 			break;
 		default:
-			temp |= PIPE_MSA_8_BPC;
-			WARN(1, "%d bpp unsupported by pipe DDI function\n",
+			temp |= TRANS_MSA_8_BPC;
+			WARN(1, "%d bpp unsupported by DDI function\n",
 			     intel_crtc->bpp);
 		}
-		I915_WRITE(PIPE_MSA_MISC(pipe), temp);
+		I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
 	}
 }
 
-- 
1.7.11.4

[PATCH 11/18] drm/i915: convert CPU M/N timings to transcoder

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Same thing as the previous commits. Not renaming this one since it
exists since way before Haswell.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 16 ++++++++--------
 drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
 drivers/gpu/drm/i915/intel_dp.c      | 10 ++++++----
 3 files changed, 19 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6ec99e3..bf411dd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3305,14 +3305,14 @@
 #define _PIPEB_LINK_M2           0x61048
 #define _PIPEB_LINK_N2           0x6104c
 
-#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
-#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
-#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
-#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
-#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
-#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
-#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
-#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
+#define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
+#define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
+#define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
+#define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
+#define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
+#define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
+#define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
+#define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
 
 /* CPU panel fitter */
 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2d1f74c..b616a1c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4995,7 +4995,7 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	enum pipe pipe = intel_crtc->pipe;
+	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 	struct intel_encoder *intel_encoder, *edp_encoder = NULL;
 	struct fdi_m_n m_n = {0};
 	int target_clock, pixel_multiplier, lane, link_bw;
@@ -5058,10 +5058,10 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
 	ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
 			     &m_n);
 
-	I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
-	I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
-	I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
-	I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+	I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
+	I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
+	I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
+	I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
 }
 
 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fe4dc35..f15ea22 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -777,6 +777,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 	int lane_count = 4;
 	struct intel_dp_m_n m_n;
 	int pipe = intel_crtc->pipe;
+	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 
 	/*
 	 * Find the lane count in the intel_encoder private
@@ -801,10 +802,11 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 			     mode->clock, adjusted_mode->clock, &m_n);
 
 	if (IS_HASWELL(dev)) {
-		I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
-		I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
-		I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
-		I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+		I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
+			   TU_SIZE(m_n.tu) | m_n.gmch_m);
+		I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
+		I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
+		I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
 	} else if (HAS_PCH_SPLIT(dev)) {
 		I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 		I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
-- 
1.7.11.4

[PATCH 12/18] drm/i915: convert pipe timing definitions to transcoder

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c      |  8 +++++---
 drivers/gpu/drm/i915/i915_reg.h      | 14 +++++++-------
 drivers/gpu/drm/i915/intel_display.c | 37 ++++++++++++++++++------------------
 3 files changed, 31 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6036d21..b92e6bfb 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -185,6 +185,8 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 	int vbl_start, vbl_end, htotal, vtotal;
 	bool in_vbl = true;
 	int ret = 0;
+	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
+								      pipe);
 
 	if (!i915_pipe_enabled(dev, pipe)) {
 		DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
@@ -193,7 +195,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 	}
 
 	/* Get vtotal. */
-	vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
+	vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 
 	if (INTEL_INFO(dev)->gen >= 4) {
 		/* No obvious pixelcount register. Only query vertical
@@ -213,13 +215,13 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 		 */
 		position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 
-		htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
+		htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 		*vpos = position / htotal;
 		*hpos = position - (*vpos * htotal);
 	}
 
 	/* Query vblank area. */
-	vbl = I915_READ(VBLANK(pipe));
+	vbl = I915_READ(VBLANK(cpu_transcoder));
 
 	/* Test position against vblank region. */
 	vbl_start = vbl & 0x1fff;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf411dd..c475310 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1568,14 +1568,14 @@
 #define _VSYNCSHIFT_B	0x61028
 
 
-#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
-#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
-#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
-#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
-#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
-#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
+#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
+#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
+#define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
+#define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B)
+#define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B)
+#define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B)
 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
-#define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
+#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
 
 /* VGA port control */
 #define ADPA			0x61100
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b616a1c..1b72f36 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4488,6 +4488,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	enum pipe pipe = intel_crtc->pipe;
+	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 	uint32_t vsyncshift;
 
 	if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
@@ -4501,25 +4502,25 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
 	}
 
 	if (INTEL_INFO(dev)->gen > 3)
-		I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
+		I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
 
-	I915_WRITE(HTOTAL(pipe),
+	I915_WRITE(HTOTAL(cpu_transcoder),
 		   (adjusted_mode->crtc_hdisplay - 1) |
 		   ((adjusted_mode->crtc_htotal - 1) << 16));
-	I915_WRITE(HBLANK(pipe),
+	I915_WRITE(HBLANK(cpu_transcoder),
 		   (adjusted_mode->crtc_hblank_start - 1) |
 		   ((adjusted_mode->crtc_hblank_end - 1) << 16));
-	I915_WRITE(HSYNC(pipe),
+	I915_WRITE(HSYNC(cpu_transcoder),
 		   (adjusted_mode->crtc_hsync_start - 1) |
 		   ((adjusted_mode->crtc_hsync_end - 1) << 16));
 
-	I915_WRITE(VTOTAL(pipe),
+	I915_WRITE(VTOTAL(cpu_transcoder),
 		   (adjusted_mode->crtc_vdisplay - 1) |
 		   ((adjusted_mode->crtc_vtotal - 1) << 16));
-	I915_WRITE(VBLANK(pipe),
+	I915_WRITE(VBLANK(cpu_transcoder),
 		   (adjusted_mode->crtc_vblank_start - 1) |
 		   ((adjusted_mode->crtc_vblank_end - 1) << 16));
-	I915_WRITE(VSYNC(pipe),
+	I915_WRITE(VSYNC(cpu_transcoder),
 		   (adjusted_mode->crtc_vsync_start - 1) |
 		   ((adjusted_mode->crtc_vsync_end - 1) << 16));
 
@@ -6481,12 +6482,12 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	int pipe = intel_crtc->pipe;
+	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 	struct drm_display_mode *mode;
-	int htot = I915_READ(HTOTAL(pipe));
-	int hsync = I915_READ(HSYNC(pipe));
-	int vtot = I915_READ(VTOTAL(pipe));
-	int vsync = I915_READ(VSYNC(pipe));
+	int htot = I915_READ(HTOTAL(cpu_transcoder));
+	int hsync = I915_READ(HSYNC(cpu_transcoder));
+	int vtot = I915_READ(VTOTAL(cpu_transcoder));
+	int vsync = I915_READ(VSYNC(cpu_transcoder));
 
 	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
 	if (!mode)
@@ -8946,12 +8947,12 @@ intel_display_capture_error_state(struct drm_device *dev)
 
 		error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
 		error->pipe[i].source = I915_READ(PIPESRC(i));
-		error->pipe[i].htotal = I915_READ(HTOTAL(i));
-		error->pipe[i].hblank = I915_READ(HBLANK(i));
-		error->pipe[i].hsync = I915_READ(HSYNC(i));
-		error->pipe[i].vtotal = I915_READ(VTOTAL(i));
-		error->pipe[i].vblank = I915_READ(VBLANK(i));
-		error->pipe[i].vsync = I915_READ(VSYNC(i));
+		error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
+		error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
+		error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
+		error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
+		error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
+		error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
 	}
 
 	return error;
-- 
1.7.11.4

[PATCH 13/18] drm/i915: implement workaround for VTOTAL when using TRANSCODER_EDP

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

See the documentation for the DDI_FUNC_CTL register, EDP Input Select
bits: when the EDP input selection is B, the VTOTAL_B must be
programmed with the VTOTAL_EDP value, same thing for selection C.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1b72f36..b7e7814 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4524,6 +4524,17 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
 		   (adjusted_mode->crtc_vsync_start - 1) |
 		   ((adjusted_mode->crtc_vsync_end - 1) << 16));
 
+	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
+	 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
+	 * documented on the DDI_FUNC_CTL register description, EDP Input Select
+	 * bits. */
+	if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
+	    (pipe == PIPE_B || pipe == PIPE_C)) {
+		I915_WRITE(VTOTAL(pipe),
+			   (adjusted_mode->crtc_vdisplay - 1) |
+			   ((adjusted_mode->crtc_vtotal - 1) << 16));
+	}
+
 	/* pipesrc controls the size that is scaled from, which should
 	 * always be the user's requested size.
 	 */
-- 
1.7.11.4

[PATCH 14/18] drm/i915: select the correct pipe when using TRANSCODER_EDP

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 3283f6f..106c375 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -954,6 +954,23 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
 	if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
 		temp |= TRANS_DDI_PHSYNC;
 
+	if (cpu_transcoder == TRANSCODER_EDP) {
+		switch (pipe) {
+		case PIPE_A:
+			temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
+			break;
+		case PIPE_B:
+			temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
+			break;
+		case PIPE_C:
+			temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
+			break;
+		default:
+			BUG();
+			break;
+		}
+	}
+
 	if (type == INTEL_OUTPUT_HDMI) {
 		struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 
-- 
1.7.11.4

[PATCH 15/18] drm/i915: set the correct eDP aux channel clock divider on DDI

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

The cdclk frequency is not always the same, so the value here should
be adjusted to match it.

Version 2: call intel_ddi_get_cdclk_freq instead of reading
CDCLK_FREQ, because the register is just for earlier HW steppings.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 2 +-
 drivers/gpu/drm/i915/intel_dp.c  | 4 +++-
 drivers/gpu/drm/i915/intel_drv.h | 1 +
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 106c375..30b0db7 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1239,7 +1239,7 @@ void intel_disable_ddi(struct intel_encoder *encoder)
 	/* This will be needed in the future, so leave it here for now */
 }
 
-static int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
+int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
 {
 	if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
 		return 450;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f15ea22..6d30b2d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -370,7 +370,9 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 	 * clock divider.
 	 */
 	if (is_cpu_edp(intel_dp)) {
-		if (IS_VALLEYVIEW(dev))
+		if (IS_HASWELL(dev))
+			aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
+		else if (IS_VALLEYVIEW(dev))
 			aux_clock_divider = 100;
 		else if (IS_GEN6(dev) || IS_GEN7(dev))
 			aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 65927d9..c05e892 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -609,6 +609,7 @@ extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 extern void intel_ddi_mode_set(struct drm_encoder *encoder,
 				struct drm_display_mode *mode,
 				struct drm_display_mode *adjusted_mode);
+extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 extern void intel_ddi_pll_init(struct drm_device *dev);
 extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);
 extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
-- 
1.7.11.4

[PATCH 16/18] drm/i915: set/unset the DDI eDP backlight

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 15 +++++++++++++--
 drivers/gpu/drm/i915/intel_dp.c  |  4 ++--
 drivers/gpu/drm/i915/intel_drv.h |  6 ++++--
 3 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 30b0db7..232f2d0 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1231,12 +1231,23 @@ void intel_enable_ddi(struct intel_encoder *intel_encoder)
 		 * enabling the port.
 		 */
 		I915_WRITE(DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE);
+	} else if (type == INTEL_OUTPUT_EDP) {
+		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+		ironlake_edp_backlight_on(intel_dp);
 	}
 }
 
-void intel_disable_ddi(struct intel_encoder *encoder)
+void intel_disable_ddi(struct intel_encoder *intel_encoder)
 {
-	/* This will be needed in the future, so leave it here for now */
+	struct drm_encoder *encoder = &intel_encoder->base;
+	int type = intel_encoder->type;
+
+	if (type == INTEL_OUTPUT_EDP) {
+		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+		ironlake_edp_backlight_off(intel_dp);
+	}
 }
 
 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6d30b2d..d926f99 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1166,7 +1166,7 @@ static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
 	ironlake_wait_panel_off(intel_dp);
 }
 
-static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
+void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1192,7 +1192,7 @@ static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
 	intel_panel_enable_backlight(dev, pipe);
 }
 
-static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
+void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c05e892..47d62fb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -439,6 +439,8 @@ extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
 extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 extern bool intel_dpd_is_edp(struct drm_device *dev);
+extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
+extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
 extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
 extern int intel_edp_target_clock(struct intel_encoder *,
 				  struct drm_display_mode *mode);
@@ -602,8 +604,8 @@ extern void intel_disable_gt_powersave(struct drm_device *dev);
 extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
 extern void ironlake_teardown_rc6(struct drm_device *dev);
 
-extern void intel_enable_ddi(struct intel_encoder *encoder);
-extern void intel_disable_ddi(struct intel_encoder *encoder);
+extern void intel_enable_ddi(struct intel_encoder *intel_encoder);
+extern void intel_disable_ddi(struct intel_encoder *intel_encoder);
 extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 				   enum pipe *pipe);
 extern void intel_ddi_mode_set(struct drm_encoder *encoder,
-- 
1.7.11.4

[PATCH 17/18] drm/i915: turn the eDP DDI panel on/off

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

It's an important step :)

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++++++++++--
 drivers/gpu/drm/i915/intel_dp.c  | 11 ++++-------
 drivers/gpu/drm/i915/intel_drv.h |  4 ++++
 3 files changed, 24 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 232f2d0..47b52eb 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1163,12 +1163,19 @@ void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	enum port port = intel_ddi_get_encoder_port(intel_encoder);
+	int type = intel_encoder->type;
 
-	WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
+	if (type == INTEL_OUTPUT_EDP) {
+		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+		ironlake_edp_panel_vdd_on(intel_dp);
+		ironlake_edp_panel_on(intel_dp);
+		ironlake_edp_panel_vdd_off(intel_dp, true);
+	}
 
+	WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
 	I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
 
-	if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
+	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
@@ -1196,6 +1203,7 @@ void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
 	struct drm_encoder *encoder = &intel_encoder->base;
 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 	enum port port = intel_ddi_get_encoder_port(intel_encoder);
+	int type = intel_encoder->type;
 	uint32_t val;
 	bool wait = false;
 
@@ -1214,6 +1222,12 @@ void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
 	if (wait)
 		intel_wait_ddi_buf_idle(dev_priv, port);
 
+	if (type == INTEL_OUTPUT_EDP) {
+		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+		ironlake_edp_panel_vdd_on(intel_dp);
+		ironlake_edp_panel_off(intel_dp);
+	}
+
 	I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d926f99..2f7acba 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -651,9 +651,6 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 	return -EREMOTEIO;
 }
 
-static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
-static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
-
 static int
 intel_dp_i2c_init(struct intel_dp *intel_dp,
 		  struct intel_connector *intel_connector, const char *name)
@@ -1004,7 +1001,7 @@ static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
 	return control;
 }
 
-static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
+void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1074,7 +1071,7 @@ static void ironlake_panel_vdd_work(struct work_struct *__work)
 	mutex_unlock(&dev->mode_config.mutex);
 }
 
-static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
+void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
 {
 	if (!is_edp(intel_dp))
 		return;
@@ -1097,7 +1094,7 @@ static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
 	}
 }
 
-static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
+void ironlake_edp_panel_on(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1139,7 +1136,7 @@ static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
 	}
 }
 
-static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
+void ironlake_edp_panel_off(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 47d62fb..b9faeec 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -441,6 +441,10 @@ extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 extern bool intel_dpd_is_edp(struct drm_device *dev);
 extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
 extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
+extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
+extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
+extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
+extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
 extern int intel_edp_target_clock(struct intel_encoder *,
 				  struct drm_display_mode *mode);
-- 
1.7.11.4

[PATCH 18/18] drm/i915: enable DDI eDP

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Now that all the eDP enablement bits are there, we can actually try to
use the eDP.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 47b52eb..760d290 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -242,8 +242,8 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
 
 	switch(port){
 	case PORT_A:
-		/* We don't handle eDP and DP yet */
 		DRM_DEBUG_DRIVER("Found digital output on DDI port A\n");
+		intel_dp_init(dev, DDI_BUF_CTL_A, PORT_A);
 		break;
 	/* Assume that the  ports B, C and D are working in HDMI mode for now */
 	case PORT_B:
-- 
1.7.11.4

Re: [PATCH 13/18] drm/i915: implement workaround for VTOTAL when using TRANSCODER_EDP

[Daniel Vetter]

On Tue, Oct 23, 2012 at 06:30:03PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> See the documentation for the DDI_FUNC_CTL register, EDP Input Select
> bits: when the EDP input selection is B, the VTOTAL_B must be
> programmed with the VTOTAL_EDP value, same thing for selection C.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 1b72f36..b7e7814 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4524,6 +4524,17 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
>  		   (adjusted_mode->crtc_vsync_start - 1) |
>  		   ((adjusted_mode->crtc_vsync_end - 1) << 16));
>  
> +	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
> +	 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
> +	 * documented on the DDI_FUNC_CTL register description, EDP Input Select
> +	 * bits. */
> +	if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
> +	    (pipe == PIPE_B || pipe == PIPE_C)) {
> +		I915_WRITE(VTOTAL(pipe),
> +			   (adjusted_mode->crtc_vdisplay - 1) |
> +			   ((adjusted_mode->crtc_vtotal - 1) << 16));

Tiny bikeshed: I'd prefer I915_WRITE(VTOTAL(pipe),
				     I915_READ(VTOTAL(cpu_transcoder));

since that makes it really clear that we're filling in the same value. We
have the same pattern already in the code, e.g. for the pch transcoder
stuff.
-Daniel

> +	}
> +
>  	/* pipesrc controls the size that is scaled from, which should
>  	 * always be the user's requested size.
>  	 */
> -- 
> 1.7.11.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 08/18] drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state

[Daniel Vetter]

On Tue, Oct 23, 2012 at 06:29:58PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> We need to check if any of the pipes is using TRANSCODER_EDP.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

One thing that irks me is that you add new state readout code here, but
don't call the same code in the modeset_check_state code. Now the design
behind all these ->get_hw_state functions is very much that we use the
exact same code to check the modeset state as we do for fastboot. For
otherwise we simply won't get enough testcoverage for the fastboot code -
but if we also use it to check all our own state, we should be able to
take over at least all the crazy configs our driver leaves behind.

I'm ok with merging this as-is, but I'd like you to fix this up in a
follow-up series. As a rule of thumb the exact same hw state readout code
should be used in setup_hw_state (for fastboot) as for the modeset state
checks. Might be that we need to add a get_crtc_hw_state function and a
intel_crtc_hw_state struct which contains all the interesting bits (which
transcoder, pch resources, eventually modes and shared plls, ...) that we
could either store in the intel_crtc (for setup_hw_state) or compare with
the stored state in intel_crtc.

Also, modeset_check_state should grow cross checks imo to ensure that we
don't wire up these cpu transcoders in a stupid way (or leave an unused
transcoder enabled).

Cheers, Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d63da7b..2f546e8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8690,6 +8690,31 @@ void intel_modeset_setup_hw_state(struct drm_device *dev)
>  	struct intel_encoder *encoder;
>  	struct intel_connector *connector;
>  
> +	if (IS_HASWELL(dev)) {
> +		tmp = I915_READ(DDI_FUNC_CTL(TRANSCODER_EDP));
> +
> +		if (tmp & TRANS_DDI_FUNC_ENABLE) {
> +			switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
> +			case TRANS_DDI_EDP_INPUT_A_ON:
> +			case TRANS_DDI_EDP_INPUT_A_ONOFF:
> +				pipe = PIPE_A;
> +				break;
> +			case TRANS_DDI_EDP_INPUT_B_ONOFF:
> +				pipe = PIPE_B;
> +				break;
> +			case TRANS_DDI_EDP_INPUT_C_ONOFF:
> +				pipe = PIPE_C;
> +				break;
> +			}
> +
> +			crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
> +			crtc->cpu_transcoder = TRANSCODER_EDP;
> +
> +			DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
> +				      pipe_name(pipe));
> +		}
> +	}
> +
>  	for_each_pipe(pipe) {
>  		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
>  
> -- 
> 1.7.11.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 01/18] drm/i915: fork a Haswell version of ironlake_crtc_{enable, disable}

[Rodrigo Vivi]

[-- Attachment #1.1: Type: text/plain, Size: 8699 bytes --]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Tue, Oct 23, 2012 at 6:29 PM, Paulo Zanoni <przanoni@gmail.com> wrote:

> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> The way we enable and disable the PCH on Haswell changed considerably
> since now we have only one PCH transcoder, so we can't keep the same
> asserts and we also can't just unconditionally disable the PCH
> transcoder for non-PCH outputs. So let's fork a Haswell version.
>
> These new functions look exactly the same as the ironlake versions.
> The next patches will introduce the differences.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 183
> ++++++++++++++++++++++++++++++++++-
>  1 file changed, 181 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 0fb5542..eb4dba6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3283,6 +3283,99 @@ static void ironlake_crtc_enable(struct drm_crtc
> *crtc)
>         intel_wait_for_vblank(dev, intel_crtc->pipe);
>  }
>
> +static void haswell_crtc_enable(struct drm_crtc *crtc)
> +{
> +       struct drm_device *dev = crtc->dev;
> +       struct drm_i915_private *dev_priv = dev->dev_private;
> +       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +       struct intel_encoder *encoder;
> +       int pipe = intel_crtc->pipe;
> +       int plane = intel_crtc->plane;
> +       u32 temp;
> +       bool is_pch_port;
> +
> +       WARN_ON(!crtc->enabled);
> +
> +       if (intel_crtc->active)
> +               return;
> +
> +       intel_crtc->active = true;
> +       intel_update_watermarks(dev);
> +
> +       if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
> +               temp = I915_READ(PCH_LVDS);
> +               if ((temp & LVDS_PORT_EN) == 0)
> +                       I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
> +       }
> +
> +       is_pch_port = intel_crtc_driving_pch(crtc);
> +
> +       if (is_pch_port) {
> +               ironlake_fdi_pll_enable(intel_crtc);
> +       } else {
> +               assert_fdi_tx_disabled(dev_priv, pipe);
> +               assert_fdi_rx_disabled(dev_priv, pipe);
> +       }
> +
> +       for_each_encoder_on_crtc(dev, crtc, encoder)
> +               if (encoder->pre_enable)
> +                       encoder->pre_enable(encoder);
> +
> +       if (IS_HASWELL(dev))
> +               intel_ddi_enable_pipe_clock(intel_crtc);
> +
> +       /* Enable panel fitting for LVDS */
> +       if (dev_priv->pch_pf_size &&
> +           (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
> +               /* Force use of hard-coded filter coefficients
> +                * as some pre-programmed values are broken,
> +                * e.g. x201.
> +                */
> +               I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
> +               I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
> +               I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
> +       }
> +
> +       /*
> +        * On ILK+ LUT must be loaded before the pipe is running but with
> +        * clocks enabled
> +        */
> +       intel_crtc_load_lut(crtc);
> +
> +       if (IS_HASWELL(dev)) {
> +               intel_ddi_set_pipe_settings(crtc);
> +               intel_ddi_enable_pipe_func(crtc);
> +       }
> +
> +       intel_enable_pipe(dev_priv, pipe, is_pch_port);
> +       intel_enable_plane(dev_priv, plane, pipe);
> +
> +       if (is_pch_port)
> +               ironlake_pch_enable(crtc);
> +
> +       mutex_lock(&dev->struct_mutex);
> +       intel_update_fbc(dev);
> +       mutex_unlock(&dev->struct_mutex);
> +
> +       intel_crtc_update_cursor(crtc, true);
> +
> +       for_each_encoder_on_crtc(dev, crtc, encoder)
> +               encoder->enable(encoder);
> +
> +       if (HAS_PCH_CPT(dev))
> +               intel_cpt_verify_modeset(dev, intel_crtc->pipe);
> +
> +       /*
> +        * There seems to be a race in PCH platform hw (at least on some
> +        * outputs) where an enabled pipe still completes any pageflip
> right
> +        * away (as if the pipe is off) instead of waiting for vblank. As
> soon
> +        * as the first vblank happend, everything works as expected.
> Hence just
> +        * wait for one vblank before returning to avoid strange things
> +        * happening.
> +        */
> +       intel_wait_for_vblank(dev, intel_crtc->pipe);
> +}
> +
>  static void ironlake_crtc_disable(struct drm_crtc *crtc)
>  {
>         struct drm_device *dev = crtc->dev;
> @@ -3369,6 +3462,92 @@ static void ironlake_crtc_disable(struct drm_crtc
> *crtc)
>         mutex_unlock(&dev->struct_mutex);
>  }
>
> +static void haswell_crtc_disable(struct drm_crtc *crtc)
> +{
> +       struct drm_device *dev = crtc->dev;
> +       struct drm_i915_private *dev_priv = dev->dev_private;
> +       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +       struct intel_encoder *encoder;
> +       int pipe = intel_crtc->pipe;
> +       int plane = intel_crtc->plane;
> +       u32 reg, temp;
> +
> +
> +       if (!intel_crtc->active)
> +               return;
> +
> +       for_each_encoder_on_crtc(dev, crtc, encoder)
> +               encoder->disable(encoder);
> +
> +       intel_crtc_wait_for_pending_flips(crtc);
> +       drm_vblank_off(dev, pipe);
> +       intel_crtc_update_cursor(crtc, false);
> +
> +       intel_disable_plane(dev_priv, plane, pipe);
> +
> +       if (dev_priv->cfb_plane == plane)
> +               intel_disable_fbc(dev);
> +
> +       intel_disable_pipe(dev_priv, pipe);
> +
> +       if (IS_HASWELL(dev))
> +               intel_ddi_disable_pipe_func(dev_priv, pipe);
> +
> +       /* Disable PF */
> +       I915_WRITE(PF_CTL(pipe), 0);
> +       I915_WRITE(PF_WIN_SZ(pipe), 0);
> +
> +       if (IS_HASWELL(dev))
> +               intel_ddi_disable_pipe_clock(intel_crtc);
> +
> +       for_each_encoder_on_crtc(dev, crtc, encoder)
> +               if (encoder->post_disable)
> +                       encoder->post_disable(encoder);
> +
> +       ironlake_fdi_disable(crtc);
> +
> +       intel_disable_transcoder(dev_priv, pipe);
> +
> +       if (HAS_PCH_CPT(dev)) {
> +               /* disable TRANS_DP_CTL */
> +               reg = TRANS_DP_CTL(pipe);
> +               temp = I915_READ(reg);
> +               temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
> +               temp |= TRANS_DP_PORT_SEL_NONE;
> +               I915_WRITE(reg, temp);
> +
> +               /* disable DPLL_SEL */
> +               temp = I915_READ(PCH_DPLL_SEL);
> +               switch (pipe) {
> +               case 0:
> +                       temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
> +                       break;
> +               case 1:
> +                       temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
> +                       break;
> +               case 2:
> +                       /* C shares PLL A or B */
> +                       temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
> +                       break;
> +               default:
> +                       BUG(); /* wtf */
> +               }
> +               I915_WRITE(PCH_DPLL_SEL, temp);
> +       }
> +
> +       /* disable PCH DPLL */
> +       intel_disable_pch_pll(intel_crtc);
> +
> +       ironlake_fdi_pll_disable(intel_crtc);
> +
> +       intel_crtc->active = false;
> +       intel_update_watermarks(dev);
> +
> +       mutex_lock(&dev->struct_mutex);
> +       intel_update_fbc(dev);
> +       mutex_unlock(&dev->struct_mutex);
> +}
> +
>  static void ironlake_crtc_off(struct drm_crtc *crtc)
>  {
>         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -8109,8 +8288,8 @@ static void intel_init_display(struct drm_device
> *dev)
>         /* We always want a DPMS function */
>         if (IS_HASWELL(dev)) {
>                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
> -               dev_priv->display.crtc_enable = ironlake_crtc_enable;
> -               dev_priv->display.crtc_disable = ironlake_crtc_disable;
> +               dev_priv->display.crtc_enable = haswell_crtc_enable;
> +               dev_priv->display.crtc_disable = haswell_crtc_disable;
>                 dev_priv->display.off = haswell_crtc_off;
>                 dev_priv->display.update_plane = ironlake_update_plane;
>         } else if (HAS_PCH_SPLIT(dev)) {
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

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Re: [PATCH 02/18] drm/i915: fix the checks inside Ironlake/Haswell crtc enable/disable

[Rodrigo Vivi]

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Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Tue, Oct 23, 2012 at 6:29 PM, Paulo Zanoni <przanoni@gmail.com> wrote:

> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> The last commit just forked the functions, this one removes Haswell
> code from the Ironlake functions and removes Ironlake code from the
> Haswell functions.
>
> It is worth noticing that we are not considering CPT possible on
> Haswell anymore. So far on Haswell enablement we kept trying to still
> consider IBX/CPT as a possibility with a Haswell CPU, but this was
> never tested, I really doubt it will work with the current code and we
> don't really have plans to support it. Future patches will remove the
> IBX/CPT code from other Haswell functions. Notice that we still have a
> WARN on haswell_crtc_mode_set in case we detect non-LPT PCH.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 73
> ++++--------------------------------
>  1 file changed, 7 insertions(+), 66 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index eb4dba6..a90da35 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3228,9 +3228,6 @@ static void ironlake_crtc_enable(struct drm_crtc
> *crtc)
>                 if (encoder->pre_enable)
>                         encoder->pre_enable(encoder);
>
> -       if (IS_HASWELL(dev))
> -               intel_ddi_enable_pipe_clock(intel_crtc);
> -
>         /* Enable panel fitting for LVDS */
>         if (dev_priv->pch_pf_size &&
>             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
> @@ -3249,11 +3246,6 @@ static void ironlake_crtc_enable(struct drm_crtc
> *crtc)
>          */
>         intel_crtc_load_lut(crtc);
>
> -       if (IS_HASWELL(dev)) {
> -               intel_ddi_set_pipe_settings(crtc);
> -               intel_ddi_enable_pipe_func(crtc);
> -       }
> -
>         intel_enable_pipe(dev_priv, pipe, is_pch_port);
>         intel_enable_plane(dev_priv, plane, pipe);
>
> @@ -3291,7 +3283,6 @@ static void haswell_crtc_enable(struct drm_crtc
> *crtc)
>         struct intel_encoder *encoder;
>         int pipe = intel_crtc->pipe;
>         int plane = intel_crtc->plane;
> -       u32 temp;
>         bool is_pch_port;
>
>         WARN_ON(!crtc->enabled);
> @@ -3302,12 +3293,6 @@ static void haswell_crtc_enable(struct drm_crtc
> *crtc)
>         intel_crtc->active = true;
>         intel_update_watermarks(dev);
>
> -       if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
> -               temp = I915_READ(PCH_LVDS);
> -               if ((temp & LVDS_PORT_EN) == 0)
> -                       I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
> -       }
> -
>         is_pch_port = intel_crtc_driving_pch(crtc);
>
>         if (is_pch_port) {
> @@ -3321,12 +3306,10 @@ static void haswell_crtc_enable(struct drm_crtc
> *crtc)
>                 if (encoder->pre_enable)
>                         encoder->pre_enable(encoder);
>
> -       if (IS_HASWELL(dev))
> -               intel_ddi_enable_pipe_clock(intel_crtc);
> +       intel_ddi_enable_pipe_clock(intel_crtc);
>
> -       /* Enable panel fitting for LVDS */
> -       if (dev_priv->pch_pf_size &&
> -           (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
> +       /* Enable panel fitting for eDP */
> +       if (dev_priv->pch_pf_size && HAS_eDP) {
>                 /* Force use of hard-coded filter coefficients
>                  * as some pre-programmed values are broken,
>                  * e.g. x201.
> @@ -3342,10 +3325,8 @@ static void haswell_crtc_enable(struct drm_crtc
> *crtc)
>          */
>         intel_crtc_load_lut(crtc);
>
> -       if (IS_HASWELL(dev)) {
> -               intel_ddi_set_pipe_settings(crtc);
> -               intel_ddi_enable_pipe_func(crtc);
> -       }
> +       intel_ddi_set_pipe_settings(crtc);
> +       intel_ddi_enable_pipe_func(crtc);
>
>         intel_enable_pipe(dev_priv, pipe, is_pch_port);
>         intel_enable_plane(dev_priv, plane, pipe);
> @@ -3362,9 +3343,6 @@ static void haswell_crtc_enable(struct drm_crtc
> *crtc)
>         for_each_encoder_on_crtc(dev, crtc, encoder)
>                 encoder->enable(encoder);
>
> -       if (HAS_PCH_CPT(dev))
> -               intel_cpt_verify_modeset(dev, intel_crtc->pipe);
> -
>         /*
>          * There seems to be a race in PCH platform hw (at least on some
>          * outputs) where an enabled pipe still completes any pageflip
> right
> @@ -3404,16 +3382,10 @@ static void ironlake_crtc_disable(struct drm_crtc
> *crtc)
>
>         intel_disable_pipe(dev_priv, pipe);
>
> -       if (IS_HASWELL(dev))
> -               intel_ddi_disable_pipe_func(dev_priv, pipe);
> -
>         /* Disable PF */
>         I915_WRITE(PF_CTL(pipe), 0);
>         I915_WRITE(PF_WIN_SZ(pipe), 0);
>
> -       if (IS_HASWELL(dev))
> -               intel_ddi_disable_pipe_clock(intel_crtc);
> -
>         for_each_encoder_on_crtc(dev, crtc, encoder)
>                 if (encoder->post_disable)
>                         encoder->post_disable(encoder);
> @@ -3470,8 +3442,6 @@ static void haswell_crtc_disable(struct drm_crtc
> *crtc)
>         struct intel_encoder *encoder;
>         int pipe = intel_crtc->pipe;
>         int plane = intel_crtc->plane;
> -       u32 reg, temp;
> -
>
>         if (!intel_crtc->active)
>                 return;
> @@ -3490,15 +3460,13 @@ static void haswell_crtc_disable(struct drm_crtc
> *crtc)
>
>         intel_disable_pipe(dev_priv, pipe);
>
> -       if (IS_HASWELL(dev))
> -               intel_ddi_disable_pipe_func(dev_priv, pipe);
> +       intel_ddi_disable_pipe_func(dev_priv, pipe);
>
>         /* Disable PF */
>         I915_WRITE(PF_CTL(pipe), 0);
>         I915_WRITE(PF_WIN_SZ(pipe), 0);
>
> -       if (IS_HASWELL(dev))
> -               intel_ddi_disable_pipe_clock(intel_crtc);
> +       intel_ddi_disable_pipe_clock(intel_crtc);
>
>         for_each_encoder_on_crtc(dev, crtc, encoder)
>                 if (encoder->post_disable)
> @@ -3508,33 +3476,6 @@ static void haswell_crtc_disable(struct drm_crtc
> *crtc)
>
>         intel_disable_transcoder(dev_priv, pipe);
>
> -       if (HAS_PCH_CPT(dev)) {
> -               /* disable TRANS_DP_CTL */
> -               reg = TRANS_DP_CTL(pipe);
> -               temp = I915_READ(reg);
> -               temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
> -               temp |= TRANS_DP_PORT_SEL_NONE;
> -               I915_WRITE(reg, temp);
> -
> -               /* disable DPLL_SEL */
> -               temp = I915_READ(PCH_DPLL_SEL);
> -               switch (pipe) {
> -               case 0:
> -                       temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
> -                       break;
> -               case 1:
> -                       temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
> -                       break;
> -               case 2:
> -                       /* C shares PLL A or B */
> -                       temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
> -                       break;
> -               default:
> -                       BUG(); /* wtf */
> -               }
> -               I915_WRITE(PCH_DPLL_SEL, temp);
> -       }
> -
>         /* disable PCH DPLL */
>         intel_disable_pch_pll(intel_crtc);
>
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

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Re: [PATCH 02/18] drm/i915: fix the checks inside Ironlake/Haswell crtc enable/disable

[Paulo Zanoni]

Hi

2012/10/23 Paulo Zanoni <przanoni@gmail.com>:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> The last commit just forked the functions, this one removes Haswell
> code from the Ironlake functions and removes Ironlake code from the
> Haswell functions.
>
> It is worth noticing that we are not considering CPT possible on
> Haswell anymore. So far on Haswell enablement we kept trying to still
> consider IBX/CPT as a possibility with a Haswell CPU, but this was
> never tested, I really doubt it will work with the current code and we
> don't really have plans to support it. Future patches will remove the
> IBX/CPT code from other Haswell functions. Notice that we still have a
> WARN on haswell_crtc_mode_set in case we detect non-LPT PCH.

Chris suggested splitting this patch in 2, so I'm resending them as
patches "02-1/18" and "02-2/18". Should be equivalent.

>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 73 ++++--------------------------------
>  1 file changed, 7 insertions(+), 66 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index eb4dba6..a90da35 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3228,9 +3228,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>                 if (encoder->pre_enable)
>                         encoder->pre_enable(encoder);
>
> -       if (IS_HASWELL(dev))
> -               intel_ddi_enable_pipe_clock(intel_crtc);
> -
>         /* Enable panel fitting for LVDS */
>         if (dev_priv->pch_pf_size &&
>             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
> @@ -3249,11 +3246,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>          */
>         intel_crtc_load_lut(crtc);
>
> -       if (IS_HASWELL(dev)) {
> -               intel_ddi_set_pipe_settings(crtc);
> -               intel_ddi_enable_pipe_func(crtc);
> -       }
> -
>         intel_enable_pipe(dev_priv, pipe, is_pch_port);
>         intel_enable_plane(dev_priv, plane, pipe);
>
> @@ -3291,7 +3283,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>         struct intel_encoder *encoder;
>         int pipe = intel_crtc->pipe;
>         int plane = intel_crtc->plane;
> -       u32 temp;
>         bool is_pch_port;
>
>         WARN_ON(!crtc->enabled);
> @@ -3302,12 +3293,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>         intel_crtc->active = true;
>         intel_update_watermarks(dev);
>
> -       if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
> -               temp = I915_READ(PCH_LVDS);
> -               if ((temp & LVDS_PORT_EN) == 0)
> -                       I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
> -       }
> -
>         is_pch_port = intel_crtc_driving_pch(crtc);
>
>         if (is_pch_port) {
> @@ -3321,12 +3306,10 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>                 if (encoder->pre_enable)
>                         encoder->pre_enable(encoder);
>
> -       if (IS_HASWELL(dev))
> -               intel_ddi_enable_pipe_clock(intel_crtc);
> +       intel_ddi_enable_pipe_clock(intel_crtc);
>
> -       /* Enable panel fitting for LVDS */
> -       if (dev_priv->pch_pf_size &&
> -           (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
> +       /* Enable panel fitting for eDP */
> +       if (dev_priv->pch_pf_size && HAS_eDP) {
>                 /* Force use of hard-coded filter coefficients
>                  * as some pre-programmed values are broken,
>                  * e.g. x201.
> @@ -3342,10 +3325,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>          */
>         intel_crtc_load_lut(crtc);
>
> -       if (IS_HASWELL(dev)) {
> -               intel_ddi_set_pipe_settings(crtc);
> -               intel_ddi_enable_pipe_func(crtc);
> -       }
> +       intel_ddi_set_pipe_settings(crtc);
> +       intel_ddi_enable_pipe_func(crtc);
>
>         intel_enable_pipe(dev_priv, pipe, is_pch_port);
>         intel_enable_plane(dev_priv, plane, pipe);
> @@ -3362,9 +3343,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>         for_each_encoder_on_crtc(dev, crtc, encoder)
>                 encoder->enable(encoder);
>
> -       if (HAS_PCH_CPT(dev))
> -               intel_cpt_verify_modeset(dev, intel_crtc->pipe);
> -
>         /*
>          * There seems to be a race in PCH platform hw (at least on some
>          * outputs) where an enabled pipe still completes any pageflip right
> @@ -3404,16 +3382,10 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
>
>         intel_disable_pipe(dev_priv, pipe);
>
> -       if (IS_HASWELL(dev))
> -               intel_ddi_disable_pipe_func(dev_priv, pipe);
> -
>         /* Disable PF */
>         I915_WRITE(PF_CTL(pipe), 0);
>         I915_WRITE(PF_WIN_SZ(pipe), 0);
>
> -       if (IS_HASWELL(dev))
> -               intel_ddi_disable_pipe_clock(intel_crtc);
> -
>         for_each_encoder_on_crtc(dev, crtc, encoder)
>                 if (encoder->post_disable)
>                         encoder->post_disable(encoder);
> @@ -3470,8 +3442,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
>         struct intel_encoder *encoder;
>         int pipe = intel_crtc->pipe;
>         int plane = intel_crtc->plane;
> -       u32 reg, temp;
> -
>
>         if (!intel_crtc->active)
>                 return;
> @@ -3490,15 +3460,13 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
>
>         intel_disable_pipe(dev_priv, pipe);
>
> -       if (IS_HASWELL(dev))
> -               intel_ddi_disable_pipe_func(dev_priv, pipe);
> +       intel_ddi_disable_pipe_func(dev_priv, pipe);
>
>         /* Disable PF */
>         I915_WRITE(PF_CTL(pipe), 0);
>         I915_WRITE(PF_WIN_SZ(pipe), 0);
>
> -       if (IS_HASWELL(dev))
> -               intel_ddi_disable_pipe_clock(intel_crtc);
> +       intel_ddi_disable_pipe_clock(intel_crtc);
>
>         for_each_encoder_on_crtc(dev, crtc, encoder)
>                 if (encoder->post_disable)
> @@ -3508,33 +3476,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
>
>         intel_disable_transcoder(dev_priv, pipe);
>
> -       if (HAS_PCH_CPT(dev)) {
> -               /* disable TRANS_DP_CTL */
> -               reg = TRANS_DP_CTL(pipe);
> -               temp = I915_READ(reg);
> -               temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
> -               temp |= TRANS_DP_PORT_SEL_NONE;
> -               I915_WRITE(reg, temp);
> -
> -               /* disable DPLL_SEL */
> -               temp = I915_READ(PCH_DPLL_SEL);
> -               switch (pipe) {
> -               case 0:
> -                       temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
> -                       break;
> -               case 1:
> -                       temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
> -                       break;
> -               case 2:
> -                       /* C shares PLL A or B */
> -                       temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
> -                       break;
> -               default:
> -                       BUG(); /* wtf */
> -               }
> -               I915_WRITE(PCH_DPLL_SEL, temp);
> -       }
> -
>         /* disable PCH DPLL */
>         intel_disable_pch_pll(intel_crtc);
>
> --
> 1.7.11.4
>



-- 
Paulo Zanoni

[PATCH 02-1/18] drm/i915: fix checks inside ironlake_crtc_{enable, disable}

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

The last commit forked a Haswell version, so now we remove Haswell
code from these functions.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 14 --------------
 1 file changed, 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index eb4dba6..e5dc22c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3228,9 +3228,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 		if (encoder->pre_enable)
 			encoder->pre_enable(encoder);
 
-	if (IS_HASWELL(dev))
-		intel_ddi_enable_pipe_clock(intel_crtc);
-
 	/* Enable panel fitting for LVDS */
 	if (dev_priv->pch_pf_size &&
 	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
@@ -3249,11 +3246,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 	 */
 	intel_crtc_load_lut(crtc);
 
-	if (IS_HASWELL(dev)) {
-		intel_ddi_set_pipe_settings(crtc);
-		intel_ddi_enable_pipe_func(crtc);
-	}
-
 	intel_enable_pipe(dev_priv, pipe, is_pch_port);
 	intel_enable_plane(dev_priv, plane, pipe);
 
@@ -3404,16 +3396,10 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 
 	intel_disable_pipe(dev_priv, pipe);
 
-	if (IS_HASWELL(dev))
-		intel_ddi_disable_pipe_func(dev_priv, pipe);
-
 	/* Disable PF */
 	I915_WRITE(PF_CTL(pipe), 0);
 	I915_WRITE(PF_WIN_SZ(pipe), 0);
 
-	if (IS_HASWELL(dev))
-		intel_ddi_disable_pipe_clock(intel_crtc);
-
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->post_disable)
 			encoder->post_disable(encoder);
-- 
1.7.11.4

[PATCH 02-2/18] drm/i915: fix checks inside haswell_crtc_{enable, disable}

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

These functions were forked from their Ironlake versions, so now fix
the gen checks to reflect the fact that they will only run on Haswell.

It is worth noticing that we are not considering IBX/CPT possible on
Haswell anymore. So far on Haswell enablement we kept trying to still
consider IBX/CPT as a possibility with a Haswell CPU, but this was
never tested, I really doubt it will work with the current code and we
don't really have plans to support it. Future patches will remove the
IBX/CPT code from other Haswell functions. Notice that we still have a
WARN on haswell_crtc_mode_set in case we detect non-LPT PCH.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 59 +++++-------------------------------
 1 file changed, 7 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e5dc22c..a90da35 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3283,7 +3283,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
-	u32 temp;
 	bool is_pch_port;
 
 	WARN_ON(!crtc->enabled);
@@ -3294,12 +3293,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	intel_crtc->active = true;
 	intel_update_watermarks(dev);
 
-	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
-		temp = I915_READ(PCH_LVDS);
-		if ((temp & LVDS_PORT_EN) == 0)
-			I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
-	}
-
 	is_pch_port = intel_crtc_driving_pch(crtc);
 
 	if (is_pch_port) {
@@ -3313,12 +3306,10 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 		if (encoder->pre_enable)
 			encoder->pre_enable(encoder);
 
-	if (IS_HASWELL(dev))
-		intel_ddi_enable_pipe_clock(intel_crtc);
+	intel_ddi_enable_pipe_clock(intel_crtc);
 
-	/* Enable panel fitting for LVDS */
-	if (dev_priv->pch_pf_size &&
-	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
+	/* Enable panel fitting for eDP */
+	if (dev_priv->pch_pf_size && HAS_eDP) {
 		/* Force use of hard-coded filter coefficients
 		 * as some pre-programmed values are broken,
 		 * e.g. x201.
@@ -3334,10 +3325,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	 */
 	intel_crtc_load_lut(crtc);
 
-	if (IS_HASWELL(dev)) {
-		intel_ddi_set_pipe_settings(crtc);
-		intel_ddi_enable_pipe_func(crtc);
-	}
+	intel_ddi_set_pipe_settings(crtc);
+	intel_ddi_enable_pipe_func(crtc);
 
 	intel_enable_pipe(dev_priv, pipe, is_pch_port);
 	intel_enable_plane(dev_priv, plane, pipe);
@@ -3354,9 +3343,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		encoder->enable(encoder);
 
-	if (HAS_PCH_CPT(dev))
-		intel_cpt_verify_modeset(dev, intel_crtc->pipe);
-
 	/*
 	 * There seems to be a race in PCH platform hw (at least on some
 	 * outputs) where an enabled pipe still completes any pageflip right
@@ -3456,8 +3442,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
-	u32 reg, temp;
-
 
 	if (!intel_crtc->active)
 		return;
@@ -3476,15 +3460,13 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 
 	intel_disable_pipe(dev_priv, pipe);
 
-	if (IS_HASWELL(dev))
-		intel_ddi_disable_pipe_func(dev_priv, pipe);
+	intel_ddi_disable_pipe_func(dev_priv, pipe);
 
 	/* Disable PF */
 	I915_WRITE(PF_CTL(pipe), 0);
 	I915_WRITE(PF_WIN_SZ(pipe), 0);
 
-	if (IS_HASWELL(dev))
-		intel_ddi_disable_pipe_clock(intel_crtc);
+	intel_ddi_disable_pipe_clock(intel_crtc);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->post_disable)
@@ -3494,33 +3476,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 
 	intel_disable_transcoder(dev_priv, pipe);
 
-	if (HAS_PCH_CPT(dev)) {
-		/* disable TRANS_DP_CTL */
-		reg = TRANS_DP_CTL(pipe);
-		temp = I915_READ(reg);
-		temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
-		temp |= TRANS_DP_PORT_SEL_NONE;
-		I915_WRITE(reg, temp);
-
-		/* disable DPLL_SEL */
-		temp = I915_READ(PCH_DPLL_SEL);
-		switch (pipe) {
-		case 0:
-			temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
-			break;
-		case 1:
-			temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
-			break;
-		case 2:
-			/* C shares PLL A or B */
-			temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
-			break;
-		default:
-			BUG(); /* wtf */
-		}
-		I915_WRITE(PCH_DPLL_SEL, temp);
-	}
-
 	/* disable PCH DPLL */
 	intel_disable_pch_pll(intel_crtc);
 
-- 
1.7.11.4

[PATCH 13/18] drm/i915: implement workaround for VTOTAL when using TRANSCODER_EDP

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

See the documentation for the DDI_FUNC_CTL register, EDP Input Select
bits: when the EDP input selection is B, the VTOTAL_B must be
programmed with the VTOTAL_EDP value, same thing for selection C.

V2: Use I915_READ as suggested by Daniel Vetter.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1b72f36..8379e12 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4524,6 +4524,14 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
 		   (adjusted_mode->crtc_vsync_start - 1) |
 		   ((adjusted_mode->crtc_vsync_end - 1) << 16));
 
+	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
+	 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
+	 * documented on the DDI_FUNC_CTL register description, EDP Input Select
+	 * bits. */
+	if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
+	    (pipe == PIPE_B || pipe == PIPE_C))
+		I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
+
 	/* pipesrc controls the size that is scaled from, which should
 	 * always be the user's requested size.
 	 */
-- 
1.7.11.4

Re: [PATCH 14/18] drm/i915: select the correct pipe when using TRANSCODER_EDP

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Tue, Oct 23, 2012 at 6:30 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
>
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 3283f6f..106c375 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -954,6 +954,23 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
>         if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
>                 temp |= TRANS_DDI_PHSYNC;
>
> +       if (cpu_transcoder == TRANSCODER_EDP) {
> +               switch (pipe) {
> +               case PIPE_A:
> +                       temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
> +                       break;
> +               case PIPE_B:
> +                       temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
> +                       break;
> +               case PIPE_C:
> +                       temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
> +                       break;
> +               default:
> +                       BUG();
> +                       break;
> +               }
> +       }
> +
>         if (type == INTEL_OUTPUT_HDMI) {
>                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
>
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx




--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 15/18] drm/i915: set the correct eDP aux channel clock divider on DDI

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Tue, Oct 23, 2012 at 6:30 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> The cdclk frequency is not always the same, so the value here should
> be adjusted to match it.
>
> Version 2: call intel_ddi_get_cdclk_freq instead of reading
> CDCLK_FREQ, because the register is just for earlier HW steppings.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 2 +-
>  drivers/gpu/drm/i915/intel_dp.c  | 4 +++-
>  drivers/gpu/drm/i915/intel_drv.h | 1 +
>  3 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 106c375..30b0db7 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1239,7 +1239,7 @@ void intel_disable_ddi(struct intel_encoder *encoder)
>         /* This will be needed in the future, so leave it here for now */
>  }
>
> -static int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
> +int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
>  {
>         if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
>                 return 450;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f15ea22..6d30b2d 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -370,7 +370,9 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
>          * clock divider.
>          */
>         if (is_cpu_edp(intel_dp)) {
> -               if (IS_VALLEYVIEW(dev))
> +               if (IS_HASWELL(dev))
> +                       aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
> +               else if (IS_VALLEYVIEW(dev))
>                         aux_clock_divider = 100;
>                 else if (IS_GEN6(dev) || IS_GEN7(dev))
>                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 65927d9..c05e892 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -609,6 +609,7 @@ extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
>  extern void intel_ddi_mode_set(struct drm_encoder *encoder,
>                                 struct drm_display_mode *mode,
>                                 struct drm_display_mode *adjusted_mode);
> +extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
>  extern void intel_ddi_pll_init(struct drm_device *dev);
>  extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);
>  extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 16/18] drm/i915: set/unset the DDI eDP backlight

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Tue, Oct 23, 2012 at 6:30 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 15 +++++++++++++--
>  drivers/gpu/drm/i915/intel_dp.c  |  4 ++--
>  drivers/gpu/drm/i915/intel_drv.h |  6 ++++--
>  3 files changed, 19 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 30b0db7..232f2d0 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1231,12 +1231,23 @@ void intel_enable_ddi(struct intel_encoder *intel_encoder)
>                  * enabling the port.
>                  */
>                 I915_WRITE(DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE);
> +       } else if (type == INTEL_OUTPUT_EDP) {
> +               struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> +               ironlake_edp_backlight_on(intel_dp);
>         }
>  }
>
> -void intel_disable_ddi(struct intel_encoder *encoder)
> +void intel_disable_ddi(struct intel_encoder *intel_encoder)
>  {
> -       /* This will be needed in the future, so leave it here for now */
> +       struct drm_encoder *encoder = &intel_encoder->base;
> +       int type = intel_encoder->type;
> +
> +       if (type == INTEL_OUTPUT_EDP) {
> +               struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> +               ironlake_edp_backlight_off(intel_dp);
> +       }
>  }
>
>  int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 6d30b2d..d926f99 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1166,7 +1166,7 @@ static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
>         ironlake_wait_panel_off(intel_dp);
>  }
>
> -static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
> +void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
>  {
>         struct drm_device *dev = intel_dp->base.base.dev;
>         struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -1192,7 +1192,7 @@ static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
>         intel_panel_enable_backlight(dev, pipe);
>  }
>
> -static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
> +void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
>  {
>         struct drm_device *dev = intel_dp->base.base.dev;
>         struct drm_i915_private *dev_priv = dev->dev_private;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index c05e892..47d62fb 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -439,6 +439,8 @@ extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
>  extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
>  extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
>  extern bool intel_dpd_is_edp(struct drm_device *dev);
> +extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
> +extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
>  extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
>  extern int intel_edp_target_clock(struct intel_encoder *,
>                                   struct drm_display_mode *mode);
> @@ -602,8 +604,8 @@ extern void intel_disable_gt_powersave(struct drm_device *dev);
>  extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
>  extern void ironlake_teardown_rc6(struct drm_device *dev);
>
> -extern void intel_enable_ddi(struct intel_encoder *encoder);
> -extern void intel_disable_ddi(struct intel_encoder *encoder);
> +extern void intel_enable_ddi(struct intel_encoder *intel_encoder);
> +extern void intel_disable_ddi(struct intel_encoder *intel_encoder);
>  extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
>                                    enum pipe *pipe);
>  extern void intel_ddi_mode_set(struct drm_encoder *encoder,
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 16/18] drm/i915: set/unset the DDI eDP backlight

[Daniel Vetter]

On Tue, Oct 23, 2012 at 10:30 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

I think in this commit message we should mention that we've just
recently added the same to all the other eDP variations. I'll add the
right commit citation when applying.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 18/18] drm/i915: enable DDI eDP

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Tue, Oct 23, 2012 at 6:30 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Now that all the eDP enablement bits are there, we can actually try to
> use the eDP.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 47b52eb..760d290 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -242,8 +242,8 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
>
>         switch(port){
>         case PORT_A:
> -               /* We don't handle eDP and DP yet */
>                 DRM_DEBUG_DRIVER("Found digital output on DDI port A\n");
> +               intel_dp_init(dev, DDI_BUF_CTL_A, PORT_A);
>                 break;
>         /* Assume that the  ports B, C and D are working in HDMI mode for now */
>         case PORT_B:
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 16/18] drm/i915: set/unset the DDI eDP backlight

[Paulo Zanoni]

Hi

2012/10/24 Daniel Vetter <daniel@ffwll.ch>:
> On Tue, Oct 23, 2012 at 10:30 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
>> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>>
>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> I think in this commit message we should mention that we've just
> recently added the same to all the other eDP variations. I'll add the
> right commit citation when applying.

This commit is orthogonal to the ones you sent recently. Here I'm just
calling ironlake_edp_backlight_{on,off}. On your recent backlight
commit you just changed the functions I call (ironlake_edp_panel_off
and ironlake_edp_backlight_on).

> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch



-- 
Paulo Zanoni

Re: [PATCH 05/18] drm/i915: add TRANSCODER_EDP

[Lespiau, Damien]

On Tue, Oct 23, 2012 at 9:29 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
>  static void haswell_crtc_off(struct drm_crtc *crtc)
>  {
> +       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +
> +       intel_crtc->cpu_transcoder = intel_crtc->pipe;
>         intel_ddi_put_crtc_pll(crtc);
>  }
>

I can't find the reason why you would set the cpu_transcoder in the
off() function, would you mind explaining why? (or maybe the clue is
in a later patch, which might mean this hunk belongs to a later patch
as well).

-- 
Damien

Re: [PATCH 06/18] drm/i915: convert PIPE_CLK_SEL to transcoder

[Lespiau, Damien]

On Tue, Oct 23, 2012 at 9:29 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> This register appeared in Haswell. It does not have an EDP version
> because the EDP transcoder is always tied to the DDIA clock. Notice
> that if we call PIPE_CLK_SEL(pipe) when pipe is PIPE_A and transcoder
> is TRANSCODER_EDP we might introduce a bug, that's why this is a
> transcoder register even though it does not have an EDP version.
>
> Even though Haswell names this register PIPE_CLK_SEL, it will be
> renamed to TRANS_CLK_SEL in the future, so let's just start using the
> real name that makes more sense and avoids misusage.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

Re: [PATCH 07/18] drm/i915: convert DDI_FUNC_CTL to transcoder

[Lespiau, Damien]

On Tue, Oct 23, 2012 at 9:29 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Because there's one instance of the register per CPU transcoder and
> not per CPU pipe. This is another register that appeared for the first
> time on Haswell, and even though its Haswell name is
> PIPE_DDI_FUNC_CTL, it will be renamed to TRANS_DDI_FUNC_CTL, so let's
> just use the new naming scheme before it confuses more people.
>
> Notice that there's a big improvement on intel_ddi_get_hw_state due to
> the new TRANSCODER_EDP.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

Re: [PATCH 17/18] drm/i915: turn the eDP DDI panel on/off

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Tue, Oct 23, 2012 at 6:30 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> It's an important step :)
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++++++++++--
>  drivers/gpu/drm/i915/intel_dp.c  | 11 ++++-------
>  drivers/gpu/drm/i915/intel_drv.h |  4 ++++
>  3 files changed, 24 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 232f2d0..47b52eb 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1163,12 +1163,19 @@ void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
>         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
>         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>         enum port port = intel_ddi_get_encoder_port(intel_encoder);
> +       int type = intel_encoder->type;
>
> -       WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
> +       if (type == INTEL_OUTPUT_EDP) {
> +               struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +               ironlake_edp_panel_vdd_on(intel_dp);
> +               ironlake_edp_panel_on(intel_dp);
> +               ironlake_edp_panel_vdd_off(intel_dp, true);
> +       }
>
> +       WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
>         I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
>
> -       if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
> +       if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
>                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
>                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> @@ -1196,6 +1203,7 @@ void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
>         struct drm_encoder *encoder = &intel_encoder->base;
>         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
>         enum port port = intel_ddi_get_encoder_port(intel_encoder);
> +       int type = intel_encoder->type;
>         uint32_t val;
>         bool wait = false;
>
> @@ -1214,6 +1222,12 @@ void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
>         if (wait)
>                 intel_wait_ddi_buf_idle(dev_priv, port);
>
> +       if (type == INTEL_OUTPUT_EDP) {
> +               struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +               ironlake_edp_panel_vdd_on(intel_dp);
> +               ironlake_edp_panel_off(intel_dp);
> +       }
> +
>         I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
>  }
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index d926f99..2f7acba 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -651,9 +651,6 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
>         return -EREMOTEIO;
>  }
>
> -static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
> -static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
> -
>  static int
>  intel_dp_i2c_init(struct intel_dp *intel_dp,
>                   struct intel_connector *intel_connector, const char *name)
> @@ -1004,7 +1001,7 @@ static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
>         return control;
>  }
>
> -static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
> +void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
>  {
>         struct drm_device *dev = intel_dp->base.base.dev;
>         struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -1074,7 +1071,7 @@ static void ironlake_panel_vdd_work(struct work_struct *__work)
>         mutex_unlock(&dev->mode_config.mutex);
>  }
>
> -static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
> +void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
>  {
>         if (!is_edp(intel_dp))
>                 return;
> @@ -1097,7 +1094,7 @@ static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
>         }
>  }
>
> -static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
> +void ironlake_edp_panel_on(struct intel_dp *intel_dp)
>  {
>         struct drm_device *dev = intel_dp->base.base.dev;
>         struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -1139,7 +1136,7 @@ static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
>         }
>  }
>
> -static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
> +void ironlake_edp_panel_off(struct intel_dp *intel_dp)
>  {
>         struct drm_device *dev = intel_dp->base.base.dev;
>         struct drm_i915_private *dev_priv = dev->dev_private;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 47d62fb..b9faeec 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -441,6 +441,10 @@ extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
>  extern bool intel_dpd_is_edp(struct drm_device *dev);
>  extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
>  extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
> +extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
> +extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
> +extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
> +extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
>  extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
>  extern int intel_edp_target_clock(struct intel_encoder *,
>                                   struct drm_display_mode *mode);
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 13/18] drm/i915: implement workaround for VTOTAL when using TRANSCODER_EDP

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Oct 24, 2012 at 11:34 AM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> See the documentation for the DDI_FUNC_CTL register, EDP Input Select
> bits: when the EDP input selection is B, the VTOTAL_B must be
> programmed with the VTOTAL_EDP value, same thing for selection C.
>
> V2: Use I915_READ as suggested by Daniel Vetter.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 1b72f36..8379e12 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4524,6 +4524,14 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
>                    (adjusted_mode->crtc_vsync_start - 1) |
>                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
>
> +       /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
> +        * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
> +        * documented on the DDI_FUNC_CTL register description, EDP Input Select
> +        * bits. */
> +       if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
> +           (pipe == PIPE_B || pipe == PIPE_C))
> +               I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
> +
>         /* pipesrc controls the size that is scaled from, which should
>          * always be the user's requested size.
>          */
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 07/18] drm/i915: convert DDI_FUNC_CTL to transcoder

[Lespiau, Damien]

On Tue, Oct 23, 2012 at 9:29 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> +#define TRANS_DDI_FUNC_CTL_A           0x60400
> +#define TRANS_DDI_FUNC_CTL_B           0x61400
> +#define TRANS_DDI_FUNC_CTL_C           0x62400
> +#define TRANS_DDI_FUNC_CTL_EDP         0x6F400
> +#define DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \
> +                                            TRANS_DDI_FUNC_CTL_B)

I was also thinking that it'd be nice to know what we need to give to
that macro at a glimpse where we call it, so maybe name it
TRANS_DDI_FUNC_CTL(trans)?

-- 
Damien

Re: [PATCH 08/18] drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state

[Lespiau, Damien]

On Wed, Oct 24, 2012 at 1:38 PM, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Tue, Oct 23, 2012 at 06:29:58PM -0200, Paulo Zanoni wrote:
>> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>>
>> We need to check if any of the pipes is using TRANSCODER_EDP.
>>
>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> One thing that irks me is that you add new state readout code here, but
> don't call the same code in the modeset_check_state code

Isn't what the previous patch introduce? (look at the
intel_ddi_get_hw_state() hunk in the patch 07/18 of the series).
AFAICS we're are already checking if the pipe returned by the encoder
is what we think it is.

-- 
Damien

Re: [PATCH 08/18] drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state

[Daniel Vetter]

On Wed, Oct 24, 2012 at 04:45:04PM +0100, Lespiau, Damien wrote:
> On Wed, Oct 24, 2012 at 1:38 PM, Daniel Vetter <daniel@ffwll.ch> wrote:
> > On Tue, Oct 23, 2012 at 06:29:58PM -0200, Paulo Zanoni wrote:
> >> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >>
> >> We need to check if any of the pipes is using TRANSCODER_EDP.
> >>
> >> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >
> > One thing that irks me is that you add new state readout code here, but
> > don't call the same code in the modeset_check_state code
> 
> Isn't what the previous patch introduce? (look at the
> intel_ddi_get_hw_state() hunk in the patch 07/18 of the series).
> AFAICS we're are already checking if the pipe returned by the encoder
> is what we think it is.

In a way, yes. But in the best case we should have the same code in both
places (now it's copied), and also should be able to check which parts of
the hw we actually need (since the get_hw_state now hides the
cpu_transcoder in between the ddi and the pipe that's not so easy to do).
So I still think we should try to unify/improve this a bit, especially
since for the other fastboo stuff we need more cleverness for pipe state
anyway (otherwise handling plls&friends will be a pain).
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 05/18] drm/i915: add TRANSCODER_EDP

[Paulo Zanoni]

Hi

2012/10/24 Lespiau, Damien <damien.lespiau@intel.com>:
> On Tue, Oct 23, 2012 at 9:29 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
>>  static void haswell_crtc_off(struct drm_crtc *crtc)
>>  {
>> +       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> +
>> +       intel_crtc->cpu_transcoder = intel_crtc->pipe;
>>         intel_ddi_put_crtc_pll(crtc);
>>  }
>>
>
> I can't find the reason why you would set the cpu_transcoder in the
> off() function, would you mind explaining why? (or maybe the clue is
> in a later patch, which might mean this hunk belongs to a later patch
> as well).

The very first version I wrote for this patch did not have this line
too, until I discovered I needed it. Fasten your seatbelts...

Because TRANSCODER_EDP can be used by any CRTC, so when you stop using
it you have to stop saying you're using it, otherwise you may have at
some point 2 crtcs claiming they're using TRANSCODER_EDP (a disable
crtc and an enabled one), then the HW state readout code will get
completely confused.

In other words:

Imagine the following case:
- xrandr --output eDP1 --auto --crtc 0
- xrandr --output eDP1 --off
- xrandr --output eDP1 --auto --crtc 2

After the last command you will get a nice "pipe A assertion failure
(expected off, current on)" because crtc 0 still claims it's using
transcoder_edp, so the hw state readout function will read it (through
pipeconf) and expect it to be off, when it is actually on because it's
being used by crtc 2.

So when we make "intel_crtc->cpu_transcoder = intel_crtc->pipe" we
make sure we're pointing to our own original crtc which is certainly
not used by any other CRTC.

>
> --
> Damien



-- 
Paulo Zanoni

Re: [PATCH 05/18] drm/i915: add TRANSCODER_EDP

[Daniel Vetter]

On Wed, Oct 24, 2012 at 6:33 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> 2012/10/24 Lespiau, Damien <damien.lespiau@intel.com>:
>> On Tue, Oct 23, 2012 at 9:29 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
>>>  static void haswell_crtc_off(struct drm_crtc *crtc)
>>>  {
>>> +       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>>> +
>>> +       intel_crtc->cpu_transcoder = intel_crtc->pipe;
>>>         intel_ddi_put_crtc_pll(crtc);
>>>  }
>>>
>>
>> I can't find the reason why you would set the cpu_transcoder in the
>> off() function, would you mind explaining why? (or maybe the clue is
>> in a later patch, which might mean this hunk belongs to a later patch
>> as well).
>
> The very first version I wrote for this patch did not have this line
> too, until I discovered I needed it. Fasten your seatbelts...
>
> Because TRANSCODER_EDP can be used by any CRTC, so when you stop using
> it you have to stop saying you're using it, otherwise you may have at
> some point 2 crtcs claiming they're using TRANSCODER_EDP (a disable
> crtc and an enabled one), then the HW state readout code will get
> completely confused.
>
> In other words:
>
> Imagine the following case:
> - xrandr --output eDP1 --auto --crtc 0
> - xrandr --output eDP1 --off
> - xrandr --output eDP1 --auto --crtc 2
>
> After the last command you will get a nice "pipe A assertion failure
> (expected off, current on)" because crtc 0 still claims it's using
> transcoder_edp, so the hw state readout function will read it (through
> pipeconf) and expect it to be off, when it is actually on because it's
> being used by crtc 2.
>
> So when we make "intel_crtc->cpu_transcoder = intel_crtc->pipe" we
> make sure we're pointing to our own original crtc which is certainly
> not used by any other CRTC.

This needs to be in a comment somewhere. I think the long version here
in the commit message, and a short one in the code.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 07/18] drm/i915: convert DDI_FUNC_CTL to transcoder

[Paulo Zanoni]

Hi

2012/10/24 Lespiau, Damien <damien.lespiau@intel.com>:
> On Tue, Oct 23, 2012 at 9:29 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
>> +#define TRANS_DDI_FUNC_CTL_A           0x60400
>> +#define TRANS_DDI_FUNC_CTL_B           0x61400
>> +#define TRANS_DDI_FUNC_CTL_C           0x62400
>> +#define TRANS_DDI_FUNC_CTL_EDP         0x6F400
>> +#define DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \
>> +                                            TRANS_DDI_FUNC_CTL_B)
>
> I was also thinking that it'd be nice to know what we need to give to
> that macro at a glimpse where we call it, so maybe name it
> TRANS_DDI_FUNC_CTL(trans)?

I agree with you. In fact even on the old code PIPE_DDI_FUNC_CTL would
be better. It looks like I got used to it :)

The only problem here is that I'll also have to resend patches 8 and
13 since they use the renamed register.
>
> --
> Damien



-- 
Paulo Zanoni

[PATCH 05/18] drm/i915: add TRANSCODER_EDP

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Before Haswell we used to have the CPU pipes and the PCH transcoders.
We had the same amount of pipes and transcoders, and there was a 1:1
mapping between them. After Haswell what we used to call CPU pipe was
split into CPU pipe and CPU transcoder. So now we have 3 CPU pipes (A,
B and C), 4 CPU transcoders (A, B, C and EDP) and 1 PCH transcoder
(only used for VGA).

For all the outputs except for EDP we have an 1:1 mapping on the CPU
pipes and CPU transcoders, so if you're using CPU pipe A you have to
use CPU transcoder A. When have an eDP output you have to use
transcoder EDP and you can attach this CPU transcoder to any of the 3
CPU pipes. When using VGA you need to select a pair of matching CPU
pipes/transcoders (A/A, B/B, C/C) and you also need to enable/use the
PCH transcoder.

For now we're just creating the cpu_transcoder definitions and setting
cpu_transcoder to TRANSCODER_EDP on DDI eDP code, but none of the
registers was ported to use transcoder instead of pipe. The goal is to
keep the code backwards-compatible since on all cases except when
using eDP we must have pipe == cpu_transcoder.

V2: Comment the haswell_crtc_off chunk, suggested by Damien Lespiau
and Daniel Vetter.

We currently need the haswell_crtc_off chunk because TRANSCODER_EDP
can be used by any CRTC, so when you stop using it you have to stop
saying you're using it, otherwise you may have at some point 2 CRTCs
claiming they're using TRANSCODER_EDP (a disabled CRTC and an enabled
one), then the HW state readout code will get completely confused.

In other words:

Imagine the following case:
  xrandr --output eDP1 --auto --crtc 0
  xrandr --output eDP1 --off
  xrandr --output eDP1 --auto --crtc 2

After the last command you could get a "pipe A assertion failure
(expected off, current on)" because CRTC 0 still claims it's using
TRANSCODER_EDP, so the HW state readout function will read it
(through PIPECONF) and expect it to be off, when it's actually on
because it's being used by CRTC 2.

So when we make "intel_crtc->cpu_transcoder = intel_crtc->pipe" we
make sure we're pointing to our own original CRTC which is certainly
not used by any other CRTC.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  8 ++++++++
 drivers/gpu/drm/i915/i915_reg.h      |  1 +
 drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h     |  4 ++++
 4 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 987af6f..2fcf284 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -58,6 +58,14 @@ enum pipe {
 };
 #define pipe_name(p) ((p) + 'A')
 
+enum transcoder {
+	TRANSCODER_A = 0,
+	TRANSCODER_B,
+	TRANSCODER_C,
+	TRANSCODER_EDP = 0xF,
+};
+#define transcoder_name(t) ((t) + 'A')
+
 enum plane {
 	PLANE_A = 0,
 	PLANE_B,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c7c4b96..598f83a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -26,6 +26,7 @@
 #define _I915_REG_H_
 
 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
+#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
 
 #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 67c9472..18aa1b6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -937,6 +937,15 @@ intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 	return true;
 }
 
+enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
+					     enum pipe pipe)
+{
+	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+	return intel_crtc->cpu_transcoder;
+}
+
 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3485,6 +3494,12 @@ static void ironlake_crtc_off(struct drm_crtc *crtc)
 
 static void haswell_crtc_off(struct drm_crtc *crtc)
 {
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+	/* Stop saying we're using TRANSCODER_EDP because some other CRTC might
+	 * start using it. */
+	intel_crtc->cpu_transcoder = intel_crtc->pipe;
+
 	intel_ddi_put_crtc_pll(crtc);
 }
 
@@ -5361,6 +5376,11 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
 		num_connectors++;
 	}
 
+	if (is_cpu_edp)
+		intel_crtc->cpu_transcoder = TRANSCODER_EDP;
+	else
+		intel_crtc->cpu_transcoder = pipe;
+
 	/* We are not sure yet this won't happen. */
 	WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
 	     INTEL_PCH_TYPE(dev));
@@ -7897,6 +7917,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
 	/* Swap pipes & planes for FBC on pre-965 */
 	intel_crtc->pipe = pipe;
 	intel_crtc->plane = pipe;
+	intel_crtc->cpu_transcoder = pipe;
 	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
 		DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
 		intel_crtc->plane = !pipe;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c2e439b..14484ef 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -195,6 +195,7 @@ struct intel_crtc {
 	struct drm_crtc base;
 	enum pipe pipe;
 	enum plane plane;
+	enum transcoder cpu_transcoder;
 	u8 lut_r[256], lut_g[256], lut_b[256];
 	/*
 	 * Whether the crtc and the connected output pipeline is active. Implies
@@ -506,6 +507,9 @@ extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 						    struct drm_crtc *crtc);
 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 				struct drm_file *file_priv);
+extern enum transcoder
+intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
+			     enum pipe pipe);
 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 
-- 
1.7.11.4

[PATCH 07/18] drm/i915: convert DDI_FUNC_CTL to transcoder

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Because there's one instance of the register per CPU transcoder and
not per CPU pipe. This is another register that appeared for the first
time on Haswell, and even though its Haswell name is
PIPE_DDI_FUNC_CTL, it will be renamed to TRANS_DDI_FUNC_CTL, so let's
just use the new naming scheme before it confuses more people.

Notice that there's a big improvement on intel_ddi_get_hw_state due to
the new TRANSCODER_EDP.

V2: Also rename the register to TRANS_DDI_FUNC_CTL as suggested by
Damien Lespiau.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  59 ++++++++++----------
 drivers/gpu/drm/i915/intel_ddi.c     | 101 ++++++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_display.c |   9 ++--
 drivers/gpu/drm/i915/intel_drv.h     |   4 +-
 4 files changed, 104 insertions(+), 69 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 99cda88..04705b6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4399,34 +4399,39 @@
 #define HSW_PWR_WELL_CTL6			0x45414
 
 /* Per-pipe DDI Function Control */
-#define PIPE_DDI_FUNC_CTL_A		0x60400
-#define PIPE_DDI_FUNC_CTL_B		0x61400
-#define PIPE_DDI_FUNC_CTL_C		0x62400
-#define PIPE_DDI_FUNC_CTL_EDP		0x6F400
-#define DDI_FUNC_CTL(pipe) _PIPE(pipe, PIPE_DDI_FUNC_CTL_A, \
-				       PIPE_DDI_FUNC_CTL_B)
-#define  PIPE_DDI_FUNC_ENABLE		(1<<31)
+#define TRANS_DDI_FUNC_CTL_A		0x60400
+#define TRANS_DDI_FUNC_CTL_B		0x61400
+#define TRANS_DDI_FUNC_CTL_C		0x62400
+#define TRANS_DDI_FUNC_CTL_EDP		0x6F400
+#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \
+						   TRANS_DDI_FUNC_CTL_B)
+#define  TRANS_DDI_FUNC_ENABLE		(1<<31)
 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
-#define  PIPE_DDI_PORT_MASK		(7<<28)
-#define  PIPE_DDI_SELECT_PORT(x)	((x)<<28)
-#define  PIPE_DDI_PORT_NONE		(0<<28)
-#define  PIPE_DDI_MODE_SELECT_MASK	(7<<24)
-#define  PIPE_DDI_MODE_SELECT_HDMI	(0<<24)
-#define  PIPE_DDI_MODE_SELECT_DVI	(1<<24)
-#define  PIPE_DDI_MODE_SELECT_DP_SST	(2<<24)
-#define  PIPE_DDI_MODE_SELECT_DP_MST	(3<<24)
-#define  PIPE_DDI_MODE_SELECT_FDI	(4<<24)
-#define  PIPE_DDI_BPC_MASK		(7<<20)
-#define  PIPE_DDI_BPC_8			(0<<20)
-#define  PIPE_DDI_BPC_10		(1<<20)
-#define  PIPE_DDI_BPC_6			(2<<20)
-#define  PIPE_DDI_BPC_12		(3<<20)
-#define  PIPE_DDI_PVSYNC		(1<<17)
-#define  PIPE_DDI_PHSYNC		(1<<16)
-#define  PIPE_DDI_BFI_ENABLE		(1<<4)
-#define  PIPE_DDI_PORT_WIDTH_X1		(0<<1)
-#define  PIPE_DDI_PORT_WIDTH_X2		(1<<1)
-#define  PIPE_DDI_PORT_WIDTH_X4		(3<<1)
+#define  TRANS_DDI_PORT_MASK		(7<<28)
+#define  TRANS_DDI_SELECT_PORT(x)	((x)<<28)
+#define  TRANS_DDI_PORT_NONE		(0<<28)
+#define  TRANS_DDI_MODE_SELECT_MASK	(7<<24)
+#define  TRANS_DDI_MODE_SELECT_HDMI	(0<<24)
+#define  TRANS_DDI_MODE_SELECT_DVI	(1<<24)
+#define  TRANS_DDI_MODE_SELECT_DP_SST	(2<<24)
+#define  TRANS_DDI_MODE_SELECT_DP_MST	(3<<24)
+#define  TRANS_DDI_MODE_SELECT_FDI	(4<<24)
+#define  TRANS_DDI_BPC_MASK		(7<<20)
+#define  TRANS_DDI_BPC_8		(0<<20)
+#define  TRANS_DDI_BPC_10		(1<<20)
+#define  TRANS_DDI_BPC_6		(2<<20)
+#define  TRANS_DDI_BPC_12		(3<<20)
+#define  TRANS_DDI_PVSYNC		(1<<17)
+#define  TRANS_DDI_PHSYNC		(1<<16)
+#define  TRANS_DDI_EDP_INPUT_MASK	(7<<12)
+#define  TRANS_DDI_EDP_INPUT_A_ON	(0<<12)
+#define  TRANS_DDI_EDP_INPUT_A_ONOFF	(4<<12)
+#define  TRANS_DDI_EDP_INPUT_B_ONOFF	(5<<12)
+#define  TRANS_DDI_EDP_INPUT_C_ONOFF	(6<<12)
+#define  TRANS_DDI_BFI_ENABLE		(1<<4)
+#define  TRANS_DDI_PORT_WIDTH_X1	(0<<1)
+#define  TRANS_DDI_PORT_WIDTH_X2	(1<<1)
+#define  TRANS_DDI_PORT_WIDTH_X4	(3<<1)
 
 /* DisplayPort Transport Control */
 #define DP_TP_CTL_A			0x64040
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f568862..4b5366b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -924,68 +924,69 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
 	struct drm_encoder *encoder = &intel_encoder->base;
 	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 	enum pipe pipe = intel_crtc->pipe;
+	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 	int type = intel_encoder->type;
 	uint32_t temp;
 
-	/* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */
-	temp = PIPE_DDI_FUNC_ENABLE;
+	/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
+	temp = TRANS_DDI_FUNC_ENABLE;
 
 	switch (intel_crtc->bpp) {
 	case 18:
-		temp |= PIPE_DDI_BPC_6;
+		temp |= TRANS_DDI_BPC_6;
 		break;
 	case 24:
-		temp |= PIPE_DDI_BPC_8;
+		temp |= TRANS_DDI_BPC_8;
 		break;
 	case 30:
-		temp |= PIPE_DDI_BPC_10;
+		temp |= TRANS_DDI_BPC_10;
 		break;
 	case 36:
-		temp |= PIPE_DDI_BPC_12;
+		temp |= TRANS_DDI_BPC_12;
 		break;
 	default:
-		WARN(1, "%d bpp unsupported by pipe DDI function\n",
+		WARN(1, "%d bpp unsupported by transcoder DDI function\n",
 		     intel_crtc->bpp);
 	}
 
 	if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
-		temp |= PIPE_DDI_PVSYNC;
+		temp |= TRANS_DDI_PVSYNC;
 	if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
-		temp |= PIPE_DDI_PHSYNC;
+		temp |= TRANS_DDI_PHSYNC;
 
 	if (type == INTEL_OUTPUT_HDMI) {
 		struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 
 		if (intel_hdmi->has_hdmi_sink)
-			temp |= PIPE_DDI_MODE_SELECT_HDMI;
+			temp |= TRANS_DDI_MODE_SELECT_HDMI;
 		else
-			temp |= PIPE_DDI_MODE_SELECT_DVI;
+			temp |= TRANS_DDI_MODE_SELECT_DVI;
 
-		temp |= PIPE_DDI_SELECT_PORT(intel_hdmi->ddi_port);
+		temp |= TRANS_DDI_SELECT_PORT(intel_hdmi->ddi_port);
 
 	} else if (type == INTEL_OUTPUT_ANALOG) {
-		temp |= PIPE_DDI_MODE_SELECT_FDI;
-		temp |= PIPE_DDI_SELECT_PORT(PORT_E);
+		temp |= TRANS_DDI_MODE_SELECT_FDI;
+		temp |= TRANS_DDI_SELECT_PORT(PORT_E);
 
 	} else if (type == INTEL_OUTPUT_DISPLAYPORT ||
 		   type == INTEL_OUTPUT_EDP) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
-		temp |= PIPE_DDI_MODE_SELECT_DP_SST;
-		temp |= PIPE_DDI_SELECT_PORT(intel_dp->port);
+		temp |= TRANS_DDI_MODE_SELECT_DP_SST;
+		temp |= TRANS_DDI_SELECT_PORT(intel_dp->port);
 
 		switch (intel_dp->lane_count) {
 		case 1:
-			temp |= PIPE_DDI_PORT_WIDTH_X1;
+			temp |= TRANS_DDI_PORT_WIDTH_X1;
 			break;
 		case 2:
-			temp |= PIPE_DDI_PORT_WIDTH_X2;
+			temp |= TRANS_DDI_PORT_WIDTH_X2;
 			break;
 		case 4:
-			temp |= PIPE_DDI_PORT_WIDTH_X4;
+			temp |= TRANS_DDI_PORT_WIDTH_X4;
 			break;
 		default:
-			temp |= PIPE_DDI_PORT_WIDTH_X4;
+			temp |= TRANS_DDI_PORT_WIDTH_X4;
 			WARN(1, "Unsupported lane count %d\n",
 			     intel_dp->lane_count);
 		}
@@ -995,17 +996,17 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
 		     intel_encoder->type, pipe);
 	}
 
-	I915_WRITE(DDI_FUNC_CTL(pipe), temp);
+	I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
 }
 
-void intel_ddi_disable_pipe_func(struct drm_i915_private *dev_priv,
-				 enum pipe pipe)
+void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
+				       enum transcoder cpu_transcoder)
 {
-	uint32_t reg = DDI_FUNC_CTL(pipe);
+	uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 	uint32_t val = I915_READ(reg);
 
-	val &= ~(PIPE_DDI_FUNC_ENABLE | PIPE_DDI_PORT_MASK);
-	val |= PIPE_DDI_PORT_NONE;
+	val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
+	val |= TRANS_DDI_PORT_NONE;
 	I915_WRITE(reg, val);
 }
 
@@ -1023,13 +1024,32 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 	if (!(tmp & DDI_BUF_CTL_ENABLE))
 		return false;
 
-	for_each_pipe(i) {
-		tmp = I915_READ(DDI_FUNC_CTL(i));
+	if (port == PORT_A) {
+		tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
 
-		if ((tmp & PIPE_DDI_PORT_MASK)
-		    == PIPE_DDI_SELECT_PORT(port)) {
-			*pipe = i;
-			return true;
+		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
+		case TRANS_DDI_EDP_INPUT_A_ON:
+		case TRANS_DDI_EDP_INPUT_A_ONOFF:
+			*pipe = PIPE_A;
+			break;
+		case TRANS_DDI_EDP_INPUT_B_ONOFF:
+			*pipe = PIPE_B;
+			break;
+		case TRANS_DDI_EDP_INPUT_C_ONOFF:
+			*pipe = PIPE_C;
+			break;
+		}
+
+		return true;
+	} else {
+		for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
+			tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
+
+			if ((tmp & TRANS_DDI_PORT_MASK)
+			    == TRANS_DDI_SELECT_PORT(port)) {
+				*pipe = i;
+				return true;
+			}
 		}
 	}
 
@@ -1043,13 +1063,20 @@ static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
 {
 	uint32_t temp, ret;
 	enum port port;
+	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
+								      pipe);
 	int i;
 
-	temp = I915_READ(DDI_FUNC_CTL(pipe));
-	temp &= PIPE_DDI_PORT_MASK;
-	for (i = PORT_A; i <= PORT_E; i++)
-		if (temp == PIPE_DDI_SELECT_PORT(i))
-			port = i;
+	if (cpu_transcoder == TRANSCODER_EDP) {
+		port = PORT_A;
+	} else {
+		temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
+		temp &= TRANS_DDI_PORT_MASK;
+
+		for (i = PORT_B; i <= PORT_E; i++)
+			if (temp == TRANS_DDI_SELECT_PORT(i))
+				port = i;
+	}
 
 	ret = I915_READ(PORT_CLK_SEL(port));
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 18aa1b6..b4cceaf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1122,12 +1122,14 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 	int reg;
 	u32 val;
 	bool cur_state;
+	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
+								      pipe);
 
 	if (IS_HASWELL(dev_priv->dev)) {
 		/* On Haswell, DDI is used instead of FDI_TX_CTL */
-		reg = DDI_FUNC_CTL(pipe);
+		reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 		val = I915_READ(reg);
-		cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
+		cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 	} else {
 		reg = FDI_TX_CTL(pipe);
 		val = I915_READ(reg);
@@ -3438,6 +3440,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
+	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 	bool is_pch_port;
 
 	if (!intel_crtc->active)
@@ -3459,7 +3462,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 
 	intel_disable_pipe(dev_priv, pipe);
 
-	intel_ddi_disable_pipe_func(dev_priv, pipe);
+	intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
 
 	/* Disable PF */
 	I915_WRITE(PF_CTL(pipe), 0);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 14484ef..65927d9 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -611,8 +611,8 @@ extern void intel_ddi_mode_set(struct drm_encoder *encoder,
 				struct drm_display_mode *adjusted_mode);
 extern void intel_ddi_pll_init(struct drm_device *dev);
 extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);
-extern void intel_ddi_disable_pipe_func(struct drm_i915_private *dev_priv,
-					enum pipe pipe);
+extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
+					      enum transcoder cpu_transcoder);
 extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
-- 
1.7.11.4

[PATCH 08/18] drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

We need to check if any of the pipes is using TRANSCODER_EDP.

V2: DDI_BUF_CTL was renamed, so fix the usage here.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b4cceaf..b164ecf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8693,6 +8693,31 @@ void intel_modeset_setup_hw_state(struct drm_device *dev)
 	struct intel_encoder *encoder;
 	struct intel_connector *connector;
 
+	if (IS_HASWELL(dev)) {
+		tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
+
+		if (tmp & TRANS_DDI_FUNC_ENABLE) {
+			switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
+			case TRANS_DDI_EDP_INPUT_A_ON:
+			case TRANS_DDI_EDP_INPUT_A_ONOFF:
+				pipe = PIPE_A;
+				break;
+			case TRANS_DDI_EDP_INPUT_B_ONOFF:
+				pipe = PIPE_B;
+				break;
+			case TRANS_DDI_EDP_INPUT_C_ONOFF:
+				pipe = PIPE_C;
+				break;
+			}
+
+			crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
+			crtc->cpu_transcoder = TRANSCODER_EDP;
+
+			DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
+				      pipe_name(pipe));
+		}
+	}
+
 	for_each_pipe(pipe) {
 		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 
-- 
1.7.11.4

Re: [PATCH 05/18] drm/i915: add TRANSCODER_EDP

[Lespiau, Damien]

On Wed, Oct 24, 2012 at 6:59 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Before Haswell we used to have the CPU pipes and the PCH transcoders.
> We had the same amount of pipes and transcoders, and there was a 1:1
> mapping between them. After Haswell what we used to call CPU pipe was
> split into CPU pipe and CPU transcoder. So now we have 3 CPU pipes (A,
> B and C), 4 CPU transcoders (A, B, C and EDP) and 1 PCH transcoder
> (only used for VGA).
>
> For all the outputs except for EDP we have an 1:1 mapping on the CPU
> pipes and CPU transcoders, so if you're using CPU pipe A you have to
> use CPU transcoder A. When have an eDP output you have to use
> transcoder EDP and you can attach this CPU transcoder to any of the 3
> CPU pipes. When using VGA you need to select a pair of matching CPU
> pipes/transcoders (A/A, B/B, C/C) and you also need to enable/use the
> PCH transcoder.
>
> For now we're just creating the cpu_transcoder definitions and setting
> cpu_transcoder to TRANSCODER_EDP on DDI eDP code, but none of the
> registers was ported to use transcoder instead of pipe. The goal is to
> keep the code backwards-compatible since on all cases except when
> using eDP we must have pipe == cpu_transcoder.
>
> V2: Comment the haswell_crtc_off chunk, suggested by Damien Lespiau
> and Daniel Vetter.
>
> We currently need the haswell_crtc_off chunk because TRANSCODER_EDP
> can be used by any CRTC, so when you stop using it you have to stop
> saying you're using it, otherwise you may have at some point 2 CRTCs
> claiming they're using TRANSCODER_EDP (a disabled CRTC and an enabled
> one), then the HW state readout code will get completely confused.
>
> In other words:
>
> Imagine the following case:
>   xrandr --output eDP1 --auto --crtc 0
>   xrandr --output eDP1 --off
>   xrandr --output eDP1 --auto --crtc 2
>
> After the last command you could get a "pipe A assertion failure
> (expected off, current on)" because CRTC 0 still claims it's using
> TRANSCODER_EDP, so the HW state readout function will read it
> (through PIPECONF) and expect it to be off, when it's actually on
> because it's being used by CRTC 2.
>
> So when we make "intel_crtc->cpu_transcoder = intel_crtc->pipe" we
> make sure we're pointing to our own original CRTC which is certainly
> not used by any other CRTC.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

Re: [PATCH 07/18] drm/i915: convert DDI_FUNC_CTL to transcoder

[Lespiau, Damien]

On Wed, Oct 24, 2012 at 7:06 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Because there's one instance of the register per CPU transcoder and
> not per CPU pipe. This is another register that appeared for the first
> time on Haswell, and even though its Haswell name is
> PIPE_DDI_FUNC_CTL, it will be renamed to TRANS_DDI_FUNC_CTL, so let's
> just use the new naming scheme before it confuses more people.
>
> Notice that there's a big improvement on intel_ddi_get_hw_state due to
> the new TRANSCODER_EDP.
>
> V2: Also rename the register to TRANS_DDI_FUNC_CTL as suggested by
> Damien Lespiau.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

Re: [PATCH 08/18] drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state

[Lespiau, Damien]

On Wed, Oct 24, 2012 at 7:09 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> We need to check if any of the pipes is using TRANSCODER_EDP.
>
> V2: DDI_BUF_CTL was renamed, so fix the usage here.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

Re: [PATCH 01/18] drm/i915: fork a Haswell version of ironlake_crtc_{enable, disable}

[Jani Nikula]

On Tue, 23 Oct 2012, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> The way we enable and disable the PCH on Haswell changed considerably
> since now we have only one PCH transcoder, so we can't keep the same
> asserts and we also can't just unconditionally disable the PCH
> transcoder for non-PCH outputs. So let's fork a Haswell version.
>
> These new functions look exactly the same as the ironlake versions.
> The next patches will introduce the differences.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 183 ++++++++++++++++++++++++++++++++++-
>  1 file changed, 181 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0fb5542..eb4dba6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3283,6 +3283,99 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>  	intel_wait_for_vblank(dev, intel_crtc->pipe);
>  }
>  
> +static void haswell_crtc_enable(struct drm_crtc *crtc)
> +{
> +	struct drm_device *dev = crtc->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	struct intel_encoder *encoder;
> +	int pipe = intel_crtc->pipe;
> +	int plane = intel_crtc->plane;
> +	u32 temp;
> +	bool is_pch_port;
> +
> +	WARN_ON(!crtc->enabled);
> +
> +	if (intel_crtc->active)
> +		return;
> +
> +	intel_crtc->active = true;
> +	intel_update_watermarks(dev);
> +
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
> +		temp = I915_READ(PCH_LVDS);
> +		if ((temp & LVDS_PORT_EN) == 0)
> +			I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
> +	}
> +
> +	is_pch_port = intel_crtc_driving_pch(crtc);
> +
> +	if (is_pch_port) {
> +		ironlake_fdi_pll_enable(intel_crtc);
> +	} else {
> +		assert_fdi_tx_disabled(dev_priv, pipe);
> +		assert_fdi_rx_disabled(dev_priv, pipe);
> +	}
> +
> +	for_each_encoder_on_crtc(dev, crtc, encoder)
> +		if (encoder->pre_enable)
> +			encoder->pre_enable(encoder);
> +
> +	if (IS_HASWELL(dev))
> +		intel_ddi_enable_pipe_clock(intel_crtc);
> +
> +	/* Enable panel fitting for LVDS */
> +	if (dev_priv->pch_pf_size &&
> +	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
> +		/* Force use of hard-coded filter coefficients
> +		 * as some pre-programmed values are broken,
> +		 * e.g. x201.
> +		 */
> +		I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
> +		I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
> +		I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
> +	}
> +
> +	/*
> +	 * On ILK+ LUT must be loaded before the pipe is running but with
> +	 * clocks enabled
> +	 */
> +	intel_crtc_load_lut(crtc);
> +
> +	if (IS_HASWELL(dev)) {
> +		intel_ddi_set_pipe_settings(crtc);
> +		intel_ddi_enable_pipe_func(crtc);
> +	}
> +
> +	intel_enable_pipe(dev_priv, pipe, is_pch_port);
> +	intel_enable_plane(dev_priv, plane, pipe);
> +
> +	if (is_pch_port)
> +		ironlake_pch_enable(crtc);
> +
> +	mutex_lock(&dev->struct_mutex);
> +	intel_update_fbc(dev);
> +	mutex_unlock(&dev->struct_mutex);
> +
> +	intel_crtc_update_cursor(crtc, true);
> +
> +	for_each_encoder_on_crtc(dev, crtc, encoder)
> +		encoder->enable(encoder);
> +
> +	if (HAS_PCH_CPT(dev))
> +		intel_cpt_verify_modeset(dev, intel_crtc->pipe);
> +
> +	/*
> +	 * There seems to be a race in PCH platform hw (at least on some
> +	 * outputs) where an enabled pipe still completes any pageflip right
> +	 * away (as if the pipe is off) instead of waiting for vblank. As soon
> +	 * as the first vblank happend, everything works as expected. Hence just
> +	 * wait for one vblank before returning to avoid strange things
> +	 * happening.
> +	 */
> +	intel_wait_for_vblank(dev, intel_crtc->pipe);
> +}
> +
>  static void ironlake_crtc_disable(struct drm_crtc *crtc)
>  {
>  	struct drm_device *dev = crtc->dev;
> @@ -3369,6 +3462,92 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
>  	mutex_unlock(&dev->struct_mutex);
>  }
>  
> +static void haswell_crtc_disable(struct drm_crtc *crtc)
> +{
> +	struct drm_device *dev = crtc->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	struct intel_encoder *encoder;
> +	int pipe = intel_crtc->pipe;
> +	int plane = intel_crtc->plane;
> +	u32 reg, temp;
> +
> +
> +	if (!intel_crtc->active)
> +		return;
> +
> +	for_each_encoder_on_crtc(dev, crtc, encoder)
> +		encoder->disable(encoder);
> +
> +	intel_crtc_wait_for_pending_flips(crtc);
> +	drm_vblank_off(dev, pipe);
> +	intel_crtc_update_cursor(crtc, false);
> +
> +	intel_disable_plane(dev_priv, plane, pipe);
> +
> +	if (dev_priv->cfb_plane == plane)
> +		intel_disable_fbc(dev);
> +
> +	intel_disable_pipe(dev_priv, pipe);
> +
> +	if (IS_HASWELL(dev))
> +		intel_ddi_disable_pipe_func(dev_priv, pipe);
> +
> +	/* Disable PF */
> +	I915_WRITE(PF_CTL(pipe), 0);
> +	I915_WRITE(PF_WIN_SZ(pipe), 0);
> +
> +	if (IS_HASWELL(dev))
> +		intel_ddi_disable_pipe_clock(intel_crtc);
> +
> +	for_each_encoder_on_crtc(dev, crtc, encoder)
> +		if (encoder->post_disable)
> +			encoder->post_disable(encoder);
> +
> +	ironlake_fdi_disable(crtc);
> +
> +	intel_disable_transcoder(dev_priv, pipe);
> +
> +	if (HAS_PCH_CPT(dev)) {
> +		/* disable TRANS_DP_CTL */
> +		reg = TRANS_DP_CTL(pipe);
> +		temp = I915_READ(reg);
> +		temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
> +		temp |= TRANS_DP_PORT_SEL_NONE;
> +		I915_WRITE(reg, temp);
> +
> +		/* disable DPLL_SEL */
> +		temp = I915_READ(PCH_DPLL_SEL);
> +		switch (pipe) {
> +		case 0:
> +			temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
> +			break;
> +		case 1:
> +			temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
> +			break;
> +		case 2:
> +			/* C shares PLL A or B */
> +			temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
> +			break;
> +		default:
> +			BUG(); /* wtf */
> +		}
> +		I915_WRITE(PCH_DPLL_SEL, temp);
> +	}
> +
> +	/* disable PCH DPLL */
> +	intel_disable_pch_pll(intel_crtc);
> +
> +	ironlake_fdi_pll_disable(intel_crtc);
> +
> +	intel_crtc->active = false;
> +	intel_update_watermarks(dev);
> +
> +	mutex_lock(&dev->struct_mutex);
> +	intel_update_fbc(dev);
> +	mutex_unlock(&dev->struct_mutex);
> +}
> +
>  static void ironlake_crtc_off(struct drm_crtc *crtc)
>  {
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -8109,8 +8288,8 @@ static void intel_init_display(struct drm_device *dev)
>  	/* We always want a DPMS function */
>  	if (IS_HASWELL(dev)) {
>  		dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
> -		dev_priv->display.crtc_enable = ironlake_crtc_enable;
> -		dev_priv->display.crtc_disable = ironlake_crtc_disable;
> +		dev_priv->display.crtc_enable = haswell_crtc_enable;
> +		dev_priv->display.crtc_disable = haswell_crtc_disable;
>  		dev_priv->display.off = haswell_crtc_off;
>  		dev_priv->display.update_plane = ironlake_update_plane;
>  	} else if (HAS_PCH_SPLIT(dev)) {
> -- 
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 02-1/18] drm/i915: fix checks inside ironlake_crtc_{enable, disable}

[Jani Nikula]

On Wed, 24 Oct 2012, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> The last commit forked a Haswell version, so now we remove Haswell
> code from these functions.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 14 --------------
>  1 file changed, 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index eb4dba6..e5dc22c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3228,9 +3228,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>  		if (encoder->pre_enable)
>  			encoder->pre_enable(encoder);
>  
> -	if (IS_HASWELL(dev))
> -		intel_ddi_enable_pipe_clock(intel_crtc);
> -
>  	/* Enable panel fitting for LVDS */
>  	if (dev_priv->pch_pf_size &&
>  	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
> @@ -3249,11 +3246,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>  	 */
>  	intel_crtc_load_lut(crtc);
>  
> -	if (IS_HASWELL(dev)) {
> -		intel_ddi_set_pipe_settings(crtc);
> -		intel_ddi_enable_pipe_func(crtc);
> -	}
> -
>  	intel_enable_pipe(dev_priv, pipe, is_pch_port);
>  	intel_enable_plane(dev_priv, plane, pipe);
>  
> @@ -3404,16 +3396,10 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
>  
>  	intel_disable_pipe(dev_priv, pipe);
>  
> -	if (IS_HASWELL(dev))
> -		intel_ddi_disable_pipe_func(dev_priv, pipe);
> -
>  	/* Disable PF */
>  	I915_WRITE(PF_CTL(pipe), 0);
>  	I915_WRITE(PF_WIN_SZ(pipe), 0);
>  
> -	if (IS_HASWELL(dev))
> -		intel_ddi_disable_pipe_clock(intel_crtc);
> -
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		if (encoder->post_disable)
>  			encoder->post_disable(encoder);
> -- 
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 02-2/18] drm/i915: fix checks inside haswell_crtc_{enable, disable}

[Jani Nikula]

On Wed, 24 Oct 2012, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> These functions were forked from their Ironlake versions, so now fix
> the gen checks to reflect the fact that they will only run on Haswell.
>
> It is worth noticing that we are not considering IBX/CPT possible on
> Haswell anymore. So far on Haswell enablement we kept trying to still
> consider IBX/CPT as a possibility with a Haswell CPU, but this was
> never tested, I really doubt it will work with the current code and we
> don't really have plans to support it. Future patches will remove the
> IBX/CPT code from other Haswell functions. Notice that we still have a
> WARN on haswell_crtc_mode_set in case we detect non-LPT PCH.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 59 +++++-------------------------------
>  1 file changed, 7 insertions(+), 52 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e5dc22c..a90da35 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3283,7 +3283,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  	struct intel_encoder *encoder;
>  	int pipe = intel_crtc->pipe;
>  	int plane = intel_crtc->plane;
> -	u32 temp;
>  	bool is_pch_port;
>  
>  	WARN_ON(!crtc->enabled);
> @@ -3294,12 +3293,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  	intel_crtc->active = true;
>  	intel_update_watermarks(dev);
>  
> -	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
> -		temp = I915_READ(PCH_LVDS);
> -		if ((temp & LVDS_PORT_EN) == 0)
> -			I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
> -	}
> -
>  	is_pch_port = intel_crtc_driving_pch(crtc);
>  
>  	if (is_pch_port) {
> @@ -3313,12 +3306,10 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  		if (encoder->pre_enable)
>  			encoder->pre_enable(encoder);
>  
> -	if (IS_HASWELL(dev))
> -		intel_ddi_enable_pipe_clock(intel_crtc);
> +	intel_ddi_enable_pipe_clock(intel_crtc);
>  
> -	/* Enable panel fitting for LVDS */
> -	if (dev_priv->pch_pf_size &&
> -	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
> +	/* Enable panel fitting for eDP */
> +	if (dev_priv->pch_pf_size && HAS_eDP) {

You could just make that intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)
instead of HAS_eDP. But it was there before, and HAS_eDP could (and
should!) be nuked afterwards anyway.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>  		/* Force use of hard-coded filter coefficients
>  		 * as some pre-programmed values are broken,
>  		 * e.g. x201.
> @@ -3334,10 +3325,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  	 */
>  	intel_crtc_load_lut(crtc);
>  
> -	if (IS_HASWELL(dev)) {
> -		intel_ddi_set_pipe_settings(crtc);
> -		intel_ddi_enable_pipe_func(crtc);
> -	}
> +	intel_ddi_set_pipe_settings(crtc);
> +	intel_ddi_enable_pipe_func(crtc);
>  
>  	intel_enable_pipe(dev_priv, pipe, is_pch_port);
>  	intel_enable_plane(dev_priv, plane, pipe);
> @@ -3354,9 +3343,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		encoder->enable(encoder);
>  
> -	if (HAS_PCH_CPT(dev))
> -		intel_cpt_verify_modeset(dev, intel_crtc->pipe);
> -
>  	/*
>  	 * There seems to be a race in PCH platform hw (at least on some
>  	 * outputs) where an enabled pipe still completes any pageflip right
> @@ -3456,8 +3442,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
>  	struct intel_encoder *encoder;
>  	int pipe = intel_crtc->pipe;
>  	int plane = intel_crtc->plane;
> -	u32 reg, temp;
> -
>  
>  	if (!intel_crtc->active)
>  		return;
> @@ -3476,15 +3460,13 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
>  
>  	intel_disable_pipe(dev_priv, pipe);
>  
> -	if (IS_HASWELL(dev))
> -		intel_ddi_disable_pipe_func(dev_priv, pipe);
> +	intel_ddi_disable_pipe_func(dev_priv, pipe);
>  
>  	/* Disable PF */
>  	I915_WRITE(PF_CTL(pipe), 0);
>  	I915_WRITE(PF_WIN_SZ(pipe), 0);
>  
> -	if (IS_HASWELL(dev))
> -		intel_ddi_disable_pipe_clock(intel_crtc);
> +	intel_ddi_disable_pipe_clock(intel_crtc);
>  
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		if (encoder->post_disable)
> @@ -3494,33 +3476,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
>  
>  	intel_disable_transcoder(dev_priv, pipe);
>  
> -	if (HAS_PCH_CPT(dev)) {
> -		/* disable TRANS_DP_CTL */
> -		reg = TRANS_DP_CTL(pipe);
> -		temp = I915_READ(reg);
> -		temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
> -		temp |= TRANS_DP_PORT_SEL_NONE;
> -		I915_WRITE(reg, temp);
> -
> -		/* disable DPLL_SEL */
> -		temp = I915_READ(PCH_DPLL_SEL);
> -		switch (pipe) {
> -		case 0:
> -			temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
> -			break;
> -		case 1:
> -			temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
> -			break;
> -		case 2:
> -			/* C shares PLL A or B */
> -			temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
> -			break;
> -		default:
> -			BUG(); /* wtf */
> -		}
> -		I915_WRITE(PCH_DPLL_SEL, temp);
> -	}
> -
>  	/* disable PCH DPLL */
>  	intel_disable_pch_pll(intel_crtc);
>  
> -- 
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 10/18] drm/i915: convert PIPE_MSA_MISC to transcoder

[Lespiau, Damien]

On Tue, Oct 23, 2012 at 9:30 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Same as the other registers. This one also appeared on Haswell for the
> first time, so that's why we are renaming it.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

Re: [PATCH 11/18] drm/i915: convert CPU M/N timings to transcoder

[Lespiau, Damien]

On Tue, Oct 23, 2012 at 9:30 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Same thing as the previous commits. Not renaming this one since it
> exists since way before Haswell.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

Re: [PATCH 12/18] drm/i915: convert pipe timing definitions to transcoder

[Lespiau, Damien]

On Tue, Oct 23, 2012 at 9:30 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

Re: [PATCH 09/18] drm/i915: convert PIPECONF to use transcoder instead of pipe

[Lespiau, Damien]

On Tue, Oct 23, 2012 at 9:29 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Because the PIPECONF register is actually part of the CPU transcoder,
> not the CPU pipe.
>
> Ideally we would also rename PIPECONF to TRANSCONF to remind people
> that they should use the transcoder instead of the pipe, but let's
> keep it like this for now since most Gens still name it PIPECONF.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

Re: [PATCH 03/18] drm/i915: simplify intel_crtc_driving_pch

[Jani Nikula]

On Tue, 23 Oct 2012, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> By forking Ironlake and Haswell functions. The only callers are
> {ironlake,haswell}_crtc_enable anyway, and this way we won't need to
> add other checks on the Haswell version for the next gens.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 31 +++++++++++--------------------
>  1 file changed, 11 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a90da35..0c4e9c5 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2849,7 +2849,7 @@ static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
>  	mutex_unlock(&dev->struct_mutex);
>  }
>  
> -static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
> +static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
>  {
>  	struct drm_device *dev = crtc->dev;
>  	struct intel_encoder *intel_encoder;
> @@ -2859,23 +2859,6 @@ static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
>  	 * must be driven by its own crtc; no sharing is possible.
>  	 */
>  	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
> -
> -		/* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
> -		 * CPU handles all others */
> -		if (IS_HASWELL(dev)) {
> -			/* It is still unclear how this will work on PPT, so throw up a warning */
> -			WARN_ON(!HAS_PCH_LPT(dev));
> -
> -			if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
> -				DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
> -				return true;
> -			} else {
> -				DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
> -					      intel_encoder->type);
> -				return false;
> -			}
> -		}
> -
>  		switch (intel_encoder->type) {
>  		case INTEL_OUTPUT_EDP:
>  			if (!intel_encoder_is_pch_edp(&intel_encoder->base))
> @@ -2887,6 +2870,14 @@ static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
>  	return true;
>  }
>  
> +static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
> +{
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
> +		return true;
> +	else
> +		return false;
> +}

Nitpick, this could be written just:

	return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);

A pedantic observation: the previous version in intel_crtc_driving_pch
unconditionally stopped at the first encoder on the crtc on HSW, this
one checks that *none* of the encoders has type INTEL_OUTPUT_ANALOG
before it returns false. It doesn't matter either way, does it?

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> +
>  /* Program iCLKIP clock to the desired frequency */
>  static void lpt_program_iclkip(struct drm_crtc *crtc)
>  {
> @@ -3215,7 +3206,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>  			I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
>  	}
>  
> -	is_pch_port = intel_crtc_driving_pch(crtc);
> +	is_pch_port = ironlake_crtc_driving_pch(crtc);
>  
>  	if (is_pch_port) {
>  		ironlake_fdi_pll_enable(intel_crtc);
> @@ -3293,7 +3284,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  	intel_crtc->active = true;
>  	intel_update_watermarks(dev);
>  
> -	is_pch_port = intel_crtc_driving_pch(crtc);
> +	is_pch_port = haswell_crtc_driving_pch(crtc);
>  
>  	if (is_pch_port) {
>  		ironlake_fdi_pll_enable(intel_crtc);
> -- 
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 03/18] drm/i915: simplify intel_crtc_driving_pch

[Paulo Zanoni]

Hi

2012/10/25 Jani Nikula <jani.nikula@linux.intel.com>:
> On Tue, 23 Oct 2012, Paulo Zanoni <przanoni@gmail.com> wrote:
>> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>>
>> By forking Ironlake and Haswell functions. The only callers are
>> {ironlake,haswell}_crtc_enable anyway, and this way we won't need to
>> add other checks on the Haswell version for the next gens.
>>
>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_display.c | 31 +++++++++++--------------------
>>  1 file changed, 11 insertions(+), 20 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index a90da35..0c4e9c5 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -2849,7 +2849,7 @@ static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
>>       mutex_unlock(&dev->struct_mutex);
>>  }
>>
>> -static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
>> +static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
>>  {
>>       struct drm_device *dev = crtc->dev;
>>       struct intel_encoder *intel_encoder;
>> @@ -2859,23 +2859,6 @@ static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
>>        * must be driven by its own crtc; no sharing is possible.
>>        */
>>       for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
>> -
>> -             /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
>> -              * CPU handles all others */
>> -             if (IS_HASWELL(dev)) {
>> -                     /* It is still unclear how this will work on PPT, so throw up a warning */
>> -                     WARN_ON(!HAS_PCH_LPT(dev));
>> -
>> -                     if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
>> -                             DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
>> -                             return true;
>> -                     } else {
>> -                             DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
>> -                                           intel_encoder->type);
>> -                             return false;
>> -                     }
>> -             }
>> -
>>               switch (intel_encoder->type) {
>>               case INTEL_OUTPUT_EDP:
>>                       if (!intel_encoder_is_pch_edp(&intel_encoder->base))
>> @@ -2887,6 +2870,14 @@ static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
>>       return true;
>>  }
>>
>> +static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
>> +{
>> +     if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
>> +             return true;
>> +     else
>> +             return false;
>> +}
>
> Nitpick, this could be written just:
>
>         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);

Now my code looks so stupid! =)

>
> A pedantic observation: the previous version in intel_crtc_driving_pch
> unconditionally stopped at the first encoder on the crtc on HSW, this
> one checks that *none* of the encoders has type INTEL_OUTPUT_ANALOG
> before it returns false. It doesn't matter either way, does it?

I think the main reason for this patch is that I don't like the fact
that the old code unconditionally returned on the first iteration, but
that's not real a problem, it's just my opinion about coding style. On
Haswell there's just 1 encoder for each crtc and we check for this
condition on haswell_crtc_mode_set. On previous gens we can have more
than 1 encoder, so we have to loop over all the encoders.

>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>
>> +
>>  /* Program iCLKIP clock to the desired frequency */
>>  static void lpt_program_iclkip(struct drm_crtc *crtc)
>>  {
>> @@ -3215,7 +3206,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>>                       I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
>>       }
>>
>> -     is_pch_port = intel_crtc_driving_pch(crtc);
>> +     is_pch_port = ironlake_crtc_driving_pch(crtc);
>>
>>       if (is_pch_port) {
>>               ironlake_fdi_pll_enable(intel_crtc);
>> @@ -3293,7 +3284,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>>       intel_crtc->active = true;
>>       intel_update_watermarks(dev);
>>
>> -     is_pch_port = intel_crtc_driving_pch(crtc);
>> +     is_pch_port = haswell_crtc_driving_pch(crtc);
>>
>>       if (is_pch_port) {
>>               ironlake_fdi_pll_enable(intel_crtc);
>> --
>> 1.7.11.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 04/18] drm/i915: don't call Haswell PCH code when we can't or don't need

[Jani Nikula]

On Tue, 23 Oct 2012, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> On Ironlake we have one PCH transcoder and FDI per pipe, so we know
> that if ironlake_crtc_driving_pch returns false we can disable the PCH
> transcoder and we also know that when we disable the crtc we can also
> disable the PCH transcoder.
>
> On Haswell there is only 1 PCH transcoder and FDI and they can be used
> by any CRTC. So if for one specific crtc haswell_crtc_driving_pch
> returns false we can't assert anything about the state of the PCH
> transcoder or the FDI link without checking if any other CRTC is using
> the PCH.
>
> So on this commit remove the "assert_fdi_{t,r}x_disabled" form
> haswell_crtc_enable and also only disable FDI and the PCH transcoder
> if the port being disabled was actually a PCH port (we only have one
> port using PCH: the VGA port).

I first wrote a message saying this is wrong, then revisited the patch,
and finally reached the same conclusions as you...

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 23 ++++++++++-------------
>  1 file changed, 10 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0c4e9c5..67c9472 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3286,12 +3286,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  
>  	is_pch_port = haswell_crtc_driving_pch(crtc);
>  
> -	if (is_pch_port) {
> +	if (is_pch_port)
>  		ironlake_fdi_pll_enable(intel_crtc);
> -	} else {
> -		assert_fdi_tx_disabled(dev_priv, pipe);
> -		assert_fdi_rx_disabled(dev_priv, pipe);
> -	}
>  
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		if (encoder->pre_enable)
> @@ -3433,10 +3429,13 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
>  	struct intel_encoder *encoder;
>  	int pipe = intel_crtc->pipe;
>  	int plane = intel_crtc->plane;
> +	bool is_pch_port;
>  
>  	if (!intel_crtc->active)
>  		return;
>  
> +	is_pch_port = haswell_crtc_driving_pch(crtc);
> +
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		encoder->disable(encoder);
>  
> @@ -3463,14 +3462,12 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
>  		if (encoder->post_disable)
>  			encoder->post_disable(encoder);
>  
> -	ironlake_fdi_disable(crtc);
> -
> -	intel_disable_transcoder(dev_priv, pipe);
> -
> -	/* disable PCH DPLL */
> -	intel_disable_pch_pll(intel_crtc);
> -
> -	ironlake_fdi_pll_disable(intel_crtc);
> +	if (is_pch_port) {
> +		ironlake_fdi_disable(crtc);
> +		intel_disable_transcoder(dev_priv, pipe);
> +		intel_disable_pch_pll(intel_crtc);
> +		ironlake_fdi_pll_disable(intel_crtc);
> +	}
>  
>  	intel_crtc->active = false;
>  	intel_update_watermarks(dev);
> -- 
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 03/18] drm/i915: simplify intel_crtc_driving_pch

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

By forking Ironlake and Haswell functions. The only callers are
{ironlake,haswell}_crtc_enable anyway, and this way we won't need to
add other checks on the Haswell version for the next gens.

V2: Even simpler, as pointed by Jani Nikula.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 28 ++++++++--------------------
 1 file changed, 8 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a90da35..10222e8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2849,7 +2849,7 @@ static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
 	mutex_unlock(&dev->struct_mutex);
 }
 
-static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
+static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct intel_encoder *intel_encoder;
@@ -2859,23 +2859,6 @@ static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
 	 * must be driven by its own crtc; no sharing is possible.
 	 */
 	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
-
-		/* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
-		 * CPU handles all others */
-		if (IS_HASWELL(dev)) {
-			/* It is still unclear how this will work on PPT, so throw up a warning */
-			WARN_ON(!HAS_PCH_LPT(dev));
-
-			if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
-				DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
-				return true;
-			} else {
-				DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
-					      intel_encoder->type);
-				return false;
-			}
-		}
-
 		switch (intel_encoder->type) {
 		case INTEL_OUTPUT_EDP:
 			if (!intel_encoder_is_pch_edp(&intel_encoder->base))
@@ -2887,6 +2870,11 @@ static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
 	return true;
 }
 
+static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
+{
+	return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
+}
+
 /* Program iCLKIP clock to the desired frequency */
 static void lpt_program_iclkip(struct drm_crtc *crtc)
 {
@@ -3215,7 +3203,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 			I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
 	}
 
-	is_pch_port = intel_crtc_driving_pch(crtc);
+	is_pch_port = ironlake_crtc_driving_pch(crtc);
 
 	if (is_pch_port) {
 		ironlake_fdi_pll_enable(intel_crtc);
@@ -3293,7 +3281,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	intel_crtc->active = true;
 	intel_update_watermarks(dev);
 
-	is_pch_port = intel_crtc_driving_pch(crtc);
+	is_pch_port = haswell_crtc_driving_pch(crtc);
 
 	if (is_pch_port) {
 		ironlake_fdi_pll_enable(intel_crtc);
-- 
1.7.11.4

Re: [PATCH 18/18] drm/i915: enable DDI eDP

[Daniel Vetter]

On Wed, Oct 24, 2012 at 12:24:15PM -0200, Rodrigo Vivi wrote:
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> 
> On Tue, Oct 23, 2012 at 6:30 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >
> > Now that all the eDP enablement bits are there, we can actually try to
> > use the eDP.
> >
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Entire pile merged. Thanks a lot for the patches and big kudos to everyone
who chipped in with reviewing.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch