* [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand
@ 2023-06-06 9:35 Vinod Govindapillai
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 1/7] drm/i915: fix the derating percentage for MTL Vinod Govindapillai
` (14 more replies)
0 siblings, 15 replies; 20+ messages in thread
From: Vinod Govindapillai @ 2023-06-06 9:35 UTC (permalink / raw)
To: intel-gfx
SAGV configuration support for MTL
v2: added one missing patch in the previous version
v3: chekcpatch warning fixes
update index handling for the icl/tgl QGV point handling
program pmdemand code simplified
v4: update to debufs and pipe values pmdemand regiters
removed the macro usage in update_pmdemand_values
V5: Addressing comments from Gustavo and Jani
And some other fixes for issues from CI
v6: Addressing some comments from Gustavo
Updates to pmdemand state struct, active phys calculations
Got rid of suppress warning patch from v5
v7: Rebased and updates to max ddiclk and active phys calculations
v8: updates to active phys calcuations
v9: Address styling issues
v10: Updates to phys calculation, pmdemand state initialization during
HW readout / sanitization
v11: Fix CI checkpatch warnings
v12: Addressing comments
v13: Updates based on imre's comments to handle non serialize cases,
updates tp phys mask during sanitize calls after HW readout
v14: check display version before accessig pmdemand functions
Mika Kahola (1):
drm/i915/mtl: Add support for PM DEMAND
Vinod Govindapillai (6):
drm/i915: fix the derating percentage for MTL
drm/i915: update the QGV point frequency calculations
drm/i915: store the peak bw per QGV point
drm/i915: extract intel_bw_check_qgv_points()
drm/i915: modify max_bw to return index to intel_bw_info
drm/i915/mtl: find the best QGV point for the SAGV configuration
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_bw.c | 345 ++++++---
drivers/gpu/drm/i915/display/intel_bw.h | 6 +
drivers/gpu/drm/i915/display/intel_display.c | 14 +
.../gpu/drm/i915/display/intel_display_core.h | 11 +
.../drm/i915/display/intel_display_driver.c | 7 +
.../gpu/drm/i915/display/intel_display_irq.c | 23 +-
.../drm/i915/display/intel_display_power.c | 14 +-
.../drm/i915/display/intel_modeset_setup.c | 36 +
drivers/gpu/drm/i915/display/intel_pmdemand.c | 714 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_pmdemand.h | 69 ++
drivers/gpu/drm/i915/i915_reg.h | 36 +-
12 files changed, 1153 insertions(+), 123 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v14 1/7] drm/i915: fix the derating percentage for MTL
2023-06-06 9:35 [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand Vinod Govindapillai
@ 2023-06-06 9:35 ` Vinod Govindapillai
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 2/7] drm/i915: update the QGV point frequency calculations Vinod Govindapillai
` (13 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Vinod Govindapillai @ 2023-06-06 9:35 UTC (permalink / raw)
To: intel-gfx
Follow the values from bspec for the percentage overhead for
efficiency in MTL BW calculations.
Bspec: 64631
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 597d5816ad1b..ab405c48ca3a 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -379,7 +379,7 @@ static const struct intel_sa_info mtl_sa_info = {
.deburst = 32,
.deprogbwlimit = 38, /* GB/s */
.displayrtids = 256,
- .derating = 20,
+ .derating = 10,
};
static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v14 2/7] drm/i915: update the QGV point frequency calculations
2023-06-06 9:35 [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand Vinod Govindapillai
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 1/7] drm/i915: fix the derating percentage for MTL Vinod Govindapillai
@ 2023-06-06 9:35 ` Vinod Govindapillai
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 3/7] drm/i915: store the peak bw per QGV point Vinod Govindapillai
` (12 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Vinod Govindapillai @ 2023-06-06 9:35 UTC (permalink / raw)
To: intel-gfx
From MTL onwwards, pcode locks the QGV point based on peak BW of
the intended QGV point passed by the driver. So the peak BW
calculation must match the value expected by the pcode. Update
the calculations as per the Bspec.
v2: use DIV_ROUND_* macro for the calculations (Ville)
v3: Use only DIV_ROUN_CLOSEST and remove divisor / 2 again
Bspec: 64636
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index ab405c48ca3a..61b3babf2d83 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -182,7 +182,7 @@ static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv,
val2 = intel_uncore_read(&dev_priv->uncore,
MTL_MEM_SS_INFO_QGV_POINT_HIGH(point));
dclk = REG_FIELD_GET(MTL_DCLK_MASK, val);
- sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000);
+ sp->dclk = DIV_ROUND_CLOSEST(16667 * dclk, 1000);
sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val);
sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v14 3/7] drm/i915: store the peak bw per QGV point
2023-06-06 9:35 [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand Vinod Govindapillai
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 1/7] drm/i915: fix the derating percentage for MTL Vinod Govindapillai
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 2/7] drm/i915: update the QGV point frequency calculations Vinod Govindapillai
@ 2023-06-06 9:35 ` Vinod Govindapillai
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 4/7] drm/i915: extract intel_bw_check_qgv_points() Vinod Govindapillai
` (11 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Vinod Govindapillai @ 2023-06-06 9:35 UTC (permalink / raw)
To: intel-gfx
In MTL onwards, pcode locks the GV point based on the peak BW
of a QGV point. So store the peak BW of all the QGV points.
v2: use DIV_ROUND_CLOSEST() for the peakBW calculation
Bspec: 64636
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 8 ++++++--
drivers/gpu/drm/i915/display/intel_display_core.h | 2 ++
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 61b3babf2d83..b792d307e9d5 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -534,10 +534,14 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
bi->deratedbw[j] = min(maxdebw,
bw * (100 - sa->derating) / 100);
+ bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
+ num_channels *
+ qi.channel_width, 8);
drm_dbg_kms(&dev_priv->drm,
- "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
- i, j, bi->num_planes, bi->deratedbw[j]);
+ "BW%d / QGV %d: num_planes=%d deratedbw=%u peakbw: %u\n",
+ i, j, bi->num_planes, bi->deratedbw[j],
+ bi->peakbw[j]);
}
for (j = 0; j < qi.num_psf_points; j++) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 2209811eb29e..dd8e08c8598f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -314,6 +314,8 @@ struct intel_display {
unsigned int deratedbw[I915_NUM_QGV_POINTS];
/* for each PSF GV point */
unsigned int psf_bw[I915_NUM_PSF_GV_POINTS];
+ /* Peak BW for each QGV point */
+ unsigned int peakbw[I915_NUM_QGV_POINTS];
u8 num_qgv_points;
u8 num_psf_gv_points;
u8 num_planes;
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v14 4/7] drm/i915: extract intel_bw_check_qgv_points()
2023-06-06 9:35 [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand Vinod Govindapillai
` (2 preceding siblings ...)
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 3/7] drm/i915: store the peak bw per QGV point Vinod Govindapillai
@ 2023-06-06 9:35 ` Vinod Govindapillai
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 5/7] drm/i915: modify max_bw to return index to intel_bw_info Vinod Govindapillai
` (10 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Vinod Govindapillai @ 2023-06-06 9:35 UTC (permalink / raw)
To: intel-gfx
Extract intel_bw_check_qgv_points() from intel_bw_atomic_check
to facilitate future platform variations in handling SAGV
configurations.
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 235 +++++++++++++-----------
1 file changed, 130 insertions(+), 105 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index b792d307e9d5..56b3975f3ccb 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -803,6 +803,128 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
return to_intel_bw_state(bw_state);
}
+static int icl_find_qgv_points(struct drm_i915_private *i915,
+ unsigned int data_rate,
+ unsigned int num_active_planes,
+ const struct intel_bw_state *old_bw_state,
+ struct intel_bw_state *new_bw_state)
+{
+ unsigned int max_bw_point = 0;
+ unsigned int max_bw = 0;
+ unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
+ unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
+ u16 psf_points = 0;
+ u16 qgv_points = 0;
+ int i;
+ int ret;
+
+ ret = intel_atomic_lock_global_state(&new_bw_state->base);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < num_qgv_points; i++) {
+ unsigned int max_data_rate;
+
+ if (DISPLAY_VER(i915) > 11)
+ max_data_rate = tgl_max_bw(i915, num_active_planes, i);
+ else
+ max_data_rate = icl_max_bw(i915, num_active_planes, i);
+ /*
+ * We need to know which qgv point gives us
+ * maximum bandwidth in order to disable SAGV
+ * if we find that we exceed SAGV block time
+ * with watermarks. By that moment we already
+ * have those, as it is calculated earlier in
+ * intel_atomic_check,
+ */
+ if (max_data_rate > max_bw) {
+ max_bw_point = i;
+ max_bw = max_data_rate;
+ }
+ if (max_data_rate >= data_rate)
+ qgv_points |= BIT(i);
+
+ drm_dbg_kms(&i915->drm, "QGV point %d: max bw %d required %d\n",
+ i, max_data_rate, data_rate);
+ }
+
+ for (i = 0; i < num_psf_gv_points; i++) {
+ unsigned int max_data_rate = adl_psf_bw(i915, i);
+
+ if (max_data_rate >= data_rate)
+ psf_points |= BIT(i);
+
+ drm_dbg_kms(&i915->drm, "PSF GV point %d: max bw %d"
+ " required %d\n",
+ i, max_data_rate, data_rate);
+ }
+
+ /*
+ * BSpec states that we always should have at least one allowed point
+ * left, so if we couldn't - simply reject the configuration for obvious
+ * reasons.
+ */
+ if (qgv_points == 0) {
+ drm_dbg_kms(&i915->drm, "No QGV points provide sufficient memory"
+ " bandwidth %d for display configuration(%d active planes).\n",
+ data_rate, num_active_planes);
+ return -EINVAL;
+ }
+
+ if (num_psf_gv_points > 0 && psf_points == 0) {
+ drm_dbg_kms(&i915->drm, "No PSF GV points provide sufficient memory"
+ " bandwidth %d for display configuration(%d active planes).\n",
+ data_rate, num_active_planes);
+ return -EINVAL;
+ }
+
+ /*
+ * Leave only single point with highest bandwidth, if
+ * we can't enable SAGV due to the increased memory latency it may
+ * cause.
+ */
+ if (!intel_can_enable_sagv(i915, new_bw_state)) {
+ qgv_points = BIT(max_bw_point);
+ drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point %d\n",
+ max_bw_point);
+ }
+
+ /*
+ * We store the ones which need to be masked as that is what PCode
+ * actually accepts as a parameter.
+ */
+ new_bw_state->qgv_points_mask =
+ ~(ICL_PCODE_REQ_QGV_PT(qgv_points) |
+ ADLS_PCODE_REQ_PSF_PT(psf_points)) &
+ icl_qgv_points_mask(i915);
+
+ /*
+ * If the actual mask had changed we need to make sure that
+ * the commits are serialized(in case this is a nomodeset, nonblocking)
+ */
+ if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
+ ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int intel_bw_check_qgv_points(struct drm_i915_private *i915,
+ const struct intel_bw_state *old_bw_state,
+ struct intel_bw_state *new_bw_state)
+{
+ unsigned int data_rate = intel_bw_data_rate(i915, new_bw_state);
+ unsigned int num_active_planes =
+ intel_bw_num_active_planes(i915, new_bw_state);
+
+ data_rate = DIV_ROUND_UP(data_rate, 1000);
+
+ return icl_find_qgv_points(i915, data_rate, num_active_planes,
+ old_bw_state, new_bw_state);
+}
+
static bool intel_bw_state_changed(struct drm_i915_private *i915,
const struct intel_bw_state *old_bw_state,
const struct intel_bw_state *new_bw_state)
@@ -1049,20 +1171,14 @@ static int intel_bw_check_data_rate(struct intel_atomic_state *state, bool *chan
int intel_bw_atomic_check(struct intel_atomic_state *state)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- const struct intel_bw_state *old_bw_state;
- struct intel_bw_state *new_bw_state;
- unsigned int data_rate;
- unsigned int num_active_planes;
- int i, ret;
- u16 qgv_points = 0, psf_points = 0;
- unsigned int max_bw_point = 0, max_bw = 0;
- unsigned int num_qgv_points = dev_priv->display.bw.max[0].num_qgv_points;
- unsigned int num_psf_gv_points = dev_priv->display.bw.max[0].num_psf_gv_points;
bool changed = false;
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_bw_state *new_bw_state;
+ const struct intel_bw_state *old_bw_state;
+ int ret;
/* FIXME earlier gens need some checks too */
- if (DISPLAY_VER(dev_priv) < 11)
+ if (DISPLAY_VER(i915) < 11)
return 0;
ret = intel_bw_check_data_rate(state, &changed);
@@ -1073,8 +1189,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
new_bw_state = intel_atomic_get_new_bw_state(state);
if (new_bw_state &&
- intel_can_enable_sagv(dev_priv, old_bw_state) !=
- intel_can_enable_sagv(dev_priv, new_bw_state))
+ intel_can_enable_sagv(i915, old_bw_state) !=
+ intel_can_enable_sagv(i915, new_bw_state))
changed = true;
/*
@@ -1084,101 +1200,10 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
if (!changed)
return 0;
- ret = intel_atomic_lock_global_state(&new_bw_state->base);
+ ret = intel_bw_check_qgv_points(i915, old_bw_state, new_bw_state);
if (ret)
return ret;
- data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
- data_rate = DIV_ROUND_UP(data_rate, 1000);
-
- num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
-
- for (i = 0; i < num_qgv_points; i++) {
- unsigned int max_data_rate;
-
- if (DISPLAY_VER(dev_priv) > 11)
- max_data_rate = tgl_max_bw(dev_priv, num_active_planes, i);
- else
- max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
- /*
- * We need to know which qgv point gives us
- * maximum bandwidth in order to disable SAGV
- * if we find that we exceed SAGV block time
- * with watermarks. By that moment we already
- * have those, as it is calculated earlier in
- * intel_atomic_check,
- */
- if (max_data_rate > max_bw) {
- max_bw_point = i;
- max_bw = max_data_rate;
- }
- if (max_data_rate >= data_rate)
- qgv_points |= BIT(i);
-
- drm_dbg_kms(&dev_priv->drm, "QGV point %d: max bw %d required %d\n",
- i, max_data_rate, data_rate);
- }
-
- for (i = 0; i < num_psf_gv_points; i++) {
- unsigned int max_data_rate = adl_psf_bw(dev_priv, i);
-
- if (max_data_rate >= data_rate)
- psf_points |= BIT(i);
-
- drm_dbg_kms(&dev_priv->drm, "PSF GV point %d: max bw %d"
- " required %d\n",
- i, max_data_rate, data_rate);
- }
-
- /*
- * BSpec states that we always should have at least one allowed point
- * left, so if we couldn't - simply reject the configuration for obvious
- * reasons.
- */
- if (qgv_points == 0) {
- drm_dbg_kms(&dev_priv->drm, "No QGV points provide sufficient memory"
- " bandwidth %d for display configuration(%d active planes).\n",
- data_rate, num_active_planes);
- return -EINVAL;
- }
-
- if (num_psf_gv_points > 0 && psf_points == 0) {
- drm_dbg_kms(&dev_priv->drm, "No PSF GV points provide sufficient memory"
- " bandwidth %d for display configuration(%d active planes).\n",
- data_rate, num_active_planes);
- return -EINVAL;
- }
-
- /*
- * Leave only single point with highest bandwidth, if
- * we can't enable SAGV due to the increased memory latency it may
- * cause.
- */
- if (!intel_can_enable_sagv(dev_priv, new_bw_state)) {
- qgv_points = BIT(max_bw_point);
- drm_dbg_kms(&dev_priv->drm, "No SAGV, using single QGV point %d\n",
- max_bw_point);
- }
-
- /*
- * We store the ones which need to be masked as that is what PCode
- * actually accepts as a parameter.
- */
- new_bw_state->qgv_points_mask =
- ~(ICL_PCODE_REQ_QGV_PT(qgv_points) |
- ADLS_PCODE_REQ_PSF_PT(psf_points)) &
- icl_qgv_points_mask(dev_priv);
-
- /*
- * If the actual mask had changed we need to make sure that
- * the commits are serialized(in case this is a nomodeset, nonblocking)
- */
- if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
- ret = intel_atomic_serialize_global_state(&new_bw_state->base);
- if (ret)
- return ret;
- }
-
return 0;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v14 5/7] drm/i915: modify max_bw to return index to intel_bw_info
2023-06-06 9:35 [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand Vinod Govindapillai
` (3 preceding siblings ...)
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 4/7] drm/i915: extract intel_bw_check_qgv_points() Vinod Govindapillai
@ 2023-06-06 9:35 ` Vinod Govindapillai
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 6/7] drm/i915/mtl: find the best QGV point for the SAGV configuration Vinod Govindapillai
` (9 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Vinod Govindapillai @ 2023-06-06 9:35 UTC (permalink / raw)
To: intel-gfx
MTL uses the peak BW of a QGV point to lock the required QGV
point instead of the QGV index. Instead of passing the deratedbw
of the selected bw_info, return the index to the selected
bw_info so that either deratedbw or peakbw can be used based on
the platform.
v2: use idx to store index returned by max_bw_index functions
v3: return UINT_MAX in icl_max_bw_index in case no match found
v3: check idx >= ARRAY_SIZE
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 27 ++++++++++++++++---------
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 56b3975f3ccb..b1cbeda0b2e3 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -593,8 +593,8 @@ static void dg2_get_bw_info(struct drm_i915_private *i915)
i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
}
-static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
- int num_planes, int qgv_point)
+static unsigned int icl_max_bw_index(struct drm_i915_private *dev_priv,
+ int num_planes, int qgv_point)
{
int i;
@@ -615,14 +615,14 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
return UINT_MAX;
if (num_planes >= bi->num_planes)
- return bi->deratedbw[qgv_point];
+ return i;
}
- return 0;
+ return UINT_MAX;
}
-static unsigned int tgl_max_bw(struct drm_i915_private *dev_priv,
- int num_planes, int qgv_point)
+static unsigned int tgl_max_bw_index(struct drm_i915_private *dev_priv,
+ int num_planes, int qgv_point)
{
int i;
@@ -643,10 +643,10 @@ static unsigned int tgl_max_bw(struct drm_i915_private *dev_priv,
return UINT_MAX;
if (num_planes <= bi->num_planes)
- return bi->deratedbw[qgv_point];
+ return i;
}
- return dev_priv->display.bw.max[0].deratedbw[qgv_point];
+ return 0;
}
static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
@@ -823,12 +823,19 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,
return ret;
for (i = 0; i < num_qgv_points; i++) {
+ unsigned int idx;
unsigned int max_data_rate;
if (DISPLAY_VER(i915) > 11)
- max_data_rate = tgl_max_bw(i915, num_active_planes, i);
+ idx = tgl_max_bw_index(i915, num_active_planes, i);
else
- max_data_rate = icl_max_bw(i915, num_active_planes, i);
+ idx = icl_max_bw_index(i915, num_active_planes, i);
+
+ if (idx >= ARRAY_SIZE(i915->display.bw.max))
+ continue;
+
+ max_data_rate = i915->display.bw.max[idx].deratedbw[i];
+
/*
* We need to know which qgv point gives us
* maximum bandwidth in order to disable SAGV
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v14 6/7] drm/i915/mtl: find the best QGV point for the SAGV configuration
2023-06-06 9:35 [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand Vinod Govindapillai
` (4 preceding siblings ...)
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 5/7] drm/i915: modify max_bw to return index to intel_bw_info Vinod Govindapillai
@ 2023-06-06 9:35 ` Vinod Govindapillai
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 7/7] drm/i915/mtl: Add support for PM DEMAND Vinod Govindapillai
` (8 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Vinod Govindapillai @ 2023-06-06 9:35 UTC (permalink / raw)
To: intel-gfx
From MTL onwards, we need to find the best QGV point based on
the required data rate and pass the peak BW of that point to
the punit to lock the corresponding QGV point.
v1: Fix for warning from kernel test robot
v2: No need to serialize for the peakbw change as pmdemand code
will do that (Imre)
Bspec: 64636
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/r/202305280253.Ab8bRV2w-lkp@intel.com/
Reported-by: Dan Carpenter <error27@gmail.com>
Closes: https://lore.kernel.org/r/202305280253.Ab8bRV2w-lkp@intel.com/
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 79 ++++++++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
2 files changed, 83 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index b1cbeda0b2e3..bef96db62c80 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -803,6 +803,77 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
return to_intel_bw_state(bw_state);
}
+static int mtl_find_qgv_points(struct drm_i915_private *i915,
+ unsigned int data_rate,
+ unsigned int num_active_planes,
+ struct intel_bw_state *new_bw_state)
+{
+ unsigned int best_rate = UINT_MAX;
+ unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
+ unsigned int qgv_peak_bw = 0;
+ int i;
+ int ret;
+
+ ret = intel_atomic_lock_global_state(&new_bw_state->base);
+ if (ret)
+ return ret;
+
+ /*
+ * If SAGV cannot be enabled, disable the pcode SAGV by passing all 1's
+ * for qgv peak bw in PM Demand request. So assign UINT_MAX if SAGV is
+ * not enabled. PM Demand code will clamp the value for the register
+ */
+ if (!intel_can_enable_sagv(i915, new_bw_state)) {
+ new_bw_state->qgv_point_peakbw = U16_MAX;
+ drm_dbg_kms(&i915->drm, "No SAGV, use UINT_MAX as peak bw.");
+ return 0;
+ }
+
+ /*
+ * Find the best QGV point by comparing the data_rate with max data rate
+ * offered per plane group
+ */
+ for (i = 0; i < num_qgv_points; i++) {
+ unsigned int bw_index =
+ tgl_max_bw_index(i915, num_active_planes, i);
+ unsigned int max_data_rate;
+
+ if (bw_index >= ARRAY_SIZE(i915->display.bw.max))
+ continue;
+
+ max_data_rate = i915->display.bw.max[bw_index].deratedbw[i];
+
+ if (max_data_rate < data_rate)
+ continue;
+
+ if (max_data_rate - data_rate < best_rate) {
+ best_rate = max_data_rate - data_rate;
+ qgv_peak_bw = i915->display.bw.max[bw_index].peakbw[i];
+ }
+
+ drm_dbg_kms(&i915->drm, "QGV point %d: max bw %d required %d qgv_peak_bw: %d\n",
+ i, max_data_rate, data_rate, qgv_peak_bw);
+ }
+
+ drm_dbg_kms(&i915->drm, "Matching peaks QGV bw: %d for required data rate: %d\n",
+ qgv_peak_bw, data_rate);
+
+ /*
+ * The display configuration cannot be supported if no QGV point
+ * satisfying the required data rate is found
+ */
+ if (qgv_peak_bw == 0) {
+ drm_dbg_kms(&i915->drm, "No QGV points for bw %d for display configuration(%d active planes).\n",
+ data_rate, num_active_planes);
+ return -EINVAL;
+ }
+
+ /* MTL PM DEMAND expects QGV BW parameter in multiples of 100 mbps */
+ new_bw_state->qgv_point_peakbw = DIV_ROUND_CLOSEST(qgv_peak_bw, 100);
+
+ return 0;
+}
+
static int icl_find_qgv_points(struct drm_i915_private *i915,
unsigned int data_rate,
unsigned int num_active_planes,
@@ -928,8 +999,12 @@ static int intel_bw_check_qgv_points(struct drm_i915_private *i915,
data_rate = DIV_ROUND_UP(data_rate, 1000);
- return icl_find_qgv_points(i915, data_rate, num_active_planes,
- old_bw_state, new_bw_state);
+ if (DISPLAY_VER(i915) >= 14)
+ return mtl_find_qgv_points(i915, data_rate, num_active_planes,
+ new_bw_state);
+ else
+ return icl_find_qgv_points(i915, data_rate, num_active_planes,
+ old_bw_state, new_bw_state);
}
static bool intel_bw_state_changed(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index f20292143745..59cb4fc5db76 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -34,6 +34,12 @@ struct intel_bw_state {
/* bitmask of active pipes */
u8 active_pipes;
+ /*
+ * From MTL onwards, to lock a QGV point, punit expects the peak BW of
+ * the selected QGV point as the parameter in multiples of 100MB/s
+ */
+ u16 qgv_point_peakbw;
+
/*
* Current QGV points mask, which restricts
* some particular SAGV states, not to confuse
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v14 7/7] drm/i915/mtl: Add support for PM DEMAND
2023-06-06 9:35 [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand Vinod Govindapillai
` (5 preceding siblings ...)
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 6/7] drm/i915/mtl: find the best QGV point for the SAGV configuration Vinod Govindapillai
@ 2023-06-06 9:35 ` Vinod Govindapillai
2023-06-06 13:50 ` Imre Deak
2023-06-06 20:10 ` [Intel-gfx] [PATCH v15 " Vinod Govindapillai
2023-06-06 10:32 ` [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand Jani Nikula
` (7 subsequent siblings)
14 siblings, 2 replies; 20+ messages in thread
From: Vinod Govindapillai @ 2023-06-06 9:35 UTC (permalink / raw)
To: intel-gfx
From: Mika Kahola <mika.kahola@intel.com>
MTL introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case scenarios. Changes made to use REG_BIT
for a register that we touched(GEN8_DE_MISC_IER _MMIO).
Wa_14016740474 is added which applies to Xe_LPD+ display
v2: checkpatch warning fixes, simplify program pmdemand part
v3: update to dbufs and pipes values to pmdemand register(stan)
Removed the macro usage in update_pmdemand_values()
v4: move the pmdemand_pre_plane_update before cdclk update
pmdemand_needs_update included cdclk params comparisons
pmdemand_state NULL check (Gustavo)
pmdemand.o in sorted order in the makefile (Jani)
update pmdemand misc irq handler loop (Gustavo)
active phys bitmask and programming correction (Gustavo)
v5: simplify pmdemand_state structure
simplify methods to find active phys and max port clock
Timeout in case of previou pmdemand task pending (Gustavo)
v6: rebasing
updates to max_ddiclk calculations (Gustavo)
updates to active_phys count method (Gustavo)
v7: use two separate loop to iterate throug old and new
crtc states to calculate the active phys (Gustavo)
v8: use uniform function names (Gustavo)
v9: For phys change iterate through connectors (Imre)
Look for change in phys for pmdemand update (Gustavo, Imre)
Some more stlying changes (Imre)
Update pmdemand state during HW readout/sanitize (Imre)
v10: Fix CI checkpatch warnings
v11: use correct pmdemand object pointer during hw readout,
simplify the check for phys need update (Gustavo)
v12: Handle possible non serialize cases (Imre)
Initialise also pmdemand params HW readout (Imre)
Update active phys mask during sanitize calls (Imre)
Check TC/encoder changes to limit connector update (Imre)
v13: Check display version before accessing pmdemand functions
Bspec: 66451, 64636, 64602, 64603
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Acked-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 14 +
.../gpu/drm/i915/display/intel_display_core.h | 9 +
.../drm/i915/display/intel_display_driver.c | 7 +
.../gpu/drm/i915/display/intel_display_irq.c | 23 +-
.../drm/i915/display/intel_display_power.c | 14 +-
.../drm/i915/display/intel_modeset_setup.c | 36 +
drivers/gpu/drm/i915/display/intel_pmdemand.c | 714 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_pmdemand.h | 69 ++
drivers/gpu/drm/i915/i915_reg.h | 36 +-
10 files changed, 917 insertions(+), 6 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1c9ed4c52760..2cd8de174bf6 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -269,6 +269,7 @@ i915-y += \
display/intel_pch_display.o \
display/intel_pch_refclk.o \
display/intel_plane_initial.o \
+ display/intel_pmdemand.o \
display/intel_psr.o \
display/intel_quirks.o \
display/intel_sprite.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f51a55f4e9d0..5cbf5eae2414 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -99,6 +99,7 @@
#include "intel_pcode.h"
#include "intel_pipe_crc.h"
#include "intel_plane_initial.h"
+#include "intel_pmdemand.h"
#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_sdvo.h"
@@ -6352,6 +6353,10 @@ int intel_atomic_check(struct drm_device *dev,
return ret;
}
+ ret = intel_pmdemand_atomic_check(state);
+ if (ret)
+ goto fail;
+
ret = intel_atomic_check_crtcs(state);
if (ret)
goto fail;
@@ -6997,6 +7002,14 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
crtc->config = new_crtc_state;
+ /*
+ * In XE_LPD+ Pmdemand combines many parameters such as voltage index,
+ * plls, cdclk frequency, QGV point selection parameter etc. Voltage
+ * index, cdclk/ddiclk frequencies are supposed to be configured before
+ * the cdclk config is set.
+ */
+ intel_pmdemand_pre_plane_update(state);
+
if (state->modeset) {
drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
@@ -7116,6 +7129,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_verify_planes(state);
intel_sagv_post_plane_update(state);
+ intel_pmdemand_post_plane_update(state);
drm_atomic_helper_commit_hw_done(&state->base);
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index dd8e08c8598f..8d2243c71dd8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -345,6 +345,15 @@ struct intel_display {
struct intel_global_obj obj;
} dbuf;
+ struct {
+ wait_queue_head_t waitqueue;
+
+ /* mutex to protect pmdemand programming sequence */
+ struct mutex lock;
+
+ struct intel_global_obj obj;
+ } pmdemand;
+
struct {
/*
* dkl.phy_lock protects against concurrent access of the
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 60ce10fc7205..dc8de861339d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -47,6 +47,7 @@
#include "intel_opregion.h"
#include "intel_overlay.h"
#include "intel_plane_initial.h"
+#include "intel_pmdemand.h"
#include "intel_pps.h"
#include "intel_quirks.h"
#include "intel_vga.h"
@@ -211,6 +212,8 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
if (ret < 0)
goto cleanup_vga;
+ intel_pmdemand_init_early(i915);
+
intel_power_domains_init_hw(i915, false);
if (!HAS_DISPLAY(i915))
@@ -240,6 +243,10 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
if (ret)
goto cleanup_vga_client_pw_domain_dmc;
+ ret = intel_pmdemand_init(i915);
+ if (ret)
+ goto cleanup_vga_client_pw_domain_dmc;
+
init_llist_head(&i915->display.atomic_helper.free_list);
INIT_WORK(&i915->display.atomic_helper.free_work,
intel_atomic_helper_free_state_worker);
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 3b2a287d2041..0b3739310f81 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -18,6 +18,7 @@
#include "intel_fifo_underrun.h"
#include "intel_gmbus.h"
#include "intel_hotplug_irq.h"
+#include "intel_pmdemand.h"
#include "intel_psr.h"
#include "intel_psr_regs.h"
@@ -827,12 +828,27 @@ static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
}
+static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv)
+{
+ wake_up_all(&dev_priv->display.pmdemand.waitqueue);
+}
+
static void
gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
{
bool found = false;
- if (iir & GEN8_DE_MISC_GSE) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ if (iir & (XELPDP_PMDEMAND_RSP |
+ XELPDP_PMDEMAND_RSPTOUT_ERR)) {
+ if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR)
+ drm_dbg(&dev_priv->drm,
+ "Error waiting for Punit PM Demand Response\n");
+
+ intel_pmdemand_irq_handler(dev_priv);
+ found = true;
+ }
+ } else if (iir & GEN8_DE_MISC_GSE) {
intel_opregion_asle_intr(dev_priv);
found = true;
}
@@ -1576,7 +1592,10 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
de_port_masked |= BXT_DE_PORT_GMBUS;
- if (DISPLAY_VER(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR |
+ XELPDP_PMDEMAND_RSP;
+ } else if (DISPLAY_VER(dev_priv) >= 11) {
enum port port;
if (intel_bios_is_dsi_present(dev_priv, &port))
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 2f4f00ae2f57..db5437043904 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -20,6 +20,7 @@
#include "intel_mchbar_regs.h"
#include "intel_pch_refclk.h"
#include "intel_pcode.h"
+#include "intel_pmdemand.h"
#include "intel_pps_regs.h"
#include "intel_snps_phy.h"
#include "skl_watermark.h"
@@ -1082,20 +1083,29 @@ void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
{
+ u8 slices_mask;
+
dev_priv->display.dbuf.enabled_slices =
intel_enabled_dbuf_slices_mask(dev_priv);
+ slices_mask = BIT(DBUF_S1) | dev_priv->display.dbuf.enabled_slices;
+
+ if (DISPLAY_VER(dev_priv) >= 14)
+ intel_pmdemand_program_dbuf(dev_priv, slices_mask);
+
/*
* Just power up at least 1 slice, we will
* figure out later which slices we have and what we need.
*/
- gen9_dbuf_slices_update(dev_priv, BIT(DBUF_S1) |
- dev_priv->display.dbuf.enabled_slices);
+ gen9_dbuf_slices_update(dev_priv, slices_mask);
}
static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
{
gen9_dbuf_slices_update(dev_priv, 0);
+
+ if (DISPLAY_VER(dev_priv) >= 14)
+ intel_pmdemand_program_dbuf(dev_priv, 0);
}
static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 5ff99ca7f1de..f6b4923de70a 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -26,6 +26,7 @@
#include "intel_fifo_underrun.h"
#include "intel_modeset_setup.h"
#include "intel_pch_display.h"
+#include "intel_pmdemand.h"
#include "intel_tc.h"
#include "intel_vblank.h"
#include "intel_wm.h"
@@ -115,6 +116,8 @@ static void set_encoder_for_connector(struct intel_connector *connector,
static void reset_encoder_connector_state(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_pmdemand_state *pmdemand_state =
+ to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
struct intel_connector *connector;
struct drm_connector_list_iter conn_iter;
@@ -123,6 +126,10 @@ static void reset_encoder_connector_state(struct intel_encoder *encoder)
if (connector->base.encoder != &encoder->base)
continue;
+ /* Clear the corresponding bit in pmdemand active phys mask */
+ intel_pmdemand_update_phys_mask(i915, encoder,
+ pmdemand_state, true);
+
set_encoder_for_connector(connector, NULL);
connector->base.dpms = DRM_MODE_DPMS_OFF;
@@ -151,6 +158,8 @@ static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
to_intel_cdclk_state(i915->display.cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
to_intel_dbuf_state(i915->display.dbuf.obj.state);
+ struct intel_pmdemand_state *pmdemand_state =
+ to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
enum pipe pipe = crtc->pipe;
@@ -174,6 +183,8 @@ static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
bw_state->data_rate[pipe] = 0;
bw_state->num_active_planes[pipe] = 0;
+
+ intel_pmdemand_update_port_clock(i915, pmdemand_state, pipe, 0);
}
/*
@@ -552,6 +563,8 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
struct intel_crtc_state *crtc_state = crtc ?
to_intel_crtc_state(crtc->base.state) : NULL;
+ struct intel_pmdemand_state *pmdemand_state =
+ to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
/*
* We need to check both for a crtc link (meaning that the encoder is
@@ -575,6 +588,10 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
encoder->base.base.id,
encoder->base.name);
+ /* Clear the corresponding bit in pmdemand active phys mask */
+ intel_pmdemand_update_phys_mask(i915, encoder,
+ pmdemand_state, true);
+
/*
* Connector is active, but has no active pipe. This is fallout
* from our resume register restoring. Disable the encoder
@@ -661,6 +678,9 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
to_intel_cdclk_state(i915->display.cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
to_intel_dbuf_state(i915->display.dbuf.obj.state);
+ struct intel_pmdemand_state *pmdemand_state =
+ to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
+ u16 active_phys = 0;
enum pipe pipe;
struct intel_crtc *crtc;
struct intel_encoder *encoder;
@@ -742,6 +762,8 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
drm_connector_list_iter_begin(&i915->drm, &conn_iter);
for_each_intel_connector_iter(connector, &conn_iter) {
+ enum phy phy;
+
if (connector->get_hw_state(connector)) {
struct intel_crtc_state *crtc_state;
struct intel_crtc *crtc;
@@ -764,6 +786,10 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
drm_connector_mask(&connector->base);
crtc_state->uapi.encoder_mask |=
drm_encoder_mask(&encoder->base);
+
+ phy = intel_port_to_phy(i915, encoder->port);
+ if (!intel_phy_is_tc(i915, phy))
+ active_phys |= BIT(phy);
}
} else {
connector->base.dpms = DRM_MODE_DPMS_OFF;
@@ -776,6 +802,9 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
}
drm_connector_list_iter_end(&conn_iter);
+ intel_pmdemand_init_active_phys_mask(i915, pmdemand_state,
+ active_phys);
+
for_each_intel_crtc(&i915->drm, crtc) {
struct intel_bw_state *bw_state =
to_intel_bw_state(i915->display.bw.obj.state);
@@ -840,9 +869,16 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
cdclk_state->min_voltage_level[crtc->pipe] =
crtc_state->min_voltage_level;
+ pmdemand_state->ddi_clocks[crtc->pipe] =
+ crtc_state->port_clock;
+
+ intel_pmdemand_update_port_clock(i915, pmdemand_state, pipe,
+ crtc_state->port_clock);
intel_bw_crtc_update(bw_state, crtc_state);
}
+
+ intel_pmdemand_init_pmdemand_params(i915, pmdemand_state);
}
static void
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
new file mode 100644
index 000000000000..3ee943810300
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -0,0 +1,714 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include <linux/bitops.h>
+
+#include "i915_drv.h"
+#include "i915_reg.h"
+#include "intel_atomic.h"
+#include "intel_bw.h"
+#include "intel_cdclk.h"
+#include "intel_de.h"
+#include "intel_display_trace.h"
+#include "intel_pmdemand.h"
+#include "skl_watermark.h"
+
+static struct intel_global_state *
+intel_pmdemand_duplicate_state(struct intel_global_obj *obj)
+{
+ struct intel_pmdemand_state *pmdemand_state;
+
+ pmdemand_state = kmemdup(obj->state, sizeof(*pmdemand_state), GFP_KERNEL);
+ if (!pmdemand_state)
+ return NULL;
+
+ return &pmdemand_state->base;
+}
+
+static void intel_pmdemand_destroy_state(struct intel_global_obj *obj,
+ struct intel_global_state *state)
+{
+ kfree(state);
+}
+
+static const struct intel_global_state_funcs intel_pmdemand_funcs = {
+ .atomic_duplicate_state = intel_pmdemand_duplicate_state,
+ .atomic_destroy_state = intel_pmdemand_destroy_state,
+};
+
+static struct intel_pmdemand_state *
+intel_atomic_get_pmdemand_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_global_state *pmdemand_state =
+ intel_atomic_get_global_obj_state(state,
+ &i915->display.pmdemand.obj);
+
+ if (IS_ERR(pmdemand_state))
+ return ERR_CAST(pmdemand_state);
+
+ return to_intel_pmdemand_state(pmdemand_state);
+}
+
+static struct intel_pmdemand_state *
+intel_atomic_get_old_pmdemand_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_global_state *pmdemand_state =
+ intel_atomic_get_old_global_obj_state(state,
+ &i915->display.pmdemand.obj);
+
+ if (!pmdemand_state)
+ return NULL;
+
+ return to_intel_pmdemand_state(pmdemand_state);
+}
+
+static struct intel_pmdemand_state *
+intel_atomic_get_new_pmdemand_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_global_state *pmdemand_state =
+ intel_atomic_get_new_global_obj_state(state,
+ &i915->display.pmdemand.obj);
+
+ if (!pmdemand_state)
+ return NULL;
+
+ return to_intel_pmdemand_state(pmdemand_state);
+}
+
+int intel_pmdemand_init(struct drm_i915_private *i915)
+{
+ struct intel_pmdemand_state *pmdemand_state;
+
+ pmdemand_state = kzalloc(sizeof(*pmdemand_state), GFP_KERNEL);
+ if (!pmdemand_state)
+ return -ENOMEM;
+
+ intel_atomic_global_obj_init(i915, &i915->display.pmdemand.obj,
+ &pmdemand_state->base,
+ &intel_pmdemand_funcs);
+
+ if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+ /* Wa_14016740474 */
+ intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
+
+ return 0;
+}
+
+void intel_pmdemand_init_early(struct drm_i915_private *i915)
+{
+ mutex_init(&i915->display.pmdemand.lock);
+ init_waitqueue_head(&i915->display.pmdemand.waitqueue);
+}
+
+void
+intel_pmdemand_init_active_phys_mask(struct drm_i915_private *i915,
+ struct intel_pmdemand_state *pmdemand_state,
+ u16 active_phys)
+{
+ if (DISPLAY_VER(i915) < 14)
+ return;
+
+ pmdemand_state->active_phys_mask = active_phys;
+}
+
+void
+intel_pmdemand_update_phys_mask(struct drm_i915_private *i915,
+ struct intel_encoder *encoder,
+ struct intel_pmdemand_state *pmdemand_state,
+ bool clear_bit)
+{
+ enum phy phy;
+
+ if (DISPLAY_VER(i915) < 14)
+ return;
+
+ if (!encoder)
+ return;
+
+ phy = intel_port_to_phy(i915, encoder->port);
+ if (intel_phy_is_tc(i915, phy))
+ return;
+
+ if (clear_bit)
+ pmdemand_state->active_phys_mask &= ~BIT(phy);
+ else
+ pmdemand_state->active_phys_mask |= BIT(phy);
+}
+
+void
+intel_pmdemand_update_port_clock(struct drm_i915_private *i915,
+ struct intel_pmdemand_state *pmdemand_state,
+ enum pipe pipe, int port_clock)
+{
+ if (DISPLAY_VER(i915) < 14)
+ return;
+
+ pmdemand_state->ddi_clocks[pipe] = port_clock;
+}
+
+static void
+intel_pmdemand_update_max_ddiclk(struct drm_i915_private *i915,
+ struct intel_atomic_state *state,
+ struct intel_pmdemand_state *pmdemand_state)
+{
+ int max_ddiclk = 0;
+ struct intel_crtc *crtc;
+ int i;
+ const struct intel_crtc_state *new_crtc_state;
+
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
+ intel_pmdemand_update_port_clock(i915, pmdemand_state,
+ crtc->pipe,
+ new_crtc_state->port_clock);
+
+ for (i = 0; i < ARRAY_SIZE(pmdemand_state->ddi_clocks); i++)
+ max_ddiclk = max(pmdemand_state->ddi_clocks[i], max_ddiclk);
+
+ pmdemand_state->params.ddiclk_max = DIV_ROUND_UP(max_ddiclk, 1000);
+}
+
+static void
+intel_pmdemand_update_connector_phys(struct drm_i915_private *i915,
+ struct intel_atomic_state *state,
+ struct drm_connector_state *conn_state,
+ bool for_old_state,
+ struct intel_pmdemand_state *pmdemand_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
+ struct intel_encoder *encoder = to_intel_encoder(conn_state->best_encoder);
+ struct intel_crtc_state *crtc_state;
+
+ if (!crtc)
+ return;
+
+ if (for_old_state)
+ crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
+ else
+ crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+
+ if (!crtc_state->hw.active)
+ return;
+
+ intel_pmdemand_update_phys_mask(i915, encoder, pmdemand_state,
+ for_old_state);
+}
+
+static void
+intel_pmdemand_update_active_non_tc_phys(struct drm_i915_private *i915,
+ struct intel_atomic_state *state,
+ struct intel_pmdemand_state *pmdemand_state)
+{
+ struct drm_connector *connector;
+ int i;
+ struct drm_connector_state *old_conn_state, *new_conn_state;
+
+ for_each_oldnew_connector_in_state(&state->base, connector,
+ old_conn_state, new_conn_state, i) {
+ if (!intel_connector_needs_modeset(state, connector))
+ continue;
+
+ /* First clear the active phys in the old connector state */
+ intel_pmdemand_update_connector_phys(i915, state,
+ old_conn_state, true,
+ pmdemand_state);
+
+ /* Then set the active phys in new connector state */
+ intel_pmdemand_update_connector_phys(i915, state,
+ new_conn_state, false,
+ pmdemand_state);
+ }
+
+ pmdemand_state->params.active_phys =
+ hweight16(pmdemand_state->active_phys_mask);
+}
+
+static bool
+intel_pmdemand_encoder_has_tc_phy(struct drm_i915_private *i915,
+ struct intel_encoder *encoder)
+{
+ enum phy phy;
+
+ if (!encoder)
+ return false;
+
+ phy = intel_port_to_phy(i915, encoder->port);
+ if (intel_phy_is_tc(i915, phy))
+ return true;
+
+ return false;
+}
+
+static bool
+intel_pmdemand_connector_needs_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct drm_connector *connector;
+ struct drm_connector_state *new_conn_state, *old_conn_state;
+ int i;
+
+ for_each_oldnew_connector_in_state(&state->base, connector,
+ old_conn_state, new_conn_state, i) {
+ struct intel_encoder *old_encoder =
+ to_intel_encoder(old_conn_state->best_encoder);
+ struct intel_encoder *new_encoder =
+ to_intel_encoder(new_conn_state->best_encoder);
+
+ if (!intel_connector_needs_modeset(state, connector))
+ continue;
+
+ if (old_encoder == new_encoder ||
+ (intel_pmdemand_encoder_has_tc_phy(i915, old_encoder) &&
+ intel_pmdemand_encoder_has_tc_phy(i915, new_encoder)))
+ continue;
+
+ return true;
+ }
+
+ return false;
+}
+
+static bool intel_pmdemand_needs_update(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ int i;
+ const struct intel_bw_state *new_bw_state, *old_bw_state;
+ const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state;
+ const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
+ const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
+
+ new_bw_state = intel_atomic_get_new_bw_state(state);
+ old_bw_state = intel_atomic_get_old_bw_state(state);
+ if (new_bw_state && new_bw_state->qgv_point_peakbw !=
+ old_bw_state->qgv_point_peakbw)
+ return true;
+
+ new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
+ old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
+ if (new_dbuf_state &&
+ (new_dbuf_state->active_pipes !=
+ old_dbuf_state->active_pipes ||
+ new_dbuf_state->enabled_slices !=
+ old_dbuf_state->enabled_slices))
+ return true;
+
+ new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
+ old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
+ if (new_cdclk_state &&
+ (new_cdclk_state->actual.cdclk !=
+ old_cdclk_state->actual.cdclk ||
+ new_cdclk_state->actual.voltage_level !=
+ old_cdclk_state->actual.voltage_level))
+ return true;
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i)
+ if (new_crtc_state->port_clock != old_crtc_state->port_clock)
+ return true;
+
+ if (intel_pmdemand_connector_needs_update(state))
+ return true;
+
+ return false;
+}
+
+int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ const struct intel_bw_state *new_bw_state;
+ const struct intel_cdclk_state *new_cdclk_state;
+ const struct intel_dbuf_state *new_dbuf_state;
+ struct intel_pmdemand_state *new_pmdemand_state;
+ int ret;
+
+ if (DISPLAY_VER(i915) < 14)
+ return 0;
+
+ if (!intel_pmdemand_needs_update(state))
+ return 0;
+
+ new_pmdemand_state = intel_atomic_get_pmdemand_state(state);
+ if (IS_ERR(new_pmdemand_state))
+ return PTR_ERR(new_pmdemand_state);
+
+ ret = intel_atomic_lock_global_state(&new_pmdemand_state->base);
+ if (ret)
+ return ret;
+
+ new_bw_state = intel_atomic_get_bw_state(state);
+ if (IS_ERR(new_bw_state))
+ return PTR_ERR(new_bw_state);
+
+ /* firmware will calculate the qclck_gc_index, requirement is set to 0 */
+ new_pmdemand_state->params.qclk_gv_index = 0;
+ new_pmdemand_state->params.qclk_gv_bw = new_bw_state->qgv_point_peakbw;
+
+ new_dbuf_state = intel_atomic_get_dbuf_state(state);
+ if (IS_ERR(new_dbuf_state))
+ return PTR_ERR(new_dbuf_state);
+
+ new_pmdemand_state->params.active_pipes =
+ min_t(u8, hweight8(new_dbuf_state->active_pipes), 3);
+ new_pmdemand_state->params.active_dbufs =
+ min_t(u8, hweight8(new_dbuf_state->enabled_slices), 3);
+
+ new_cdclk_state = intel_atomic_get_cdclk_state(state);
+ if (IS_ERR(new_cdclk_state))
+ return PTR_ERR(new_cdclk_state);
+
+ new_pmdemand_state->params.voltage_index =
+ new_cdclk_state->actual.voltage_level;
+ new_pmdemand_state->params.cdclk_freq_mhz =
+ DIV_ROUND_UP(new_cdclk_state->actual.cdclk, 1000);
+
+ intel_pmdemand_update_max_ddiclk(i915, state, new_pmdemand_state);
+
+ intel_pmdemand_update_active_non_tc_phys(i915, state, new_pmdemand_state);
+
+ /*
+ * Setting scalers to max as it can not be calculated during flips and
+ * fastsets without taking global states locks.
+ */
+ new_pmdemand_state->params.scalers = 7;
+
+ /*
+ * If no modesetting is allowed, it doesn't allow adding additional
+ * crtcs to the state. So we cannot call serialize here.
+ */
+ if (!state->base.allow_modeset)
+ return 0;
+
+ return intel_atomic_serialize_global_state(&new_pmdemand_state->base);
+}
+
+static bool intel_pmdemand_check_prev_transaction(struct drm_i915_private *i915)
+{
+ return !(intel_de_wait_for_clear(i915,
+ XELPDP_INITIATE_PMDEMAND_REQUEST(1),
+ XELPDP_PMDEMAND_REQ_ENABLE, 10) ||
+ intel_de_wait_for_clear(i915,
+ GEN12_DCPR_STATUS_1,
+ XELPDP_PMDEMAND_INFLIGHT_STATUS, 10));
+}
+
+void
+intel_pmdemand_init_pmdemand_params(struct drm_i915_private *i915,
+ struct intel_pmdemand_state *pmdemand_state)
+{
+ u32 reg1, reg2;
+
+ if (DISPLAY_VER(i915) < 14)
+ return;
+
+ mutex_lock(&i915->display.pmdemand.lock);
+ if (drm_WARN_ON(&i915->drm,
+ !intel_pmdemand_check_prev_transaction(i915)))
+ goto unlock;
+
+ reg1 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
+
+ reg2 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
+
+ /* Set 1*/
+ pmdemand_state->params.qclk_gv_bw =
+ REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, reg1);
+ pmdemand_state->params.voltage_index =
+ REG_FIELD_GET(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, reg1);
+ pmdemand_state->params.qclk_gv_index =
+ REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, reg1);
+ pmdemand_state->params.active_pipes =
+ REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, reg1);
+ pmdemand_state->params.active_dbufs =
+ REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, reg1);
+ pmdemand_state->params.active_phys =
+ REG_FIELD_GET(XELPDP_PMDEMAND_PHYS_MASK, reg1);
+
+ /* Set 2*/
+ pmdemand_state->params.cdclk_freq_mhz =
+ REG_FIELD_GET(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, reg2);
+ pmdemand_state->params.ddiclk_max =
+ REG_FIELD_GET(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, reg2);
+ pmdemand_state->params.scalers =
+ REG_FIELD_GET(XELPDP_PMDEMAND_SCALERS_MASK, reg2);
+
+unlock:
+ memset(&pmdemand_state->params, 0, sizeof(pmdemand_state->params));
+ mutex_unlock(&i915->display.pmdemand.lock);
+}
+
+static bool intel_pmdemand_req_complete(struct drm_i915_private *i915)
+{
+ return !(intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
+ XELPDP_PMDEMAND_REQ_ENABLE);
+}
+
+static void intel_pmdemand_wait(struct drm_i915_private *i915)
+{
+ if (!wait_event_timeout(i915->display.pmdemand.waitqueue,
+ intel_pmdemand_req_complete(i915),
+ msecs_to_jiffies_timeout(10)))
+ drm_err(&i915->drm,
+ "timed out waiting for Punit PM Demand Response\n");
+}
+
+/* Required to be programmed during Display Init Sequences. */
+void intel_pmdemand_program_dbuf(struct drm_i915_private *i915,
+ u8 dbuf_slices)
+{
+ u32 dbufs = min_t(u32, hweight8(dbuf_slices), 3);
+
+ mutex_lock(&i915->display.pmdemand.lock);
+ if (drm_WARN_ON(&i915->drm,
+ !intel_pmdemand_check_prev_transaction(i915)))
+ goto unlock;
+
+ intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
+ XELPDP_PMDEMAND_DBUFS_MASK, XELPDP_PMDEMAND_DBUFS(dbufs));
+ intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
+ XELPDP_PMDEMAND_REQ_ENABLE);
+
+ intel_pmdemand_wait(i915);
+
+unlock:
+ mutex_unlock(&i915->display.pmdemand.lock);
+}
+
+static void
+intel_pmdemand_update_params(const struct intel_pmdemand_state *new,
+ const struct intel_pmdemand_state *old,
+ u32 *reg1, u32 *reg2, bool serialized)
+{
+ u32 plls, tmp, current_val;
+
+ /*
+ * The pmdemand parameter updates happens in two steps. Pre plane and
+ * post plane updates. During the pre plane, as DE might still be
+ * handling with some old operations, to avoid unexpected performance
+ * issues, program the pmdemand parameters with higher of old and new
+ * values. And then after once settled, use the new parameter values
+ * as part of the post plane update.
+ *
+ * If the pmdemand params update happens without modeset allowed, this
+ * means we can't serialize the updates. So that implies possbility of
+ * some parallel atomic commits affecting the pmdemand parameters. In
+ * that case, we need to consider the current values from the register
+ * as well. So in pre-plane case, we need to check the max of old, new
+ * and current register value if not serialized. In post plance update
+ * we need to consider max of new and current register value if not
+ * serialized
+ */
+
+ /* Set 1*/
+ current_val = REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, *reg1);
+ *reg1 &= ~XELPDP_PMDEMAND_QCLK_GV_BW_MASK;
+ tmp = old ? max(old->params.qclk_gv_bw, new->params.qclk_gv_bw) :
+ new->params.qclk_gv_bw;
+ if (!serialized)
+ tmp = max(tmp, current_val);
+ *reg1 |= XELPDP_PMDEMAND_QCLK_GV_BW(tmp);
+
+ current_val = REG_FIELD_GET(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, *reg1);
+ *reg1 &= ~XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK;
+ tmp = old ? max(old->params.voltage_index, new->params.voltage_index) :
+ new->params.voltage_index;
+ if (!serialized)
+ tmp = max(tmp, current_val);
+ *reg1 |= XELPDP_PMDEMAND_VOLTAGE_INDEX(tmp);
+
+ current_val = REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, *reg1);
+ *reg1 &= ~XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK;
+ tmp = old ? max(old->params.qclk_gv_index, new->params.qclk_gv_index) :
+ new->params.qclk_gv_index;
+ if (!serialized)
+ tmp = max(tmp, current_val);
+ *reg1 |= XELPDP_PMDEMAND_QCLK_GV_INDEX(tmp);
+
+ current_val = REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, *reg1);
+ *reg1 &= ~XELPDP_PMDEMAND_PIPES_MASK;
+ tmp = old ? max(old->params.active_pipes, new->params.active_pipes) :
+ new->params.active_pipes;
+ if (!serialized)
+ tmp = max(tmp, current_val);
+ *reg1 |= XELPDP_PMDEMAND_PIPES(tmp);
+
+ current_val = REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, *reg1);
+ *reg1 &= ~XELPDP_PMDEMAND_DBUFS_MASK;
+ tmp = old ? max(old->params.active_dbufs, new->params.active_dbufs) :
+ new->params.active_dbufs;
+ if (!serialized)
+ tmp = max(tmp, current_val);
+ *reg1 |= XELPDP_PMDEMAND_DBUFS(tmp);
+
+ current_val = REG_FIELD_GET(XELPDP_PMDEMAND_PHYS_MASK, *reg1);
+ *reg1 &= ~XELPDP_PMDEMAND_PHYS_MASK;
+ plls = old ? max(old->params.active_phys, new->params.active_phys) :
+ new->params.active_phys;
+ if (!serialized)
+ plls = max(plls, current_val);
+ plls = min_t(u32, plls, 7);
+ *reg1 |= XELPDP_PMDEMAND_PHYS(plls);
+
+ /* Set 2*/
+ current_val = REG_FIELD_GET(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, *reg2);
+ *reg2 &= ~XELPDP_PMDEMAND_CDCLK_FREQ_MASK;
+ tmp = old ? max(old->params.cdclk_freq_mhz,
+ new->params.cdclk_freq_mhz) :
+ new->params.cdclk_freq_mhz;
+ if (!serialized)
+ tmp = max(tmp, current_val);
+ *reg2 |= XELPDP_PMDEMAND_CDCLK_FREQ(tmp);
+
+ current_val = REG_FIELD_GET(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, *reg2);
+ *reg2 &= ~XELPDP_PMDEMAND_DDICLK_FREQ_MASK;
+ tmp = old ? max(old->params.ddiclk_max, new->params.ddiclk_max) :
+ new->params.ddiclk_max;
+ if (!serialized)
+ tmp = max(tmp, current_val);
+ *reg2 |= XELPDP_PMDEMAND_DDICLK_FREQ(tmp);
+
+ current_val = REG_FIELD_GET(XELPDP_PMDEMAND_SCALERS_MASK, *reg2);
+ *reg2 &= ~XELPDP_PMDEMAND_SCALERS_MASK;
+ tmp = old ? max(old->params.scalers, new->params.scalers) :
+ new->params.scalers;
+ if (!serialized)
+ tmp = max(tmp, current_val);
+ *reg2 |= XELPDP_PMDEMAND_SCALERS(tmp);
+
+ /*
+ * Active_PLLs starts with 1 because of CDCLK PLL.
+ * TODO: Missing to account genlock filter when it gets used.
+ */
+ plls = min_t(u32, plls + 1, 7);
+ *reg2 &= ~XELPDP_PMDEMAND_PLLS_MASK;
+ *reg2 |= XELPDP_PMDEMAND_PLLS(plls);
+}
+
+static void
+intel_pmdemand_program_params(struct drm_i915_private *i915,
+ const struct intel_pmdemand_state *new,
+ const struct intel_pmdemand_state *old,
+ bool serialized)
+{
+ bool changed = false;
+ u32 reg1, mod_reg1;
+ u32 reg2, mod_reg2;
+
+ mutex_lock(&i915->display.pmdemand.lock);
+ if (drm_WARN_ON(&i915->drm,
+ !intel_pmdemand_check_prev_transaction(i915)))
+ goto unlock;
+
+ reg1 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
+ mod_reg1 = reg1;
+
+ reg2 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
+ mod_reg2 = reg2;
+
+ intel_pmdemand_update_params(new, old, &mod_reg1, &mod_reg2,
+ serialized);
+
+ if (reg1 != mod_reg1) {
+ intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
+ mod_reg1);
+ changed = true;
+ }
+
+ if (reg2 != mod_reg2) {
+ intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
+ mod_reg2);
+ changed = true;
+ }
+
+ /* Initiate pm demand request only if register values are changed */
+ if (!changed)
+ goto unlock;
+
+ drm_dbg_kms(&i915->drm,
+ "initate pmdemand request values: (0x%x 0x%x)\n",
+ mod_reg1, mod_reg2);
+
+ intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
+ XELPDP_PMDEMAND_REQ_ENABLE);
+
+ intel_pmdemand_wait(i915);
+
+unlock:
+ mutex_unlock(&i915->display.pmdemand.lock);
+}
+
+static bool
+intel_pmdemand_state_changed(const struct intel_pmdemand_state *new,
+ const struct intel_pmdemand_state *old)
+{
+ return memcmp(&new->params, &old->params, sizeof(new->params)) != 0;
+}
+
+static bool
+intel_pmdemand_check_serialized(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+
+ for_each_intel_crtc(&i915->drm, crtc) {
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ if (!crtc_state)
+ return false;
+ }
+
+ return true;
+}
+
+void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ const struct intel_pmdemand_state *new_pmdemand_state =
+ intel_atomic_get_new_pmdemand_state(state);
+ const struct intel_pmdemand_state *old_pmdemand_state =
+ intel_atomic_get_old_pmdemand_state(state);
+ bool serialized;
+
+ if (DISPLAY_VER(i915) < 14)
+ return;
+
+ if (!new_pmdemand_state ||
+ !intel_pmdemand_state_changed(new_pmdemand_state,
+ old_pmdemand_state))
+ return;
+
+ serialized = intel_pmdemand_check_serialized(state);
+
+ WARN_ON(!new_pmdemand_state->base.changed);
+
+ intel_pmdemand_program_params(i915, new_pmdemand_state,
+ old_pmdemand_state, serialized);
+}
+
+void intel_pmdemand_post_plane_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ const struct intel_pmdemand_state *new_pmdemand_state =
+ intel_atomic_get_new_pmdemand_state(state);
+ const struct intel_pmdemand_state *old_pmdemand_state =
+ intel_atomic_get_old_pmdemand_state(state);
+ bool serialized;
+
+ if (DISPLAY_VER(i915) < 14)
+ return;
+
+ if (!new_pmdemand_state ||
+ !intel_pmdemand_state_changed(new_pmdemand_state,
+ old_pmdemand_state))
+ return;
+
+ serialized = intel_pmdemand_check_serialized(state);
+
+ WARN_ON(!new_pmdemand_state->base.changed);
+
+ intel_pmdemand_program_params(i915, new_pmdemand_state, NULL,
+ serialized);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.h b/drivers/gpu/drm/i915/display/intel_pmdemand.h
new file mode 100644
index 000000000000..9ff3eefb600a
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __INTEL_PMDEMAND_H__
+#define __INTEL_PMDEMAND_H__
+
+#include "intel_display_limits.h"
+#include "intel_global_state.h"
+
+struct drm_i915_private;
+struct intel_atomic_state;
+struct intel_crtc_state;
+struct intel_encoder;
+struct intel_plane_state;
+
+struct pmdemand_params {
+ u16 qclk_gv_bw;
+ u8 voltage_index;
+ u8 qclk_gv_index;
+ u8 active_pipes;
+ u8 active_dbufs;
+ /* Total number of non type C active phys from active_phys_mask */
+ u8 active_phys;
+ u16 cdclk_freq_mhz;
+ /* max from ddi_clocks[] */
+ u16 ddiclk_max;
+ u8 scalers;
+};
+
+struct intel_pmdemand_state {
+ struct intel_global_state base;
+
+ /* Maintain a persistent list of port clocks across all crtcs */
+ int ddi_clocks[I915_MAX_PIPES];
+
+ /* Maintain a persistent list of non type C phys mask */
+ u16 active_phys_mask;
+
+ /* Parameters to be configured in the pmdemand registers */
+ struct pmdemand_params params;
+};
+
+#define to_intel_pmdemand_state(x) container_of((x), \
+ struct intel_pmdemand_state, \
+ base)
+
+void intel_pmdemand_init_early(struct drm_i915_private *i915);
+int intel_pmdemand_init(struct drm_i915_private *i915);
+void intel_pmdemand_init_pmdemand_params(struct drm_i915_private *i915,
+ struct intel_pmdemand_state *pmdemand_state);
+void intel_pmdemand_init_active_phys_mask(struct drm_i915_private *i915,
+ struct intel_pmdemand_state *pmdemand_state,
+ u16 active_phys);
+void intel_pmdemand_update_port_clock(struct drm_i915_private *i915,
+ struct intel_pmdemand_state *pmdemand_state,
+ enum pipe pipe, int port_clock);
+void intel_pmdemand_update_phys_mask(struct drm_i915_private *i915,
+ struct intel_encoder *encoder,
+ struct intel_pmdemand_state *pmdemand_state,
+ bool clear_bit);
+void intel_pmdemand_program_dbuf(struct drm_i915_private *i915,
+ u8 dbuf_slices);
+void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state);
+void intel_pmdemand_post_plane_update(struct intel_atomic_state *state);
+int intel_pmdemand_atomic_check(struct intel_atomic_state *state);
+
+#endif /* __INTEL_PMDEMAND_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0523418129c5..6d34d9f59b1c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4418,8 +4418,10 @@
#define GEN8_DE_MISC_IMR _MMIO(0x44464)
#define GEN8_DE_MISC_IIR _MMIO(0x44468)
#define GEN8_DE_MISC_IER _MMIO(0x4446c)
-#define GEN8_DE_MISC_GSE (1 << 27)
-#define GEN8_DE_EDP_PSR (1 << 19)
+#define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27)
+#define GEN8_DE_MISC_GSE REG_BIT(27)
+#define GEN8_DE_EDP_PSR REG_BIT(19)
+#define XELPDP_PMDEMAND_RSP REG_BIT(3)
#define GEN8_PCU_ISR _MMIO(0x444e0)
#define GEN8_PCU_IMR _MMIO(0x444e4)
@@ -4504,6 +4506,33 @@
#define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1)
#define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0)
+#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword))
+#define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16)
+#define XELPDP_PMDEMAND_QCLK_GV_BW(x) REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, x)
+#define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12)
+#define XELPDP_PMDEMAND_VOLTAGE_INDEX(x) REG_FIELD_PREP(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, x)
+#define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8)
+#define XELPDP_PMDEMAND_QCLK_GV_INDEX(x) REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, x)
+#define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6)
+#define XELPDP_PMDEMAND_PIPES(x) REG_FIELD_PREP(XELPDP_PMDEMAND_PIPES_MASK, x)
+#define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4)
+#define XELPDP_PMDEMAND_DBUFS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK, x)
+#define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0)
+#define XELPDP_PMDEMAND_PHYS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_PHYS_MASK, x)
+
+#define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31)
+#define XELPDP_PMDEMAND_CDCLK_FREQ_MASK REG_GENMASK(30, 20)
+#define XELPDP_PMDEMAND_CDCLK_FREQ(x) REG_FIELD_PREP(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, x)
+#define XELPDP_PMDEMAND_DDICLK_FREQ_MASK REG_GENMASK(18, 8)
+#define XELPDP_PMDEMAND_DDICLK_FREQ(x) REG_FIELD_PREP(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, x)
+#define XELPDP_PMDEMAND_SCALERS_MASK REG_GENMASK(6, 4)
+#define XELPDP_PMDEMAND_SCALERS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_SCALERS_MASK, x)
+#define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0)
+#define XELPDP_PMDEMAND_PLLS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_PLLS_MASK, x)
+
+#define GEN12_DCPR_STATUS_1 _MMIO(0x46440)
+#define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26)
+
#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
/* Required on all Ironlake and Sandybridge according to the B-Spec. */
#define ILK_ELPIN_409_SELECT REG_BIT(25)
@@ -4663,6 +4692,9 @@
#define DCPR_SEND_RESP_IMM REG_BIT(25)
#define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
+#define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438)
+#define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19)
+
#define SKL_DFSM _MMIO(0x51000)
#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand
2023-06-06 9:35 [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand Vinod Govindapillai
` (6 preceding siblings ...)
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 7/7] drm/i915/mtl: Add support for PM DEMAND Vinod Govindapillai
@ 2023-06-06 10:32 ` Jani Nikula
2023-06-06 10:48 ` Govindapillai, Vinod
2023-06-06 14:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for mtl: add support for pmdemand (rev14) Patchwork
` (6 subsequent siblings)
14 siblings, 1 reply; 20+ messages in thread
From: Jani Nikula @ 2023-06-06 10:32 UTC (permalink / raw)
To: Vinod Govindapillai, intel-gfx
On Tue, 06 Jun 2023, Vinod Govindapillai <vinod.govindapillai@intel.com> wrote:
> SAGV configuration support for MTL
>
> v2: added one missing patch in the previous version
>
> v3: chekcpatch warning fixes
> update index handling for the icl/tgl QGV point handling
> program pmdemand code simplified
>
> v4: update to debufs and pipe values pmdemand regiters
> removed the macro usage in update_pmdemand_values
>
> V5: Addressing comments from Gustavo and Jani
> And some other fixes for issues from CI
>
> v6: Addressing some comments from Gustavo
> Updates to pmdemand state struct, active phys calculations
> Got rid of suppress warning patch from v5
>
> v7: Rebased and updates to max ddiclk and active phys calculations
>
> v8: updates to active phys calcuations
>
> v9: Address styling issues
>
> v10: Updates to phys calculation, pmdemand state initialization during
> HW readout / sanitization
>
> v11: Fix CI checkpatch warnings
>
> v12: Addressing comments
>
> v13: Updates based on imre's comments to handle non serialize cases,
> updates tp phys mask during sanitize calls after HW readout
>
> v14: check display version before accessig pmdemand functions
Okay, please stop sending new versions now.
We don't want to reach v14 on any patch series. It's a burden on the
developer, the reviewers, the CI, everyone. Please adjust towards
waiting for more review comments before sending another version, and
making the most of each version sent. There are several versions of the
series that didn't receive any feedback; why send another version?
In this case, AFAICT, some of the patches in the series have Reviewed-by
but haven't been changed in the last ten versions of the series. Why
haven't they been merged already? What's the point in resending them
over and over again?
BR,
Jani.
>
> Mika Kahola (1):
> drm/i915/mtl: Add support for PM DEMAND
>
> Vinod Govindapillai (6):
> drm/i915: fix the derating percentage for MTL
> drm/i915: update the QGV point frequency calculations
> drm/i915: store the peak bw per QGV point
> drm/i915: extract intel_bw_check_qgv_points()
> drm/i915: modify max_bw to return index to intel_bw_info
> drm/i915/mtl: find the best QGV point for the SAGV configuration
>
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_bw.c | 345 ++++++---
> drivers/gpu/drm/i915/display/intel_bw.h | 6 +
> drivers/gpu/drm/i915/display/intel_display.c | 14 +
> .../gpu/drm/i915/display/intel_display_core.h | 11 +
> .../drm/i915/display/intel_display_driver.c | 7 +
> .../gpu/drm/i915/display/intel_display_irq.c | 23 +-
> .../drm/i915/display/intel_display_power.c | 14 +-
> .../drm/i915/display/intel_modeset_setup.c | 36 +
> drivers/gpu/drm/i915/display/intel_pmdemand.c | 714 ++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_pmdemand.h | 69 ++
> drivers/gpu/drm/i915/i915_reg.h | 36 +-
> 12 files changed, 1153 insertions(+), 123 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand
2023-06-06 10:32 ` [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand Jani Nikula
@ 2023-06-06 10:48 ` Govindapillai, Vinod
0 siblings, 0 replies; 20+ messages in thread
From: Govindapillai, Vinod @ 2023-06-06 10:48 UTC (permalink / raw)
To: intel-gfx, jani.nikula
On Tue, 2023-06-06 at 13:32 +0300, Jani Nikula wrote:
> On Tue, 06 Jun 2023, Vinod Govindapillai <vinod.govindapillai@intel.com> wrote:
> > SAGV configuration support for MTL
> >
> > v2: added one missing patch in the previous version
> >
> > v3: chekcpatch warning fixes
> > update index handling for the icl/tgl QGV point handling
> > program pmdemand code simplified
> >
> > v4: update to debufs and pipe values pmdemand regiters
> > removed the macro usage in update_pmdemand_values
> >
> > V5: Addressing comments from Gustavo and Jani
> > And some other fixes for issues from CI
> >
> > v6: Addressing some comments from Gustavo
> > Updates to pmdemand state struct, active phys calculations
> > Got rid of suppress warning patch from v5
> >
> > v7: Rebased and updates to max ddiclk and active phys calculations
> >
> > v8: updates to active phys calcuations
> >
> > v9: Address styling issues
> >
> > v10: Updates to phys calculation, pmdemand state initialization during
> > HW readout / sanitization
> >
> > v11: Fix CI checkpatch warnings
> >
> > v12: Addressing comments
> >
> > v13: Updates based on imre's comments to handle non serialize cases,
> > updates tp phys mask during sanitize calls after HW readout
> >
> > v14: check display version before accessig pmdemand functions
>
> Okay, please stop sending new versions now.
>
> We don't want to reach v14 on any patch series. It's a burden on the
> developer, the reviewers, the CI, everyone. Please adjust towards
> waiting for more review comments before sending another version, and
> making the most of each version sent. There are several versions of the
> series that didn't receive any feedback; why send another version?
>
> In this case, AFAICT, some of the patches in the series have Reviewed-by
> but haven't been changed in the last ten versions of the series. Why
> haven't they been merged already? What's the point in resending them
> over and over again?
Yeah! This Pmdemand stuffs has been a nightmare! Apparently it looks like the original version
lacked many functionalities and had been many review comments! I overlooked some fixes which i only
noticed after i sent the patch. That might be the reason why some patch revisions are sent without
any review comments.
Now Imre is actively reviewing the pmdemand patch. Hopefully could be closed soon
Yes. The other patches in the series could be merged. I dont have the commit rights.
It would be nice if someone can merge those
BR
Vinod
>
>
> BR,
> Jani.
>
>
> >
> > Mika Kahola (1):
> > drm/i915/mtl: Add support for PM DEMAND
> >
> > Vinod Govindapillai (6):
> > drm/i915: fix the derating percentage for MTL
> > drm/i915: update the QGV point frequency calculations
> > drm/i915: store the peak bw per QGV point
> > drm/i915: extract intel_bw_check_qgv_points()
> > drm/i915: modify max_bw to return index to intel_bw_info
> > drm/i915/mtl: find the best QGV point for the SAGV configuration
> >
> > drivers/gpu/drm/i915/Makefile | 1 +
> > drivers/gpu/drm/i915/display/intel_bw.c | 345 ++++++---
> > drivers/gpu/drm/i915/display/intel_bw.h | 6 +
> > drivers/gpu/drm/i915/display/intel_display.c | 14 +
> > .../gpu/drm/i915/display/intel_display_core.h | 11 +
> > .../drm/i915/display/intel_display_driver.c | 7 +
> > .../gpu/drm/i915/display/intel_display_irq.c | 23 +-
> > .../drm/i915/display/intel_display_power.c | 14 +-
> > .../drm/i915/display/intel_modeset_setup.c | 36 +
> > drivers/gpu/drm/i915/display/intel_pmdemand.c | 714 ++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_pmdemand.h | 69 ++
> > drivers/gpu/drm/i915/i915_reg.h | 36 +-
> > 12 files changed, 1153 insertions(+), 123 deletions(-)
> > create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
> > create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH v14 7/7] drm/i915/mtl: Add support for PM DEMAND
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 7/7] drm/i915/mtl: Add support for PM DEMAND Vinod Govindapillai
@ 2023-06-06 13:50 ` Imre Deak
2023-06-06 20:10 ` [Intel-gfx] [PATCH v15 " Vinod Govindapillai
1 sibling, 0 replies; 20+ messages in thread
From: Imre Deak @ 2023-06-06 13:50 UTC (permalink / raw)
To: Vinod Govindapillai; +Cc: intel-gfx
On Tue, Jun 06, 2023 at 12:35:09PM +0300, Vinod Govindapillai wrote:
> From: Mika Kahola <mika.kahola@intel.com>
>
> MTL introduces a new way to instruct the PUnit with
> power and bandwidth requirements of DE. Add the functionality
> to program the registers and handle waits using interrupts.
> The current wait time for timeouts is programmed for 10 msecs to
> factor in the worst case scenarios. Changes made to use REG_BIT
> for a register that we touched(GEN8_DE_MISC_IER _MMIO).
>
> Wa_14016740474 is added which applies to Xe_LPD+ display
>
> v2: checkpatch warning fixes, simplify program pmdemand part
>
> v3: update to dbufs and pipes values to pmdemand register(stan)
> Removed the macro usage in update_pmdemand_values()
>
> v4: move the pmdemand_pre_plane_update before cdclk update
> pmdemand_needs_update included cdclk params comparisons
> pmdemand_state NULL check (Gustavo)
> pmdemand.o in sorted order in the makefile (Jani)
> update pmdemand misc irq handler loop (Gustavo)
> active phys bitmask and programming correction (Gustavo)
>
> v5: simplify pmdemand_state structure
> simplify methods to find active phys and max port clock
> Timeout in case of previou pmdemand task pending (Gustavo)
>
> v6: rebasing
> updates to max_ddiclk calculations (Gustavo)
> updates to active_phys count method (Gustavo)
>
> v7: use two separate loop to iterate throug old and new
> crtc states to calculate the active phys (Gustavo)
>
> v8: use uniform function names (Gustavo)
>
> v9: For phys change iterate through connectors (Imre)
> Look for change in phys for pmdemand update (Gustavo, Imre)
> Some more stlying changes (Imre)
> Update pmdemand state during HW readout/sanitize (Imre)
>
> v10: Fix CI checkpatch warnings
>
> v11: use correct pmdemand object pointer during hw readout,
> simplify the check for phys need update (Gustavo)
>
> v12: Handle possible non serialize cases (Imre)
> Initialise also pmdemand params HW readout (Imre)
> Update active phys mask during sanitize calls (Imre)
> Check TC/encoder changes to limit connector update (Imre)
>
> v13: Check display version before accessing pmdemand functions
>
> Bspec: 66451, 64636, 64602, 64603
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Acked-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 14 +
> .../gpu/drm/i915/display/intel_display_core.h | 9 +
> .../drm/i915/display/intel_display_driver.c | 7 +
> .../gpu/drm/i915/display/intel_display_irq.c | 23 +-
> .../drm/i915/display/intel_display_power.c | 14 +-
> .../drm/i915/display/intel_modeset_setup.c | 36 +
> drivers/gpu/drm/i915/display/intel_pmdemand.c | 714 ++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_pmdemand.h | 69 ++
> drivers/gpu/drm/i915/i915_reg.h | 36 +-
> 10 files changed, 917 insertions(+), 6 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 1c9ed4c52760..2cd8de174bf6 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -269,6 +269,7 @@ i915-y += \
> display/intel_pch_display.o \
> display/intel_pch_refclk.o \
> display/intel_plane_initial.o \
> + display/intel_pmdemand.o \
> display/intel_psr.o \
> display/intel_quirks.o \
> display/intel_sprite.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f51a55f4e9d0..5cbf5eae2414 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -99,6 +99,7 @@
> #include "intel_pcode.h"
> #include "intel_pipe_crc.h"
> #include "intel_plane_initial.h"
> +#include "intel_pmdemand.h"
> #include "intel_pps.h"
> #include "intel_psr.h"
> #include "intel_sdvo.h"
> @@ -6352,6 +6353,10 @@ int intel_atomic_check(struct drm_device *dev,
> return ret;
> }
>
> + ret = intel_pmdemand_atomic_check(state);
> + if (ret)
> + goto fail;
> +
> ret = intel_atomic_check_crtcs(state);
> if (ret)
> goto fail;
> @@ -6997,6 +7002,14 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
> crtc->config = new_crtc_state;
>
> + /*
> + * In XE_LPD+ Pmdemand combines many parameters such as voltage index,
> + * plls, cdclk frequency, QGV point selection parameter etc. Voltage
> + * index, cdclk/ddiclk frequencies are supposed to be configured before
> + * the cdclk config is set.
> + */
> + intel_pmdemand_pre_plane_update(state);
> +
> if (state->modeset) {
> drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
>
> @@ -7116,6 +7129,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> intel_verify_planes(state);
>
> intel_sagv_post_plane_update(state);
> + intel_pmdemand_post_plane_update(state);
>
> drm_atomic_helper_commit_hw_done(&state->base);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index dd8e08c8598f..8d2243c71dd8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -345,6 +345,15 @@ struct intel_display {
> struct intel_global_obj obj;
> } dbuf;
>
> + struct {
> + wait_queue_head_t waitqueue;
> +
> + /* mutex to protect pmdemand programming sequence */
> + struct mutex lock;
> +
> + struct intel_global_obj obj;
> + } pmdemand;
> +
> struct {
> /*
> * dkl.phy_lock protects against concurrent access of the
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index 60ce10fc7205..dc8de861339d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -47,6 +47,7 @@
> #include "intel_opregion.h"
> #include "intel_overlay.h"
> #include "intel_plane_initial.h"
> +#include "intel_pmdemand.h"
> #include "intel_pps.h"
> #include "intel_quirks.h"
> #include "intel_vga.h"
> @@ -211,6 +212,8 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
> if (ret < 0)
> goto cleanup_vga;
>
> + intel_pmdemand_init_early(i915);
> +
> intel_power_domains_init_hw(i915, false);
>
> if (!HAS_DISPLAY(i915))
> @@ -240,6 +243,10 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
> if (ret)
> goto cleanup_vga_client_pw_domain_dmc;
>
> + ret = intel_pmdemand_init(i915);
> + if (ret)
> + goto cleanup_vga_client_pw_domain_dmc;
> +
> init_llist_head(&i915->display.atomic_helper.free_list);
> INIT_WORK(&i915->display.atomic_helper.free_work,
> intel_atomic_helper_free_state_worker);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 3b2a287d2041..0b3739310f81 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -18,6 +18,7 @@
> #include "intel_fifo_underrun.h"
> #include "intel_gmbus.h"
> #include "intel_hotplug_irq.h"
> +#include "intel_pmdemand.h"
> #include "intel_psr.h"
> #include "intel_psr_regs.h"
>
> @@ -827,12 +828,27 @@ static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
> return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> }
>
> +static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv)
> +{
> + wake_up_all(&dev_priv->display.pmdemand.waitqueue);
> +}
> +
> static void
> gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
> {
> bool found = false;
>
> - if (iir & GEN8_DE_MISC_GSE) {
> + if (DISPLAY_VER(dev_priv) >= 14) {
> + if (iir & (XELPDP_PMDEMAND_RSP |
> + XELPDP_PMDEMAND_RSPTOUT_ERR)) {
> + if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR)
> + drm_dbg(&dev_priv->drm,
> + "Error waiting for Punit PM Demand Response\n");
> +
> + intel_pmdemand_irq_handler(dev_priv);
> + found = true;
> + }
> + } else if (iir & GEN8_DE_MISC_GSE) {
> intel_opregion_asle_intr(dev_priv);
> found = true;
> }
> @@ -1576,7 +1592,10 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> de_port_masked |= BXT_DE_PORT_GMBUS;
>
> - if (DISPLAY_VER(dev_priv) >= 11) {
> + if (DISPLAY_VER(dev_priv) >= 14) {
> + de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR |
> + XELPDP_PMDEMAND_RSP;
> + } else if (DISPLAY_VER(dev_priv) >= 11) {
> enum port port;
>
> if (intel_bios_is_dsi_present(dev_priv, &port))
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 2f4f00ae2f57..db5437043904 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -20,6 +20,7 @@
> #include "intel_mchbar_regs.h"
> #include "intel_pch_refclk.h"
> #include "intel_pcode.h"
> +#include "intel_pmdemand.h"
> #include "intel_pps_regs.h"
> #include "intel_snps_phy.h"
> #include "skl_watermark.h"
> @@ -1082,20 +1083,29 @@ void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
>
> static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
> {
> + u8 slices_mask;
> +
> dev_priv->display.dbuf.enabled_slices =
> intel_enabled_dbuf_slices_mask(dev_priv);
>
> + slices_mask = BIT(DBUF_S1) | dev_priv->display.dbuf.enabled_slices;
> +
> + if (DISPLAY_VER(dev_priv) >= 14)
> + intel_pmdemand_program_dbuf(dev_priv, slices_mask);
> +
> /*
> * Just power up at least 1 slice, we will
> * figure out later which slices we have and what we need.
> */
> - gen9_dbuf_slices_update(dev_priv, BIT(DBUF_S1) |
> - dev_priv->display.dbuf.enabled_slices);
> + gen9_dbuf_slices_update(dev_priv, slices_mask);
> }
>
> static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
> {
> gen9_dbuf_slices_update(dev_priv, 0);
> +
> + if (DISPLAY_VER(dev_priv) >= 14)
> + intel_pmdemand_program_dbuf(dev_priv, 0);
> }
>
> static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index 5ff99ca7f1de..f6b4923de70a 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -26,6 +26,7 @@
> #include "intel_fifo_underrun.h"
> #include "intel_modeset_setup.h"
> #include "intel_pch_display.h"
> +#include "intel_pmdemand.h"
> #include "intel_tc.h"
> #include "intel_vblank.h"
> #include "intel_wm.h"
> @@ -115,6 +116,8 @@ static void set_encoder_for_connector(struct intel_connector *connector,
> static void reset_encoder_connector_state(struct intel_encoder *encoder)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_pmdemand_state *pmdemand_state =
> + to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
> struct intel_connector *connector;
> struct drm_connector_list_iter conn_iter;
>
> @@ -123,6 +126,10 @@ static void reset_encoder_connector_state(struct intel_encoder *encoder)
> if (connector->base.encoder != &encoder->base)
> continue;
>
> + /* Clear the corresponding bit in pmdemand active phys mask */
> + intel_pmdemand_update_phys_mask(i915, encoder,
> + pmdemand_state, true);
Imo, would be clearer to pass a set_bit instead of a clear_bit parameter.
> +
> set_encoder_for_connector(connector, NULL);
>
> connector->base.dpms = DRM_MODE_DPMS_OFF;
> @@ -151,6 +158,8 @@ static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
> to_intel_cdclk_state(i915->display.cdclk.obj.state);
> struct intel_dbuf_state *dbuf_state =
> to_intel_dbuf_state(i915->display.dbuf.obj.state);
> + struct intel_pmdemand_state *pmdemand_state =
> + to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
> struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
> enum pipe pipe = crtc->pipe;
> @@ -174,6 +183,8 @@ static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
>
> bw_state->data_rate[pipe] = 0;
> bw_state->num_active_planes[pipe] = 0;
> +
> + intel_pmdemand_update_port_clock(i915, pmdemand_state, pipe, 0);
> }
>
> /*
> @@ -552,6 +563,8 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
> struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> struct intel_crtc_state *crtc_state = crtc ?
> to_intel_crtc_state(crtc->base.state) : NULL;
> + struct intel_pmdemand_state *pmdemand_state =
> + to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
>
> /*
> * We need to check both for a crtc link (meaning that the encoder is
> @@ -575,6 +588,10 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
> encoder->base.base.id,
> encoder->base.name);
>
> + /* Clear the corresponding bit in pmdemand active phys mask */
> + intel_pmdemand_update_phys_mask(i915, encoder,
> + pmdemand_state, true);
> +
> /*
> * Connector is active, but has no active pipe. This is fallout
> * from our resume register restoring. Disable the encoder
> @@ -661,6 +678,9 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
> to_intel_cdclk_state(i915->display.cdclk.obj.state);
> struct intel_dbuf_state *dbuf_state =
> to_intel_dbuf_state(i915->display.dbuf.obj.state);
> + struct intel_pmdemand_state *pmdemand_state =
> + to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
> + u16 active_phys = 0;
> enum pipe pipe;
> struct intel_crtc *crtc;
> struct intel_encoder *encoder;
> @@ -742,6 +762,8 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
>
> drm_connector_list_iter_begin(&i915->drm, &conn_iter);
> for_each_intel_connector_iter(connector, &conn_iter) {
> + enum phy phy;
> +
> if (connector->get_hw_state(connector)) {
> struct intel_crtc_state *crtc_state;
> struct intel_crtc *crtc;
> @@ -764,6 +786,10 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
> drm_connector_mask(&connector->base);
> crtc_state->uapi.encoder_mask |=
> drm_encoder_mask(&encoder->base);
> +
> + phy = intel_port_to_phy(i915, encoder->port);
> + if (!intel_phy_is_tc(i915, phy))
> + active_phys |= BIT(phy);
> }
> } else {
> connector->base.dpms = DRM_MODE_DPMS_OFF;
The above could just call intel_pmdemand_update_phys_mask(...,
true/false) as needed, instead of adding
intel_pmdemand_init_active_phys_mask() used later.
> @@ -776,6 +802,9 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
> }
> drm_connector_list_iter_end(&conn_iter);
>
> + intel_pmdemand_init_active_phys_mask(i915, pmdemand_state,
> + active_phys);
> +
> for_each_intel_crtc(&i915->drm, crtc) {
> struct intel_bw_state *bw_state =
> to_intel_bw_state(i915->display.bw.obj.state);
> @@ -840,9 +869,16 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
> cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
> cdclk_state->min_voltage_level[crtc->pipe] =
> crtc_state->min_voltage_level;
> + pmdemand_state->ddi_clocks[crtc->pipe] =
> + crtc_state->port_clock;
> +
> + intel_pmdemand_update_port_clock(i915, pmdemand_state, pipe,
> + crtc_state->port_clock);
>
> intel_bw_crtc_update(bw_state, crtc_state);
> }
> +
> + intel_pmdemand_init_pmdemand_params(i915, pmdemand_state);
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> new file mode 100644
> index 000000000000..3ee943810300
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> @@ -0,0 +1,714 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#include <linux/bitops.h>
> +
> +#include "i915_drv.h"
> +#include "i915_reg.h"
> +#include "intel_atomic.h"
> +#include "intel_bw.h"
> +#include "intel_cdclk.h"
> +#include "intel_de.h"
> +#include "intel_display_trace.h"
> +#include "intel_pmdemand.h"
> +#include "skl_watermark.h"
> +
> +static struct intel_global_state *
> +intel_pmdemand_duplicate_state(struct intel_global_obj *obj)
> +{
> + struct intel_pmdemand_state *pmdemand_state;
> +
> + pmdemand_state = kmemdup(obj->state, sizeof(*pmdemand_state), GFP_KERNEL);
> + if (!pmdemand_state)
> + return NULL;
> +
> + return &pmdemand_state->base;
> +}
> +
> +static void intel_pmdemand_destroy_state(struct intel_global_obj *obj,
> + struct intel_global_state *state)
> +{
> + kfree(state);
> +}
> +
> +static const struct intel_global_state_funcs intel_pmdemand_funcs = {
> + .atomic_duplicate_state = intel_pmdemand_duplicate_state,
> + .atomic_destroy_state = intel_pmdemand_destroy_state,
> +};
> +
> +static struct intel_pmdemand_state *
> +intel_atomic_get_pmdemand_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_global_state *pmdemand_state =
> + intel_atomic_get_global_obj_state(state,
> + &i915->display.pmdemand.obj);
> +
> + if (IS_ERR(pmdemand_state))
> + return ERR_CAST(pmdemand_state);
> +
> + return to_intel_pmdemand_state(pmdemand_state);
> +}
> +
> +static struct intel_pmdemand_state *
> +intel_atomic_get_old_pmdemand_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_global_state *pmdemand_state =
> + intel_atomic_get_old_global_obj_state(state,
> + &i915->display.pmdemand.obj);
> +
> + if (!pmdemand_state)
> + return NULL;
> +
> + return to_intel_pmdemand_state(pmdemand_state);
> +}
> +
> +static struct intel_pmdemand_state *
> +intel_atomic_get_new_pmdemand_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_global_state *pmdemand_state =
> + intel_atomic_get_new_global_obj_state(state,
> + &i915->display.pmdemand.obj);
> +
> + if (!pmdemand_state)
> + return NULL;
> +
> + return to_intel_pmdemand_state(pmdemand_state);
> +}
> +
> +int intel_pmdemand_init(struct drm_i915_private *i915)
> +{
> + struct intel_pmdemand_state *pmdemand_state;
> +
> + pmdemand_state = kzalloc(sizeof(*pmdemand_state), GFP_KERNEL);
> + if (!pmdemand_state)
> + return -ENOMEM;
> +
> + intel_atomic_global_obj_init(i915, &i915->display.pmdemand.obj,
> + &pmdemand_state->base,
> + &intel_pmdemand_funcs);
> +
> + if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> + /* Wa_14016740474 */
> + intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
> +
> + return 0;
> +}
> +
> +void intel_pmdemand_init_early(struct drm_i915_private *i915)
> +{
> + mutex_init(&i915->display.pmdemand.lock);
> + init_waitqueue_head(&i915->display.pmdemand.waitqueue);
> +}
> +
> +void
> +intel_pmdemand_init_active_phys_mask(struct drm_i915_private *i915,
> + struct intel_pmdemand_state *pmdemand_state,
> + u16 active_phys)
> +{
> + if (DISPLAY_VER(i915) < 14)
> + return;
> +
> + pmdemand_state->active_phys_mask = active_phys;
> +}
> +
> +void
> +intel_pmdemand_update_phys_mask(struct drm_i915_private *i915,
> + struct intel_encoder *encoder,
> + struct intel_pmdemand_state *pmdemand_state,
> + bool clear_bit)
> +{
> + enum phy phy;
> +
> + if (DISPLAY_VER(i915) < 14)
> + return;
> +
> + if (!encoder)
> + return;
> +
> + phy = intel_port_to_phy(i915, encoder->port);
> + if (intel_phy_is_tc(i915, phy))
> + return;
> +
> + if (clear_bit)
> + pmdemand_state->active_phys_mask &= ~BIT(phy);
> + else
> + pmdemand_state->active_phys_mask |= BIT(phy);
> +}
> +
> +void
> +intel_pmdemand_update_port_clock(struct drm_i915_private *i915,
> + struct intel_pmdemand_state *pmdemand_state,
> + enum pipe pipe, int port_clock)
> +{
> + if (DISPLAY_VER(i915) < 14)
> + return;
> +
> + pmdemand_state->ddi_clocks[pipe] = port_clock;
> +}
> +
> +static void
> +intel_pmdemand_update_max_ddiclk(struct drm_i915_private *i915,
> + struct intel_atomic_state *state,
> + struct intel_pmdemand_state *pmdemand_state)
> +{
> + int max_ddiclk = 0;
> + struct intel_crtc *crtc;
> + int i;
> + const struct intel_crtc_state *new_crtc_state;
> +
> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
> + intel_pmdemand_update_port_clock(i915, pmdemand_state,
> + crtc->pipe,
> + new_crtc_state->port_clock);
> +
> + for (i = 0; i < ARRAY_SIZE(pmdemand_state->ddi_clocks); i++)
> + max_ddiclk = max(pmdemand_state->ddi_clocks[i], max_ddiclk);
> +
> + pmdemand_state->params.ddiclk_max = DIV_ROUND_UP(max_ddiclk, 1000);
> +}
> +
> +static void
> +intel_pmdemand_update_connector_phys(struct drm_i915_private *i915,
> + struct intel_atomic_state *state,
> + struct drm_connector_state *conn_state,
> + bool for_old_state,
> + struct intel_pmdemand_state *pmdemand_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
> + struct intel_encoder *encoder = to_intel_encoder(conn_state->best_encoder);
> + struct intel_crtc_state *crtc_state;
> +
> + if (!crtc)
> + return;
> +
> + if (for_old_state)
> + crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
> + else
> + crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> +
> + if (!crtc_state->hw.active)
> + return;
> +
> + intel_pmdemand_update_phys_mask(i915, encoder, pmdemand_state,
> + for_old_state);
> +}
> +
> +static void
> +intel_pmdemand_update_active_non_tc_phys(struct drm_i915_private *i915,
> + struct intel_atomic_state *state,
> + struct intel_pmdemand_state *pmdemand_state)
> +{
> + struct drm_connector *connector;
> + int i;
> + struct drm_connector_state *old_conn_state, *new_conn_state;
> +
> + for_each_oldnew_connector_in_state(&state->base, connector,
> + old_conn_state, new_conn_state, i) {
> + if (!intel_connector_needs_modeset(state, connector))
> + continue;
> +
> + /* First clear the active phys in the old connector state */
> + intel_pmdemand_update_connector_phys(i915, state,
> + old_conn_state, true,
> + pmdemand_state);
> +
> + /* Then set the active phys in new connector state */
> + intel_pmdemand_update_connector_phys(i915, state,
> + new_conn_state, false,
> + pmdemand_state);
> + }
> +
> + pmdemand_state->params.active_phys =
> + hweight16(pmdemand_state->active_phys_mask);
> +}
> +
> +static bool
> +intel_pmdemand_encoder_has_tc_phy(struct drm_i915_private *i915,
> + struct intel_encoder *encoder)
> +{
> + enum phy phy;
> +
> + if (!encoder)
> + return false;
> +
> + phy = intel_port_to_phy(i915, encoder->port);
> + if (intel_phy_is_tc(i915, phy))
> + return true;
> +
> + return false;
> +}
> +
> +static bool
> +intel_pmdemand_connector_needs_update(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct drm_connector *connector;
> + struct drm_connector_state *new_conn_state, *old_conn_state;
> + int i;
> +
> + for_each_oldnew_connector_in_state(&state->base, connector,
> + old_conn_state, new_conn_state, i) {
> + struct intel_encoder *old_encoder =
> + to_intel_encoder(old_conn_state->best_encoder);
> + struct intel_encoder *new_encoder =
> + to_intel_encoder(new_conn_state->best_encoder);
> +
> + if (!intel_connector_needs_modeset(state, connector))
> + continue;
> +
> + if (old_encoder == new_encoder ||
> + (intel_pmdemand_encoder_has_tc_phy(i915, old_encoder) &&
> + intel_pmdemand_encoder_has_tc_phy(i915, new_encoder)))
> + continue;
> +
> + return true;
> + }
> +
> + return false;
> +}
> +
> +static bool intel_pmdemand_needs_update(struct intel_atomic_state *state)
> +{
> + struct intel_crtc *crtc;
> + int i;
> + const struct intel_bw_state *new_bw_state, *old_bw_state;
> + const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state;
> + const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> + const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
> +
> + new_bw_state = intel_atomic_get_new_bw_state(state);
> + old_bw_state = intel_atomic_get_old_bw_state(state);
> + if (new_bw_state && new_bw_state->qgv_point_peakbw !=
> + old_bw_state->qgv_point_peakbw)
> + return true;
> +
> + new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
> + old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
> + if (new_dbuf_state &&
> + (new_dbuf_state->active_pipes !=
> + old_dbuf_state->active_pipes ||
> + new_dbuf_state->enabled_slices !=
> + old_dbuf_state->enabled_slices))
> + return true;
> +
> + new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
> + old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
> + if (new_cdclk_state &&
> + (new_cdclk_state->actual.cdclk !=
> + old_cdclk_state->actual.cdclk ||
> + new_cdclk_state->actual.voltage_level !=
> + old_cdclk_state->actual.voltage_level))
> + return true;
> +
> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> + new_crtc_state, i)
> + if (new_crtc_state->port_clock != old_crtc_state->port_clock)
> + return true;
> +
> + if (intel_pmdemand_connector_needs_update(state))
> + return true;
> +
> + return false;
> +}
> +
> +int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + const struct intel_bw_state *new_bw_state;
> + const struct intel_cdclk_state *new_cdclk_state;
> + const struct intel_dbuf_state *new_dbuf_state;
> + struct intel_pmdemand_state *new_pmdemand_state;
> + int ret;
> +
> + if (DISPLAY_VER(i915) < 14)
> + return 0;
> +
> + if (!intel_pmdemand_needs_update(state))
> + return 0;
> +
> + new_pmdemand_state = intel_atomic_get_pmdemand_state(state);
> + if (IS_ERR(new_pmdemand_state))
> + return PTR_ERR(new_pmdemand_state);
> +
> + ret = intel_atomic_lock_global_state(&new_pmdemand_state->base);
> + if (ret)
> + return ret;
> +
> + new_bw_state = intel_atomic_get_bw_state(state);
> + if (IS_ERR(new_bw_state))
> + return PTR_ERR(new_bw_state);
> +
> + /* firmware will calculate the qclck_gc_index, requirement is set to 0 */
> + new_pmdemand_state->params.qclk_gv_index = 0;
> + new_pmdemand_state->params.qclk_gv_bw = new_bw_state->qgv_point_peakbw;
> +
> + new_dbuf_state = intel_atomic_get_dbuf_state(state);
> + if (IS_ERR(new_dbuf_state))
> + return PTR_ERR(new_dbuf_state);
> +
> + new_pmdemand_state->params.active_pipes =
> + min_t(u8, hweight8(new_dbuf_state->active_pipes), 3);
> + new_pmdemand_state->params.active_dbufs =
> + min_t(u8, hweight8(new_dbuf_state->enabled_slices), 3);
> +
> + new_cdclk_state = intel_atomic_get_cdclk_state(state);
> + if (IS_ERR(new_cdclk_state))
> + return PTR_ERR(new_cdclk_state);
> +
> + new_pmdemand_state->params.voltage_index =
> + new_cdclk_state->actual.voltage_level;
> + new_pmdemand_state->params.cdclk_freq_mhz =
> + DIV_ROUND_UP(new_cdclk_state->actual.cdclk, 1000);
> +
> + intel_pmdemand_update_max_ddiclk(i915, state, new_pmdemand_state);
> +
> + intel_pmdemand_update_active_non_tc_phys(i915, state, new_pmdemand_state);
> +
> + /*
> + * Setting scalers to max as it can not be calculated during flips and
> + * fastsets without taking global states locks.
> + */
> + new_pmdemand_state->params.scalers = 7;
> +
> + /*
> + * If no modesetting is allowed, it doesn't allow adding additional
> + * crtcs to the state. So we cannot call serialize here.
> + */
> + if (!state->base.allow_modeset)
> + return 0;
> +
> + return intel_atomic_serialize_global_state(&new_pmdemand_state->base);
Either locking or serializing the state is enough, so doing either of
them here at a single place would be clearer.
> +}
> +
> +static bool intel_pmdemand_check_prev_transaction(struct drm_i915_private *i915)
> +{
> + return !(intel_de_wait_for_clear(i915,
> + XELPDP_INITIATE_PMDEMAND_REQUEST(1),
> + XELPDP_PMDEMAND_REQ_ENABLE, 10) ||
> + intel_de_wait_for_clear(i915,
> + GEN12_DCPR_STATUS_1,
> + XELPDP_PMDEMAND_INFLIGHT_STATUS, 10));
> +}
> +
> +void
> +intel_pmdemand_init_pmdemand_params(struct drm_i915_private *i915,
> + struct intel_pmdemand_state *pmdemand_state)
> +{
> + u32 reg1, reg2;
> +
> + if (DISPLAY_VER(i915) < 14)
> + return;
> +
> + mutex_lock(&i915->display.pmdemand.lock);
> + if (drm_WARN_ON(&i915->drm,
> + !intel_pmdemand_check_prev_transaction(i915)))
> + goto unlock;
> +
> + reg1 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
> +
> + reg2 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
> +
> + /* Set 1*/
> + pmdemand_state->params.qclk_gv_bw =
> + REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, reg1);
> + pmdemand_state->params.voltage_index =
> + REG_FIELD_GET(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, reg1);
> + pmdemand_state->params.qclk_gv_index =
> + REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, reg1);
> + pmdemand_state->params.active_pipes =
> + REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, reg1);
> + pmdemand_state->params.active_dbufs =
> + REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, reg1);
> + pmdemand_state->params.active_phys =
> + REG_FIELD_GET(XELPDP_PMDEMAND_PHYS_MASK, reg1);
> +
> + /* Set 2*/
> + pmdemand_state->params.cdclk_freq_mhz =
> + REG_FIELD_GET(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, reg2);
> + pmdemand_state->params.ddiclk_max =
> + REG_FIELD_GET(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, reg2);
> + pmdemand_state->params.scalers =
> + REG_FIELD_GET(XELPDP_PMDEMAND_SCALERS_MASK, reg2);
> +
> +unlock:
> + memset(&pmdemand_state->params, 0, sizeof(pmdemand_state->params));
The above is misplaced.
> + mutex_unlock(&i915->display.pmdemand.lock);
> +}
> +
> +static bool intel_pmdemand_req_complete(struct drm_i915_private *i915)
> +{
> + return !(intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
> + XELPDP_PMDEMAND_REQ_ENABLE);
> +}
> +
> +static void intel_pmdemand_wait(struct drm_i915_private *i915)
> +{
> + if (!wait_event_timeout(i915->display.pmdemand.waitqueue,
> + intel_pmdemand_req_complete(i915),
> + msecs_to_jiffies_timeout(10)))
> + drm_err(&i915->drm,
> + "timed out waiting for Punit PM Demand Response\n");
> +}
> +
> +/* Required to be programmed during Display Init Sequences. */
> +void intel_pmdemand_program_dbuf(struct drm_i915_private *i915,
> + u8 dbuf_slices)
> +{
> + u32 dbufs = min_t(u32, hweight8(dbuf_slices), 3);
> +
> + mutex_lock(&i915->display.pmdemand.lock);
> + if (drm_WARN_ON(&i915->drm,
> + !intel_pmdemand_check_prev_transaction(i915)))
> + goto unlock;
> +
> + intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
> + XELPDP_PMDEMAND_DBUFS_MASK, XELPDP_PMDEMAND_DBUFS(dbufs));
> + intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
> + XELPDP_PMDEMAND_REQ_ENABLE);
> +
> + intel_pmdemand_wait(i915);
> +
> +unlock:
> + mutex_unlock(&i915->display.pmdemand.lock);
> +}
> +
> +static void
> +intel_pmdemand_update_params(const struct intel_pmdemand_state *new,
> + const struct intel_pmdemand_state *old,
> + u32 *reg1, u32 *reg2, bool serialized)
> +{
> + u32 plls, tmp, current_val;
> +
> + /*
> + * The pmdemand parameter updates happens in two steps. Pre plane and
> + * post plane updates. During the pre plane, as DE might still be
> + * handling with some old operations, to avoid unexpected performance
> + * issues, program the pmdemand parameters with higher of old and new
> + * values. And then after once settled, use the new parameter values
> + * as part of the post plane update.
> + *
> + * If the pmdemand params update happens without modeset allowed, this
> + * means we can't serialize the updates. So that implies possbility of
> + * some parallel atomic commits affecting the pmdemand parameters. In
> + * that case, we need to consider the current values from the register
> + * as well. So in pre-plane case, we need to check the max of old, new
> + * and current register value if not serialized. In post plance update
> + * we need to consider max of new and current register value if not
> + * serialized
> + */
> +
> + /* Set 1*/
> + current_val = REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, *reg1);
> + *reg1 &= ~XELPDP_PMDEMAND_QCLK_GV_BW_MASK;
> + tmp = old ? max(old->params.qclk_gv_bw, new->params.qclk_gv_bw) :
> + new->params.qclk_gv_bw;
> + if (!serialized)
> + tmp = max(tmp, current_val);
> + *reg1 |= XELPDP_PMDEMAND_QCLK_GV_BW(tmp);
> +
> + current_val = REG_FIELD_GET(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, *reg1);
> + *reg1 &= ~XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK;
> + tmp = old ? max(old->params.voltage_index, new->params.voltage_index) :
> + new->params.voltage_index;
> + if (!serialized)
> + tmp = max(tmp, current_val);
> + *reg1 |= XELPDP_PMDEMAND_VOLTAGE_INDEX(tmp);
> +
> + current_val = REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, *reg1);
> + *reg1 &= ~XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK;
> + tmp = old ? max(old->params.qclk_gv_index, new->params.qclk_gv_index) :
> + new->params.qclk_gv_index;
> + if (!serialized)
> + tmp = max(tmp, current_val);
> + *reg1 |= XELPDP_PMDEMAND_QCLK_GV_INDEX(tmp);
> +
> + current_val = REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, *reg1);
> + *reg1 &= ~XELPDP_PMDEMAND_PIPES_MASK;
> + tmp = old ? max(old->params.active_pipes, new->params.active_pipes) :
> + new->params.active_pipes;
> + if (!serialized)
> + tmp = max(tmp, current_val);
> + *reg1 |= XELPDP_PMDEMAND_PIPES(tmp);
> +
> + current_val = REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, *reg1);
> + *reg1 &= ~XELPDP_PMDEMAND_DBUFS_MASK;
> + tmp = old ? max(old->params.active_dbufs, new->params.active_dbufs) :
> + new->params.active_dbufs;
> + if (!serialized)
> + tmp = max(tmp, current_val);
> + *reg1 |= XELPDP_PMDEMAND_DBUFS(tmp);
> +
> + current_val = REG_FIELD_GET(XELPDP_PMDEMAND_PHYS_MASK, *reg1);
> + *reg1 &= ~XELPDP_PMDEMAND_PHYS_MASK;
> + plls = old ? max(old->params.active_phys, new->params.active_phys) :
> + new->params.active_phys;
> + if (!serialized)
> + plls = max(plls, current_val);
> + plls = min_t(u32, plls, 7);
Clamping active_phys should happen when calculating it, similarly
to the rest of the fields. Also using a
update_reg(reg, field, mask)
helper, would make this function more readable.
> + *reg1 |= XELPDP_PMDEMAND_PHYS(plls);
> +
> + /* Set 2*/
> + current_val = REG_FIELD_GET(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, *reg2);
> + *reg2 &= ~XELPDP_PMDEMAND_CDCLK_FREQ_MASK;
> + tmp = old ? max(old->params.cdclk_freq_mhz,
> + new->params.cdclk_freq_mhz) :
> + new->params.cdclk_freq_mhz;
> + if (!serialized)
> + tmp = max(tmp, current_val);
> + *reg2 |= XELPDP_PMDEMAND_CDCLK_FREQ(tmp);
> +
> + current_val = REG_FIELD_GET(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, *reg2);
> + *reg2 &= ~XELPDP_PMDEMAND_DDICLK_FREQ_MASK;
> + tmp = old ? max(old->params.ddiclk_max, new->params.ddiclk_max) :
> + new->params.ddiclk_max;
> + if (!serialized)
> + tmp = max(tmp, current_val);
> + *reg2 |= XELPDP_PMDEMAND_DDICLK_FREQ(tmp);
> +
> + current_val = REG_FIELD_GET(XELPDP_PMDEMAND_SCALERS_MASK, *reg2);
> + *reg2 &= ~XELPDP_PMDEMAND_SCALERS_MASK;
> + tmp = old ? max(old->params.scalers, new->params.scalers) :
> + new->params.scalers;
> + if (!serialized)
> + tmp = max(tmp, current_val);
> + *reg2 |= XELPDP_PMDEMAND_SCALERS(tmp);
> +
> + /*
> + * Active_PLLs starts with 1 because of CDCLK PLL.
> + * TODO: Missing to account genlock filter when it gets used.
> + */
> + plls = min_t(u32, plls + 1, 7);
> + *reg2 &= ~XELPDP_PMDEMAND_PLLS_MASK;
> + *reg2 |= XELPDP_PMDEMAND_PLLS(plls);
> +}
> +
> +static void
> +intel_pmdemand_program_params(struct drm_i915_private *i915,
> + const struct intel_pmdemand_state *new,
> + const struct intel_pmdemand_state *old,
> + bool serialized)
> +{
> + bool changed = false;
> + u32 reg1, mod_reg1;
> + u32 reg2, mod_reg2;
> +
> + mutex_lock(&i915->display.pmdemand.lock);
> + if (drm_WARN_ON(&i915->drm,
> + !intel_pmdemand_check_prev_transaction(i915)))
> + goto unlock;
> +
> + reg1 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
> + mod_reg1 = reg1;
> +
> + reg2 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
> + mod_reg2 = reg2;
> +
> + intel_pmdemand_update_params(new, old, &mod_reg1, &mod_reg2,
> + serialized);
> +
> + if (reg1 != mod_reg1) {
> + intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
> + mod_reg1);
> + changed = true;
> + }
> +
> + if (reg2 != mod_reg2) {
> + intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
> + mod_reg2);
> + changed = true;
> + }
> +
> + /* Initiate pm demand request only if register values are changed */
> + if (!changed)
> + goto unlock;
> +
> + drm_dbg_kms(&i915->drm,
> + "initate pmdemand request values: (0x%x 0x%x)\n",
> + mod_reg1, mod_reg2);
> +
> + intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
> + XELPDP_PMDEMAND_REQ_ENABLE);
> +
> + intel_pmdemand_wait(i915);
> +
> +unlock:
> + mutex_unlock(&i915->display.pmdemand.lock);
> +}
> +
> +static bool
> +intel_pmdemand_state_changed(const struct intel_pmdemand_state *new,
> + const struct intel_pmdemand_state *old)
> +{
> + return memcmp(&new->params, &old->params, sizeof(new->params)) != 0;
> +}
> +
> +static bool
> +intel_pmdemand_check_serialized(struct intel_atomic_state *state)
A better name for this is something like
intel_atomic_global_state_is_serialized() exported from
intel_global_state.c.
I think we'd also need to verify/dump pmdemand_state, but that could be
added later. With the above things fixed the patch looks ok to me:
Reviewed-by: Imre Deak <imre.deak@intel.com>
If you resend this patch, you could send only this one as a reply to the
previous version of the patch, instead of sending the whole patchset.
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(&i915->drm, crtc) {
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + if (!crtc_state)
> + return false;
> + }
> +
> + return true;
> +}
> +
> +void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + const struct intel_pmdemand_state *new_pmdemand_state =
> + intel_atomic_get_new_pmdemand_state(state);
> + const struct intel_pmdemand_state *old_pmdemand_state =
> + intel_atomic_get_old_pmdemand_state(state);
> + bool serialized;
> +
> + if (DISPLAY_VER(i915) < 14)
> + return;
> +
> + if (!new_pmdemand_state ||
> + !intel_pmdemand_state_changed(new_pmdemand_state,
> + old_pmdemand_state))
> + return;
> +
> + serialized = intel_pmdemand_check_serialized(state);
> +
> + WARN_ON(!new_pmdemand_state->base.changed);
> +
> + intel_pmdemand_program_params(i915, new_pmdemand_state,
> + old_pmdemand_state, serialized);
> +}
> +
> +void intel_pmdemand_post_plane_update(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + const struct intel_pmdemand_state *new_pmdemand_state =
> + intel_atomic_get_new_pmdemand_state(state);
> + const struct intel_pmdemand_state *old_pmdemand_state =
> + intel_atomic_get_old_pmdemand_state(state);
> + bool serialized;
> +
> + if (DISPLAY_VER(i915) < 14)
> + return;
> +
> + if (!new_pmdemand_state ||
> + !intel_pmdemand_state_changed(new_pmdemand_state,
> + old_pmdemand_state))
> + return;
> +
> + serialized = intel_pmdemand_check_serialized(state);
> +
> + WARN_ON(!new_pmdemand_state->base.changed);
> +
> + intel_pmdemand_program_params(i915, new_pmdemand_state, NULL,
> + serialized);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.h b/drivers/gpu/drm/i915/display/intel_pmdemand.h
> new file mode 100644
> index 000000000000..9ff3eefb600a
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.h
> @@ -0,0 +1,69 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef __INTEL_PMDEMAND_H__
> +#define __INTEL_PMDEMAND_H__
> +
> +#include "intel_display_limits.h"
> +#include "intel_global_state.h"
> +
> +struct drm_i915_private;
> +struct intel_atomic_state;
> +struct intel_crtc_state;
> +struct intel_encoder;
> +struct intel_plane_state;
> +
> +struct pmdemand_params {
> + u16 qclk_gv_bw;
> + u8 voltage_index;
> + u8 qclk_gv_index;
> + u8 active_pipes;
> + u8 active_dbufs;
> + /* Total number of non type C active phys from active_phys_mask */
> + u8 active_phys;
> + u16 cdclk_freq_mhz;
> + /* max from ddi_clocks[] */
> + u16 ddiclk_max;
> + u8 scalers;
> +};
> +
> +struct intel_pmdemand_state {
> + struct intel_global_state base;
> +
> + /* Maintain a persistent list of port clocks across all crtcs */
> + int ddi_clocks[I915_MAX_PIPES];
> +
> + /* Maintain a persistent list of non type C phys mask */
> + u16 active_phys_mask;
> +
> + /* Parameters to be configured in the pmdemand registers */
> + struct pmdemand_params params;
> +};
> +
> +#define to_intel_pmdemand_state(x) container_of((x), \
> + struct intel_pmdemand_state, \
> + base)
> +
> +void intel_pmdemand_init_early(struct drm_i915_private *i915);
> +int intel_pmdemand_init(struct drm_i915_private *i915);
> +void intel_pmdemand_init_pmdemand_params(struct drm_i915_private *i915,
> + struct intel_pmdemand_state *pmdemand_state);
> +void intel_pmdemand_init_active_phys_mask(struct drm_i915_private *i915,
> + struct intel_pmdemand_state *pmdemand_state,
> + u16 active_phys);
> +void intel_pmdemand_update_port_clock(struct drm_i915_private *i915,
> + struct intel_pmdemand_state *pmdemand_state,
> + enum pipe pipe, int port_clock);
> +void intel_pmdemand_update_phys_mask(struct drm_i915_private *i915,
> + struct intel_encoder *encoder,
> + struct intel_pmdemand_state *pmdemand_state,
> + bool clear_bit);
> +void intel_pmdemand_program_dbuf(struct drm_i915_private *i915,
> + u8 dbuf_slices);
> +void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state);
> +void intel_pmdemand_post_plane_update(struct intel_atomic_state *state);
> +int intel_pmdemand_atomic_check(struct intel_atomic_state *state);
> +
> +#endif /* __INTEL_PMDEMAND_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0523418129c5..6d34d9f59b1c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4418,8 +4418,10 @@
> #define GEN8_DE_MISC_IMR _MMIO(0x44464)
> #define GEN8_DE_MISC_IIR _MMIO(0x44468)
> #define GEN8_DE_MISC_IER _MMIO(0x4446c)
> -#define GEN8_DE_MISC_GSE (1 << 27)
> -#define GEN8_DE_EDP_PSR (1 << 19)
> +#define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27)
> +#define GEN8_DE_MISC_GSE REG_BIT(27)
> +#define GEN8_DE_EDP_PSR REG_BIT(19)
> +#define XELPDP_PMDEMAND_RSP REG_BIT(3)
>
> #define GEN8_PCU_ISR _MMIO(0x444e0)
> #define GEN8_PCU_IMR _MMIO(0x444e4)
> @@ -4504,6 +4506,33 @@
> #define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1)
> #define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0)
>
> +#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword))
> +#define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16)
> +#define XELPDP_PMDEMAND_QCLK_GV_BW(x) REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, x)
> +#define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12)
> +#define XELPDP_PMDEMAND_VOLTAGE_INDEX(x) REG_FIELD_PREP(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, x)
> +#define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8)
> +#define XELPDP_PMDEMAND_QCLK_GV_INDEX(x) REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, x)
> +#define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6)
> +#define XELPDP_PMDEMAND_PIPES(x) REG_FIELD_PREP(XELPDP_PMDEMAND_PIPES_MASK, x)
> +#define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4)
> +#define XELPDP_PMDEMAND_DBUFS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK, x)
> +#define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0)
> +#define XELPDP_PMDEMAND_PHYS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_PHYS_MASK, x)
> +
> +#define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31)
> +#define XELPDP_PMDEMAND_CDCLK_FREQ_MASK REG_GENMASK(30, 20)
> +#define XELPDP_PMDEMAND_CDCLK_FREQ(x) REG_FIELD_PREP(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, x)
> +#define XELPDP_PMDEMAND_DDICLK_FREQ_MASK REG_GENMASK(18, 8)
> +#define XELPDP_PMDEMAND_DDICLK_FREQ(x) REG_FIELD_PREP(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, x)
> +#define XELPDP_PMDEMAND_SCALERS_MASK REG_GENMASK(6, 4)
> +#define XELPDP_PMDEMAND_SCALERS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_SCALERS_MASK, x)
> +#define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0)
> +#define XELPDP_PMDEMAND_PLLS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_PLLS_MASK, x)
> +
> +#define GEN12_DCPR_STATUS_1 _MMIO(0x46440)
> +#define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26)
> +
> #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
> /* Required on all Ironlake and Sandybridge according to the B-Spec. */
> #define ILK_ELPIN_409_SELECT REG_BIT(25)
> @@ -4663,6 +4692,9 @@
> #define DCPR_SEND_RESP_IMM REG_BIT(25)
> #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
>
> +#define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438)
> +#define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19)
> +
> #define SKL_DFSM _MMIO(0x51000)
> #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
> #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for mtl: add support for pmdemand (rev14)
2023-06-06 9:35 [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand Vinod Govindapillai
` (7 preceding siblings ...)
2023-06-06 10:32 ` [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand Jani Nikula
@ 2023-06-06 14:15 ` Patchwork
2023-06-06 14:15 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (5 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2023-06-06 14:15 UTC (permalink / raw)
To: Vinod Govindapillai; +Cc: intel-gfx
== Series Details ==
Series: mtl: add support for pmdemand (rev14)
URL : https://patchwork.freedesktop.org/series/116949/
State : warning
== Summary ==
Error: dim checkpatch failed
8bf8cd20b5c7 drm/i915: fix the derating percentage for MTL
0e53e38b6107 drm/i915: update the QGV point frequency calculations
2453db29ae96 drm/i915: store the peak bw per QGV point
6be9b38effe8 drm/i915: extract intel_bw_check_qgv_points()
b67308525d7d drm/i915: modify max_bw to return index to intel_bw_info
d56333a485fd drm/i915/mtl: find the best QGV point for the SAGV configuration
96502e589e60 drm/i915/mtl: Add support for PM DEMAND
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:409: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#409:
new file mode 100644
-:1226: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#1226: FILE: drivers/gpu/drm/i915/i915_reg.h:4514:
+#define XELPDP_PMDEMAND_QCLK_GV_BW(x) REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, x)
-:1228: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#1228: FILE: drivers/gpu/drm/i915/i915_reg.h:4516:
+#define XELPDP_PMDEMAND_VOLTAGE_INDEX(x) REG_FIELD_PREP(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, x)
-:1230: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#1230: FILE: drivers/gpu/drm/i915/i915_reg.h:4518:
+#define XELPDP_PMDEMAND_QCLK_GV_INDEX(x) REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, x)
-:1232: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#1232: FILE: drivers/gpu/drm/i915/i915_reg.h:4520:
+#define XELPDP_PMDEMAND_PIPES(x) REG_FIELD_PREP(XELPDP_PMDEMAND_PIPES_MASK, x)
-:1234: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#1234: FILE: drivers/gpu/drm/i915/i915_reg.h:4522:
+#define XELPDP_PMDEMAND_DBUFS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK, x)
-:1240: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#1240: FILE: drivers/gpu/drm/i915/i915_reg.h:4528:
+#define XELPDP_PMDEMAND_CDCLK_FREQ(x) REG_FIELD_PREP(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, x)
-:1242: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#1242: FILE: drivers/gpu/drm/i915/i915_reg.h:4530:
+#define XELPDP_PMDEMAND_DDICLK_FREQ(x) REG_FIELD_PREP(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, x)
-:1244: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#1244: FILE: drivers/gpu/drm/i915/i915_reg.h:4532:
+#define XELPDP_PMDEMAND_SCALERS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_SCALERS_MASK, x)
total: 0 errors, 9 warnings, 0 checks, 1117 lines checked
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for mtl: add support for pmdemand (rev14)
2023-06-06 9:35 [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand Vinod Govindapillai
` (8 preceding siblings ...)
2023-06-06 14:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for mtl: add support for pmdemand (rev14) Patchwork
@ 2023-06-06 14:15 ` Patchwork
2023-06-06 14:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (4 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2023-06-06 14:15 UTC (permalink / raw)
To: Vinod Govindapillai; +Cc: intel-gfx
== Series Details ==
Series: mtl: add support for pmdemand (rev14)
URL : https://patchwork.freedesktop.org/series/116949/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for mtl: add support for pmdemand (rev14)
2023-06-06 9:35 [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand Vinod Govindapillai
` (9 preceding siblings ...)
2023-06-06 14:15 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-06-06 14:35 ` Patchwork
2023-06-06 23:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for mtl: add support for pmdemand (rev15) Patchwork
` (3 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2023-06-06 14:35 UTC (permalink / raw)
To: Vinod Govindapillai; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6005 bytes --]
== Series Details ==
Series: mtl: add support for pmdemand (rev14)
URL : https://patchwork.freedesktop.org/series/116949/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13236 -> Patchwork_116949v14
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v14/index.html
Participating hosts (41 -> 40)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_116949v14 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@hangcheck:
- bat-dg2-11: [PASS][1] -> [ABORT][2] ([i915#7913] / [i915#7979])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-dg2-11/igt@i915_selftest@live@hangcheck.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v14/bat-dg2-11/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@slpc:
- bat-rpls-1: NOTRUN -> [DMESG-WARN][3] ([i915#6367])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v14/bat-rpls-1/igt@i915_selftest@live@slpc.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][4] ([i915#6687] / [i915#7978])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v14/bat-rpls-1/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1:
- bat-dg2-8: [PASS][5] -> [FAIL][6] ([i915#7932])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v14/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1.html
#### Possible fixes ####
* igt@i915_selftest@live@requests:
- bat-rpls-1: [ABORT][7] ([i915#7911] / [i915#7920] / [i915#7982]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-rpls-1/igt@i915_selftest@live@requests.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v14/bat-rpls-1/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: [DMESG-WARN][9] ([i915#6367]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-rpls-2/igt@i915_selftest@live@slpc.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v14/bat-rpls-2/igt@i915_selftest@live@slpc.html
* {igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-c-dp-5}:
- {bat-adlp-11}: [DMESG-FAIL][11] ([i915#6868]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-c-dp-5.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v14/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-c-dp-5.html
* {igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-d-dp-5}:
- {bat-adlp-11}: [FAIL][13] -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-d-dp-5.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v14/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-d-dp-5.html
#### Warnings ####
* igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: [SKIP][15] ([i915#3555] / [i915#4579]) -> [ABORT][16] ([i915#4579] / [i915#8260])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-rplp-1/igt@kms_setmode@basic-clone-single-crtc.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v14/bat-rplp-1/igt@kms_setmode@basic-clone-single-crtc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4309]: https://gitlab.freedesktop.org/drm/intel/issues/4309
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#6868]: https://gitlab.freedesktop.org/drm/intel/issues/6868
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#7979]: https://gitlab.freedesktop.org/drm/intel/issues/7979
[i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982
[i915#8260]: https://gitlab.freedesktop.org/drm/intel/issues/8260
Build changes
-------------
* Linux: CI_DRM_13236 -> Patchwork_116949v14
CI-20190529: 20190529
CI_DRM_13236: 6ef9ba991d96572648aa75eb7818d8c111f2eb4f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7320: 1c96b08a4cde6f2d49824a8cc3303bd860617b52 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116949v14: 6ef9ba991d96572648aa75eb7818d8c111f2eb4f @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
46aded55bb94 drm/i915/mtl: Add support for PM DEMAND
42e32b76efa3 drm/i915/mtl: find the best QGV point for the SAGV configuration
73818eb86855 drm/i915: modify max_bw to return index to intel_bw_info
5399be787b9c drm/i915: extract intel_bw_check_qgv_points()
ff20774d4974 drm/i915: store the peak bw per QGV point
0fd351e0eb75 drm/i915: update the QGV point frequency calculations
94cbc2597bd5 drm/i915: fix the derating percentage for MTL
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v14/index.html
[-- Attachment #2: Type: text/html, Size: 6857 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v15 7/7] drm/i915/mtl: Add support for PM DEMAND
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 7/7] drm/i915/mtl: Add support for PM DEMAND Vinod Govindapillai
2023-06-06 13:50 ` Imre Deak
@ 2023-06-06 20:10 ` Vinod Govindapillai
2023-06-07 19:57 ` Sripada, Radhakrishna
1 sibling, 1 reply; 20+ messages in thread
From: Vinod Govindapillai @ 2023-06-06 20:10 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.saarinene
From: Mika Kahola <mika.kahola@intel.com>
MTL introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case scenarios. Changes made to use REG_BIT
for a register that we touched(GEN8_DE_MISC_IER _MMIO).
Wa_14016740474 is added which applies to Xe_LPD+ display
v2: checkpatch warning fixes, simplify program pmdemand part
v3: update to dbufs and pipes values to pmdemand register(stan)
Removed the macro usage in update_pmdemand_values()
v4: move the pmdemand_pre_plane_update before cdclk update
pmdemand_needs_update included cdclk params comparisons
pmdemand_state NULL check (Gustavo)
pmdemand.o in sorted order in the makefile (Jani)
update pmdemand misc irq handler loop (Gustavo)
active phys bitmask and programming correction (Gustavo)
v5: simplify pmdemand_state structure
simplify methods to find active phys and max port clock
Timeout in case of previou pmdemand task pending (Gustavo)
v6: rebasing
updates to max_ddiclk calculations (Gustavo)
updates to active_phys count method (Gustavo)
v7: use two separate loop to iterate throug old and new
crtc states to calculate the active phys (Gustavo)
v8: use uniform function names (Gustavo)
v9: For phys change iterate through connectors (Imre)
Look for change in phys for pmdemand update (Gustavo, Imre)
Some more stlying changes (Imre)
Update pmdemand state during HW readout/sanitize (Imre)
v10: Fix CI checkpatch warnings
v11: use correct pmdemand object pointer during hw readout,
simplify the check for phys need update (Gustavo)
v12: Handle possible non serialize cases (Imre)
Initialise also pmdemand params HW readout (Imre)
Update active phys mask during sanitize calls (Imre)
Check TC/encoder changes to limit connector update (Imre)
v13: Check display version before accessing pmdemand functions
v14: Move is_serialized to intel_global_state.c
simplify update params and other stlying issues (Imre)
Bspec: 66451, 64636, 64602, 64603
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> #v4
Acked-by: Gustavo Sousa <gustavo.sousa@intel.com> #v11
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 14 +
.../gpu/drm/i915/display/intel_display_core.h | 9 +
.../drm/i915/display/intel_display_driver.c | 7 +
.../gpu/drm/i915/display/intel_display_irq.c | 23 +-
.../drm/i915/display/intel_display_power.c | 14 +-
.../gpu/drm/i915/display/intel_global_state.c | 12 +
.../gpu/drm/i915/display/intel_global_state.h | 2 +
.../drm/i915/display/intel_modeset_setup.c | 32 +
drivers/gpu/drm/i915/display/intel_pmdemand.c | 620 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_pmdemand.h | 67 ++
drivers/gpu/drm/i915/i915_reg.h | 26 +-
12 files changed, 821 insertions(+), 6 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1c9ed4c52760..2cd8de174bf6 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -269,6 +269,7 @@ i915-y += \
display/intel_pch_display.o \
display/intel_pch_refclk.o \
display/intel_plane_initial.o \
+ display/intel_pmdemand.o \
display/intel_psr.o \
display/intel_quirks.o \
display/intel_sprite.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f51a55f4e9d0..5cbf5eae2414 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -99,6 +99,7 @@
#include "intel_pcode.h"
#include "intel_pipe_crc.h"
#include "intel_plane_initial.h"
+#include "intel_pmdemand.h"
#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_sdvo.h"
@@ -6352,6 +6353,10 @@ int intel_atomic_check(struct drm_device *dev,
return ret;
}
+ ret = intel_pmdemand_atomic_check(state);
+ if (ret)
+ goto fail;
+
ret = intel_atomic_check_crtcs(state);
if (ret)
goto fail;
@@ -6997,6 +7002,14 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
crtc->config = new_crtc_state;
+ /*
+ * In XE_LPD+ Pmdemand combines many parameters such as voltage index,
+ * plls, cdclk frequency, QGV point selection parameter etc. Voltage
+ * index, cdclk/ddiclk frequencies are supposed to be configured before
+ * the cdclk config is set.
+ */
+ intel_pmdemand_pre_plane_update(state);
+
if (state->modeset) {
drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
@@ -7116,6 +7129,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_verify_planes(state);
intel_sagv_post_plane_update(state);
+ intel_pmdemand_post_plane_update(state);
drm_atomic_helper_commit_hw_done(&state->base);
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index dd8e08c8598f..8d2243c71dd8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -345,6 +345,15 @@ struct intel_display {
struct intel_global_obj obj;
} dbuf;
+ struct {
+ wait_queue_head_t waitqueue;
+
+ /* mutex to protect pmdemand programming sequence */
+ struct mutex lock;
+
+ struct intel_global_obj obj;
+ } pmdemand;
+
struct {
/*
* dkl.phy_lock protects against concurrent access of the
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 60ce10fc7205..dc8de861339d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -47,6 +47,7 @@
#include "intel_opregion.h"
#include "intel_overlay.h"
#include "intel_plane_initial.h"
+#include "intel_pmdemand.h"
#include "intel_pps.h"
#include "intel_quirks.h"
#include "intel_vga.h"
@@ -211,6 +212,8 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
if (ret < 0)
goto cleanup_vga;
+ intel_pmdemand_init_early(i915);
+
intel_power_domains_init_hw(i915, false);
if (!HAS_DISPLAY(i915))
@@ -240,6 +243,10 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
if (ret)
goto cleanup_vga_client_pw_domain_dmc;
+ ret = intel_pmdemand_init(i915);
+ if (ret)
+ goto cleanup_vga_client_pw_domain_dmc;
+
init_llist_head(&i915->display.atomic_helper.free_list);
INIT_WORK(&i915->display.atomic_helper.free_work,
intel_atomic_helper_free_state_worker);
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 3b2a287d2041..0b3739310f81 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -18,6 +18,7 @@
#include "intel_fifo_underrun.h"
#include "intel_gmbus.h"
#include "intel_hotplug_irq.h"
+#include "intel_pmdemand.h"
#include "intel_psr.h"
#include "intel_psr_regs.h"
@@ -827,12 +828,27 @@ static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
}
+static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv)
+{
+ wake_up_all(&dev_priv->display.pmdemand.waitqueue);
+}
+
static void
gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
{
bool found = false;
- if (iir & GEN8_DE_MISC_GSE) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ if (iir & (XELPDP_PMDEMAND_RSP |
+ XELPDP_PMDEMAND_RSPTOUT_ERR)) {
+ if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR)
+ drm_dbg(&dev_priv->drm,
+ "Error waiting for Punit PM Demand Response\n");
+
+ intel_pmdemand_irq_handler(dev_priv);
+ found = true;
+ }
+ } else if (iir & GEN8_DE_MISC_GSE) {
intel_opregion_asle_intr(dev_priv);
found = true;
}
@@ -1576,7 +1592,10 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
de_port_masked |= BXT_DE_PORT_GMBUS;
- if (DISPLAY_VER(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR |
+ XELPDP_PMDEMAND_RSP;
+ } else if (DISPLAY_VER(dev_priv) >= 11) {
enum port port;
if (intel_bios_is_dsi_present(dev_priv, &port))
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 2f4f00ae2f57..db5437043904 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -20,6 +20,7 @@
#include "intel_mchbar_regs.h"
#include "intel_pch_refclk.h"
#include "intel_pcode.h"
+#include "intel_pmdemand.h"
#include "intel_pps_regs.h"
#include "intel_snps_phy.h"
#include "skl_watermark.h"
@@ -1082,20 +1083,29 @@ void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
{
+ u8 slices_mask;
+
dev_priv->display.dbuf.enabled_slices =
intel_enabled_dbuf_slices_mask(dev_priv);
+ slices_mask = BIT(DBUF_S1) | dev_priv->display.dbuf.enabled_slices;
+
+ if (DISPLAY_VER(dev_priv) >= 14)
+ intel_pmdemand_program_dbuf(dev_priv, slices_mask);
+
/*
* Just power up at least 1 slice, we will
* figure out later which slices we have and what we need.
*/
- gen9_dbuf_slices_update(dev_priv, BIT(DBUF_S1) |
- dev_priv->display.dbuf.enabled_slices);
+ gen9_dbuf_slices_update(dev_priv, slices_mask);
}
static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
{
gen9_dbuf_slices_update(dev_priv, 0);
+
+ if (DISPLAY_VER(dev_priv) >= 14)
+ intel_pmdemand_program_dbuf(dev_priv, 0);
}
static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_global_state.c b/drivers/gpu/drm/i915/display/intel_global_state.c
index 02b593b1e2ea..e8e8be54143b 100644
--- a/drivers/gpu/drm/i915/display/intel_global_state.c
+++ b/drivers/gpu/drm/i915/display/intel_global_state.c
@@ -255,3 +255,15 @@ int intel_atomic_serialize_global_state(struct intel_global_state *obj_state)
return 0;
}
+
+bool
+intel_atomic_global_state_is_serialized(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+
+ for_each_intel_crtc(&i915->drm, crtc)
+ if (!intel_atomic_get_new_crtc_state(state, crtc))
+ return false;
+ return true;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_global_state.h b/drivers/gpu/drm/i915/display/intel_global_state.h
index f01ee0bb3e5a..5477de8f0b30 100644
--- a/drivers/gpu/drm/i915/display/intel_global_state.h
+++ b/drivers/gpu/drm/i915/display/intel_global_state.h
@@ -87,4 +87,6 @@ void intel_atomic_clear_global_state(struct intel_atomic_state *state);
int intel_atomic_lock_global_state(struct intel_global_state *obj_state);
int intel_atomic_serialize_global_state(struct intel_global_state *obj_state);
+bool intel_atomic_global_state_is_serialized(struct intel_atomic_state *state);
+
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 5ff99ca7f1de..b8f43efb0ab5 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -26,6 +26,7 @@
#include "intel_fifo_underrun.h"
#include "intel_modeset_setup.h"
#include "intel_pch_display.h"
+#include "intel_pmdemand.h"
#include "intel_tc.h"
#include "intel_vblank.h"
#include "intel_wm.h"
@@ -115,6 +116,8 @@ static void set_encoder_for_connector(struct intel_connector *connector,
static void reset_encoder_connector_state(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_pmdemand_state *pmdemand_state =
+ to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
struct intel_connector *connector;
struct drm_connector_list_iter conn_iter;
@@ -123,6 +126,10 @@ static void reset_encoder_connector_state(struct intel_encoder *encoder)
if (connector->base.encoder != &encoder->base)
continue;
+ /* Clear the corresponding bit in pmdemand active phys mask */
+ intel_pmdemand_update_phys_mask(i915, encoder,
+ pmdemand_state, false);
+
set_encoder_for_connector(connector, NULL);
connector->base.dpms = DRM_MODE_DPMS_OFF;
@@ -151,6 +158,8 @@ static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
to_intel_cdclk_state(i915->display.cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
to_intel_dbuf_state(i915->display.dbuf.obj.state);
+ struct intel_pmdemand_state *pmdemand_state =
+ to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
enum pipe pipe = crtc->pipe;
@@ -174,6 +183,8 @@ static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
bw_state->data_rate[pipe] = 0;
bw_state->num_active_planes[pipe] = 0;
+
+ intel_pmdemand_update_port_clock(i915, pmdemand_state, pipe, 0);
}
/*
@@ -552,6 +563,8 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
struct intel_crtc_state *crtc_state = crtc ?
to_intel_crtc_state(crtc->base.state) : NULL;
+ struct intel_pmdemand_state *pmdemand_state =
+ to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
/*
* We need to check both for a crtc link (meaning that the encoder is
@@ -575,6 +588,10 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
encoder->base.base.id,
encoder->base.name);
+ /* Clear the corresponding bit in pmdemand active phys mask */
+ intel_pmdemand_update_phys_mask(i915, encoder,
+ pmdemand_state, false);
+
/*
* Connector is active, but has no active pipe. This is fallout
* from our resume register restoring. Disable the encoder
@@ -661,6 +678,8 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
to_intel_cdclk_state(i915->display.cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
to_intel_dbuf_state(i915->display.dbuf.obj.state);
+ struct intel_pmdemand_state *pmdemand_state =
+ to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
enum pipe pipe;
struct intel_crtc *crtc;
struct intel_encoder *encoder;
@@ -724,7 +743,15 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
intel_encoder_get_config(encoder, slave_crtc_state);
}
}
+
+ intel_pmdemand_update_phys_mask(i915, encoder,
+ pmdemand_state,
+ true);
} else {
+ intel_pmdemand_update_phys_mask(i915, encoder,
+ pmdemand_state,
+ false);
+
encoder->base.crtc = NULL;
}
@@ -841,8 +868,13 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
cdclk_state->min_voltage_level[crtc->pipe] =
crtc_state->min_voltage_level;
+ intel_pmdemand_update_port_clock(i915, pmdemand_state, pipe,
+ crtc_state->port_clock);
+
intel_bw_crtc_update(bw_state, crtc_state);
}
+
+ intel_pmdemand_init_pmdemand_params(i915, pmdemand_state);
}
static void
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
new file mode 100644
index 000000000000..2f8cf29a861b
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -0,0 +1,620 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include <linux/bitops.h>
+
+#include "i915_drv.h"
+#include "i915_reg.h"
+#include "intel_atomic.h"
+#include "intel_bw.h"
+#include "intel_cdclk.h"
+#include "intel_de.h"
+#include "intel_display_trace.h"
+#include "intel_pmdemand.h"
+#include "skl_watermark.h"
+
+static struct intel_global_state *
+intel_pmdemand_duplicate_state(struct intel_global_obj *obj)
+{
+ struct intel_pmdemand_state *pmdemand_state;
+
+ pmdemand_state = kmemdup(obj->state, sizeof(*pmdemand_state), GFP_KERNEL);
+ if (!pmdemand_state)
+ return NULL;
+
+ return &pmdemand_state->base;
+}
+
+static void intel_pmdemand_destroy_state(struct intel_global_obj *obj,
+ struct intel_global_state *state)
+{
+ kfree(state);
+}
+
+static const struct intel_global_state_funcs intel_pmdemand_funcs = {
+ .atomic_duplicate_state = intel_pmdemand_duplicate_state,
+ .atomic_destroy_state = intel_pmdemand_destroy_state,
+};
+
+static struct intel_pmdemand_state *
+intel_atomic_get_pmdemand_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_global_state *pmdemand_state =
+ intel_atomic_get_global_obj_state(state,
+ &i915->display.pmdemand.obj);
+
+ if (IS_ERR(pmdemand_state))
+ return ERR_CAST(pmdemand_state);
+
+ return to_intel_pmdemand_state(pmdemand_state);
+}
+
+static struct intel_pmdemand_state *
+intel_atomic_get_old_pmdemand_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_global_state *pmdemand_state =
+ intel_atomic_get_old_global_obj_state(state,
+ &i915->display.pmdemand.obj);
+
+ if (!pmdemand_state)
+ return NULL;
+
+ return to_intel_pmdemand_state(pmdemand_state);
+}
+
+static struct intel_pmdemand_state *
+intel_atomic_get_new_pmdemand_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_global_state *pmdemand_state =
+ intel_atomic_get_new_global_obj_state(state,
+ &i915->display.pmdemand.obj);
+
+ if (!pmdemand_state)
+ return NULL;
+
+ return to_intel_pmdemand_state(pmdemand_state);
+}
+
+int intel_pmdemand_init(struct drm_i915_private *i915)
+{
+ struct intel_pmdemand_state *pmdemand_state;
+
+ pmdemand_state = kzalloc(sizeof(*pmdemand_state), GFP_KERNEL);
+ if (!pmdemand_state)
+ return -ENOMEM;
+
+ intel_atomic_global_obj_init(i915, &i915->display.pmdemand.obj,
+ &pmdemand_state->base,
+ &intel_pmdemand_funcs);
+
+ if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+ /* Wa_14016740474 */
+ intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
+
+ return 0;
+}
+
+void intel_pmdemand_init_early(struct drm_i915_private *i915)
+{
+ mutex_init(&i915->display.pmdemand.lock);
+ init_waitqueue_head(&i915->display.pmdemand.waitqueue);
+}
+
+void
+intel_pmdemand_update_phys_mask(struct drm_i915_private *i915,
+ struct intel_encoder *encoder,
+ struct intel_pmdemand_state *pmdemand_state,
+ bool set_bit)
+{
+ enum phy phy;
+
+ if (DISPLAY_VER(i915) < 14)
+ return;
+
+ if (!encoder)
+ return;
+
+ phy = intel_port_to_phy(i915, encoder->port);
+ if (intel_phy_is_tc(i915, phy))
+ return;
+
+ if (set_bit)
+ pmdemand_state->active_combo_phys_mask |= BIT(phy);
+ else
+ pmdemand_state->active_combo_phys_mask &= ~BIT(phy);
+}
+
+void
+intel_pmdemand_update_port_clock(struct drm_i915_private *i915,
+ struct intel_pmdemand_state *pmdemand_state,
+ enum pipe pipe, int port_clock)
+{
+ if (DISPLAY_VER(i915) < 14)
+ return;
+
+ pmdemand_state->ddi_clocks[pipe] = port_clock;
+}
+
+static void
+intel_pmdemand_update_max_ddiclk(struct drm_i915_private *i915,
+ struct intel_atomic_state *state,
+ struct intel_pmdemand_state *pmdemand_state)
+{
+ int max_ddiclk = 0;
+ const struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc *crtc;
+ int i;
+
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
+ intel_pmdemand_update_port_clock(i915, pmdemand_state,
+ crtc->pipe,
+ new_crtc_state->port_clock);
+
+ for (i = 0; i < ARRAY_SIZE(pmdemand_state->ddi_clocks); i++)
+ max_ddiclk = max(pmdemand_state->ddi_clocks[i], max_ddiclk);
+
+ pmdemand_state->params.ddiclk_max = DIV_ROUND_UP(max_ddiclk, 1000);
+}
+
+static void
+intel_pmdemand_update_connector_phys(struct drm_i915_private *i915,
+ struct intel_atomic_state *state,
+ struct drm_connector_state *conn_state,
+ bool set_bit,
+ struct intel_pmdemand_state *pmdemand_state)
+{
+ struct intel_encoder *encoder = to_intel_encoder(conn_state->best_encoder);
+ struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
+ struct intel_crtc_state *crtc_state;
+
+ if (!crtc)
+ return;
+
+ if (set_bit)
+ crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+ else
+ crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
+
+ if (!crtc_state->hw.active)
+ return;
+
+ intel_pmdemand_update_phys_mask(i915, encoder, pmdemand_state,
+ set_bit);
+}
+
+static void
+intel_pmdemand_update_active_non_tc_phys(struct drm_i915_private *i915,
+ struct intel_atomic_state *state,
+ struct intel_pmdemand_state *pmdemand_state)
+{
+ struct drm_connector_state *old_conn_state;
+ struct drm_connector_state *new_conn_state;
+ struct drm_connector *connector;
+ int i;
+
+ for_each_oldnew_connector_in_state(&state->base, connector,
+ old_conn_state, new_conn_state, i) {
+ if (!intel_connector_needs_modeset(state, connector))
+ continue;
+
+ /* First clear the active phys in the old connector state */
+ intel_pmdemand_update_connector_phys(i915, state,
+ old_conn_state, false,
+ pmdemand_state);
+
+ /* Then set the active phys in new connector state */
+ intel_pmdemand_update_connector_phys(i915, state,
+ new_conn_state, true,
+ pmdemand_state);
+ }
+
+ pmdemand_state->params.active_phys =
+ min_t(u16, hweight16(pmdemand_state->active_combo_phys_mask),
+ 7);
+}
+
+static bool
+intel_pmdemand_encoder_has_tc_phy(struct drm_i915_private *i915,
+ struct intel_encoder *encoder)
+{
+ enum phy phy;
+
+ if (!encoder)
+ return false;
+
+ phy = intel_port_to_phy(i915, encoder->port);
+
+ return intel_phy_is_tc(i915, phy);
+}
+
+static bool
+intel_pmdemand_connector_needs_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct drm_connector_state *old_conn_state;
+ struct drm_connector_state *new_conn_state;
+ struct drm_connector *connector;
+ int i;
+
+ for_each_oldnew_connector_in_state(&state->base, connector,
+ old_conn_state, new_conn_state, i) {
+ struct intel_encoder *old_encoder =
+ to_intel_encoder(old_conn_state->best_encoder);
+ struct intel_encoder *new_encoder =
+ to_intel_encoder(new_conn_state->best_encoder);
+
+ if (!intel_connector_needs_modeset(state, connector))
+ continue;
+
+ if (old_encoder == new_encoder ||
+ (intel_pmdemand_encoder_has_tc_phy(i915, old_encoder) &&
+ intel_pmdemand_encoder_has_tc_phy(i915, new_encoder)))
+ continue;
+
+ return true;
+ }
+
+ return false;
+}
+
+static bool intel_pmdemand_needs_update(struct intel_atomic_state *state)
+{
+ const struct intel_bw_state *new_bw_state, *old_bw_state;
+ const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state;
+ const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
+ const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
+ struct intel_crtc *crtc;
+ int i;
+
+ new_bw_state = intel_atomic_get_new_bw_state(state);
+ old_bw_state = intel_atomic_get_old_bw_state(state);
+ if (new_bw_state && new_bw_state->qgv_point_peakbw !=
+ old_bw_state->qgv_point_peakbw)
+ return true;
+
+ new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
+ old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
+ if (new_dbuf_state &&
+ (new_dbuf_state->active_pipes !=
+ old_dbuf_state->active_pipes ||
+ new_dbuf_state->enabled_slices !=
+ old_dbuf_state->enabled_slices))
+ return true;
+
+ new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
+ old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
+ if (new_cdclk_state &&
+ (new_cdclk_state->actual.cdclk !=
+ old_cdclk_state->actual.cdclk ||
+ new_cdclk_state->actual.voltage_level !=
+ old_cdclk_state->actual.voltage_level))
+ return true;
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i)
+ if (new_crtc_state->port_clock != old_crtc_state->port_clock)
+ return true;
+
+ return intel_pmdemand_connector_needs_update(state);
+}
+
+int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ const struct intel_bw_state *new_bw_state;
+ const struct intel_cdclk_state *new_cdclk_state;
+ const struct intel_dbuf_state *new_dbuf_state;
+ struct intel_pmdemand_state *new_pmdemand_state;
+
+ if (DISPLAY_VER(i915) < 14)
+ return 0;
+
+ if (!intel_pmdemand_needs_update(state))
+ return 0;
+
+ new_pmdemand_state = intel_atomic_get_pmdemand_state(state);
+ if (IS_ERR(new_pmdemand_state))
+ return PTR_ERR(new_pmdemand_state);
+
+ new_bw_state = intel_atomic_get_bw_state(state);
+ if (IS_ERR(new_bw_state))
+ return PTR_ERR(new_bw_state);
+
+ /* firmware will calculate the qclck_gc_index, requirement is set to 0 */
+ new_pmdemand_state->params.qclk_gv_index = 0;
+ new_pmdemand_state->params.qclk_gv_bw = new_bw_state->qgv_point_peakbw;
+
+ new_dbuf_state = intel_atomic_get_dbuf_state(state);
+ if (IS_ERR(new_dbuf_state))
+ return PTR_ERR(new_dbuf_state);
+
+ new_pmdemand_state->params.active_pipes =
+ min_t(u8, hweight8(new_dbuf_state->active_pipes), 3);
+ new_pmdemand_state->params.active_dbufs =
+ min_t(u8, hweight8(new_dbuf_state->enabled_slices), 3);
+
+ new_cdclk_state = intel_atomic_get_cdclk_state(state);
+ if (IS_ERR(new_cdclk_state))
+ return PTR_ERR(new_cdclk_state);
+
+ new_pmdemand_state->params.voltage_index =
+ new_cdclk_state->actual.voltage_level;
+ new_pmdemand_state->params.cdclk_freq_mhz =
+ DIV_ROUND_UP(new_cdclk_state->actual.cdclk, 1000);
+
+ intel_pmdemand_update_max_ddiclk(i915, state, new_pmdemand_state);
+
+ intel_pmdemand_update_active_non_tc_phys(i915, state, new_pmdemand_state);
+
+ /*
+ * Active_PLLs starts with 1 because of CDCLK PLL.
+ * TODO: Missing to account genlock filter when it gets used.
+ */
+ new_pmdemand_state->params.plls =
+ min_t(u16, new_pmdemand_state->params.active_phys + 1, 7);
+
+ /*
+ * Setting scalers to max as it can not be calculated during flips and
+ * fastsets without taking global states locks.
+ */
+ new_pmdemand_state->params.scalers = 7;
+
+ if (state->base.allow_modeset)
+ return intel_atomic_serialize_global_state(&new_pmdemand_state->base);
+ else
+ return intel_atomic_lock_global_state(&new_pmdemand_state->base);
+}
+
+static bool intel_pmdemand_check_prev_transaction(struct drm_i915_private *i915)
+{
+ return !(intel_de_wait_for_clear(i915,
+ XELPDP_INITIATE_PMDEMAND_REQUEST(1),
+ XELPDP_PMDEMAND_REQ_ENABLE, 10) ||
+ intel_de_wait_for_clear(i915,
+ GEN12_DCPR_STATUS_1,
+ XELPDP_PMDEMAND_INFLIGHT_STATUS, 10));
+}
+
+void
+intel_pmdemand_init_pmdemand_params(struct drm_i915_private *i915,
+ struct intel_pmdemand_state *pmdemand_state)
+{
+ u32 reg1, reg2;
+
+ if (DISPLAY_VER(i915) < 14)
+ return;
+
+ mutex_lock(&i915->display.pmdemand.lock);
+ if (drm_WARN_ON(&i915->drm,
+ !intel_pmdemand_check_prev_transaction(i915))) {
+ memset(&pmdemand_state->params, 0,
+ sizeof(pmdemand_state->params));
+ goto unlock;
+ }
+
+ reg1 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
+
+ reg2 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
+
+ /* Set 1*/
+ pmdemand_state->params.qclk_gv_bw =
+ REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, reg1);
+ pmdemand_state->params.voltage_index =
+ REG_FIELD_GET(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, reg1);
+ pmdemand_state->params.qclk_gv_index =
+ REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, reg1);
+ pmdemand_state->params.active_pipes =
+ REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, reg1);
+ pmdemand_state->params.active_dbufs =
+ REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, reg1);
+ pmdemand_state->params.active_phys =
+ REG_FIELD_GET(XELPDP_PMDEMAND_PHYS_MASK, reg1);
+
+ /* Set 2*/
+ pmdemand_state->params.cdclk_freq_mhz =
+ REG_FIELD_GET(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, reg2);
+ pmdemand_state->params.ddiclk_max =
+ REG_FIELD_GET(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, reg2);
+ pmdemand_state->params.scalers =
+ REG_FIELD_GET(XELPDP_PMDEMAND_SCALERS_MASK, reg2);
+
+unlock:
+ mutex_unlock(&i915->display.pmdemand.lock);
+}
+
+static bool intel_pmdemand_req_complete(struct drm_i915_private *i915)
+{
+ return !(intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
+ XELPDP_PMDEMAND_REQ_ENABLE);
+}
+
+static void intel_pmdemand_wait(struct drm_i915_private *i915)
+{
+ if (!wait_event_timeout(i915->display.pmdemand.waitqueue,
+ intel_pmdemand_req_complete(i915),
+ msecs_to_jiffies_timeout(10)))
+ drm_err(&i915->drm,
+ "timed out waiting for Punit PM Demand Response\n");
+}
+
+/* Required to be programmed during Display Init Sequences. */
+void intel_pmdemand_program_dbuf(struct drm_i915_private *i915,
+ u8 dbuf_slices)
+{
+ u32 dbufs = min_t(u32, hweight8(dbuf_slices), 3);
+
+ mutex_lock(&i915->display.pmdemand.lock);
+ if (drm_WARN_ON(&i915->drm,
+ !intel_pmdemand_check_prev_transaction(i915)))
+ goto unlock;
+
+ intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
+ XELPDP_PMDEMAND_DBUFS_MASK,
+ REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK, dbufs));
+ intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
+ XELPDP_PMDEMAND_REQ_ENABLE);
+
+ intel_pmdemand_wait(i915);
+
+unlock:
+ mutex_unlock(&i915->display.pmdemand.lock);
+}
+
+static void
+intel_pmdemand_update_params(const struct intel_pmdemand_state *new,
+ const struct intel_pmdemand_state *old,
+ u32 *reg1, u32 *reg2, bool serialized)
+{
+ /*
+ * The pmdemand parameter updates happens in two steps. Pre plane and
+ * post plane updates. During the pre plane, as DE might still be
+ * handling with some old operations, to avoid unexpected performance
+ * issues, program the pmdemand parameters with higher of old and new
+ * values. And then after once settled, use the new parameter values
+ * as part of the post plane update.
+ *
+ * If the pmdemand params update happens without modeset allowed, this
+ * means we can't serialize the updates. So that implies possibility of
+ * some parallel atomic commits affecting the pmdemand parameters. In
+ * that case, we need to consider the current values from the register
+ * as well. So in pre-plane case, we need to check the max of old, new
+ * and current register value if not serialized. In post plane update
+ * we need to consider max of new and current register value if not
+ * serialized
+ */
+
+#define update_reg(reg, field, mask) do { \
+ u32 current_val = serialized ? 0 : REG_FIELD_GET((mask), *(reg)); \
+ u32 old_val = old ? old->params.field : 0; \
+ u32 new_val = new->params.field; \
+\
+ *(reg) &= ~(mask); \
+ *(reg) |= REG_FIELD_PREP((mask), max3(old_val, new_val, current_val)); \
+} while (0)
+
+ /* Set 1*/
+ update_reg(reg1, qclk_gv_bw, XELPDP_PMDEMAND_QCLK_GV_BW_MASK);
+ update_reg(reg1, voltage_index, XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK);
+ update_reg(reg1, qclk_gv_index, XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK);
+ update_reg(reg1, active_pipes, XELPDP_PMDEMAND_PIPES_MASK);
+ update_reg(reg1, active_dbufs, XELPDP_PMDEMAND_DBUFS_MASK);
+ update_reg(reg1, active_phys, XELPDP_PMDEMAND_PHYS_MASK);
+
+ /* Set 2*/
+ update_reg(reg2, cdclk_freq_mhz, XELPDP_PMDEMAND_CDCLK_FREQ_MASK);
+ update_reg(reg2, ddiclk_max, XELPDP_PMDEMAND_DDICLK_FREQ_MASK);
+ update_reg(reg2, scalers, XELPDP_PMDEMAND_SCALERS_MASK);
+ update_reg(reg2, plls, XELPDP_PMDEMAND_PLLS_MASK);
+
+#undef update_reg
+}
+
+static void
+intel_pmdemand_program_params(struct drm_i915_private *i915,
+ const struct intel_pmdemand_state *new,
+ const struct intel_pmdemand_state *old,
+ bool serialized)
+{
+ bool changed = false;
+ u32 reg1, mod_reg1;
+ u32 reg2, mod_reg2;
+
+ mutex_lock(&i915->display.pmdemand.lock);
+ if (drm_WARN_ON(&i915->drm,
+ !intel_pmdemand_check_prev_transaction(i915)))
+ goto unlock;
+
+ reg1 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
+ mod_reg1 = reg1;
+
+ reg2 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
+ mod_reg2 = reg2;
+
+ intel_pmdemand_update_params(new, old, &mod_reg1, &mod_reg2,
+ serialized);
+
+ if (reg1 != mod_reg1) {
+ intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
+ mod_reg1);
+ changed = true;
+ }
+
+ if (reg2 != mod_reg2) {
+ intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
+ mod_reg2);
+ changed = true;
+ }
+
+ /* Initiate pm demand request only if register values are changed */
+ if (!changed)
+ goto unlock;
+
+ drm_dbg_kms(&i915->drm,
+ "initate pmdemand request values: (0x%x 0x%x)\n",
+ mod_reg1, mod_reg2);
+
+ intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
+ XELPDP_PMDEMAND_REQ_ENABLE);
+
+ intel_pmdemand_wait(i915);
+
+unlock:
+ mutex_unlock(&i915->display.pmdemand.lock);
+}
+
+static bool
+intel_pmdemand_state_changed(const struct intel_pmdemand_state *new,
+ const struct intel_pmdemand_state *old)
+{
+ return memcmp(&new->params, &old->params, sizeof(new->params)) != 0;
+}
+
+void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ const struct intel_pmdemand_state *new_pmdemand_state =
+ intel_atomic_get_new_pmdemand_state(state);
+ const struct intel_pmdemand_state *old_pmdemand_state =
+ intel_atomic_get_old_pmdemand_state(state);
+
+ if (DISPLAY_VER(i915) < 14)
+ return;
+
+ if (!new_pmdemand_state ||
+ !intel_pmdemand_state_changed(new_pmdemand_state,
+ old_pmdemand_state))
+ return;
+
+ WARN_ON(!new_pmdemand_state->base.changed);
+
+ intel_pmdemand_program_params(i915, new_pmdemand_state,
+ old_pmdemand_state,
+ intel_atomic_global_state_is_serialized(state));
+}
+
+void intel_pmdemand_post_plane_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ const struct intel_pmdemand_state *new_pmdemand_state =
+ intel_atomic_get_new_pmdemand_state(state);
+ const struct intel_pmdemand_state *old_pmdemand_state =
+ intel_atomic_get_old_pmdemand_state(state);
+
+ if (DISPLAY_VER(i915) < 14)
+ return;
+
+ if (!new_pmdemand_state ||
+ !intel_pmdemand_state_changed(new_pmdemand_state,
+ old_pmdemand_state))
+ return;
+
+ WARN_ON(!new_pmdemand_state->base.changed);
+
+ intel_pmdemand_program_params(i915, new_pmdemand_state, NULL,
+ intel_atomic_global_state_is_serialized(state));
+}
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.h b/drivers/gpu/drm/i915/display/intel_pmdemand.h
new file mode 100644
index 000000000000..2941a1a18b72
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __INTEL_PMDEMAND_H__
+#define __INTEL_PMDEMAND_H__
+
+#include "intel_display_limits.h"
+#include "intel_global_state.h"
+
+struct drm_i915_private;
+struct intel_atomic_state;
+struct intel_crtc_state;
+struct intel_encoder;
+struct intel_plane_state;
+
+struct pmdemand_params {
+ u16 qclk_gv_bw;
+ u8 voltage_index;
+ u8 qclk_gv_index;
+ u8 active_pipes;
+ u8 active_dbufs;
+ /* Total number of non type C active phys from active_phys_mask */
+ u8 active_phys;
+ u8 plls;
+ u16 cdclk_freq_mhz;
+ /* max from ddi_clocks[] */
+ u16 ddiclk_max;
+ u8 scalers;
+};
+
+struct intel_pmdemand_state {
+ struct intel_global_state base;
+
+ /* Maintain a persistent list of port clocks across all crtcs */
+ int ddi_clocks[I915_MAX_PIPES];
+
+ /* Maintain a persistent list of non type C phys mask */
+ u16 active_combo_phys_mask;
+
+ /* Parameters to be configured in the pmdemand registers */
+ struct pmdemand_params params;
+};
+
+#define to_intel_pmdemand_state(x) container_of((x), \
+ struct intel_pmdemand_state, \
+ base)
+
+void intel_pmdemand_init_early(struct drm_i915_private *i915);
+int intel_pmdemand_init(struct drm_i915_private *i915);
+void intel_pmdemand_init_pmdemand_params(struct drm_i915_private *i915,
+ struct intel_pmdemand_state *pmdemand_state);
+void intel_pmdemand_update_port_clock(struct drm_i915_private *i915,
+ struct intel_pmdemand_state *pmdemand_state,
+ enum pipe pipe, int port_clock);
+void intel_pmdemand_update_phys_mask(struct drm_i915_private *i915,
+ struct intel_encoder *encoder,
+ struct intel_pmdemand_state *pmdemand_state,
+ bool clear_bit);
+void intel_pmdemand_program_dbuf(struct drm_i915_private *i915,
+ u8 dbuf_slices);
+void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state);
+void intel_pmdemand_post_plane_update(struct intel_atomic_state *state);
+int intel_pmdemand_atomic_check(struct intel_atomic_state *state);
+
+#endif /* __INTEL_PMDEMAND_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0523418129c5..27d75215d3eb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4418,8 +4418,10 @@
#define GEN8_DE_MISC_IMR _MMIO(0x44464)
#define GEN8_DE_MISC_IIR _MMIO(0x44468)
#define GEN8_DE_MISC_IER _MMIO(0x4446c)
-#define GEN8_DE_MISC_GSE (1 << 27)
-#define GEN8_DE_EDP_PSR (1 << 19)
+#define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27)
+#define GEN8_DE_MISC_GSE REG_BIT(27)
+#define GEN8_DE_EDP_PSR REG_BIT(19)
+#define XELPDP_PMDEMAND_RSP REG_BIT(3)
#define GEN8_PCU_ISR _MMIO(0x444e0)
#define GEN8_PCU_IMR _MMIO(0x444e4)
@@ -4504,6 +4506,23 @@
#define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1)
#define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0)
+#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword))
+#define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16)
+#define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12)
+#define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8)
+#define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6)
+#define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4)
+#define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0)
+
+#define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31)
+#define XELPDP_PMDEMAND_CDCLK_FREQ_MASK REG_GENMASK(30, 20)
+#define XELPDP_PMDEMAND_DDICLK_FREQ_MASK REG_GENMASK(18, 8)
+#define XELPDP_PMDEMAND_SCALERS_MASK REG_GENMASK(6, 4)
+#define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0)
+
+#define GEN12_DCPR_STATUS_1 _MMIO(0x46440)
+#define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26)
+
#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
/* Required on all Ironlake and Sandybridge according to the B-Spec. */
#define ILK_ELPIN_409_SELECT REG_BIT(25)
@@ -4663,6 +4682,9 @@
#define DCPR_SEND_RESP_IMM REG_BIT(25)
#define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
+#define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438)
+#define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19)
+
#define SKL_DFSM _MMIO(0x51000)
#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for mtl: add support for pmdemand (rev15)
2023-06-06 9:35 [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand Vinod Govindapillai
` (10 preceding siblings ...)
2023-06-06 14:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-06-06 23:31 ` Patchwork
2023-06-06 23:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2023-06-06 23:31 UTC (permalink / raw)
To: Vinod Govindapillai; +Cc: intel-gfx
== Series Details ==
Series: mtl: add support for pmdemand (rev15)
URL : https://patchwork.freedesktop.org/series/116949/
State : warning
== Summary ==
Error: dim checkpatch failed
595a7ad922f2 drm/i915: fix the derating percentage for MTL
6c642218f0cc drm/i915: update the QGV point frequency calculations
f73e6f3d3a89 drm/i915: store the peak bw per QGV point
a12a6f28079a drm/i915: extract intel_bw_check_qgv_points()
e1dbf9927a1c drm/i915: modify max_bw to return index to intel_bw_info
49909f81b052 drm/i915/mtl: find the best QGV point for the SAGV configuration
11ac7a3d546d drm/i915/mtl: Add support for PM DEMAND
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:425: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#425:
new file mode 100644
-:920: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'reg' - possible side-effects?
#920: FILE: drivers/gpu/drm/i915/display/intel_pmdemand.c:491:
+#define update_reg(reg, field, mask) do { \
+ u32 current_val = serialized ? 0 : REG_FIELD_GET((mask), *(reg)); \
+ u32 old_val = old ? old->params.field : 0; \
+ u32 new_val = new->params.field; \
+\
+ *(reg) &= ~(mask); \
+ *(reg) |= REG_FIELD_PREP((mask), max3(old_val, new_val, current_val)); \
+} while (0)
-:920: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'field' - possible side-effects?
#920: FILE: drivers/gpu/drm/i915/display/intel_pmdemand.c:491:
+#define update_reg(reg, field, mask) do { \
+ u32 current_val = serialized ? 0 : REG_FIELD_GET((mask), *(reg)); \
+ u32 old_val = old ? old->params.field : 0; \
+ u32 new_val = new->params.field; \
+\
+ *(reg) &= ~(mask); \
+ *(reg) |= REG_FIELD_PREP((mask), max3(old_val, new_val, current_val)); \
+} while (0)
-:920: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mask' - possible side-effects?
#920: FILE: drivers/gpu/drm/i915/display/intel_pmdemand.c:491:
+#define update_reg(reg, field, mask) do { \
+ u32 current_val = serialized ? 0 : REG_FIELD_GET((mask), *(reg)); \
+ u32 old_val = old ? old->params.field : 0; \
+ u32 new_val = new->params.field; \
+\
+ *(reg) &= ~(mask); \
+ *(reg) |= REG_FIELD_PREP((mask), max3(old_val, new_val, current_val)); \
+} while (0)
total: 0 errors, 1 warnings, 3 checks, 1016 lines checked
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for mtl: add support for pmdemand (rev15)
2023-06-06 9:35 [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand Vinod Govindapillai
` (11 preceding siblings ...)
2023-06-06 23:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for mtl: add support for pmdemand (rev15) Patchwork
@ 2023-06-06 23:31 ` Patchwork
2023-06-06 23:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-06-07 15:42 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
14 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2023-06-06 23:31 UTC (permalink / raw)
To: Vinod Govindapillai; +Cc: intel-gfx
== Series Details ==
Series: mtl: add support for pmdemand (rev15)
URL : https://patchwork.freedesktop.org/series/116949/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for mtl: add support for pmdemand (rev15)
2023-06-06 9:35 [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand Vinod Govindapillai
` (12 preceding siblings ...)
2023-06-06 23:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-06-06 23:40 ` Patchwork
2023-06-07 15:42 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
14 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2023-06-06 23:40 UTC (permalink / raw)
To: Vinod Govindapillai; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5792 bytes --]
== Series Details ==
Series: mtl: add support for pmdemand (rev15)
URL : https://patchwork.freedesktop.org/series/116949/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13238 -> Patchwork_116949v15
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/index.html
Participating hosts (41 -> 39)
------------------------------
Missing (2): bat-rpls-2 fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_116949v15 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@reset:
- bat-rpls-1: [PASS][1] -> [ABORT][2] ([i915#4983] / [i915#7461] / [i915#7981] / [i915#8347] / [i915#8384])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-rpls-1/igt@i915_selftest@live@reset.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/bat-rpls-1/igt@i915_selftest@live@reset.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][3] ([i915#7828])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/bat-dg2-11/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
- bat-adlm-1: NOTRUN -> [SKIP][4] ([i915#7828])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/bat-adlm-1/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [PASS][5] -> [FAIL][6] ([i915#7932])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlm-1: NOTRUN -> [SKIP][7] ([i915#1845])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/bat-adlm-1/igt@kms_pipe_crc_basic@suspend-read-crc.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- bat-dg2-11: [ABORT][8] ([i915#7913] / [i915#7979]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-dg2-11/igt@i915_selftest@live@hangcheck.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/bat-dg2-11/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@workarounds:
- bat-adlm-1: [INCOMPLETE][10] ([i915#4983] / [i915#7677]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-adlm-1/igt@i915_selftest@live@workarounds.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/bat-adlm-1/igt@i915_selftest@live@workarounds.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-dp-5:
- {bat-adlp-11}: [ABORT][12] -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-dp-5.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-dp-5.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4309]: https://gitlab.freedesktop.org/drm/intel/issues/4309
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6868]: https://gitlab.freedesktop.org/drm/intel/issues/6868
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7677]: https://gitlab.freedesktop.org/drm/intel/issues/7677
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7953]: https://gitlab.freedesktop.org/drm/intel/issues/7953
[i915#7979]: https://gitlab.freedesktop.org/drm/intel/issues/7979
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
[i915#8384]: https://gitlab.freedesktop.org/drm/intel/issues/8384
Build changes
-------------
* Linux: CI_DRM_13238 -> Patchwork_116949v15
CI-20190529: 20190529
CI_DRM_13238: 8c0b302811d744b945dcb6d78164a76188914db9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7320: 1c96b08a4cde6f2d49824a8cc3303bd860617b52 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116949v15: 8c0b302811d744b945dcb6d78164a76188914db9 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
8332310949bd drm/i915/mtl: Add support for PM DEMAND
322900e23c17 drm/i915/mtl: find the best QGV point for the SAGV configuration
265b91dd4a92 drm/i915: modify max_bw to return index to intel_bw_info
9a10f7cdc18c drm/i915: extract intel_bw_check_qgv_points()
b80dfd04e961 drm/i915: store the peak bw per QGV point
63a5e45d0f36 drm/i915: update the QGV point frequency calculations
11c8c8b7b224 drm/i915: fix the derating percentage for MTL
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/index.html
[-- Attachment #2: Type: text/html, Size: 6144 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for mtl: add support for pmdemand (rev15)
2023-06-06 9:35 [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand Vinod Govindapillai
` (13 preceding siblings ...)
2023-06-06 23:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-06-07 15:42 ` Patchwork
14 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2023-06-07 15:42 UTC (permalink / raw)
To: Vinod Govindapillai; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 13113 bytes --]
== Series Details ==
Series: mtl: add support for pmdemand (rev15)
URL : https://patchwork.freedesktop.org/series/116949/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13238_full -> Patchwork_116949v15_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_116949v15_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@engines-hang:
- shard-snb: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/shard-snb5/igt@gem_ctx_persistence@engines-hang.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [PASS][2] -> [FAIL][3] ([i915#2842])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/shard-glk5/igt@gem_exec_fair@basic-none-share@rcs0.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/shard-glk9/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [PASS][4] -> [FAIL][5] ([i915#2842])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/shard-apl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/shard-apl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_mmap_gtt@fault-concurrent-x:
- shard-snb: [PASS][6] -> [ABORT][7] ([i915#5161])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/shard-snb7/igt@gem_mmap_gtt@fault-concurrent-x.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/shard-snb7/igt@gem_mmap_gtt@fault-concurrent-x.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][8] -> [ABORT][9] ([i915#5566])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/shard-apl4/igt@gen9_exec_parse@allowed-single.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/shard-apl7/igt@gen9_exec_parse@allowed-single.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-180:
- shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271]) +39 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/shard-snb5/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#2122])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/shard-glk4/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/shard-glk1/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1:
- shard-glk: [PASS][13] -> [FAIL][14] ([i915#79])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/shard-glk6/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4579]) +10 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/shard-snb1/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1.html
#### Possible fixes ####
* igt@gem_barrier_race@remote-request@rcs0:
- {shard-dg1}: [ABORT][16] ([i915#7461] / [i915#8234]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/shard-dg1-18/igt@gem_barrier_race@remote-request@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/shard-dg1-19/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][18] ([i915#2842]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/shard-apl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/shard-apl2/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [FAIL][20] ([i915#2842]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/shard-glk8/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/shard-glk3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- {shard-dg1}: [SKIP][22] ([i915#1397]) -> [PASS][23] +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/shard-dg1-19/igt@i915_pm_rpm@modeset-non-lpsp.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/shard-dg1-15/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- {shard-rkl}: [SKIP][24] ([i915#1397]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/shard-rkl-4/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
* igt@i915_pm_rps@reset:
- shard-snb: [INCOMPLETE][26] ([i915#7790]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/shard-snb1/igt@i915_pm_rps@reset.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/shard-snb5/igt@i915_pm_rps@reset.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [FAIL][28] ([i915#2346]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@forked-move@pipe-b:
- {shard-dg1}: [INCOMPLETE][30] ([i915#8011] / [i915#8347]) -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/shard-dg1-19/igt@kms_cursor_legacy@forked-move@pipe-b.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/shard-dg1-12/igt@kms_cursor_legacy@forked-move@pipe-b.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [FAIL][32] ([i915#4767]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/shard-apl4/igt@kms_fbcon_fbt@fbc-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#5161]: https://gitlab.freedesktop.org/drm/intel/issues/5161
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7790]: https://gitlab.freedesktop.org/drm/intel/issues/7790
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
[i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
[i915#8516]: https://gitlab.freedesktop.org/drm/intel/issues/8516
Build changes
-------------
* Linux: CI_DRM_13238 -> Patchwork_116949v15
CI-20190529: 20190529
CI_DRM_13238: 8c0b302811d744b945dcb6d78164a76188914db9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7320: 1c96b08a4cde6f2d49824a8cc3303bd860617b52 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116949v15: 8c0b302811d744b945dcb6d78164a76188914db9 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/index.html
[-- Attachment #2: Type: text/html, Size: 10278 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH v15 7/7] drm/i915/mtl: Add support for PM DEMAND
2023-06-06 20:10 ` [Intel-gfx] [PATCH v15 " Vinod Govindapillai
@ 2023-06-07 19:57 ` Sripada, Radhakrishna
0 siblings, 0 replies; 20+ messages in thread
From: Sripada, Radhakrishna @ 2023-06-07 19:57 UTC (permalink / raw)
To: Govindapillai, Vinod, intel-gfx; +Cc: jani.saarinene
Thank you for the series and the review. Pushed with a minor spelling fix in the comment s/qclck_gc/qclk_gv/
--Radhakrishna(RK) Sripada
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Vinod
> Govindapillai
> Sent: Tuesday, June 6, 2023 1:11 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: jani.saarinene@intel.com
> Subject: [Intel-gfx] [PATCH v15 7/7] drm/i915/mtl: Add support for PM DEMAND
>
> From: Mika Kahola <mika.kahola@intel.com>
>
> MTL introduces a new way to instruct the PUnit with
> power and bandwidth requirements of DE. Add the functionality
> to program the registers and handle waits using interrupts.
> The current wait time for timeouts is programmed for 10 msecs to
> factor in the worst case scenarios. Changes made to use REG_BIT
> for a register that we touched(GEN8_DE_MISC_IER _MMIO).
>
> Wa_14016740474 is added which applies to Xe_LPD+ display
>
> v2: checkpatch warning fixes, simplify program pmdemand part
>
> v3: update to dbufs and pipes values to pmdemand register(stan)
> Removed the macro usage in update_pmdemand_values()
>
> v4: move the pmdemand_pre_plane_update before cdclk update
> pmdemand_needs_update included cdclk params comparisons
> pmdemand_state NULL check (Gustavo)
> pmdemand.o in sorted order in the makefile (Jani)
> update pmdemand misc irq handler loop (Gustavo)
> active phys bitmask and programming correction (Gustavo)
>
> v5: simplify pmdemand_state structure
> simplify methods to find active phys and max port clock
> Timeout in case of previou pmdemand task pending (Gustavo)
>
> v6: rebasing
> updates to max_ddiclk calculations (Gustavo)
> updates to active_phys count method (Gustavo)
>
> v7: use two separate loop to iterate throug old and new
> crtc states to calculate the active phys (Gustavo)
>
> v8: use uniform function names (Gustavo)
>
> v9: For phys change iterate through connectors (Imre)
> Look for change in phys for pmdemand update (Gustavo, Imre)
> Some more stlying changes (Imre)
> Update pmdemand state during HW readout/sanitize (Imre)
>
> v10: Fix CI checkpatch warnings
>
> v11: use correct pmdemand object pointer during hw readout,
> simplify the check for phys need update (Gustavo)
>
> v12: Handle possible non serialize cases (Imre)
> Initialise also pmdemand params HW readout (Imre)
> Update active phys mask during sanitize calls (Imre)
> Check TC/encoder changes to limit connector update (Imre)
>
> v13: Check display version before accessing pmdemand functions
>
> v14: Move is_serialized to intel_global_state.c
> simplify update params and other stlying issues (Imre)
>
> Bspec: 66451, 64636, 64602, 64603
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> #v4
> Acked-by: Gustavo Sousa <gustavo.sousa@intel.com> #v11
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 14 +
> .../gpu/drm/i915/display/intel_display_core.h | 9 +
> .../drm/i915/display/intel_display_driver.c | 7 +
> .../gpu/drm/i915/display/intel_display_irq.c | 23 +-
> .../drm/i915/display/intel_display_power.c | 14 +-
> .../gpu/drm/i915/display/intel_global_state.c | 12 +
> .../gpu/drm/i915/display/intel_global_state.h | 2 +
> .../drm/i915/display/intel_modeset_setup.c | 32 +
> drivers/gpu/drm/i915/display/intel_pmdemand.c | 620 ++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_pmdemand.h | 67 ++
> drivers/gpu/drm/i915/i915_reg.h | 26 +-
> 12 files changed, 821 insertions(+), 6 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 1c9ed4c52760..2cd8de174bf6 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -269,6 +269,7 @@ i915-y += \
> display/intel_pch_display.o \
> display/intel_pch_refclk.o \
> display/intel_plane_initial.o \
> + display/intel_pmdemand.o \
> display/intel_psr.o \
> display/intel_quirks.o \
> display/intel_sprite.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f51a55f4e9d0..5cbf5eae2414 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -99,6 +99,7 @@
> #include "intel_pcode.h"
> #include "intel_pipe_crc.h"
> #include "intel_plane_initial.h"
> +#include "intel_pmdemand.h"
> #include "intel_pps.h"
> #include "intel_psr.h"
> #include "intel_sdvo.h"
> @@ -6352,6 +6353,10 @@ int intel_atomic_check(struct drm_device *dev,
> return ret;
> }
>
> + ret = intel_pmdemand_atomic_check(state);
> + if (ret)
> + goto fail;
> +
> ret = intel_atomic_check_crtcs(state);
> if (ret)
> goto fail;
> @@ -6997,6 +7002,14 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
> crtc->config = new_crtc_state;
>
> + /*
> + * In XE_LPD+ Pmdemand combines many parameters such as voltage
> index,
> + * plls, cdclk frequency, QGV point selection parameter etc. Voltage
> + * index, cdclk/ddiclk frequencies are supposed to be configured before
> + * the cdclk config is set.
> + */
> + intel_pmdemand_pre_plane_update(state);
> +
> if (state->modeset) {
> drm_atomic_helper_update_legacy_modeset_state(dev,
> &state->base);
>
> @@ -7116,6 +7129,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> intel_verify_planes(state);
>
> intel_sagv_post_plane_update(state);
> + intel_pmdemand_post_plane_update(state);
>
> drm_atomic_helper_commit_hw_done(&state->base);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index dd8e08c8598f..8d2243c71dd8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -345,6 +345,15 @@ struct intel_display {
> struct intel_global_obj obj;
> } dbuf;
>
> + struct {
> + wait_queue_head_t waitqueue;
> +
> + /* mutex to protect pmdemand programming sequence */
> + struct mutex lock;
> +
> + struct intel_global_obj obj;
> + } pmdemand;
> +
> struct {
> /*
> * dkl.phy_lock protects against concurrent access of the
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index 60ce10fc7205..dc8de861339d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -47,6 +47,7 @@
> #include "intel_opregion.h"
> #include "intel_overlay.h"
> #include "intel_plane_initial.h"
> +#include "intel_pmdemand.h"
> #include "intel_pps.h"
> #include "intel_quirks.h"
> #include "intel_vga.h"
> @@ -211,6 +212,8 @@ int intel_display_driver_probe_noirq(struct
> drm_i915_private *i915)
> if (ret < 0)
> goto cleanup_vga;
>
> + intel_pmdemand_init_early(i915);
> +
> intel_power_domains_init_hw(i915, false);
>
> if (!HAS_DISPLAY(i915))
> @@ -240,6 +243,10 @@ int intel_display_driver_probe_noirq(struct
> drm_i915_private *i915)
> if (ret)
> goto cleanup_vga_client_pw_domain_dmc;
>
> + ret = intel_pmdemand_init(i915);
> + if (ret)
> + goto cleanup_vga_client_pw_domain_dmc;
> +
> init_llist_head(&i915->display.atomic_helper.free_list);
> INIT_WORK(&i915->display.atomic_helper.free_work,
> intel_atomic_helper_free_state_worker);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
> b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 3b2a287d2041..0b3739310f81 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -18,6 +18,7 @@
> #include "intel_fifo_underrun.h"
> #include "intel_gmbus.h"
> #include "intel_hotplug_irq.h"
> +#include "intel_pmdemand.h"
> #include "intel_psr.h"
> #include "intel_psr_regs.h"
>
> @@ -827,12 +828,27 @@ static u32 gen8_de_pipe_fault_mask(struct
> drm_i915_private *dev_priv)
> return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> }
>
> +static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv)
> +{
> + wake_up_all(&dev_priv->display.pmdemand.waitqueue);
> +}
> +
> static void
> gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
> {
> bool found = false;
>
> - if (iir & GEN8_DE_MISC_GSE) {
> + if (DISPLAY_VER(dev_priv) >= 14) {
> + if (iir & (XELPDP_PMDEMAND_RSP |
> + XELPDP_PMDEMAND_RSPTOUT_ERR)) {
> + if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR)
> + drm_dbg(&dev_priv->drm,
> + "Error waiting for Punit PM Demand
> Response\n");
> +
> + intel_pmdemand_irq_handler(dev_priv);
> + found = true;
> + }
> + } else if (iir & GEN8_DE_MISC_GSE) {
> intel_opregion_asle_intr(dev_priv);
> found = true;
> }
> @@ -1576,7 +1592,10 @@ void gen8_de_irq_postinstall(struct
> drm_i915_private *dev_priv)
> if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> de_port_masked |= BXT_DE_PORT_GMBUS;
>
> - if (DISPLAY_VER(dev_priv) >= 11) {
> + if (DISPLAY_VER(dev_priv) >= 14) {
> + de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR |
> + XELPDP_PMDEMAND_RSP;
> + } else if (DISPLAY_VER(dev_priv) >= 11) {
> enum port port;
>
> if (intel_bios_is_dsi_present(dev_priv, &port))
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 2f4f00ae2f57..db5437043904 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -20,6 +20,7 @@
> #include "intel_mchbar_regs.h"
> #include "intel_pch_refclk.h"
> #include "intel_pcode.h"
> +#include "intel_pmdemand.h"
> #include "intel_pps_regs.h"
> #include "intel_snps_phy.h"
> #include "skl_watermark.h"
> @@ -1082,20 +1083,29 @@ void gen9_dbuf_slices_update(struct
> drm_i915_private *dev_priv,
>
> static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
> {
> + u8 slices_mask;
> +
> dev_priv->display.dbuf.enabled_slices =
> intel_enabled_dbuf_slices_mask(dev_priv);
>
> + slices_mask = BIT(DBUF_S1) | dev_priv->display.dbuf.enabled_slices;
> +
> + if (DISPLAY_VER(dev_priv) >= 14)
> + intel_pmdemand_program_dbuf(dev_priv, slices_mask);
> +
> /*
> * Just power up at least 1 slice, we will
> * figure out later which slices we have and what we need.
> */
> - gen9_dbuf_slices_update(dev_priv, BIT(DBUF_S1) |
> - dev_priv->display.dbuf.enabled_slices);
> + gen9_dbuf_slices_update(dev_priv, slices_mask);
> }
>
> static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
> {
> gen9_dbuf_slices_update(dev_priv, 0);
> +
> + if (DISPLAY_VER(dev_priv) >= 14)
> + intel_pmdemand_program_dbuf(dev_priv, 0);
> }
>
> static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/display/intel_global_state.c
> b/drivers/gpu/drm/i915/display/intel_global_state.c
> index 02b593b1e2ea..e8e8be54143b 100644
> --- a/drivers/gpu/drm/i915/display/intel_global_state.c
> +++ b/drivers/gpu/drm/i915/display/intel_global_state.c
> @@ -255,3 +255,15 @@ int intel_atomic_serialize_global_state(struct
> intel_global_state *obj_state)
>
> return 0;
> }
> +
> +bool
> +intel_atomic_global_state_is_serialized(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(&i915->drm, crtc)
> + if (!intel_atomic_get_new_crtc_state(state, crtc))
> + return false;
> + return true;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_global_state.h
> b/drivers/gpu/drm/i915/display/intel_global_state.h
> index f01ee0bb3e5a..5477de8f0b30 100644
> --- a/drivers/gpu/drm/i915/display/intel_global_state.h
> +++ b/drivers/gpu/drm/i915/display/intel_global_state.h
> @@ -87,4 +87,6 @@ void intel_atomic_clear_global_state(struct
> intel_atomic_state *state);
> int intel_atomic_lock_global_state(struct intel_global_state *obj_state);
> int intel_atomic_serialize_global_state(struct intel_global_state *obj_state);
>
> +bool intel_atomic_global_state_is_serialized(struct intel_atomic_state *state);
> +
> #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index 5ff99ca7f1de..b8f43efb0ab5 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -26,6 +26,7 @@
> #include "intel_fifo_underrun.h"
> #include "intel_modeset_setup.h"
> #include "intel_pch_display.h"
> +#include "intel_pmdemand.h"
> #include "intel_tc.h"
> #include "intel_vblank.h"
> #include "intel_wm.h"
> @@ -115,6 +116,8 @@ static void set_encoder_for_connector(struct
> intel_connector *connector,
> static void reset_encoder_connector_state(struct intel_encoder *encoder)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_pmdemand_state *pmdemand_state =
> + to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
> struct intel_connector *connector;
> struct drm_connector_list_iter conn_iter;
>
> @@ -123,6 +126,10 @@ static void reset_encoder_connector_state(struct
> intel_encoder *encoder)
> if (connector->base.encoder != &encoder->base)
> continue;
>
> + /* Clear the corresponding bit in pmdemand active phys mask */
> + intel_pmdemand_update_phys_mask(i915, encoder,
> + pmdemand_state, false);
> +
> set_encoder_for_connector(connector, NULL);
>
> connector->base.dpms = DRM_MODE_DPMS_OFF;
> @@ -151,6 +158,8 @@ static void
> intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
> to_intel_cdclk_state(i915->display.cdclk.obj.state);
> struct intel_dbuf_state *dbuf_state =
> to_intel_dbuf_state(i915->display.dbuf.obj.state);
> + struct intel_pmdemand_state *pmdemand_state =
> + to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
> struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
> enum pipe pipe = crtc->pipe;
> @@ -174,6 +183,8 @@ static void
> intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
>
> bw_state->data_rate[pipe] = 0;
> bw_state->num_active_planes[pipe] = 0;
> +
> + intel_pmdemand_update_port_clock(i915, pmdemand_state, pipe, 0);
> }
>
> /*
> @@ -552,6 +563,8 @@ static void intel_sanitize_encoder(struct intel_encoder
> *encoder)
> struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> struct intel_crtc_state *crtc_state = crtc ?
> to_intel_crtc_state(crtc->base.state) : NULL;
> + struct intel_pmdemand_state *pmdemand_state =
> + to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
>
> /*
> * We need to check both for a crtc link (meaning that the encoder is
> @@ -575,6 +588,10 @@ static void intel_sanitize_encoder(struct intel_encoder
> *encoder)
> encoder->base.base.id,
> encoder->base.name);
>
> + /* Clear the corresponding bit in pmdemand active phys mask */
> + intel_pmdemand_update_phys_mask(i915, encoder,
> + pmdemand_state, false);
> +
> /*
> * Connector is active, but has no active pipe. This is fallout
> * from our resume register restoring. Disable the encoder
> @@ -661,6 +678,8 @@ static void intel_modeset_readout_hw_state(struct
> drm_i915_private *i915)
> to_intel_cdclk_state(i915->display.cdclk.obj.state);
> struct intel_dbuf_state *dbuf_state =
> to_intel_dbuf_state(i915->display.dbuf.obj.state);
> + struct intel_pmdemand_state *pmdemand_state =
> + to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
> enum pipe pipe;
> struct intel_crtc *crtc;
> struct intel_encoder *encoder;
> @@ -724,7 +743,15 @@ static void intel_modeset_readout_hw_state(struct
> drm_i915_private *i915)
> intel_encoder_get_config(encoder,
> slave_crtc_state);
> }
> }
> +
> + intel_pmdemand_update_phys_mask(i915, encoder,
> + pmdemand_state,
> + true);
> } else {
> + intel_pmdemand_update_phys_mask(i915, encoder,
> + pmdemand_state,
> + false);
> +
> encoder->base.crtc = NULL;
> }
>
> @@ -841,8 +868,13 @@ static void intel_modeset_readout_hw_state(struct
> drm_i915_private *i915)
> cdclk_state->min_voltage_level[crtc->pipe] =
> crtc_state->min_voltage_level;
>
> + intel_pmdemand_update_port_clock(i915, pmdemand_state,
> pipe,
> + crtc_state->port_clock);
> +
> intel_bw_crtc_update(bw_state, crtc_state);
> }
> +
> + intel_pmdemand_init_pmdemand_params(i915, pmdemand_state);
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> new file mode 100644
> index 000000000000..2f8cf29a861b
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> @@ -0,0 +1,620 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#include <linux/bitops.h>
> +
> +#include "i915_drv.h"
> +#include "i915_reg.h"
> +#include "intel_atomic.h"
> +#include "intel_bw.h"
> +#include "intel_cdclk.h"
> +#include "intel_de.h"
> +#include "intel_display_trace.h"
> +#include "intel_pmdemand.h"
> +#include "skl_watermark.h"
> +
> +static struct intel_global_state *
> +intel_pmdemand_duplicate_state(struct intel_global_obj *obj)
> +{
> + struct intel_pmdemand_state *pmdemand_state;
> +
> + pmdemand_state = kmemdup(obj->state, sizeof(*pmdemand_state),
> GFP_KERNEL);
> + if (!pmdemand_state)
> + return NULL;
> +
> + return &pmdemand_state->base;
> +}
> +
> +static void intel_pmdemand_destroy_state(struct intel_global_obj *obj,
> + struct intel_global_state *state)
> +{
> + kfree(state);
> +}
> +
> +static const struct intel_global_state_funcs intel_pmdemand_funcs = {
> + .atomic_duplicate_state = intel_pmdemand_duplicate_state,
> + .atomic_destroy_state = intel_pmdemand_destroy_state,
> +};
> +
> +static struct intel_pmdemand_state *
> +intel_atomic_get_pmdemand_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_global_state *pmdemand_state =
> + intel_atomic_get_global_obj_state(state,
> + &i915-
> >display.pmdemand.obj);
> +
> + if (IS_ERR(pmdemand_state))
> + return ERR_CAST(pmdemand_state);
> +
> + return to_intel_pmdemand_state(pmdemand_state);
> +}
> +
> +static struct intel_pmdemand_state *
> +intel_atomic_get_old_pmdemand_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_global_state *pmdemand_state =
> + intel_atomic_get_old_global_obj_state(state,
> + &i915-
> >display.pmdemand.obj);
> +
> + if (!pmdemand_state)
> + return NULL;
> +
> + return to_intel_pmdemand_state(pmdemand_state);
> +}
> +
> +static struct intel_pmdemand_state *
> +intel_atomic_get_new_pmdemand_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_global_state *pmdemand_state =
> + intel_atomic_get_new_global_obj_state(state,
> + &i915-
> >display.pmdemand.obj);
> +
> + if (!pmdemand_state)
> + return NULL;
> +
> + return to_intel_pmdemand_state(pmdemand_state);
> +}
> +
> +int intel_pmdemand_init(struct drm_i915_private *i915)
> +{
> + struct intel_pmdemand_state *pmdemand_state;
> +
> + pmdemand_state = kzalloc(sizeof(*pmdemand_state), GFP_KERNEL);
> + if (!pmdemand_state)
> + return -ENOMEM;
> +
> + intel_atomic_global_obj_init(i915, &i915->display.pmdemand.obj,
> + &pmdemand_state->base,
> + &intel_pmdemand_funcs);
> +
> + if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> + /* Wa_14016740474 */
> + intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0,
> DMD_RSP_TIMEOUT_DISABLE);
> +
> + return 0;
> +}
> +
> +void intel_pmdemand_init_early(struct drm_i915_private *i915)
> +{
> + mutex_init(&i915->display.pmdemand.lock);
> + init_waitqueue_head(&i915->display.pmdemand.waitqueue);
> +}
> +
> +void
> +intel_pmdemand_update_phys_mask(struct drm_i915_private *i915,
> + struct intel_encoder *encoder,
> + struct intel_pmdemand_state
> *pmdemand_state,
> + bool set_bit)
> +{
> + enum phy phy;
> +
> + if (DISPLAY_VER(i915) < 14)
> + return;
> +
> + if (!encoder)
> + return;
> +
> + phy = intel_port_to_phy(i915, encoder->port);
> + if (intel_phy_is_tc(i915, phy))
> + return;
> +
> + if (set_bit)
> + pmdemand_state->active_combo_phys_mask |= BIT(phy);
> + else
> + pmdemand_state->active_combo_phys_mask &= ~BIT(phy);
> +}
> +
> +void
> +intel_pmdemand_update_port_clock(struct drm_i915_private *i915,
> + struct intel_pmdemand_state
> *pmdemand_state,
> + enum pipe pipe, int port_clock)
> +{
> + if (DISPLAY_VER(i915) < 14)
> + return;
> +
> + pmdemand_state->ddi_clocks[pipe] = port_clock;
> +}
> +
> +static void
> +intel_pmdemand_update_max_ddiclk(struct drm_i915_private *i915,
> + struct intel_atomic_state *state,
> + struct intel_pmdemand_state
> *pmdemand_state)
> +{
> + int max_ddiclk = 0;
> + const struct intel_crtc_state *new_crtc_state;
> + struct intel_crtc *crtc;
> + int i;
> +
> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
> + intel_pmdemand_update_port_clock(i915, pmdemand_state,
> + crtc->pipe,
> + new_crtc_state->port_clock);
> +
> + for (i = 0; i < ARRAY_SIZE(pmdemand_state->ddi_clocks); i++)
> + max_ddiclk = max(pmdemand_state->ddi_clocks[i],
> max_ddiclk);
> +
> + pmdemand_state->params.ddiclk_max = DIV_ROUND_UP(max_ddiclk,
> 1000);
> +}
> +
> +static void
> +intel_pmdemand_update_connector_phys(struct drm_i915_private *i915,
> + struct intel_atomic_state *state,
> + struct drm_connector_state *conn_state,
> + bool set_bit,
> + struct intel_pmdemand_state
> *pmdemand_state)
> +{
> + struct intel_encoder *encoder = to_intel_encoder(conn_state-
> >best_encoder);
> + struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
> + struct intel_crtc_state *crtc_state;
> +
> + if (!crtc)
> + return;
> +
> + if (set_bit)
> + crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> + else
> + crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
> +
> + if (!crtc_state->hw.active)
> + return;
> +
> + intel_pmdemand_update_phys_mask(i915, encoder, pmdemand_state,
> + set_bit);
> +}
> +
> +static void
> +intel_pmdemand_update_active_non_tc_phys(struct drm_i915_private *i915,
> + struct intel_atomic_state *state,
> + struct intel_pmdemand_state
> *pmdemand_state)
> +{
> + struct drm_connector_state *old_conn_state;
> + struct drm_connector_state *new_conn_state;
> + struct drm_connector *connector;
> + int i;
> +
> + for_each_oldnew_connector_in_state(&state->base, connector,
> + old_conn_state, new_conn_state, i) {
> + if (!intel_connector_needs_modeset(state, connector))
> + continue;
> +
> + /* First clear the active phys in the old connector state */
> + intel_pmdemand_update_connector_phys(i915, state,
> + old_conn_state, false,
> + pmdemand_state);
> +
> + /* Then set the active phys in new connector state */
> + intel_pmdemand_update_connector_phys(i915, state,
> + new_conn_state, true,
> + pmdemand_state);
> + }
> +
> + pmdemand_state->params.active_phys =
> + min_t(u16, hweight16(pmdemand_state-
> >active_combo_phys_mask),
> + 7);
> +}
> +
> +static bool
> +intel_pmdemand_encoder_has_tc_phy(struct drm_i915_private *i915,
> + struct intel_encoder *encoder)
> +{
> + enum phy phy;
> +
> + if (!encoder)
> + return false;
> +
> + phy = intel_port_to_phy(i915, encoder->port);
> +
> + return intel_phy_is_tc(i915, phy);
> +}
> +
> +static bool
> +intel_pmdemand_connector_needs_update(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct drm_connector_state *old_conn_state;
> + struct drm_connector_state *new_conn_state;
> + struct drm_connector *connector;
> + int i;
> +
> + for_each_oldnew_connector_in_state(&state->base, connector,
> + old_conn_state, new_conn_state, i) {
> + struct intel_encoder *old_encoder =
> + to_intel_encoder(old_conn_state->best_encoder);
> + struct intel_encoder *new_encoder =
> + to_intel_encoder(new_conn_state->best_encoder);
> +
> + if (!intel_connector_needs_modeset(state, connector))
> + continue;
> +
> + if (old_encoder == new_encoder ||
> + (intel_pmdemand_encoder_has_tc_phy(i915, old_encoder)
> &&
> + intel_pmdemand_encoder_has_tc_phy(i915, new_encoder)))
> + continue;
> +
> + return true;
> + }
> +
> + return false;
> +}
> +
> +static bool intel_pmdemand_needs_update(struct intel_atomic_state *state)
> +{
> + const struct intel_bw_state *new_bw_state, *old_bw_state;
> + const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state;
> + const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> + const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
> + struct intel_crtc *crtc;
> + int i;
> +
> + new_bw_state = intel_atomic_get_new_bw_state(state);
> + old_bw_state = intel_atomic_get_old_bw_state(state);
> + if (new_bw_state && new_bw_state->qgv_point_peakbw !=
> + old_bw_state->qgv_point_peakbw)
> + return true;
> +
> + new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
> + old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
> + if (new_dbuf_state &&
> + (new_dbuf_state->active_pipes !=
> + old_dbuf_state->active_pipes ||
> + new_dbuf_state->enabled_slices !=
> + old_dbuf_state->enabled_slices))
> + return true;
> +
> + new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
> + old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
> + if (new_cdclk_state &&
> + (new_cdclk_state->actual.cdclk !=
> + old_cdclk_state->actual.cdclk ||
> + new_cdclk_state->actual.voltage_level !=
> + old_cdclk_state->actual.voltage_level))
> + return true;
> +
> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> + new_crtc_state, i)
> + if (new_crtc_state->port_clock != old_crtc_state->port_clock)
> + return true;
> +
> + return intel_pmdemand_connector_needs_update(state);
> +}
> +
> +int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + const struct intel_bw_state *new_bw_state;
> + const struct intel_cdclk_state *new_cdclk_state;
> + const struct intel_dbuf_state *new_dbuf_state;
> + struct intel_pmdemand_state *new_pmdemand_state;
> +
> + if (DISPLAY_VER(i915) < 14)
> + return 0;
> +
> + if (!intel_pmdemand_needs_update(state))
> + return 0;
> +
> + new_pmdemand_state = intel_atomic_get_pmdemand_state(state);
> + if (IS_ERR(new_pmdemand_state))
> + return PTR_ERR(new_pmdemand_state);
> +
> + new_bw_state = intel_atomic_get_bw_state(state);
> + if (IS_ERR(new_bw_state))
> + return PTR_ERR(new_bw_state);
> +
> + /* firmware will calculate the qclck_gc_index, requirement is set to 0 */
> + new_pmdemand_state->params.qclk_gv_index = 0;
> + new_pmdemand_state->params.qclk_gv_bw = new_bw_state-
> >qgv_point_peakbw;
> +
> + new_dbuf_state = intel_atomic_get_dbuf_state(state);
> + if (IS_ERR(new_dbuf_state))
> + return PTR_ERR(new_dbuf_state);
> +
> + new_pmdemand_state->params.active_pipes =
> + min_t(u8, hweight8(new_dbuf_state->active_pipes), 3);
> + new_pmdemand_state->params.active_dbufs =
> + min_t(u8, hweight8(new_dbuf_state->enabled_slices), 3);
> +
> + new_cdclk_state = intel_atomic_get_cdclk_state(state);
> + if (IS_ERR(new_cdclk_state))
> + return PTR_ERR(new_cdclk_state);
> +
> + new_pmdemand_state->params.voltage_index =
> + new_cdclk_state->actual.voltage_level;
> + new_pmdemand_state->params.cdclk_freq_mhz =
> + DIV_ROUND_UP(new_cdclk_state->actual.cdclk, 1000);
> +
> + intel_pmdemand_update_max_ddiclk(i915, state,
> new_pmdemand_state);
> +
> + intel_pmdemand_update_active_non_tc_phys(i915, state,
> new_pmdemand_state);
> +
> + /*
> + * Active_PLLs starts with 1 because of CDCLK PLL.
> + * TODO: Missing to account genlock filter when it gets used.
> + */
> + new_pmdemand_state->params.plls =
> + min_t(u16, new_pmdemand_state->params.active_phys + 1, 7);
> +
> + /*
> + * Setting scalers to max as it can not be calculated during flips and
> + * fastsets without taking global states locks.
> + */
> + new_pmdemand_state->params.scalers = 7;
> +
> + if (state->base.allow_modeset)
> + return
> intel_atomic_serialize_global_state(&new_pmdemand_state->base);
> + else
> + return
> intel_atomic_lock_global_state(&new_pmdemand_state->base);
> +}
> +
> +static bool intel_pmdemand_check_prev_transaction(struct drm_i915_private
> *i915)
> +{
> + return !(intel_de_wait_for_clear(i915,
> +
> XELPDP_INITIATE_PMDEMAND_REQUEST(1),
> + XELPDP_PMDEMAND_REQ_ENABLE,
> 10) ||
> + intel_de_wait_for_clear(i915,
> + GEN12_DCPR_STATUS_1,
> +
> XELPDP_PMDEMAND_INFLIGHT_STATUS, 10));
> +}
> +
> +void
> +intel_pmdemand_init_pmdemand_params(struct drm_i915_private *i915,
> + struct intel_pmdemand_state
> *pmdemand_state)
> +{
> + u32 reg1, reg2;
> +
> + if (DISPLAY_VER(i915) < 14)
> + return;
> +
> + mutex_lock(&i915->display.pmdemand.lock);
> + if (drm_WARN_ON(&i915->drm,
> + !intel_pmdemand_check_prev_transaction(i915))) {
> + memset(&pmdemand_state->params, 0,
> + sizeof(pmdemand_state->params));
> + goto unlock;
> + }
> +
> + reg1 = intel_de_read(i915,
> XELPDP_INITIATE_PMDEMAND_REQUEST(0));
> +
> + reg2 = intel_de_read(i915,
> XELPDP_INITIATE_PMDEMAND_REQUEST(1));
> +
> + /* Set 1*/
> + pmdemand_state->params.qclk_gv_bw =
> + REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_BW_MASK,
> reg1);
> + pmdemand_state->params.voltage_index =
> + REG_FIELD_GET(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK,
> reg1);
> + pmdemand_state->params.qclk_gv_index =
> + REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK,
> reg1);
> + pmdemand_state->params.active_pipes =
> + REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, reg1);
> + pmdemand_state->params.active_dbufs =
> + REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, reg1);
> + pmdemand_state->params.active_phys =
> + REG_FIELD_GET(XELPDP_PMDEMAND_PHYS_MASK, reg1);
> +
> + /* Set 2*/
> + pmdemand_state->params.cdclk_freq_mhz =
> + REG_FIELD_GET(XELPDP_PMDEMAND_CDCLK_FREQ_MASK,
> reg2);
> + pmdemand_state->params.ddiclk_max =
> + REG_FIELD_GET(XELPDP_PMDEMAND_DDICLK_FREQ_MASK,
> reg2);
> + pmdemand_state->params.scalers =
> + REG_FIELD_GET(XELPDP_PMDEMAND_SCALERS_MASK, reg2);
> +
> +unlock:
> + mutex_unlock(&i915->display.pmdemand.lock);
> +}
> +
> +static bool intel_pmdemand_req_complete(struct drm_i915_private *i915)
> +{
> + return !(intel_de_read(i915,
> XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
> + XELPDP_PMDEMAND_REQ_ENABLE);
> +}
> +
> +static void intel_pmdemand_wait(struct drm_i915_private *i915)
> +{
> + if (!wait_event_timeout(i915->display.pmdemand.waitqueue,
> + intel_pmdemand_req_complete(i915),
> + msecs_to_jiffies_timeout(10)))
> + drm_err(&i915->drm,
> + "timed out waiting for Punit PM Demand Response\n");
> +}
> +
> +/* Required to be programmed during Display Init Sequences. */
> +void intel_pmdemand_program_dbuf(struct drm_i915_private *i915,
> + u8 dbuf_slices)
> +{
> + u32 dbufs = min_t(u32, hweight8(dbuf_slices), 3);
> +
> + mutex_lock(&i915->display.pmdemand.lock);
> + if (drm_WARN_ON(&i915->drm,
> + !intel_pmdemand_check_prev_transaction(i915)))
> + goto unlock;
> +
> + intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
> + XELPDP_PMDEMAND_DBUFS_MASK,
> + REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK,
> dbufs));
> + intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
> + XELPDP_PMDEMAND_REQ_ENABLE);
> +
> + intel_pmdemand_wait(i915);
> +
> +unlock:
> + mutex_unlock(&i915->display.pmdemand.lock);
> +}
> +
> +static void
> +intel_pmdemand_update_params(const struct intel_pmdemand_state *new,
> + const struct intel_pmdemand_state *old,
> + u32 *reg1, u32 *reg2, bool serialized)
> +{
> + /*
> + * The pmdemand parameter updates happens in two steps. Pre plane
> and
> + * post plane updates. During the pre plane, as DE might still be
> + * handling with some old operations, to avoid unexpected performance
> + * issues, program the pmdemand parameters with higher of old and
> new
> + * values. And then after once settled, use the new parameter values
> + * as part of the post plane update.
> + *
> + * If the pmdemand params update happens without modeset allowed,
> this
> + * means we can't serialize the updates. So that implies possibility of
> + * some parallel atomic commits affecting the pmdemand parameters.
> In
> + * that case, we need to consider the current values from the register
> + * as well. So in pre-plane case, we need to check the max of old, new
> + * and current register value if not serialized. In post plane update
> + * we need to consider max of new and current register value if not
> + * serialized
> + */
> +
> +#define update_reg(reg, field, mask) do { \
> + u32 current_val = serialized ? 0 : REG_FIELD_GET((mask), *(reg)); \
> + u32 old_val = old ? old->params.field : 0; \
> + u32 new_val = new->params.field; \
> +\
> + *(reg) &= ~(mask); \
> + *(reg) |= REG_FIELD_PREP((mask), max3(old_val, new_val,
> current_val)); \
> +} while (0)
> +
> + /* Set 1*/
> + update_reg(reg1, qclk_gv_bw,
> XELPDP_PMDEMAND_QCLK_GV_BW_MASK);
> + update_reg(reg1, voltage_index,
> XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK);
> + update_reg(reg1, qclk_gv_index,
> XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK);
> + update_reg(reg1, active_pipes, XELPDP_PMDEMAND_PIPES_MASK);
> + update_reg(reg1, active_dbufs, XELPDP_PMDEMAND_DBUFS_MASK);
> + update_reg(reg1, active_phys, XELPDP_PMDEMAND_PHYS_MASK);
> +
> + /* Set 2*/
> + update_reg(reg2, cdclk_freq_mhz,
> XELPDP_PMDEMAND_CDCLK_FREQ_MASK);
> + update_reg(reg2, ddiclk_max,
> XELPDP_PMDEMAND_DDICLK_FREQ_MASK);
> + update_reg(reg2, scalers, XELPDP_PMDEMAND_SCALERS_MASK);
> + update_reg(reg2, plls, XELPDP_PMDEMAND_PLLS_MASK);
> +
> +#undef update_reg
> +}
> +
> +static void
> +intel_pmdemand_program_params(struct drm_i915_private *i915,
> + const struct intel_pmdemand_state *new,
> + const struct intel_pmdemand_state *old,
> + bool serialized)
> +{
> + bool changed = false;
> + u32 reg1, mod_reg1;
> + u32 reg2, mod_reg2;
> +
> + mutex_lock(&i915->display.pmdemand.lock);
> + if (drm_WARN_ON(&i915->drm,
> + !intel_pmdemand_check_prev_transaction(i915)))
> + goto unlock;
> +
> + reg1 = intel_de_read(i915,
> XELPDP_INITIATE_PMDEMAND_REQUEST(0));
> + mod_reg1 = reg1;
> +
> + reg2 = intel_de_read(i915,
> XELPDP_INITIATE_PMDEMAND_REQUEST(1));
> + mod_reg2 = reg2;
> +
> + intel_pmdemand_update_params(new, old, &mod_reg1, &mod_reg2,
> + serialized);
> +
> + if (reg1 != mod_reg1) {
> + intel_de_write(i915,
> XELPDP_INITIATE_PMDEMAND_REQUEST(0),
> + mod_reg1);
> + changed = true;
> + }
> +
> + if (reg2 != mod_reg2) {
> + intel_de_write(i915,
> XELPDP_INITIATE_PMDEMAND_REQUEST(1),
> + mod_reg2);
> + changed = true;
> + }
> +
> + /* Initiate pm demand request only if register values are changed */
> + if (!changed)
> + goto unlock;
> +
> + drm_dbg_kms(&i915->drm,
> + "initate pmdemand request values: (0x%x 0x%x)\n",
> + mod_reg1, mod_reg2);
> +
> + intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
> + XELPDP_PMDEMAND_REQ_ENABLE);
> +
> + intel_pmdemand_wait(i915);
> +
> +unlock:
> + mutex_unlock(&i915->display.pmdemand.lock);
> +}
> +
> +static bool
> +intel_pmdemand_state_changed(const struct intel_pmdemand_state *new,
> + const struct intel_pmdemand_state *old)
> +{
> + return memcmp(&new->params, &old->params, sizeof(new->params))
> != 0;
> +}
> +
> +void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + const struct intel_pmdemand_state *new_pmdemand_state =
> + intel_atomic_get_new_pmdemand_state(state);
> + const struct intel_pmdemand_state *old_pmdemand_state =
> + intel_atomic_get_old_pmdemand_state(state);
> +
> + if (DISPLAY_VER(i915) < 14)
> + return;
> +
> + if (!new_pmdemand_state ||
> + !intel_pmdemand_state_changed(new_pmdemand_state,
> + old_pmdemand_state))
> + return;
> +
> + WARN_ON(!new_pmdemand_state->base.changed);
> +
> + intel_pmdemand_program_params(i915, new_pmdemand_state,
> + old_pmdemand_state,
> +
> intel_atomic_global_state_is_serialized(state));
> +}
> +
> +void intel_pmdemand_post_plane_update(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + const struct intel_pmdemand_state *new_pmdemand_state =
> + intel_atomic_get_new_pmdemand_state(state);
> + const struct intel_pmdemand_state *old_pmdemand_state =
> + intel_atomic_get_old_pmdemand_state(state);
> +
> + if (DISPLAY_VER(i915) < 14)
> + return;
> +
> + if (!new_pmdemand_state ||
> + !intel_pmdemand_state_changed(new_pmdemand_state,
> + old_pmdemand_state))
> + return;
> +
> + WARN_ON(!new_pmdemand_state->base.changed);
> +
> + intel_pmdemand_program_params(i915, new_pmdemand_state, NULL,
> +
> intel_atomic_global_state_is_serialized(state));
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.h
> b/drivers/gpu/drm/i915/display/intel_pmdemand.h
> new file mode 100644
> index 000000000000..2941a1a18b72
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.h
> @@ -0,0 +1,67 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef __INTEL_PMDEMAND_H__
> +#define __INTEL_PMDEMAND_H__
> +
> +#include "intel_display_limits.h"
> +#include "intel_global_state.h"
> +
> +struct drm_i915_private;
> +struct intel_atomic_state;
> +struct intel_crtc_state;
> +struct intel_encoder;
> +struct intel_plane_state;
> +
> +struct pmdemand_params {
> + u16 qclk_gv_bw;
> + u8 voltage_index;
> + u8 qclk_gv_index;
> + u8 active_pipes;
> + u8 active_dbufs;
> + /* Total number of non type C active phys from active_phys_mask */
> + u8 active_phys;
> + u8 plls;
> + u16 cdclk_freq_mhz;
> + /* max from ddi_clocks[] */
> + u16 ddiclk_max;
> + u8 scalers;
> +};
> +
> +struct intel_pmdemand_state {
> + struct intel_global_state base;
> +
> + /* Maintain a persistent list of port clocks across all crtcs */
> + int ddi_clocks[I915_MAX_PIPES];
> +
> + /* Maintain a persistent list of non type C phys mask */
> + u16 active_combo_phys_mask;
> +
> + /* Parameters to be configured in the pmdemand registers */
> + struct pmdemand_params params;
> +};
> +
> +#define to_intel_pmdemand_state(x) container_of((x), \
> + struct intel_pmdemand_state,
> \
> + base)
> +
> +void intel_pmdemand_init_early(struct drm_i915_private *i915);
> +int intel_pmdemand_init(struct drm_i915_private *i915);
> +void intel_pmdemand_init_pmdemand_params(struct drm_i915_private *i915,
> + struct intel_pmdemand_state
> *pmdemand_state);
> +void intel_pmdemand_update_port_clock(struct drm_i915_private *i915,
> + struct intel_pmdemand_state
> *pmdemand_state,
> + enum pipe pipe, int port_clock);
> +void intel_pmdemand_update_phys_mask(struct drm_i915_private *i915,
> + struct intel_encoder *encoder,
> + struct intel_pmdemand_state
> *pmdemand_state,
> + bool clear_bit);
> +void intel_pmdemand_program_dbuf(struct drm_i915_private *i915,
> + u8 dbuf_slices);
> +void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state);
> +void intel_pmdemand_post_plane_update(struct intel_atomic_state *state);
> +int intel_pmdemand_atomic_check(struct intel_atomic_state *state);
> +
> +#endif /* __INTEL_PMDEMAND_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0523418129c5..27d75215d3eb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4418,8 +4418,10 @@
> #define GEN8_DE_MISC_IMR _MMIO(0x44464)
> #define GEN8_DE_MISC_IIR _MMIO(0x44468)
> #define GEN8_DE_MISC_IER _MMIO(0x4446c)
> -#define GEN8_DE_MISC_GSE (1 << 27)
> -#define GEN8_DE_EDP_PSR (1 << 19)
> +#define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27)
> +#define GEN8_DE_MISC_GSE REG_BIT(27)
> +#define GEN8_DE_EDP_PSR REG_BIT(19)
> +#define XELPDP_PMDEMAND_RSP REG_BIT(3)
>
> #define GEN8_PCU_ISR _MMIO(0x444e0)
> #define GEN8_PCU_IMR _MMIO(0x444e4)
> @@ -4504,6 +4506,23 @@
> #define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1)
> #define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0)
>
> +#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword)
> _MMIO(0x45230 + 4 * (dword))
> +#define XELPDP_PMDEMAND_QCLK_GV_BW_MASK
> REG_GENMASK(31, 16)
> +#define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK
> REG_GENMASK(14, 12)
> +#define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK
> REG_GENMASK(11, 8)
> +#define XELPDP_PMDEMAND_PIPES_MASK
> REG_GENMASK(7, 6)
> +#define XELPDP_PMDEMAND_DBUFS_MASK
> REG_GENMASK(5, 4)
> +#define XELPDP_PMDEMAND_PHYS_MASK
> REG_GENMASK(2, 0)
> +
> +#define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31)
> +#define XELPDP_PMDEMAND_CDCLK_FREQ_MASK
> REG_GENMASK(30, 20)
> +#define XELPDP_PMDEMAND_DDICLK_FREQ_MASK
> REG_GENMASK(18, 8)
> +#define XELPDP_PMDEMAND_SCALERS_MASK
> REG_GENMASK(6, 4)
> +#define XELPDP_PMDEMAND_PLLS_MASK
> REG_GENMASK(2, 0)
> +
> +#define GEN12_DCPR_STATUS_1
> _MMIO(0x46440)
> +#define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26)
> +
> #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
> /* Required on all Ironlake and Sandybridge according to the B-Spec. */
> #define ILK_ELPIN_409_SELECT REG_BIT(25)
> @@ -4663,6 +4682,9 @@
> #define DCPR_SEND_RESP_IMM REG_BIT(25)
> #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
>
> +#define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438)
> +#define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19)
> +
> #define SKL_DFSM _MMIO(0x51000)
> #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
> #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
> --
> 2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2023-06-07 19:57 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-06 9:35 [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand Vinod Govindapillai
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 1/7] drm/i915: fix the derating percentage for MTL Vinod Govindapillai
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 2/7] drm/i915: update the QGV point frequency calculations Vinod Govindapillai
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 3/7] drm/i915: store the peak bw per QGV point Vinod Govindapillai
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 4/7] drm/i915: extract intel_bw_check_qgv_points() Vinod Govindapillai
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 5/7] drm/i915: modify max_bw to return index to intel_bw_info Vinod Govindapillai
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 6/7] drm/i915/mtl: find the best QGV point for the SAGV configuration Vinod Govindapillai
2023-06-06 9:35 ` [Intel-gfx] [PATCH v14 7/7] drm/i915/mtl: Add support for PM DEMAND Vinod Govindapillai
2023-06-06 13:50 ` Imre Deak
2023-06-06 20:10 ` [Intel-gfx] [PATCH v15 " Vinod Govindapillai
2023-06-07 19:57 ` Sripada, Radhakrishna
2023-06-06 10:32 ` [Intel-gfx] [PATCH v14 0/7] mtl: add support for pmdemand Jani Nikula
2023-06-06 10:48 ` Govindapillai, Vinod
2023-06-06 14:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for mtl: add support for pmdemand (rev14) Patchwork
2023-06-06 14:15 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-06-06 14:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-06-06 23:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for mtl: add support for pmdemand (rev15) Patchwork
2023-06-06 23:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-06-06 23:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-06-07 15:42 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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