From: "Kahola, Mika" <mika.kahola@intel.com>
To: "Deak, Imre" <imre.deak@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 25/29] drm/i915/adlp/tc: Align the connect/disconnect PHY sequence with bspec
Date: Tue, 28 Mar 2023 10:13:04 +0000 [thread overview]
Message-ID: <MW4PR11MB7054E5858E272D6D8AAB9C22EF889@MW4PR11MB7054.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20230323142035.1432621-26-imre.deak@intel.com>
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Imre
> Deak
> Sent: Thursday, March 23, 2023 4:21 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 25/29] drm/i915/adlp/tc: Align the
> connect/disconnect PHY sequence with bspec
>
> Bspec has updated the TC connect/disconnect sequences, add the required
> platform hooks for these.
>
> The difference wrt. the old sequence is the order of taking the PHY ownership -
> while holding a port power reference this requires - and blocking the TC-cold
> power state.
>
> Bspec: 49294
>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_tc.c | 111 ++++++++++++++++++++----
> 1 file changed, 94 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> b/drivers/gpu/drm/i915/display/intel_tc.c
> index f202ba324fd0a..36454ec5e8e09 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -59,7 +59,6 @@ static enum intel_display_power_domain
> tc_phy_cold_off_domain(struct intel_tc_port *); static u32
> tc_phy_hpd_live_status(struct intel_tc_port *tc); static bool
> tc_phy_is_ready(struct intel_tc_port *tc); -static bool
> tc_phy_take_ownership(struct intel_tc_port *tc, bool take); static enum
> tc_port_mode tc_phy_get_current_mode(struct intel_tc_port *tc);
>
> static const char *tc_port_mode_name(enum tc_port_mode mode) @@ -581,7
> +580,7 @@ static bool icl_tc_phy_connect(struct intel_tc_port *tc,
> return true;
>
> if ((!tc_phy_is_ready(tc) ||
> - !tc_phy_take_ownership(tc, true)) &&
> + !icl_tc_phy_take_ownership(tc, true)) &&
> !drm_WARN_ON(&i915->drm, tc->mode == TC_PORT_LEGACY)) {
> drm_dbg_kms(&i915->drm, "Port %s: can't take PHY ownership
> (ready %s)\n",
> tc->port_name,
> @@ -596,7 +595,7 @@ static bool icl_tc_phy_connect(struct intel_tc_port *tc,
> return true;
>
> out_release_phy:
> - tc_phy_take_ownership(tc, false);
> + icl_tc_phy_take_ownership(tc, false);
> out_unblock_tc_cold:
> tc_cold_unblock(tc, fetch_and_zero(&tc->lock_wakeref));
>
> @@ -612,7 +611,7 @@ static void icl_tc_phy_disconnect(struct intel_tc_port
> *tc)
> switch (tc->mode) {
> case TC_PORT_LEGACY:
> case TC_PORT_DP_ALT:
> - tc_phy_take_ownership(tc, false);
> + icl_tc_phy_take_ownership(tc, false);
> fallthrough;
> case TC_PORT_TBT_ALT:
> tc_cold_unblock(tc, fetch_and_zero(&tc->lock_wakeref));
> @@ -769,6 +768,94 @@ static bool adlp_tc_phy_is_owned(struct intel_tc_port
> *tc)
> return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP; }
>
> +static void adlp_tc_phy_get_hw_state(struct intel_tc_port *tc) {
> + struct drm_i915_private *i915 = tc_to_i915(tc);
> + enum intel_display_power_domain port_power_domain =
> + tc_port_power_domain(tc);
> + intel_wakeref_t port_wakeref;
> +
> + port_wakeref = intel_display_power_get(i915, port_power_domain);
> +
> + tc->mode = tc_phy_get_current_mode(tc);
> + if (tc->mode != TC_PORT_DISCONNECTED)
> + tc->lock_wakeref = tc_cold_block(tc);
> +
> + intel_display_power_put(i915, port_power_domain, port_wakeref); }
> +
> +static bool adlp_tc_phy_connect(struct intel_tc_port *tc, int
> +required_lanes) {
> + struct drm_i915_private *i915 = tc_to_i915(tc);
> + enum intel_display_power_domain port_power_domain =
> + tc_port_power_domain(tc);
> + intel_wakeref_t port_wakeref;
> +
> + if (tc->mode == TC_PORT_TBT_ALT) {
> + tc->lock_wakeref = tc_cold_block(tc);
> + return true;
> + }
> +
> + port_wakeref = intel_display_power_get(i915, port_power_domain);
> +
> + if (!adlp_tc_phy_take_ownership(tc, true) &&
> + !drm_WARN_ON(&i915->drm, tc->mode == TC_PORT_LEGACY)) {
> + drm_dbg_kms(&i915->drm, "Port %s: can't take PHY
> ownership\n",
> + tc->port_name);
> + goto out_put_port_power;
> + }
> +
> + if (!tc_phy_is_ready(tc) &&
> + !drm_WARN_ON(&i915->drm, tc->mode == TC_PORT_LEGACY)) {
> + drm_dbg_kms(&i915->drm, "Port %s: PHY not ready\n",
> + tc->port_name);
> + goto out_release_phy;
> + }
> +
> + tc->lock_wakeref = tc_cold_block(tc);
> +
> + if (!tc_phy_verify_legacy_or_dp_alt_mode(tc, required_lanes))
> + goto out_unblock_tc_cold;
> +
> + intel_display_power_put(i915, port_power_domain, port_wakeref);
> +
> + return true;
> +
> +out_unblock_tc_cold:
> + tc_cold_unblock(tc, fetch_and_zero(&tc->lock_wakeref));
> +out_release_phy:
> + adlp_tc_phy_take_ownership(tc, false);
> +out_put_port_power:
> + intel_display_power_put(i915, port_power_domain, port_wakeref);
> +
> + return false;
> +}
> +
> +static void adlp_tc_phy_disconnect(struct intel_tc_port *tc) {
> + struct drm_i915_private *i915 = tc_to_i915(tc);
> + enum intel_display_power_domain port_power_domain =
> + tc_port_power_domain(tc);
> + intel_wakeref_t port_wakeref;
> +
> + port_wakeref = intel_display_power_get(i915, port_power_domain);
> +
> + tc_cold_unblock(tc, fetch_and_zero(&tc->lock_wakeref));
> +
> + switch (tc->mode) {
> + case TC_PORT_LEGACY:
> + case TC_PORT_DP_ALT:
> + adlp_tc_phy_take_ownership(tc, false);
> + fallthrough;
> + case TC_PORT_TBT_ALT:
> + break;
> + default:
> + MISSING_CASE(tc->mode);
> + }
> +
> + intel_display_power_put(i915, port_power_domain, port_wakeref); }
> +
> static void adlp_tc_phy_init(struct intel_tc_port *tc) {
> tc_phy_load_fia_params(tc, true);
> @@ -779,9 +866,9 @@ static const struct intel_tc_phy_ops adlp_tc_phy_ops = {
> .hpd_live_status = adlp_tc_phy_hpd_live_status,
> .is_ready = adlp_tc_phy_is_ready,
> .is_owned = adlp_tc_phy_is_owned,
> - .get_hw_state = icl_tc_phy_get_hw_state,
> - .connect = icl_tc_phy_connect,
> - .disconnect = icl_tc_phy_disconnect,
> + .get_hw_state = adlp_tc_phy_get_hw_state,
> + .connect = adlp_tc_phy_connect,
> + .disconnect = adlp_tc_phy_disconnect,
> .init = adlp_tc_phy_init,
> };
>
> @@ -823,16 +910,6 @@ static void tc_phy_get_hw_state(struct intel_tc_port
> *tc)
> tc->phy_ops->get_hw_state(tc);
> }
>
> -static bool tc_phy_take_ownership(struct intel_tc_port *tc, bool take) -{
> - struct drm_i915_private *i915 = tc_to_i915(tc);
> -
> - if (IS_ALDERLAKE_P(i915))
> - return adlp_tc_phy_take_ownership(tc, take);
> -
> - return icl_tc_phy_take_ownership(tc, take);
> -}
> -
> static bool tc_phy_is_ready_and_owned(struct intel_tc_port *tc,
> bool phy_is_ready, bool phy_is_owned) {
> --
> 2.37.1
next prev parent reply other threads:[~2023-03-28 10:13 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-23 14:20 [Intel-gfx] [PATCH 00/29] drm/i915/tc: Align the ADLP TypeC sequences with bspec Imre Deak
2023-03-23 14:20 ` [Intel-gfx] [PATCH 01/29] drm/i915/tc: Group the TC PHY setup/query functions per platform Imre Deak
2023-03-23 14:33 ` Jani Nikula
2023-03-24 9:36 ` Kahola, Mika
2023-03-23 16:50 ` kernel test robot
2023-03-23 16:50 ` kernel test robot
2023-03-23 14:20 ` [Intel-gfx] [PATCH 02/29] drm/i915/tc: Use the adlp prefix for ADLP TC PHY functions Imre Deak
2023-03-24 9:41 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 03/29] drm/i915/tc: Rename tc_phy_status_complete() to tc_phy_is_ready() Imre Deak
2023-03-24 9:48 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 04/29] drm/i915/tc: Use the tc_phy prefix for all TC PHY functions Imre Deak
2023-03-24 9:51 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 05/29] drm/i915/tc: Move TC port fields to a new intel_tc_port struct Imre Deak
2023-03-24 12:01 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 06/29] drm/i915/tc: Check for TC PHY explicitly in intel_tc_port_fia_max_lane_count() Imre Deak
2023-03-24 13:07 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 07/29] drm/i915/tc: Move the intel_tc_port struct declaration to intel_tc.c Imre Deak
2023-03-24 13:08 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 08/29] drm/i915/tc: Add TC PHY hook to get the PHY HPD live status Imre Deak
2023-03-24 13:10 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 09/29] drm/i915/tc: Add TC PHY hooks to get the PHY ready/owned state Imre Deak
2023-03-24 13:11 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 10/29] drm/i915/tc: Add TC PHY hook to read out the PHY HW state Imre Deak
2023-03-24 13:35 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 11/29] drm/i915/tc: Add generic TC PHY connect/disconnect handlers Imre Deak
2023-03-24 14:20 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 12/29] drm/i915/tc: Factor out tc_phy_verify_legacy_or_dp_alt_mode() Imre Deak
2023-03-24 14:21 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 13/29] drm/i915/tc: Add TC PHY hooks to connect/disconnect the PHY Imre Deak
2023-03-27 11:04 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 14/29] drm/i915/tc: Fix up the legacy VBT flag only in disconnected mode Imre Deak
2023-03-27 11:05 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 15/29] drm/i915/tc: Check TC mode instead of the VBT legacy flag Imre Deak
2023-03-27 11:06 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 16/29] drm/i915/tc: Block/unblock TC-cold in the PHY connect/disconnect hooks Imre Deak
2023-03-27 11:52 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 17/29] drm/i915/tc: Remove redundant wakeref=0 check from unblock_tc_cold() Imre Deak
2023-03-27 11:53 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 18/29] drm/i915/tc: Drop tc_cold_block()/unblock()'s power domain parameter Imre Deak
2023-03-27 11:55 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 19/29] drm/i915/tc: Add TC PHY hook to get the TC-cold blocking power domain Imre Deak
2023-03-27 11:57 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 20/29] drm/i915/tc: Add asserts in TC PHY hooks that the required power is on Imre Deak
2023-03-23 14:33 ` Jani Nikula
2023-03-23 17:08 ` Imre Deak
2023-03-27 12:00 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 21/29] drm/i915/tc: Add TC PHY hook to init the PHY Imre Deak
2023-03-27 12:01 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 22/29] drm/i915/adlp/tc: Use the DE HPD ISR register for hotplug detection Imre Deak
2023-03-27 12:15 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 23/29] drm/i915/tc: Get power ref for reading the HPD live status register Imre Deak
2023-03-27 12:43 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 24/29] drm/i915/tc: Don't connect the PHY in intel_tc_port_connected() Imre Deak
2023-03-27 12:48 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 25/29] drm/i915/adlp/tc: Align the connect/disconnect PHY sequence with bspec Imre Deak
2023-03-28 10:13 ` Kahola, Mika [this message]
2023-03-23 14:20 ` [Intel-gfx] [PATCH 26/29] drm/i915: Move shared DPLL disabling into CRTC disable hook Imre Deak
2023-03-28 10:14 ` Kahola, Mika
2023-03-30 16:16 ` [Intel-gfx] [PATCH v2 " Imre Deak
2023-03-23 14:20 ` [Intel-gfx] [PATCH 27/29] drm/i915: Disable DPLLs before disconnecting the TC PHY Imre Deak
2023-03-28 10:15 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 28/29] drm/i915: Remove TC PHY disconnect workaround Imre Deak
2023-03-28 10:16 ` Kahola, Mika
2023-03-23 14:20 ` [Intel-gfx] [PATCH 29/29] drm/i915: Remove the encoder update_prepare()/complete() hooks Imre Deak
2023-03-28 10:18 ` Kahola, Mika
2023-03-23 16:03 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tc: Align the ADLP TypeC sequences with bspec Patchwork
2023-03-23 16:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-03-23 16:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-23 20:26 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-03-30 23:23 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tc: Align the ADLP TypeC sequences with bspec (rev2) Patchwork
2023-03-30 23:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-03-30 23:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-04-01 0:02 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-04-03 9:06 ` Imre Deak
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