* [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196
@ 2023-05-17 13:22 Tejas Upadhyay
2023-05-17 17:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Add workaround 14016712196 (rev2) Patchwork
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Tejas Upadhyay @ 2023-05-17 13:22 UTC (permalink / raw)
To: intel-gfx
Wa_14016712196 implementation for mtl
Bspec: 72197
V2:
- Fix kernel test robot warnings
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202305121525.3EWdGoBY-lkp@intel.com/
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 41 ++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index e1c76e5bfa82..737eb515544b 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -177,14 +177,38 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
return cs;
}
+static int mtl_dummy_pipe_control(struct i915_request *rq, u32 *cs)
+{
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+ cs = gen12_emit_pipe_control(cs,
+ 0,
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH,
+ LRC_PPHWSP_SCRATCH_ADDR);
+ intel_ring_advance(rq, cs);
+
+ return 0;
+}
+
int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
{
struct intel_engine_cs *engine = rq->engine;
+ int err;
if (mode & EMIT_FLUSH) {
u32 flags = 0;
u32 *cs;
+ /* Wa_14016712196 */
+ if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(engine->i915, P, STEP_A0, STEP_B0)) {
+ /* dummy PIPE_CONTROL + depth flush */
+ cs = intel_ring_begin(rq, 6);
+ err = mtl_dummy_pipe_control(rq, cs);
+ if (err)
+ return err;
+ }
+
flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
flags |= PIPE_CONTROL_FLUSH_L3;
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
@@ -218,6 +242,16 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
u32 flags = 0;
u32 *cs, count;
+ /* Wa_14016712196 */
+ if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(engine->i915, P, STEP_A0, STEP_B0)) {
+ /* dummy PIPE_CONTROL + depth flush */
+ cs = intel_ring_begin(rq, 6);
+ err = mtl_dummy_pipe_control(rq, cs);
+ if (err)
+ return err;
+ }
+
flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
flags |= PIPE_CONTROL_TLB_INVALIDATE;
flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
@@ -733,6 +767,13 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
PIPE_CONTROL_DC_FLUSH_ENABLE |
PIPE_CONTROL_FLUSH_ENABLE);
+ /* Wa_14016712196 */
+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ /* dummy PIPE_CONTROL + depth flush */
+ cs = gen12_emit_pipe_control(cs, 0,
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
+
if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
/* Wa_1409600907 */
flags |= PIPE_CONTROL_DEPTH_STALL;
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Add workaround 14016712196 (rev2)
2023-05-17 13:22 [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196 Tejas Upadhyay
@ 2023-05-17 17:53 ` Patchwork
2023-05-18 6:54 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2023-05-17 17:53 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6686 bytes --]
== Series Details ==
Series: drm/i915/gt: Add workaround 14016712196 (rev2)
URL : https://patchwork.freedesktop.org/series/117661/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13160 -> Patchwork_117661v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/index.html
Participating hosts (36 -> 37)
------------------------------
Additional (2): fi-kbl-soraka bat-mtlp-6
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_117661v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][3] ([i915#1886] / [i915#7913])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][4] ([i915#6367])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/bat-rpls-2/igt@i915_selftest@live@slpc.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][5] ([i915#6687])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/bat-rpls-2/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][6] ([i915#6687] / [i915#7978])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/bat-rpls-1/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271]) +14 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/fi-kbl-soraka/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#1845] / [i915#5354])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4579])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/fi-kbl-soraka/igt@kms_setmode@basic-clone-single-crtc.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- bat-rpls-1: [INCOMPLETE][10] ([i915#4983] / [i915#7677]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/bat-rpls-1/igt@i915_selftest@live@hangcheck.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/bat-rpls-1/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][12] ([i915#4983] / [i915#7461] / [i915#7913] / [i915#8347]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/bat-rpls-2/igt@i915_selftest@live@reset.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/bat-rpls-2/igt@i915_selftest@live@reset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4342]: https://gitlab.freedesktop.org/drm/intel/issues/4342
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7677]: https://gitlab.freedesktop.org/drm/intel/issues/7677
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
Build changes
-------------
* Linux: CI_DRM_13160 -> Patchwork_117661v2
CI-20190529: 20190529
CI_DRM_13160: 2147c8fcc283c183aba29e5f51b653332d90a3ed @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7294: e1ab60dc90fc49f6b2ec1b37f14b021e59455e73 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_117661v2: 2147c8fcc283c183aba29e5f51b653332d90a3ed @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
ca02ed496951 drm/i915/gt: Add workaround 14016712196
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/index.html
[-- Attachment #2: Type: text/html, Size: 6667 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Add workaround 14016712196 (rev2)
2023-05-17 13:22 [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196 Tejas Upadhyay
2023-05-17 17:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Add workaround 14016712196 (rev2) Patchwork
@ 2023-05-18 6:54 ` Patchwork
2023-05-30 21:05 ` [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196 Andi Shyti
2023-05-31 11:52 ` Andrzej Hajda
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2023-05-18 6:54 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 11781 bytes --]
== Series Details ==
Series: drm/i915/gt: Add workaround 14016712196 (rev2)
URL : https://patchwork.freedesktop.org/series/117661/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13160_full -> Patchwork_117661v2_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_117661v2_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_fbcon_fbt@fbc-suspend:
- {shard-dg1}: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-dg1-16/igt@kms_fbcon_fbt@fbc-suspend.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-dg1-13/igt@kms_fbcon_fbt@fbc-suspend.html
Known issues
------------
Here are the changes found in Patchwork_117661v2_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_barrier_race@remote-request@rcs0:
- shard-glk: [PASS][3] -> [ABORT][4] ([i915#7461] / [i915#8211])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-glk1/igt@gem_barrier_race@remote-request@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-glk3/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][5] -> [ABORT][6] ([i915#5566])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-apl3/igt@gen9_exec_parse@allowed-single.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-apl4/igt@gen9_exec_parse@allowed-single.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#79])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-glk4/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
#### Possible fixes ####
* igt@gem_barrier_race@remote-request@rcs0:
- {shard-dg1}: [ABORT][9] ([i915#7461] / [i915#8234]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-dg1-17/igt@gem_barrier_race@remote-request@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-dg1-18/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][11] ([i915#2842]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
- {shard-tglu}: [FAIL][13] ([i915#2842]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-tglu-6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-tglu-4/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@i915_module_load@reload-with-fault-injection:
- {shard-dg1}: [DMESG-WARN][15] ([i915#4391]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-dg1-17/igt@i915_module_load@reload-with-fault-injection.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-dg1-16/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- {shard-rkl}: [SKIP][17] ([i915#1937] / [i915#4579]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-rkl-2/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-rkl-7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-dg1}: [FAIL][19] ([i915#3591]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
* igt@i915_pm_rps@reset:
- {shard-tglu}: [INCOMPLETE][21] ([i915#8320]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-tglu-5/igt@i915_pm_rps@reset.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-tglu-7/igt@i915_pm_rps@reset.html
* igt@i915_suspend@basic-s3-without-i915:
- {shard-rkl}: [FAIL][23] ([fdo#103375]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-rkl-6/igt@i915_suspend@basic-s3-without-i915.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-rkl-7/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_cursor_legacy@forked-bo@pipe-b:
- {shard-rkl}: [INCOMPLETE][25] ([i915#8011]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-rkl-7/igt@kms_cursor_legacy@forked-bo@pipe-b.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-rkl-3/igt@kms_cursor_legacy@forked-bo@pipe-b.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][27] ([i915#2122]) -> [PASS][28] +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-glk8/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-glk5/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234
[i915#8311]: https://gitlab.freedesktop.org/drm/intel/issues/8311
[i915#8320]: https://gitlab.freedesktop.org/drm/intel/issues/8320
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
Build changes
-------------
* Linux: CI_DRM_13160 -> Patchwork_117661v2
CI-20190529: 20190529
CI_DRM_13160: 2147c8fcc283c183aba29e5f51b653332d90a3ed @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7294: e1ab60dc90fc49f6b2ec1b37f14b021e59455e73 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_117661v2: 2147c8fcc283c183aba29e5f51b653332d90a3ed @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/index.html
[-- Attachment #2: Type: text/html, Size: 8777 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196
2023-05-17 13:22 [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196 Tejas Upadhyay
2023-05-17 17:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Add workaround 14016712196 (rev2) Patchwork
2023-05-18 6:54 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2023-05-30 21:05 ` Andi Shyti
2023-05-31 10:14 ` Upadhyay, Tejas
2023-05-31 11:52 ` Andrzej Hajda
3 siblings, 1 reply; 9+ messages in thread
From: Andi Shyti @ 2023-05-30 21:05 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: intel-gfx
Hi Tejas,
On Wed, May 17, 2023 at 06:52:30PM +0530, Tejas Upadhyay wrote:
> Wa_14016712196 implementation for mtl
>
> Bspec: 72197
>
> V2:
> - Fix kernel test robot warnings
>
> Reported-by: kernel test robot <lkp@intel.com>
> Closes: https://lore.kernel.org/oe-kbuild-all/202305121525.3EWdGoBY-lkp@intel.com/
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> ---
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 41 ++++++++++++++++++++++++
> 1 file changed, 41 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index e1c76e5bfa82..737eb515544b 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -177,14 +177,38 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
> return cs;
> }
>
> +static int mtl_dummy_pipe_control(struct i915_request *rq, u32 *cs)
> +{
> + if (IS_ERR(cs))
> + return PTR_ERR(cs);
> + cs = gen12_emit_pipe_control(cs,
> + 0,
> + PIPE_CONTROL_DEPTH_CACHE_FLUSH,
> + LRC_PPHWSP_SCRATCH_ADDR);
> + intel_ring_advance(rq, cs);
> +
> + return 0;
> +}
> +
> int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> {
> struct intel_engine_cs *engine = rq->engine;
> + int err;
>
> if (mode & EMIT_FLUSH) {
> u32 flags = 0;
> u32 *cs;
>
> + /* Wa_14016712196 */
> + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(engine->i915, P, STEP_A0, STEP_B0)) {
> + /* dummy PIPE_CONTROL + depth flush */
> + cs = intel_ring_begin(rq, 6);
> + err = mtl_dummy_pipe_control(rq, cs);
> + if (err)
> + return err;
> + }
> +
> flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
> flags |= PIPE_CONTROL_FLUSH_L3;
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> @@ -218,6 +242,16 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> u32 flags = 0;
> u32 *cs, count;
>
> + /* Wa_14016712196 */
> + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(engine->i915, P, STEP_A0, STEP_B0)) {
> + /* dummy PIPE_CONTROL + depth flush */
> + cs = intel_ring_begin(rq, 6);
> + err = mtl_dummy_pipe_control(rq, cs);
> + if (err)
> + return err;
> + }
> +
as the two blocks are basically identical, why not put both of
them inside mtl_dummy_pipe_control() and you would basically have
something like:
/* Wa_14016712196 */
cs = mtl_dummy_pipe_control(rq, cs);
if (IS_ERR(cs))
return PTR_ERR(cs);
Besides, you check the err value from intel_ring_begin inside
mtl_dummy_pipe_control(), which looks a bit weird to me.
I'm wondering, though, if we can put both dummy pipe and real
pipe in the same command and advance the ring only once at the
end... nevermind.
Andi
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196
2023-05-30 21:05 ` [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196 Andi Shyti
@ 2023-05-31 10:14 ` Upadhyay, Tejas
2023-05-31 10:33 ` Andi Shyti
0 siblings, 1 reply; 9+ messages in thread
From: Upadhyay, Tejas @ 2023-05-31 10:14 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
> -----Original Message-----
> From: Andi Shyti <andi.shyti@linux.intel.com>
> Sent: Wednesday, May 31, 2023 2:36 AM
> To: Upadhyay, Tejas <tejas.upadhyay@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround
> 14016712196
>
> Hi Tejas,
>
> On Wed, May 17, 2023 at 06:52:30PM +0530, Tejas Upadhyay wrote:
> > Wa_14016712196 implementation for mtl
> >
> > Bspec: 72197
> >
> > V2:
> > - Fix kernel test robot warnings
> >
> > Reported-by: kernel test robot <lkp@intel.com>
> > Closes:
> > https://lore.kernel.org/oe-kbuild-all/202305121525.3EWdGoBY-lkp@intel.
> > com/
> > Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 41
> > ++++++++++++++++++++++++
> > 1 file changed, 41 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > index e1c76e5bfa82..737eb515544b 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > @@ -177,14 +177,38 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt
> *gt, u32 *cs, const i915_reg_t inv
> > return cs;
> > }
> >
> > +static int mtl_dummy_pipe_control(struct i915_request *rq, u32 *cs) {
> > + if (IS_ERR(cs))
> > + return PTR_ERR(cs);
> > + cs = gen12_emit_pipe_control(cs,
> > + 0,
> > + PIPE_CONTROL_DEPTH_CACHE_FLUSH,
> > + LRC_PPHWSP_SCRATCH_ADDR);
> > + intel_ring_advance(rq, cs);
> > +
> > + return 0;
> > +}
> > +
> > int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) {
> > struct intel_engine_cs *engine = rq->engine;
> > + int err;
> >
> > if (mode & EMIT_FLUSH) {
> > u32 flags = 0;
> > u32 *cs;
> >
> > + /* Wa_14016712196 */
> > + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0,
> STEP_B0) ||
> > + IS_MTL_GRAPHICS_STEP(engine->i915, P, STEP_A0,
> STEP_B0)) {
> > + /* dummy PIPE_CONTROL + depth flush */
> > + cs = intel_ring_begin(rq, 6);
> > + err = mtl_dummy_pipe_control(rq, cs);
> > + if (err)
> > + return err;
> > + }
> > +
> > flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
> > flags |= PIPE_CONTROL_FLUSH_L3;
> > flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> > @@ -218,6 +242,16 @@ int gen12_emit_flush_rcs(struct i915_request *rq,
> u32 mode)
> > u32 flags = 0;
> > u32 *cs, count;
> >
> > + /* Wa_14016712196 */
> > + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0,
> STEP_B0) ||
> > + IS_MTL_GRAPHICS_STEP(engine->i915, P, STEP_A0,
> STEP_B0)) {
> > + /* dummy PIPE_CONTROL + depth flush */
> > + cs = intel_ring_begin(rq, 6);
> > + err = mtl_dummy_pipe_control(rq, cs);
> > + if (err)
> > + return err;
> > + }
> > +
>
> as the two blocks are basically identical, why not put both of them inside
> mtl_dummy_pipe_control() and you would basically have something like:
>
> /* Wa_14016712196 */
> cs = mtl_dummy_pipe_control(rq, cs);
> if (IS_ERR(cs))
> return PTR_ERR(cs);
>
I agree initially I had same, but problem I have is kernel bot is complaining for uninitialized "cs" passed to mtl_dummy_pipe_control. I did not get simple solution to it. Suggestions!
> Besides, you check the err value from intel_ring_begin inside
> mtl_dummy_pipe_control(), which looks a bit weird to me.
Yes it looks weird. I will change it.
>
> I'm wondering, though, if we can put both dummy pipe and real pipe in the
> same command and advance the ring only once at the end... nevermind.
As we have conditional ring increments, we cant decide ring size at start in ring begin for whole bunch at once. Though double checking.
Thanks,
Tejas
>
> Andi
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196
2023-05-31 10:14 ` Upadhyay, Tejas
@ 2023-05-31 10:33 ` Andi Shyti
0 siblings, 0 replies; 9+ messages in thread
From: Andi Shyti @ 2023-05-31 10:33 UTC (permalink / raw)
To: Upadhyay, Tejas; +Cc: intel-gfx
Hi Tejas,
> >
> > I'm wondering, though, if we can put both dummy pipe and real pipe in the
> > same command and advance the ring only once at the end... nevermind.
>
> As we have conditional ring increments, we cant decide ring size at start in ring begin for whole bunch at once. Though double checking.
yes, you add it conditionally. Check, e.g., the control:
if (!HAS_FLAT_CCS(rq->engine->i915))
count = 8 + 4;
else
count = 8;
In the second if block. You are basically doing the same thing.
But I'm not strong with this.
Andi
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196
2023-05-17 13:22 [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196 Tejas Upadhyay
` (2 preceding siblings ...)
2023-05-30 21:05 ` [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196 Andi Shyti
@ 2023-05-31 11:52 ` Andrzej Hajda
2023-05-31 12:14 ` Andi Shyti
3 siblings, 1 reply; 9+ messages in thread
From: Andrzej Hajda @ 2023-05-31 11:52 UTC (permalink / raw)
To: Tejas Upadhyay, intel-gfx
On 17.05.2023 15:22, Tejas Upadhyay wrote:
> Wa_14016712196 implementation for mtl
>
> Bspec: 72197
>
> V2:
> - Fix kernel test robot warnings
>
> Reported-by: kernel test robot <lkp@intel.com>
I do not think robot reported lack of this wa :), putting lkp in
changelog should be enough.
> Closes: https://lore.kernel.org/oe-kbuild-all/202305121525.3EWdGoBY-lkp@intel.com/
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> ---
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 41 ++++++++++++++++++++++++
> 1 file changed, 41 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index e1c76e5bfa82..737eb515544b 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -177,14 +177,38 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
> return cs;
> }
>
> +static int mtl_dummy_pipe_control(struct i915_request *rq, u32 *cs)
> +{
> + if (IS_ERR(cs))
> + return PTR_ERR(cs);
> + cs = gen12_emit_pipe_control(cs,
> + 0,
> + PIPE_CONTROL_DEPTH_CACHE_FLUSH,
> + LRC_PPHWSP_SCRATCH_ADDR);
> + intel_ring_advance(rq, cs);
> +
> + return 0;
> +}
> +
> int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> {
> struct intel_engine_cs *engine = rq->engine;
> + int err;
>
> if (mode & EMIT_FLUSH) {
> u32 flags = 0;
> u32 *cs;
>
> + /* Wa_14016712196 */
> + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(engine->i915, P, STEP_A0, STEP_B0)) {
> + /* dummy PIPE_CONTROL + depth flush */
> + cs = intel_ring_begin(rq, 6);
> + err = mtl_dummy_pipe_control(rq, cs);
> + if (err)
> + return err;
Like Andi suggested, you can replace above sequence with:
cs = mtl_dummy_pipe_control(rq);
> + }
> +
> flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
> flags |= PIPE_CONTROL_FLUSH_L3;
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> @@ -218,6 +242,16 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> u32 flags = 0;
> u32 *cs, count;
>
> + /* Wa_14016712196 */
> + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(engine->i915, P, STEP_A0, STEP_B0)) {
> + /* dummy PIPE_CONTROL + depth flush */
> + cs = intel_ring_begin(rq, 6);
> + err = mtl_dummy_pipe_control(rq, cs);
> + if (err)
> + return err;
> + }
> +
In case gen12_emit_flush_rcs is called with EMIT_BARRIER =
(EMIT_INVALIDATE | EMIT_FLUSH) dummy pipe will be inserted twice, is it OK?
> flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
> flags |= PIPE_CONTROL_TLB_INVALIDATE;
> flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
> @@ -733,6 +767,13 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> PIPE_CONTROL_DC_FLUSH_ENABLE |
> PIPE_CONTROL_FLUSH_ENABLE);
>
> + /* Wa_14016712196 */
> + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> + /* dummy PIPE_CONTROL + depth flush */
> + cs = gen12_emit_pipe_control(cs, 0,
> + PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
How do we know there is enough space for dummy pipe?
Regards
Andrzej
> +
> if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> /* Wa_1409600907 */
> flags |= PIPE_CONTROL_DEPTH_STALL;
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196
2023-05-31 11:52 ` Andrzej Hajda
@ 2023-05-31 12:14 ` Andi Shyti
2023-05-31 12:48 ` Upadhyay, Tejas
0 siblings, 1 reply; 9+ messages in thread
From: Andi Shyti @ 2023-05-31 12:14 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx
Hi Andrzej,
> > @@ -218,6 +242,16 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> > u32 flags = 0;
> > u32 *cs, count;
> > + /* Wa_14016712196 */
> > + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> > + IS_MTL_GRAPHICS_STEP(engine->i915, P, STEP_A0, STEP_B0)) {
> > + /* dummy PIPE_CONTROL + depth flush */
> > + cs = intel_ring_begin(rq, 6);
> > + err = mtl_dummy_pipe_control(rq, cs);
> > + if (err)
> > + return err;
> > + }
> > +
>
> In case gen12_emit_flush_rcs is called with EMIT_BARRIER = (EMIT_INVALIDATE
> | EMIT_FLUSH) dummy pipe will be inserted twice, is it OK?
good point... I also meant to ask this, indeed. I assumed that
before the pipe control we needed the dummy pipe. Is that the
case, Tejas?
> > flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
> > flags |= PIPE_CONTROL_TLB_INVALIDATE;
> > flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
> > @@ -733,6 +767,13 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> > PIPE_CONTROL_DC_FLUSH_ENABLE |
> > PIPE_CONTROL_FLUSH_ENABLE);
> > + /* Wa_14016712196 */
> > + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > + /* dummy PIPE_CONTROL + depth flush */
> > + cs = gen12_emit_pipe_control(cs, 0,
> > + PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
>
> How do we know there is enough space for dummy pipe?
This should be ensured by intel_ring_begin().
Andi
> Regards
> Andrzej
>
> > +
> > if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> > /* Wa_1409600907 */
> > flags |= PIPE_CONTROL_DEPTH_STALL;
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196
2023-05-31 12:14 ` Andi Shyti
@ 2023-05-31 12:48 ` Upadhyay, Tejas
0 siblings, 0 replies; 9+ messages in thread
From: Upadhyay, Tejas @ 2023-05-31 12:48 UTC (permalink / raw)
To: Andi Shyti, Hajda, Andrzej; +Cc: intel-gfx
> -----Original Message-----
> From: Andi Shyti <andi.shyti@linux.intel.com>
> Sent: Wednesday, May 31, 2023 5:45 PM
> To: Hajda, Andrzej <andrzej.hajda@intel.com>
> Cc: Upadhyay, Tejas <tejas.upadhyay@intel.com>; intel-
> gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround
> 14016712196
>
> Hi Andrzej,
>
> > > @@ -218,6 +242,16 @@ int gen12_emit_flush_rcs(struct i915_request
> *rq, u32 mode)
> > > u32 flags = 0;
> > > u32 *cs, count;
> > > + /* Wa_14016712196 */
> > > + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0,
> STEP_B0) ||
> > > + IS_MTL_GRAPHICS_STEP(engine->i915, P, STEP_A0,
> STEP_B0)) {
> > > + /* dummy PIPE_CONTROL + depth flush */
> > > + cs = intel_ring_begin(rq, 6);
> > > + err = mtl_dummy_pipe_control(rq, cs);
> > > + if (err)
> > > + return err;
> > > + }
> > > +
> >
> > In case gen12_emit_flush_rcs is called with EMIT_BARRIER =
> > (EMIT_INVALIDATE
> > | EMIT_FLUSH) dummy pipe will be inserted twice, is it OK?
>
> good point... I also meant to ask this, indeed. I assumed that before the pipe
> control we needed the dummy pipe. Is that the case, Tejas?
Yes before any DEPTH flush + pipe control we need dummy pipe control.
Thanks,
Tejas
>
> > > flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
> > > flags |= PIPE_CONTROL_TLB_INVALIDATE;
> > > flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
> > > @@ -733,6 +767,13 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct
> i915_request *rq, u32 *cs)
> > > PIPE_CONTROL_DC_FLUSH_ENABLE |
> > > PIPE_CONTROL_FLUSH_ENABLE);
> > > + /* Wa_14016712196 */
> > > + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > > + /* dummy PIPE_CONTROL + depth flush */
> > > + cs = gen12_emit_pipe_control(cs, 0,
> > > +
> PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
> >
> > How do we know there is enough space for dummy pipe?
>
> This should be ensured by intel_ring_begin().
>
> Andi
>
> > Regards
> > Andrzej
> >
> > > +
> > > if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) <
> IP_VER(12, 50))
> > > /* Wa_1409600907 */
> > > flags |= PIPE_CONTROL_DEPTH_STALL;
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-05-31 12:48 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-17 13:22 [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196 Tejas Upadhyay
2023-05-17 17:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Add workaround 14016712196 (rev2) Patchwork
2023-05-18 6:54 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-05-30 21:05 ` [Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196 Andi Shyti
2023-05-31 10:14 ` Upadhyay, Tejas
2023-05-31 10:33 ` Andi Shyti
2023-05-31 11:52 ` Andrzej Hajda
2023-05-31 12:14 ` Andi Shyti
2023-05-31 12:48 ` Upadhyay, Tejas
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