[Intel-gfx] [PATCH V2] drm/i915/jsl: Disable cursor clock gating in HDR mode

[Intel-gfx] [PATCH V2] drm/i915/jsl: Disable cursor clock gating in HDR mode

[Tejas Upadhyay]

Display underrun in HDR mode when cursor is enabled.
RTL fix will be implemented CLKGATE_DIS_PSL_A bit 28-46520h.
As per W/A 1604331009, Disable cursor clock gating in HDR mode.

Bspec : 33451

Changes since V1:
	- Modified way CLKGATE_DIS_PSL bit 28 was modified

Cc: Souza Jose <jose.souza@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 28 ++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h              |  5 ++++
 2 files changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index cddbda5303ff..b132585d9e78 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -541,6 +541,15 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 		               intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
 }
 
+/* Wa_1604331009:jsl */
+static void
+jsl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
+		       bool enable)
+{
+	intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
+		     CURSOR_GATING_DIS, enable ? CURSOR_GATING_DIS : 0);
+}
+
 static bool
 needs_modeset(const struct intel_crtc_state *state)
 {
@@ -6637,6 +6646,16 @@ static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
 	return false;
 }
 
+static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	/* Wa_1604331009:jsl */
+	if (crtc_state->active_planes & icl_hdr_plane_mask() &&
+	    IS_GEN(dev_priv, 11))
+		return true;
+	return false;
+}
+
 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
 			    const struct intel_crtc_state *new_crtc_state)
 {
@@ -6678,6 +6697,10 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
 	if (needs_scalerclk_wa(old_crtc_state) &&
 	    !needs_scalerclk_wa(new_crtc_state))
 		icl_wa_scalerclkgating(dev_priv, pipe, false);
+
+	if (needs_cursorclk_wa(old_crtc_state) &&
+	    !needs_cursorclk_wa(new_crtc_state))
+		jsl_wa_cursorclkgating(dev_priv, pipe, false);
 }
 
 static void skl_disable_async_flip_wa(struct intel_atomic_state *state,
@@ -6743,6 +6766,11 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 	    needs_scalerclk_wa(new_crtc_state))
 		icl_wa_scalerclkgating(dev_priv, pipe, true);
 
+	/* Wa_1604331009:jsl */
+	if (!needs_cursorclk_wa(old_crtc_state) &&
+	    needs_cursorclk_wa(new_crtc_state))
+		jsl_wa_cursorclkgating(dev_priv, pipe, true);
+
 	/*
 	 * Vblank time updates from the shadow to live plane control register
 	 * are blocked if the memory self-refresh mode is active at that
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bb0656875697..f81a503c5d4b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4194,6 +4194,11 @@ enum {
 #define INF_UNIT_LEVEL_CLKGATE		_MMIO(0x9560)
 #define   CGPSF_CLKGATE_DIS		(1 << 3)
 
+/*
+ * GEN11 clock gating regs
+ */
+#define   CURSOR_GATING_DIS		BIT(28)
+
 /*
  * Display engine regs
  */
-- 
2.28.0

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/jsl: Disable cursor clock gating in HDR mode (rev2)

[Patchwork]

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== Series Details ==

Series: drm/i915/jsl: Disable cursor clock gating in HDR mode (rev2)
URL   : https://patchwork.freedesktop.org/series/83142/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9238 -> Patchwork_18824
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/index.html

New tests
---------

  New tests have been introduced between CI_DRM_9238 and Patchwork_18824:

### New CI tests (1) ###

  * boot:
    - Statuses : 38 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18824 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@unbind-rebind:
    - fi-blb-e6850:       [PASS][1] -> [INCOMPLETE][2] ([i915#2540])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload:
    - fi-byt-j1900:       [DMESG-WARN][3] ([i915#1982]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/fi-byt-j1900/igt@i915_module_load@reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/fi-byt-j1900/igt@i915_module_load@reload.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-bsw-n3050:       [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/fi-bsw-n3050/igt@i915_pm_rpm@basic-pci-d3-state.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/fi-bsw-n3050/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-lmem:        [DMESG-WARN][7] -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-cml-u2:          [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
    - fi-icl-u2:          [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] +2 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html

  
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2540]: https://gitlab.freedesktop.org/drm/intel/issues/2540


Participating hosts (42 -> 38)
------------------------------

  Missing    (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u 


Build changes
-------------

  * Linux: CI_DRM_9238 -> Patchwork_18824

  CI-20190529: 20190529
  CI_DRM_9238: acdb28c0a634b8dcf8c6946de851a25d1c532b10 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5830: 12d370cb57e0cfcb781c87ad9e15e68b17a1f41f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18824: 00b610ef040a290703523a706ef6e7611bc3c451 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

00b610ef040a drm/i915/jsl: Disable cursor clock gating in HDR mode

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/index.html

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/jsl: Disable cursor clock gating in HDR mode (rev2)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 19712 bytes --]

== Series Details ==

Series: drm/i915/jsl: Disable cursor clock gating in HDR mode (rev2)
URL   : https://patchwork.freedesktop.org/series/83142/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9238_full -> Patchwork_18824_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_18824_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18824_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18824_full:

### IGT changes ###

#### Possible regressions ####

  * igt@feature_discovery@chamelium:
    - shard-hsw:          NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-hsw4/igt@feature_discovery@chamelium.html

  * igt@gem_exec_fence@invalid-fence-array:
    - shard-hsw:          [PASS][2] -> [FAIL][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-hsw1/igt@gem_exec_fence@invalid-fence-array.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-hsw8/igt@gem_exec_fence@invalid-fence-array.html

  
#### Warnings ####

  * igt@core_hotunplug@hotrebind-lateclose:
    - shard-hsw:          [WARN][4] ([i915#2283]) -> [FAIL][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-hsw1/igt@core_hotunplug@hotrebind-lateclose.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-hsw8/igt@core_hotunplug@hotrebind-lateclose.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile}:
    - shard-skl:          NOTRUN -> [FAIL][6]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-skl7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html

  
New tests
---------

  New tests have been introduced between CI_DRM_9238_full and Patchwork_18824_full:

### New CI tests (1) ###

  * boot:
    - Statuses : 199 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18824_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@unbind-rebind:
    - shard-skl:          [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +6 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-skl7/igt@core_hotunplug@unbind-rebind.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-skl8/igt@core_hotunplug@unbind-rebind.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x128-random:
    - shard-skl:          [PASS][9] -> [FAIL][10] ([i915#54]) +3 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html

  * igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge:
    - shard-glk:          [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +2 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-glk9/igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-glk6/igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge.html

  * igt@kms_cursor_edge_walk@pipe-c-256x256-top-edge:
    - shard-hsw:          [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-hsw2/igt@kms_cursor_edge_walk@pipe-c-256x256-top-edge.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-hsw6/igt@kms_cursor_edge_walk@pipe-c-256x256-top-edge.html

  * igt@kms_flip@2x-plain-flip-ts-check@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][15] -> [FAIL][16] ([i915#2122])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-glk4/igt@kms_flip@2x-plain-flip-ts-check@ab-hdmi-a1-hdmi-a2.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-glk5/igt@kms_flip@2x-plain-flip-ts-check@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@plain-flip-ts-check@b-edp1:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([i915#2122])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-skl10/igt@kms_flip@plain-flip-ts-check@b-edp1.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-skl2/igt@kms_flip@plain-flip-ts-check@b-edp1.html

  * igt@kms_flip_tiling@flip-x-tiled:
    - shard-kbl:          [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-kbl1/igt@kms_flip_tiling@flip-x-tiled.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-kbl2/igt@kms_flip_tiling@flip-x-tiled.html

  * igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
    - shard-tglb:         [PASS][21] -> [DMESG-WARN][22] ([i915#1982])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-tglb6/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-tglb7/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_cursor_blt:
    - shard-iclb:         [PASS][25] -> [SKIP][26] ([fdo#109441])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-iclb8/igt@kms_psr@psr2_cursor_blt.html

  * igt@kms_vblank@pipe-b-ts-continuation-suspend:
    - shard-skl:          [PASS][27] -> [INCOMPLETE][28] ([i915#198])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-skl2/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-skl7/igt@kms_vblank@pipe-b-ts-continuation-suspend.html

  * igt@perf@short-reads:
    - shard-skl:          [PASS][29] -> [FAIL][30] ([i915#51])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-skl4/igt@perf@short-reads.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-skl4/igt@perf@short-reads.html

  * igt@perf_pmu@module-unload:
    - shard-apl:          [PASS][31] -> [DMESG-WARN][32] ([i915#1635] / [i915#1982]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-apl4/igt@perf_pmu@module-unload.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-apl7/igt@perf_pmu@module-unload.html

  
#### Possible fixes ####

  * igt@gem_exec_schedule@deep@vecs0:
    - shard-skl:          [INCOMPLETE][33] -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-skl3/igt@gem_exec_schedule@deep@vecs0.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-skl3/igt@gem_exec_schedule@deep@vecs0.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
    - shard-hsw:          [FAIL][35] ([i915#1888]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-hsw1/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-hsw8/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html

  * {igt@kms_async_flips@alternate-sync-async-flip}:
    - shard-apl:          [FAIL][37] ([i915#1635] / [i915#2521]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-apl2/igt@kms_async_flips@alternate-sync-async-flip.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-apl1/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen:
    - shard-skl:          [FAIL][39] ([i915#54]) -> [PASS][40] +5 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen.html

  * igt@kms_cursor_edge_walk@pipe-b-128x128-top-edge:
    - shard-apl:          [DMESG-WARN][41] ([i915#1635] / [i915#1982]) -> [PASS][42] +1 similar issue
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-apl1/igt@kms_cursor_edge_walk@pipe-b-128x128-top-edge.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-apl1/igt@kms_cursor_edge_walk@pipe-b-128x128-top-edge.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
    - shard-hsw:          [FAIL][43] ([i915#96]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-vga1-hdmi-a1:
    - shard-hsw:          [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +1 similar issue
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-hsw1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-vga1-hdmi-a1.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-hsw8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-vga1-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@b-edp1:
    - shard-iclb:         [INCOMPLETE][47] ([i915#1185]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-iclb3/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-iclb7/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-suspend@c-hdmi-a1:
    - shard-hsw:          [INCOMPLETE][49] ([i915#2055]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-hsw4/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-hsw4/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend@c-hdmi-a2:
    - shard-glk:          [INCOMPLETE][51] -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-glk2/igt@kms_flip@flip-vs-suspend@c-hdmi-a2.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-glk1/igt@kms_flip@flip-vs-suspend@c-hdmi-a2.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
    - shard-skl:          [FAIL][53] ([i915#2122]) -> [PASS][54] +1 similar issue
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu:
    - shard-tglb:         [DMESG-WARN][55] ([i915#1982]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [FAIL][57] ([i915#1188]) -> [PASS][58] +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-c:
    - shard-skl:          [FAIL][59] -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-skl4/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-c.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-skl6/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-c.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [FAIL][61] ([fdo#108145] / [i915#265]) -> [PASS][62] +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_plane_cursor@pipe-b-viewport-size-128:
    - shard-skl:          [DMESG-WARN][63] ([i915#1982]) -> [PASS][64] +4 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-skl7/igt@kms_plane_cursor@pipe-b-viewport-size-128.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-skl8/igt@kms_plane_cursor@pipe-b-viewport-size-128.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [SKIP][65] ([fdo#109441]) -> [PASS][66] +1 similar issue
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-iclb3/igt@kms_psr@psr2_no_drrs.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-iclb2/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_vblank@pipe-b-wait-forked-busy-hang:
    - shard-glk:          [DMESG-WARN][67] ([i915#1982]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-glk8/igt@kms_vblank@pipe-b-wait-forked-busy-hang.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-glk4/igt@kms_vblank@pipe-b-wait-forked-busy-hang.html

  * igt@kms_vblank@pipe-c-query-forked-busy-hang:
    - shard-kbl:          [DMESG-WARN][69] ([i915#1982]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-kbl2/igt@kms_vblank@pipe-c-query-forked-busy-hang.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-kbl3/igt@kms_vblank@pipe-c-query-forked-busy-hang.html

  * igt@perf@non-system-wide-paranoid:
    - shard-hsw:          [SKIP][71] ([fdo#109271]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-hsw1/igt@perf@non-system-wide-paranoid.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-hsw8/igt@perf@non-system-wide-paranoid.html

  
#### Warnings ####

  * igt@kms_color@pipe-a-ctm-red-to-blue:
    - shard-skl:          [DMESG-WARN][73] ([i915#1982]) -> [DMESG-FAIL][74] ([i915#1982])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-skl6/igt@kms_color@pipe-a-ctm-red-to-blue.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-skl2/igt@kms_color@pipe-a-ctm-red-to-blue.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-edp1:
    - shard-tglb:         [DMESG-WARN][75] ([i915#2411]) -> [INCOMPLETE][76] ([i915#1436] / [i915#456])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-tglb2/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-tglb2/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
    - shard-skl:          [DMESG-FAIL][77] ([i915#1982]) -> [DMESG-WARN][78] ([i915#1982])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html

  * igt@kms_flip_tiling@flip-x-tiled:
    - shard-skl:          [DMESG-WARN][79] ([i915#1982]) -> [DMESG-FAIL][80] ([fdo#108145] / [i915#1982])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-skl6/igt@kms_flip_tiling@flip-x-tiled.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-skl2/igt@kms_flip_tiling@flip-x-tiled.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-apl:          [FAIL][81] ([fdo#108145] / [i915#1635] / [i915#265]) -> [DMESG-FAIL][82] ([fdo#108145] / [i915#1635] / [i915#1982])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html

  * igt@runner@aborted:
    - shard-tglb:         [FAIL][83] ([i915#2439]) -> ([FAIL][84], [FAIL][85]) ([i915#2248] / [i915#2439])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9238/shard-tglb8/igt@runner@aborted.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-tglb3/igt@runner@aborted.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/shard-tglb2/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2248]: https://gitlab.freedesktop.org/drm/intel/issues/2248
  [i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
  [i915#51]: https://gitlab.freedesktop.org/drm/intel/issues/51
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_9238 -> Patchwork_18824

  CI-20190529: 20190529
  CI_DRM_9238: acdb28c0a634b8dcf8c6946de851a25d1c532b10 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5830: 12d370cb57e0cfcb781c87ad9e15e68b17a1f41f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18824: 00b610ef040a290703523a706ef6e7611bc3c451 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18824/index.html

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Re: [Intel-gfx] [PATCH V2] drm/i915/jsl: Disable cursor clock gating in HDR mode

[Souza, Jose]

On Mon, 2020-11-02 at 13:09 +0530, Tejas Upadhyay wrote:
> Display underrun in HDR mode when cursor is enabled.
> RTL fix will be implemented CLKGATE_DIS_PSL_A bit 28-46520h.
> As per W/A 1604331009, Disable cursor clock gating in HDR mode.
> 
> Bspec : 33451
> 
> Changes since V1:
> 	- Modified way CLKGATE_DIS_PSL bit 28 was modified
> 
> Cc: Souza Jose <jose.souza@intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 28 ++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h              |  5 ++++
>  2 files changed, 33 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index cddbda5303ff..b132585d9e78 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -541,6 +541,15 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
>  		               intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
>  }
>  
> 
> 
> 
> 
> 
> 
> 
> +/* Wa_1604331009:jsl */
> +static void
> +jsl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
> +		       bool enable)

if this is a gen11 WA why naming as jsl? also include in the comment icl and ehl.

> +{
> +	intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
> +		     CURSOR_GATING_DIS, enable ? CURSOR_GATING_DIS : 0);
> +}
> +
>  static bool
>  needs_modeset(const struct intel_crtc_state *state)
>  {
> @@ -6637,6 +6646,16 @@ static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
>  	return false;
>  }
>  
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> +static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);

line break here

> +	/* Wa_1604331009:jsl */
> +	if (crtc_state->active_planes & icl_hdr_plane_mask() &&
> +	    IS_GEN(dev_priv, 11))
> +		return true;

line break here

> +	return false;
> +}
> +
>  static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
>  			    const struct intel_crtc_state *new_crtc_state)
>  {
> @@ -6678,6 +6697,10 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
>  	if (needs_scalerclk_wa(old_crtc_state) &&
>  	    !needs_scalerclk_wa(new_crtc_state))
>  		icl_wa_scalerclkgating(dev_priv, pipe, false);
> +
> +	if (needs_cursorclk_wa(old_crtc_state) &&
> +	    !needs_cursorclk_wa(new_crtc_state))
> +		jsl_wa_cursorclkgating(dev_priv, pipe, false);
>  }
>  
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>  static void skl_disable_async_flip_wa(struct intel_atomic_state *state,
> @@ -6743,6 +6766,11 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
>  	    needs_scalerclk_wa(new_crtc_state))
>  		icl_wa_scalerclkgating(dev_priv, pipe, true);
>  
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> +	/* Wa_1604331009:jsl */
> +	if (!needs_cursorclk_wa(old_crtc_state) &&
> +	    needs_cursorclk_wa(new_crtc_state))
> +		jsl_wa_cursorclkgating(dev_priv, pipe, true);

Like the idea of only enable the WA when a HDR plane is enabled but there is some problems:
- never disable the wa
- not checking if a cursor plane is also active
- calling it in the post and pre plane update, I think only the pre is needed
- checking the old state, no need to do optimizations like that for just one MMIO write

other thing, would be better have the wa function being called and inside of that function it will check if the WA is needed and write to the
register, no need of a function to check if needs and another to apply the WA.

ICL WA description says that it can only be applied if "CUR_CTL[18], CUR_CTL[16] or CUR_COLOR_CTL[15]" is not set, did you checked if when a HDR plane
is enabled it causes a complete modeset(disable pipe, set wa, enable pipe) in the pipe? if that happens it is complying if not we have a problem here.

> +
>  	/*
>  	 * Vblank time updates from the shadow to live plane control register
>  	 * are blocked if the memory self-refresh mode is active at that
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bb0656875697..f81a503c5d4b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4194,6 +4194,11 @@ enum {
>  #define INF_UNIT_LEVEL_CLKGATE		_MMIO(0x9560)
>  #define   CGPSF_CLKGATE_DIS		(1 << 3)
>  
> 
> 
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> 
> 
> +/*
> + * GEN11 clock gating regs
> + */
> +#define   CURSOR_GATING_DIS		BIT(28)

should be defined between other CLKGATE_DIS_PSL bits.

> +
>  /*
>   * Display engine regs
>   */

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Re: [Intel-gfx] [PATCH V2] drm/i915/jsl: Disable cursor clock gating in HDR mode

[Surendrakumar Upadhyay, TejaskumarX]

> -----Original Message-----
> From: Souza, Jose <jose.souza@intel.com>
> Sent: 03 November 2020 05:32
> To: Surendrakumar Upadhyay, TejaskumarX
> <tejaskumarx.surendrakumar.upadhyay@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Pandey, Hariom <hariom.pandey@intel.com>
> Subject: Re: [PATCH V2] drm/i915/jsl: Disable cursor clock gating in HDR
> mode
> 
> On Mon, 2020-11-02 at 13:09 +0530, Tejas Upadhyay wrote:
> > Display underrun in HDR mode when cursor is enabled.
> > RTL fix will be implemented CLKGATE_DIS_PSL_A bit 28-46520h.
> > As per W/A 1604331009, Disable cursor clock gating in HDR mode.
> >
> > Bspec : 33451
> >
> > Changes since V1:
> > - Modified way CLKGATE_DIS_PSL bit 28 was modified
> >
> > Cc: Souza Jose <jose.souza@intel.com>
> > Signed-off-by: Tejas Upadhyay
> > <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 28 ++++++++++++++++++++
> >  drivers/gpu/drm/i915/i915_reg.h              |  5 ++++
> >  2 files changed, 33 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index cddbda5303ff..b132585d9e78 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -541,6 +541,15 @@ icl_wa_scalerclkgating(struct drm_i915_private
> *dev_priv, enum pipe pipe,
> >                 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) &
> > ~DPFR_GATING_DIS);  }
> >
> >
> >
> >
> >
> >
> >
> >
> > +/* Wa_1604331009:jsl */
> > +static void
> > +jsl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe
> pipe,
> > +       bool enable)
> 
> if this is a gen11 WA why naming as jsl? also include in the comment icl and
> ehl.
> 
> > +{
> > +intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
> > +     CURSOR_GATING_DIS, enable ? CURSOR_GATING_DIS : 0); }
> > +
> >  static bool
> >  needs_modeset(const struct intel_crtc_state *state)  { @@ -6637,6
> > +6646,16 @@ static bool needs_scalerclk_wa(const struct
> > intel_crtc_state *crtc_state)  return false;  }
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> > +static bool needs_cursorclk_wa(const struct intel_crtc_state
> > +*crtc_state) { struct drm_i915_private *dev_priv =
> > +to_i915(crtc_state->uapi.crtc->dev);
> 
> line break here
> 
> > +/* Wa_1604331009:jsl */
> > +if (crtc_state->active_planes & icl_hdr_plane_mask() &&
> > +    IS_GEN(dev_priv, 11))
> > +return true;
> 
> line break here
> 
> > +return false;
> > +}
> > +
> >  static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
> >      const struct intel_crtc_state *new_crtc_state)  { @@ -6678,6
> > +6697,10 @@ static void intel_post_plane_update(struct
> > intel_atomic_state *state,  if (needs_scalerclk_wa(old_crtc_state) &&
> >      !needs_scalerclk_wa(new_crtc_state))
> >  icl_wa_scalerclkgating(dev_priv, pipe, false);
> > +
> > +if (needs_cursorclk_wa(old_crtc_state) &&
> > +    !needs_cursorclk_wa(new_crtc_state))
> > +jsl_wa_cursorclkgating(dev_priv, pipe, false);
> >  }
> >
> >
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> >
> >  static void skl_disable_async_flip_wa(struct intel_atomic_state
> > *state, @@ -6743,6 +6766,11 @@ static void
> intel_pre_plane_update(struct intel_atomic_state *state,
> >      needs_scalerclk_wa(new_crtc_state))
> >  icl_wa_scalerclkgating(dev_priv, pipe, true);
> >
> >
> >
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> >
> > +/* Wa_1604331009:jsl */
> > +if (!needs_cursorclk_wa(old_crtc_state) &&
> > +    needs_cursorclk_wa(new_crtc_state))
> > +jsl_wa_cursorclkgating(dev_priv, pipe, true);
> 
> Like the idea of only enable the WA when a HDR plane is enabled but there is
> some problems:
> - never disable the wa
> - not checking if a cursor plane is also active
> - calling it in the post and pre plane update, I think only the pre is needed
> - checking the old state, no need to do optimizations like that for just one
> MMIO write
> 
> other thing, would be better have the wa function being called and inside of
> that function it will check if the WA is needed and write to the register, no
> need of a function to check if needs and another to apply the WA.

Tejas : I have addressed all above review comments in next patchset.

> 
> ICL WA description says that it can only be applied if "CUR_CTL[18],
> CUR_CTL[16] or CUR_COLOR_CTL[15]" is not set, did you checked if when a
> HDR plane is enabled it causes a complete modeset(disable pipe, set wa,
> enable pipe) in the pipe? if that happens it is complying if not we have a
> problem here.

Tejas : Would you elaborate more this scenario? As far as I understand once planes are attached to CRTC/pipe they can be updated runtime. Are you referring planes attached to CRTC/pipe will change while CRTC is enable? I would like to understand if I am missing something.  

> 
> > +
> >  /*
> >   * Vblank time updates from the shadow to live plane control register
> >   * are blocked if the memory self-refresh mode is active at that diff
> > --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index bb0656875697..f81a503c5d4b
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4194,6 +4194,11 @@ enum {
> >  #define INF_UNIT_LEVEL_CLKGATE_MMIO(0x9560)
> >  #define   CGPSF_CLKGATE_DIS(1 << 3)
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> > +/*
> > + * GEN11 clock gating regs
> > + */
> > +#define   CURSOR_GATING_DISBIT(28)
> 
> should be defined between other CLKGATE_DIS_PSL bits.
> 
> > +
> >  /*
> >   * Display engine regs
> >   */
> 

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Re: [Intel-gfx] [PATCH V2] drm/i915/jsl: Disable cursor clock gating in HDR mode

[Surendrakumar Upadhyay, TejaskumarX]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Surendrakumar Upadhyay, TejaskumarX
> Sent: 30 November 2020 21:21
> To: Souza, Jose <jose.souza@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Pandey, Hariom <hariom.pandey@intel.com>
> Subject: Re: [Intel-gfx] [PATCH V2] drm/i915/jsl: Disable cursor clock gating in
> HDR mode
> 
> 
> 
> > -----Original Message-----
> > From: Souza, Jose <jose.souza@intel.com>
> > Sent: 03 November 2020 05:32
> > To: Surendrakumar Upadhyay, TejaskumarX
> > <tejaskumarx.surendrakumar.upadhyay@intel.com>; intel-
> > gfx@lists.freedesktop.org
> > Cc: Pandey, Hariom <hariom.pandey@intel.com>
> > Subject: Re: [PATCH V2] drm/i915/jsl: Disable cursor clock gating in
> > HDR mode
> >
> > On Mon, 2020-11-02 at 13:09 +0530, Tejas Upadhyay wrote:
> > > Display underrun in HDR mode when cursor is enabled.
> > > RTL fix will be implemented CLKGATE_DIS_PSL_A bit 28-46520h.
> > > As per W/A 1604331009, Disable cursor clock gating in HDR mode.
> > >
> > > Bspec : 33451
> > >
> > > Changes since V1:
> > > - Modified way CLKGATE_DIS_PSL bit 28 was modified
> > >
> > > Cc: Souza Jose <jose.souza@intel.com>
> > > Signed-off-by: Tejas Upadhyay
> > > <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display.c | 28
> ++++++++++++++++++++
> > >  drivers/gpu/drm/i915/i915_reg.h              |  5 ++++
> > >  2 files changed, 33 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index cddbda5303ff..b132585d9e78 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -541,6 +541,15 @@ icl_wa_scalerclkgating(struct drm_i915_private
> > *dev_priv, enum pipe pipe,
> > >                 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) &
> > > ~DPFR_GATING_DIS);  }
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > +/* Wa_1604331009:jsl */
> > > +static void
> > > +jsl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe
> > pipe,
> > > +       bool enable)
> >
> > if this is a gen11 WA why naming as jsl? also include in the comment
> > icl and ehl.
> >
> > > +{
> > > +intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
> > > +     CURSOR_GATING_DIS, enable ? CURSOR_GATING_DIS : 0); }
> > > +
> > >  static bool
> > >  needs_modeset(const struct intel_crtc_state *state)  { @@ -6637,6
> > > +6646,16 @@ static bool needs_scalerclk_wa(const struct
> > > intel_crtc_state *crtc_state)  return false;  }
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > +static bool needs_cursorclk_wa(const struct intel_crtc_state
> > > +*crtc_state) { struct drm_i915_private *dev_priv =
> > > +to_i915(crtc_state->uapi.crtc->dev);
> >
> > line break here
> >
> > > +/* Wa_1604331009:jsl */
> > > +if (crtc_state->active_planes & icl_hdr_plane_mask() &&
> > > +    IS_GEN(dev_priv, 11))
> > > +return true;
> >
> > line break here
> >
> > > +return false;
> > > +}
> > > +
> > >  static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
> > >      const struct intel_crtc_state *new_crtc_state)  { @@ -6678,6
> > > +6697,10 @@ static void intel_post_plane_update(struct
> > > intel_atomic_state *state,  if (needs_scalerclk_wa(old_crtc_state) &&
> > >      !needs_scalerclk_wa(new_crtc_state))
> > >  icl_wa_scalerclkgating(dev_priv, pipe, false);
> > > +
> > > +if (needs_cursorclk_wa(old_crtc_state) &&
> > > +    !needs_cursorclk_wa(new_crtc_state))
> > > +jsl_wa_cursorclkgating(dev_priv, pipe, false);
> > >  }
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
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> > >
> > >
> > >
> > >  static void skl_disable_async_flip_wa(struct intel_atomic_state
> > > *state, @@ -6743,6 +6766,11 @@ static void
> > intel_pre_plane_update(struct intel_atomic_state *state,
> > >      needs_scalerclk_wa(new_crtc_state))
> > >  icl_wa_scalerclkgating(dev_priv, pipe, true);
> > >
> > >
> > >
> > >
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> > >
> > >
> > >
> > >
> > > +/* Wa_1604331009:jsl */
> > > +if (!needs_cursorclk_wa(old_crtc_state) &&
> > > +    needs_cursorclk_wa(new_crtc_state))
> > > +jsl_wa_cursorclkgating(dev_priv, pipe, true);
> >
> > Like the idea of only enable the WA when a HDR plane is enabled but
> > there is some problems:
> > - never disable the wa
> > - not checking if a cursor plane is also active
> > - calling it in the post and pre plane update, I think only the pre is
> > needed
> > - checking the old state, no need to do optimizations like that for
> > just one MMIO write
> >
> > other thing, would be better have the wa function being called and
> > inside of that function it will check if the WA is needed and write to
> > the register, no need of a function to check if needs and another to apply
> the WA.
> 
> Tejas : I have addressed all above review comments in next patchset.
> 
> >
> > ICL WA description says that it can only be applied if "CUR_CTL[18],
> > CUR_CTL[16] or CUR_COLOR_CTL[15]" is not set, did you checked if when
> > a HDR plane is enabled it causes a complete modeset(disable pipe, set
> > wa, enable pipe) in the pipe? if that happens it is complying if not
> > we have a problem here.
> 
> Tejas : Would you elaborate more this scenario? As far as I understand once
> planes are attached to CRTC/pipe they can be updated runtime. Are you
> referring planes attached to CRTC/pipe will change while CRTC is enable? I
> would like to understand if I am missing something.

V3 patch is ready but Jose as I understand, here you referring to check when system normally boots up with 
planes are initialized and it finds HDR plane is enabled it should basically restart pipe and during restart it 
should enable W/a as well. Is there any other workaround which is doing same which I can refer ? Or if I check 
myself it will be putting logs which I can show you as proof, right!. Any other way you can suggest to prove it!

Regards,
Tejas

> 
> >
> > > +
> > >  /*
> > >   * Vblank time updates from the shadow to live plane control register
> > >   * are blocked if the memory self-refresh mode is active at that
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h index bb0656875697..f81a503c5d4b
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -4194,6 +4194,11 @@ enum {
> > >  #define INF_UNIT_LEVEL_CLKGATE_MMIO(0x9560)
> > >  #define   CGPSF_CLKGATE_DIS(1 << 3)
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > +/*
> > > + * GEN11 clock gating regs
> > > + */
> > > +#define   CURSOR_GATING_DISBIT(28)
> >
> > should be defined between other CLKGATE_DIS_PSL bits.
> >
> > > +
> > >  /*
> > >   * Display engine regs
> > >   */
> >
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
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