* [Intel-gfx] [PATCH v2] drm/i915/display: Set correct voltage level for 480MHz CDCLK
@ 2023-05-29 6:07 Chaitanya Kumar Borah
2023-05-29 7:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Set correct voltage level for 480MHz CDCLK (rev2) Patchwork
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Chaitanya Kumar Borah @ 2023-05-29 6:07 UTC (permalink / raw)
To: intel-gfx; +Cc: matthew.d.roper
According to Bspec, the voltage level for 480MHz is to be set as 1
instead of 2.
BSpec: 49208
Fixes: 06f1b06dc5b7 ("drm/i915/display: Add 480 MHz CDCLK steps for RPL-U")
v2: rebase
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 30 +++++++++++++++++++---
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 6bed75f1541a..1a5268e3d0a3 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1453,6 +1453,18 @@ static u8 tgl_calc_voltage_level(int cdclk)
return 0;
}
+static u8 rplu_calc_voltage_level(int cdclk)
+{
+ if (cdclk > 556800)
+ return 3;
+ else if (cdclk > 480000)
+ return 2;
+ else if (cdclk > 312000)
+ return 1;
+ else
+ return 0;
+}
+
static void icl_readout_refclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
@@ -3397,6 +3409,13 @@ static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
.calc_voltage_level = tgl_calc_voltage_level,
};
+static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = rplu_calc_voltage_level,
+};
+
static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3539,14 +3558,17 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
- dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
/* Wa_22011320316:adl-p[a0] */
- if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+ if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
- else if (IS_ADLP_RPLU(dev_priv))
+ dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
+ } else if (IS_ADLP_RPLU(dev_priv)) {
dev_priv->display.cdclk.table = rplu_cdclk_table;
- else
+ dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
+ } else {
dev_priv->display.cdclk.table = adlp_cdclk_table;
+ dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
+ }
} else if (IS_ROCKETLAKE(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->display.cdclk.table = rkl_cdclk_table;
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Set correct voltage level for 480MHz CDCLK (rev2)
2023-05-29 6:07 [Intel-gfx] [PATCH v2] drm/i915/display: Set correct voltage level for 480MHz CDCLK Chaitanya Kumar Borah
@ 2023-05-29 7:14 ` Patchwork
2023-05-29 9:25 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-05-31 11:08 ` [Intel-gfx] [PATCH v2] drm/i915/display: Set correct voltage level for 480MHz CDCLK Kahola, Mika
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2023-05-29 7:14 UTC (permalink / raw)
To: Chaitanya Kumar Borah; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5782 bytes --]
== Series Details ==
Series: drm/i915/display: Set correct voltage level for 480MHz CDCLK (rev2)
URL : https://patchwork.freedesktop.org/series/114752/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13198 -> Patchwork_114752v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/index.html
Participating hosts (38 -> 37)
------------------------------
Missing (1): fi-kbl-soraka
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_114752v2:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@migrate:
- {bat-mtlp-8}: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13198/bat-mtlp-8/igt@i915_selftest@live@migrate.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/bat-mtlp-8/igt@i915_selftest@live@migrate.html
Known issues
------------
Here are the changes found in Patchwork_114752v2 that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- fi-kbl-8809g: [PASS][3] -> [FAIL][4] ([i915#8293] / [i915#8298])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13198/fi-kbl-8809g/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/fi-kbl-8809g/boot.html
### IGT changes ###
#### Issues hit ####
* igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][5] ([i915#6687] / [i915#7978])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/bat-rpls-1/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- fi-skl-6600u: NOTRUN -> [SKIP][6] ([fdo#109271])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/fi-skl-6600u/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
#### Possible fixes ####
* igt@dmabuf@all-tests@dma_fence:
- fi-skl-6600u: [DMESG-FAIL][7] ([i915#8189]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13198/fi-skl-6600u/igt@dmabuf@all-tests@dma_fence.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/fi-skl-6600u/igt@dmabuf@all-tests@dma_fence.html
* igt@dmabuf@all-tests@sanitycheck:
- fi-skl-6600u: [ABORT][9] -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13198/fi-skl-6600u/igt@dmabuf@all-tests@sanitycheck.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/fi-skl-6600u/igt@dmabuf@all-tests@sanitycheck.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [ABORT][11] ([i915#4983] / [i915#7911] / [i915#7920]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13198/bat-rpls-1/igt@i915_selftest@live@requests.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/bat-rpls-1/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@slpc:
- {bat-mtlp-6}: [DMESG-WARN][13] ([i915#6367]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13198/bat-mtlp-6/igt@i915_selftest@live@slpc.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/bat-mtlp-6/igt@i915_selftest@live@slpc.html
- bat-rpls-2: [DMESG-WARN][15] ([i915#6367]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13198/bat-rpls-2/igt@i915_selftest@live@slpc.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/bat-rpls-2/igt@i915_selftest@live@slpc.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [FAIL][17] ([i915#7932]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13198/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#8189]: https://gitlab.freedesktop.org/drm/intel/issues/8189
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8298]: https://gitlab.freedesktop.org/drm/intel/issues/8298
Build changes
-------------
* Linux: CI_DRM_13198 -> Patchwork_114752v2
CI-20190529: 20190529
CI_DRM_13198: cf59b48ea3c0c0075d7c4e8538177d38999da7b0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7308: 766edf96979bf13a10c9985c007f2baca5c9e308 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_114752v2: cf59b48ea3c0c0075d7c4e8538177d38999da7b0 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
150b7df9350c drm/i915/display: Set correct voltage level for 480MHz CDCLK
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/index.html
[-- Attachment #2: Type: text/html, Size: 6625 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Set correct voltage level for 480MHz CDCLK (rev2)
2023-05-29 6:07 [Intel-gfx] [PATCH v2] drm/i915/display: Set correct voltage level for 480MHz CDCLK Chaitanya Kumar Borah
2023-05-29 7:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Set correct voltage level for 480MHz CDCLK (rev2) Patchwork
@ 2023-05-29 9:25 ` Patchwork
2023-05-31 11:08 ` [Intel-gfx] [PATCH v2] drm/i915/display: Set correct voltage level for 480MHz CDCLK Kahola, Mika
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2023-05-29 9:25 UTC (permalink / raw)
To: Chaitanya Kumar Borah; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 15071 bytes --]
== Series Details ==
Series: drm/i915/display: Set correct voltage level for 480MHz CDCLK (rev2)
URL : https://patchwork.freedesktop.org/series/114752/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13198_full -> Patchwork_114752v2_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_114752v2_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_114752v2_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (8 -> 7)
------------------------------
Missing (1): shard-rkl0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_114752v2_full:
### IGT changes ###
#### Warnings ####
* igt@kms_hdmi_inject@inject-audio:
- shard-snb: [SKIP][1] ([fdo#109271]) -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13198/shard-snb6/igt@kms_hdmi_inject@inject-audio.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-snb2/igt@kms_hdmi_inject@inject-audio.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_hdmi_inject@inject-audio:
- {shard-tglu}: [SKIP][3] ([i915#433]) -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13198/shard-tglu-3/igt@kms_hdmi_inject@inject-audio.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-tglu-7/igt@kms_hdmi_inject@inject-audio.html
Known issues
------------
Here are the changes found in Patchwork_114752v2_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-apl: [PASS][5] -> [ABORT][6] ([i915#180])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13198/shard-apl6/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-apl3/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2846])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13198/shard-glk7/igt@gem_exec_fair@basic-deadline.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-glk5/igt@gem_exec_fair@basic-deadline.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-apl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-apl7/igt@gem_lmem_swapping@heavy-multi.html
* igt@i915_pm_rpm@modeset-lpsp:
- shard-apl: NOTRUN -> [SKIP][10] ([fdo#109271]) +30 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-apl7/igt@i915_pm_rpm@modeset-lpsp.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#3886]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-apl7/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_flip@2x-plain-flip-fb-recreate:
- shard-snb: NOTRUN -> [SKIP][12] ([fdo#109271]) +10 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-snb6/igt@kms_flip@2x-plain-flip-fb-recreate.html
* igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-valid-mode:
- shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4579]) +4 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-apl7/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
- shard-apl: NOTRUN -> [SKIP][14] ([IGT#6] / [fdo#109271]) +21 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-apl7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_hdr@static-swap:
- shard-apl: NOTRUN -> [SKIP][15] ([IGT#6] / [fdo#109271] / [i915#4579])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-apl7/igt@kms_hdr@static-swap.html
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-b-vga-1:
- shard-snb: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4579]) +6 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-snb6/igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-b-vga-1.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#658])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-apl7/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- {shard-rkl}: [FAIL][18] ([i915#7742]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13198/shard-rkl-3/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-rkl-2/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@gem_ctx_freq@sysfs:
- {shard-dg1}: [FAIL][20] ([i915#6786]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13198/shard-dg1-16/igt@gem_ctx_freq@sysfs.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-dg1-16/igt@gem_ctx_freq@sysfs.html
* igt@gem_exec_fair@basic-none@bcs0:
- {shard-rkl}: [FAIL][22] ([i915#2842]) -> [PASS][23] +2 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13198/shard-rkl-7/igt@gem_exec_fair@basic-none@bcs0.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-rkl-7/igt@gem_exec_fair@basic-none@bcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [FAIL][24] ([i915#2842]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13198/shard-glk6/igt@gem_exec_fair@basic-pace@rcs0.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-glk2/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1:
- shard-apl: [ABORT][26] ([i915#180]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13198/shard-apl1/igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-apl7/igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-apl: [FAIL][28] ([IGT#6] / [i915#2346]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13198/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [FAIL][30] ([IGT#6] / [i915#2346]) -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13198/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][32] ([i915#79]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13198/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@plain-flip-ts-check@b-hdmi-a1:
- shard-glk: [FAIL][34] ([i915#2122]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13198/shard-glk6/igt@kms_flip@plain-flip-ts-check@b-hdmi-a1.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/shard-glk4/igt@kms_flip@plain-flip-ts-check@b-hdmi-a1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6786]: https://gitlab.freedesktop.org/drm/intel/issues/6786
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#7984]: https://gitlab.freedesktop.org/drm/intel/issues/7984
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234
[i915#8398]: https://gitlab.freedesktop.org/drm/intel/issues/8398
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
Build changes
-------------
* Linux: CI_DRM_13198 -> Patchwork_114752v2
CI-20190529: 20190529
CI_DRM_13198: cf59b48ea3c0c0075d7c4e8538177d38999da7b0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7308: 766edf96979bf13a10c9985c007f2baca5c9e308 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_114752v2: cf59b48ea3c0c0075d7c4e8538177d38999da7b0 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114752v2/index.html
[-- Attachment #2: Type: text/html, Size: 12631 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/display: Set correct voltage level for 480MHz CDCLK
2023-05-29 6:07 [Intel-gfx] [PATCH v2] drm/i915/display: Set correct voltage level for 480MHz CDCLK Chaitanya Kumar Borah
2023-05-29 7:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Set correct voltage level for 480MHz CDCLK (rev2) Patchwork
2023-05-29 9:25 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2023-05-31 11:08 ` Kahola, Mika
2023-06-02 22:01 ` Matt Roper
2 siblings, 1 reply; 5+ messages in thread
From: Kahola, Mika @ 2023-05-31 11:08 UTC (permalink / raw)
To: Borah, Chaitanya Kumar, intel-gfx; +Cc: Roper, Matthew D
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Chaitanya Kumar Borah
> Sent: Monday, May 29, 2023 9:08 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D <matthew.d.roper@intel.com>
> Subject: [Intel-gfx] [PATCH v2] drm/i915/display: Set correct voltage level for 480MHz CDCLK
>
> According to Bspec, the voltage level for 480MHz is to be set as 1 instead of 2.
>
> BSpec: 49208
>
> Fixes: 06f1b06dc5b7 ("drm/i915/display: Add 480 MHz CDCLK steps for RPL-U")
>
> v2: rebase
>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 30 +++++++++++++++++++---
> 1 file changed, 26 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 6bed75f1541a..1a5268e3d0a3 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1453,6 +1453,18 @@ static u8 tgl_calc_voltage_level(int cdclk)
> return 0;
> }
>
> +static u8 rplu_calc_voltage_level(int cdclk) {
> + if (cdclk > 556800)
> + return 3;
> + else if (cdclk > 480000)
> + return 2;
> + else if (cdclk > 312000)
> + return 1;
> + else
> + return 0;
> +}
The spec defines that we should use level 1 in case of SKU supports 480MHz cd clock and max DDI symbol clock is less than or equal to 594MHz. I didn't spot from the spec a scenario where we would have SKU with 480 MHz cd clock frequency and the DDI symbol clock rate would exceed 594MHz.
Therefore, the change looks ok to me.
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> +
> static void icl_readout_refclk(struct drm_i915_private *dev_priv,
> struct intel_cdclk_config *cdclk_config) { @@ -3397,6 +3409,13 @@ static const struct
> intel_cdclk_funcs mtl_cdclk_funcs = {
> .calc_voltage_level = tgl_calc_voltage_level, };
>
> +static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
> + .get_cdclk = bxt_get_cdclk,
> + .set_cdclk = bxt_set_cdclk,
> + .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
> + .calc_voltage_level = rplu_calc_voltage_level, };
> +
> static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
> .get_cdclk = bxt_get_cdclk,
> .set_cdclk = bxt_set_cdclk,
> @@ -3539,14 +3558,17 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> dev_priv->display.cdclk.table = dg2_cdclk_table;
> } else if (IS_ALDERLAKE_P(dev_priv)) {
> - dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> /* Wa_22011320316:adl-p[a0] */
> - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> + if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
> dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
> - else if (IS_ADLP_RPLU(dev_priv))
> + dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> + } else if (IS_ADLP_RPLU(dev_priv)) {
> dev_priv->display.cdclk.table = rplu_cdclk_table;
> - else
> + dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
> + } else {
> dev_priv->display.cdclk.table = adlp_cdclk_table;
> + dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> + }
> } else if (IS_ROCKETLAKE(dev_priv)) {
> dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> dev_priv->display.cdclk.table = rkl_cdclk_table;
> --
> 2.25.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/display: Set correct voltage level for 480MHz CDCLK
2023-05-31 11:08 ` [Intel-gfx] [PATCH v2] drm/i915/display: Set correct voltage level for 480MHz CDCLK Kahola, Mika
@ 2023-06-02 22:01 ` Matt Roper
0 siblings, 0 replies; 5+ messages in thread
From: Matt Roper @ 2023-06-02 22:01 UTC (permalink / raw)
To: Kahola, Mika; +Cc: intel-gfx
On Wed, May 31, 2023 at 11:08:12AM +0000, Kahola, Mika wrote:
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Chaitanya Kumar Borah
> > Sent: Monday, May 29, 2023 9:08 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Roper, Matthew D <matthew.d.roper@intel.com>
> > Subject: [Intel-gfx] [PATCH v2] drm/i915/display: Set correct voltage level for 480MHz CDCLK
> >
> > According to Bspec, the voltage level for 480MHz is to be set as 1 instead of 2.
> >
> > BSpec: 49208
> >
> > Fixes: 06f1b06dc5b7 ("drm/i915/display: Add 480 MHz CDCLK steps for RPL-U")
> >
> > v2: rebase
> >
> > Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 30 +++++++++++++++++++---
> > 1 file changed, 26 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 6bed75f1541a..1a5268e3d0a3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1453,6 +1453,18 @@ static u8 tgl_calc_voltage_level(int cdclk)
> > return 0;
> > }
> >
> > +static u8 rplu_calc_voltage_level(int cdclk) {
> > + if (cdclk > 556800)
> > + return 3;
> > + else if (cdclk > 480000)
> > + return 2;
> > + else if (cdclk > 312000)
> > + return 1;
> > + else
> > + return 0;
> > +}
>
> The spec defines that we should use level 1 in case of SKU supports 480MHz cd clock and max DDI symbol clock is less than or equal to 594MHz. I didn't spot from the spec a scenario where we would have SKU with 480 MHz cd clock frequency and the DDI symbol clock rate would exceed 594MHz.
>
> Therefore, the change looks ok to me.
>
> Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Applied to drm-intel-next. Thanks for the patch and review.
Matt
>
> > +
> > static void icl_readout_refclk(struct drm_i915_private *dev_priv,
> > struct intel_cdclk_config *cdclk_config) { @@ -3397,6 +3409,13 @@ static const struct
> > intel_cdclk_funcs mtl_cdclk_funcs = {
> > .calc_voltage_level = tgl_calc_voltage_level, };
> >
> > +static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
> > + .get_cdclk = bxt_get_cdclk,
> > + .set_cdclk = bxt_set_cdclk,
> > + .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
> > + .calc_voltage_level = rplu_calc_voltage_level, };
> > +
> > static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
> > .get_cdclk = bxt_get_cdclk,
> > .set_cdclk = bxt_set_cdclk,
> > @@ -3539,14 +3558,17 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> > dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> > dev_priv->display.cdclk.table = dg2_cdclk_table;
> > } else if (IS_ALDERLAKE_P(dev_priv)) {
> > - dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> > /* Wa_22011320316:adl-p[a0] */
> > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > + if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
> > dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
> > - else if (IS_ADLP_RPLU(dev_priv))
> > + dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> > + } else if (IS_ADLP_RPLU(dev_priv)) {
> > dev_priv->display.cdclk.table = rplu_cdclk_table;
> > - else
> > + dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
> > + } else {
> > dev_priv->display.cdclk.table = adlp_cdclk_table;
> > + dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> > + }
> > } else if (IS_ROCKETLAKE(dev_priv)) {
> > dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> > dev_priv->display.cdclk.table = rkl_cdclk_table;
> > --
> > 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-06-02 22:01 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-29 6:07 [Intel-gfx] [PATCH v2] drm/i915/display: Set correct voltage level for 480MHz CDCLK Chaitanya Kumar Borah
2023-05-29 7:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Set correct voltage level for 480MHz CDCLK (rev2) Patchwork
2023-05-29 9:25 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-05-31 11:08 ` [Intel-gfx] [PATCH v2] drm/i915/display: Set correct voltage level for 480MHz CDCLK Kahola, Mika
2023-06-02 22:01 ` Matt Roper
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