[Intel-gfx] [PATCH v4 00/18] VRR/Adaptive Sync Enabling on DP/eDP for TGL+

[Intel-gfx] [PATCH v4 00/18] VRR/Adaptive Sync Enabling on DP/eDP for TGL+

[Manasi Navare]

This series address review comments from Ville
and incorporates some suggested fixes plus his
patches.

Aditya Swarup (1):
  drm/i915/display/dp: Attach and set drm connector VRR property

Manasi Navare (8):
  drm/i915/display/vrr: Create VRR file and add VRR capability check
  drm/i915/display/dp: Compute VRR state in atomic_check
  drm/i915/display/dp: Do not enable PSR if VRR is enabled
  drm/i915/display/vrr: Configure and enable VRR in modeset enable
  drm/i915/display/vrr: Send VRR push to flip the frame
  drm/i915/display/vrr: Disable VRR in modeset disable path
  drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink
  drm/i915/display: Add HW state readout for VRR

Ville Syrjälä (9):
  drm/i915: Store framestart_delay in dev_priv
  drm/i915: Extract intel_mode_vblank_start()
  drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp()
  drm/i915/display: VRR + DRRS cannot be enabled together
  drm/i915: Rename VRR_CTL reg fields
  drm/i915/display: Helpers for VRR vblank min and max start
  drm/i915: Add vrr state dump
  drm/i915: Fix vblank timestamps with VRR
  drm/i915: Fix vblank evasion with vrr

 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/intel_ddi.c      |  24 ++
 drivers/gpu/drm/i915/display/intel_display.c  |  58 +++--
 .../drm/i915/display/intel_display_types.h    |  11 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  12 +
 .../drm/i915/display/intel_dp_link_training.c |   2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |   7 +
 drivers/gpu/drm/i915/display/intel_sprite.c   |  21 +-
 drivers/gpu/drm/i915/display/intel_vrr.c      | 209 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h      |  33 +++
 drivers/gpu/drm/i915/i915_drv.h               |   4 +
 drivers/gpu/drm/i915/i915_irq.c               |  53 +++--
 drivers/gpu/drm/i915/i915_reg.h               |  14 +-
 13 files changed, 408 insertions(+), 41 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.h

-- 
2.19.1

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[Intel-gfx] [PATCH v4 01/18] drm/i915/display/vrr: Create VRR file and add VRR capability check

[Manasi Navare]

We create a new file for all VRR related helpers.
Also add a function to check vrr capability based on
platform support, DPCD bits and EDID monitor range.

v2:
* Remove author (Jani N)
* Define HAS_VRR (Jani N)
* Ensure intel_dp can be obtained from conn (Jani N)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/Makefile            |  1 +
 drivers/gpu/drm/i915/display/intel_vrr.c | 32 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h | 15 +++++++++++
 drivers/gpu/drm/i915/i915_drv.h          |  2 ++
 4 files changed, 50 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d6ac946d0407..c9edaa5d2821 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -255,6 +255,7 @@ i915-y += \
 	display/intel_sdvo.o \
 	display/intel_tv.o \
 	display/intel_vdsc.o \
+	display/intel_vrr.o \
 	display/vlv_dsi.o \
 	display/vlv_dsi_pll.o
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
new file mode 100644
index 000000000000..8a427c152341
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ */
+
+#include "i915_drv.h"
+#include "intel_display_types.h"
+#include "intel_vrr.h"
+
+bool intel_vrr_is_capable(struct drm_connector *connector)
+{
+	struct intel_dp *intel_dp;
+	const struct drm_display_info *info = &connector->display_info;
+	struct drm_i915_private *i915 = to_i915(connector->dev);
+
+	if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
+	    connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
+		return false;
+
+	intel_dp = intel_attached_dp(to_intel_connector(connector));
+	/*
+	 * DP Sink is capable of Variable refresh video timings if
+	 * Ignore MSA bit is set in DPCD.
+	 * EDID monitor range also should be atleast 10 for reasonable
+	 * Adaptive sync/ VRR end user experience.
+	 */
+	return HAS_VRR(i915) &&
+		drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) &&
+		info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
+}
+
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
new file mode 100644
index 000000000000..3700acec5d09
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+*/
+
+#ifndef __INTEL_VRR_H__
+#define __INTEL_VRR_H__
+
+#include <linux/types.h>
+
+struct drm_connector;
+
+bool intel_vrr_is_capable(struct drm_connector *connector);
+
+#endif /* __INTEL_VRR_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e3d58299b323..15e016194685 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1758,6 +1758,8 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
 
 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
 
+#define HAS_VRR(i915)	(INTEL_GEN(i915) >= 12)
+
 /* Only valid when HAS_DISPLAY() is true */
 #define INTEL_DISPLAY_ENABLED(dev_priv) \
 	(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
-- 
2.19.1

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[Intel-gfx] [PATCH v4 02/18] drm/i915/display/dp: Attach and set drm connector VRR property

[Manasi Navare]

From: Aditya Swarup <aditya.swarup@intel.com>

This function sets the VRR property for connector based
on the platform support, EDID monitor range and DP sink
DPCD capability of outputing video without msa
timing information.

v8:
* Use HAS_VRR, remove drm_conn declaration (Jani N)
* Fix typos in Comment (Jani N)
v7:
* Move the helper to separate file (Manasi)
v6:
* Remove unset of prop
v5:
* Fix the vrr prop not being set in kernel (Manasi)
* Unset the prop on connector disconnect (Manasi)
v4:
* Rebase (Mansi)
v3:
* intel_dp_is_vrr_capable can be used for debugfs, make it
non static (Manasi)
v2:
* Just set this in intel_dp_get_modes instead of new hook (Jani)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c  | 8 ++++++++
 drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++--
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0433b6394137..dd093ae5b8bb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -62,6 +62,7 @@
 #include "intel_sideband.h"
 #include "intel_tc.h"
 #include "intel_vdsc.h"
+#include "intel_vrr.h"
 
 #define DP_DPRX_ESI_LEN 14
 
@@ -7235,6 +7236,10 @@ static int intel_dp_get_modes(struct drm_connector *connector)
 	edid = intel_connector->detect_edid;
 	if (edid) {
 		int ret = intel_connector_update_modes(connector, edid);
+
+		if (intel_vrr_is_capable(connector))
+			drm_connector_set_vrr_capable_property(connector,
+							       true);
 		if (ret)
 			return ret;
 	}
@@ -7719,6 +7724,9 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
 		connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
 
 	}
+
+	if (HAS_VRR(dev_priv))
+		drm_connector_attach_vrr_capable_property(connector);
 }
 
 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 8a427c152341..869e41aa8396 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -20,10 +20,10 @@ bool intel_vrr_is_capable(struct drm_connector *connector)
 
 	intel_dp = intel_attached_dp(to_intel_connector(connector));
 	/*
-	 * DP Sink is capable of Variable refresh video timings if
+	 * DP Sink is capable of VRR video timings if
 	 * Ignore MSA bit is set in DPCD.
 	 * EDID monitor range also should be atleast 10 for reasonable
-	 * Adaptive sync/ VRR end user experience.
+	 * Adaptive Sync or Variable Refresh Rate end user experience.
 	 */
 	return HAS_VRR(i915) &&
 		drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) &&
-- 
2.19.1

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[Intel-gfx] [PATCH v4 03/18] drm/i915: Store framestart_delay in dev_priv

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The vrr calculations will need to know the framestart delay value
we use. Currently we program it always to zero, but should that change
we probably want to stash it somewhere.

Could stick it into the crtc_state I suppose, but since we never
change it let's just stuff it into dev_priv for now.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++++---------
 drivers/gpu/drm/i915/i915_drv.h              |  2 ++
 2 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0189d379a55e..67a55cfa5354 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1610,7 +1610,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 		val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
 		/* Configure frame start delay to match the CPU */
 		val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
-		val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
+		val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay);
 		intel_de_write(dev_priv, reg, val);
 	}
 
@@ -1621,7 +1621,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 	if (HAS_PCH_IBX(dev_priv)) {
 		/* Configure frame start delay to match the CPU */
 		val &= ~TRANS_FRAME_START_DELAY_MASK;
-		val |= TRANS_FRAME_START_DELAY(0);
+		val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay);
 
 		/*
 		 * Make the BPC in transcoder be consistent with
@@ -1666,7 +1666,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 	val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
 	/* Configure frame start delay to match the CPU */
 	val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
-	val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
+	val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay);
 	intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
 
 	val = TRANS_ENABLE;
@@ -6679,7 +6679,7 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
 
 	val = intel_de_read(dev_priv, reg);
 	val &= ~HSW_FRAME_START_DELAY_MASK;
-	val |= HSW_FRAME_START_DELAY(0);
+	val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay);
 	intel_de_write(dev_priv, reg, val);
 }
 
@@ -8741,7 +8741,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
 
 	pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
 
-	pipeconf |= PIPECONF_FRAME_START_DELAY(0);
+	pipeconf |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay);
 
 	intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
 	intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
@@ -9850,7 +9850,7 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
 
 	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
 
-	val |= PIPECONF_FRAME_START_DELAY(0);
+	val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay);
 
 	intel_de_write(dev_priv, PIPECONF(pipe), val);
 	intel_de_posting_read(dev_priv, PIPECONF(pipe));
@@ -17153,6 +17153,8 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
 	i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
 					WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
 
+	i915->framestart_delay = 0; /* 0-3 */
+
 	intel_mode_config_init(i915);
 
 	ret = intel_cdclk_init(i915);
@@ -17487,7 +17489,7 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
 
 		val = intel_de_read(dev_priv, reg);
 		val &= ~HSW_FRAME_START_DELAY_MASK;
-		val |= HSW_FRAME_START_DELAY(0);
+		val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay);
 		intel_de_write(dev_priv, reg, val);
 	} else {
 		i915_reg_t reg = PIPECONF(cpu_transcoder);
@@ -17495,7 +17497,7 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
 
 		val = intel_de_read(dev_priv, reg);
 		val &= ~PIPECONF_FRAME_START_DELAY_MASK;
-		val |= PIPECONF_FRAME_START_DELAY(0);
+		val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay);
 		intel_de_write(dev_priv, reg, val);
 	}
 
@@ -17508,7 +17510,7 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
 
 		val = intel_de_read(dev_priv, reg);
 		val &= ~TRANS_FRAME_START_DELAY_MASK;
-		val |= TRANS_FRAME_START_DELAY(0);
+		val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay);
 		intel_de_write(dev_priv, reg, val);
 	} else {
 		enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
@@ -17517,7 +17519,7 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
 
 		val = intel_de_read(dev_priv, reg);
 		val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
-		val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
+		val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay);
 		intel_de_write(dev_priv, reg, val);
 	}
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 15e016194685..94a27e72b0a8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1182,6 +1182,8 @@ struct drm_i915_private {
 		struct file *mmap_singleton;
 	} gem;
 
+	u8 framestart_delay;
+
 	u8 pch_ssc_use;
 
 	/* For i915gm/i945gm vblank irq workaround */
-- 
2.19.1

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[Intel-gfx] [PATCH v4 04/18] drm/i915: Extract intel_mode_vblank_start()

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We want to calculate the vblank_start for vblank evasion
differently for vrr. To make that nicer lets first extract
the current non-vrr case to a helper.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_sprite.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index cf3589fd0ddb..ced6af7cdc84 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -62,6 +62,16 @@ int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
 			    1000 * adjusted_mode->crtc_htotal);
 }
 
+static int intel_mode_vblank_start(const struct drm_display_mode *mode)
+{
+	int vblank_start = mode->crtc_vblank_start;
+
+	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+		vblank_start = DIV_ROUND_UP(vblank_start, 2);
+
+	return vblank_start;
+}
+
 /**
  * intel_pipe_update_start() - start update of a set of display registers
  * @new_crtc_state: the new crtc state
@@ -90,9 +100,7 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
 	if (new_crtc_state->uapi.async_flip)
 		return;
 
-	vblank_start = adjusted_mode->crtc_vblank_start;
-	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
-		vblank_start = DIV_ROUND_UP(vblank_start, 2);
+	vblank_start = intel_mode_vblank_start(adjusted_mode);
 
 	/* FIXME needs to be calibrated sensibly */
 	min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
-- 
2.19.1

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[Intel-gfx] [PATCH v4 05/18] drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp()

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract intel_crtc_scanlines_since_frame_timestamp() from
__intel_get_crtc_scanline_from_timestamp(). We'll reuse this
for VRR vblank timestamps.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 38 +++++++++++++++++++++------------
 1 file changed, 24 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dd1971040bbc..8505ceca87d5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -718,25 +718,15 @@ u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
 	return intel_uncore_read(&dev_priv->uncore, PIPE_FRMCOUNT_G4X(pipe));
 }
 
-/*
- * On certain encoders on certain platforms, pipe
- * scanline register will not work to get the scanline,
- * since the timings are driven from the PORT or issues
- * with scanline register updates.
- * This function will use Framestamp and current
- * timestamp registers to calculate the scanline.
- */
-static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
+static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct drm_vblank_crtc *vblank =
 		&crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
 	const struct drm_display_mode *mode = &vblank->hwmode;
-	u32 vblank_start = mode->crtc_vblank_start;
-	u32 vtotal = mode->crtc_vtotal;
 	u32 htotal = mode->crtc_htotal;
 	u32 clock = mode->crtc_clock;
-	u32 scanline, scan_prev_time, scan_curr_time, scan_post_time;
+	u32 scan_prev_time, scan_curr_time, scan_post_time;
 
 	/*
 	 * To avoid the race condition where we might cross into the
@@ -763,8 +753,28 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
 						  PIPE_FRMTMSTMP(crtc->pipe));
 	} while (scan_post_time != scan_prev_time);
 
-	scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
-					clock), 1000 * htotal);
+	return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
+				   clock), 1000 * htotal);
+}
+
+/*
+ * On certain encoders on certain platforms, pipe
+ * scanline register will not work to get the scanline,
+ * since the timings are driven from the PORT or issues
+ * with scanline register updates.
+ * This function will use Framestamp and current
+ * timestamp registers to calculate the scanline.
+ */
+static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
+{
+	struct drm_vblank_crtc *vblank =
+		&crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
+	const struct drm_display_mode *mode = &vblank->hwmode;
+	u32 vblank_start = mode->crtc_vblank_start;
+	u32 vtotal = mode->crtc_vtotal;
+	u32 scanline;
+
+	scanline = intel_crtc_scanlines_since_frame_timestamp(crtc);
 	scanline = min(scanline, vtotal - 1);
 	scanline = (scanline + vblank_start) % vtotal;
 
-- 
2.19.1

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[Intel-gfx] [PATCH v4 06/18] drm/i915/display/dp: Compute VRR state in atomic_check

[Manasi Navare]

This forces a complete modeset if vrr drm crtc state goes
from enabled to disabled and vice versa.
This patch also computes vrr state variables from the mode timings
and based on the vrr property set by userspace as well as hardware's
vrr capability.

v2:
*Rebase
v3:
* Vmin = max (vtotal, vmin) (Manasi)
v4:
* set crtc_state->vrr.enable = 0 for disable request
v5:
* drm_dbg_kms, squash crtc states def patch (Jani N)
v6:
* Move vrr modeset check to separate function (Jani N)
v7:
* Ville's fixes - vmin, vmax rename, fix rounding dir
* Add pipeline full, flipline to crtc state
* Pass conn state to vrr_compute_config (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |  9 +++
 .../drm/i915/display/intel_display_types.h    |  7 ++
 drivers/gpu/drm/i915/display/intel_dp.c       |  1 +
 drivers/gpu/drm/i915/display/intel_vrr.c      | 70 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h      |  8 +++
 5 files changed, 95 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 67a55cfa5354..22bda7a55cc0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -57,6 +57,7 @@
 #include "display/intel_sdvo.h"
 #include "display/intel_tv.h"
 #include "display/intel_vdsc.h"
+#include "display/intel_vrr.h"
 
 #include "gt/intel_rps.h"
 
@@ -13360,6 +13361,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
 	PIPE_CONF_CHECK_I(mst_master_transcoder);
 
+	PIPE_CONF_CHECK_BOOL(vrr.enable);
+	PIPE_CONF_CHECK_I(vrr.vmin);
+	PIPE_CONF_CHECK_I(vrr.vmax);
+	PIPE_CONF_CHECK_I(vrr.flipline);
+	PIPE_CONF_CHECK_I(vrr.pipeline_full);
+
 #undef PIPE_CONF_CHECK_X
 #undef PIPE_CONF_CHECK_I
 #undef PIPE_CONF_CHECK_BOOL
@@ -14517,6 +14524,8 @@ static int intel_atomic_check(struct drm_device *dev,
 			new_crtc_state->uapi.mode_changed = true;
 	}
 
+	intel_vrr_check_modeset(state);
+
 	ret = drm_atomic_helper_check_modeset(dev, &state->base);
 	if (ret)
 		goto fail;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 24792102bcf6..aa0842028414 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1137,6 +1137,13 @@ struct intel_crtc_state {
 	struct intel_dsb *dsb;
 
 	u32 psr2_man_track_ctl;
+
+	/* Variable Refresh Rate state */
+	struct {
+		bool enable;
+		u8 pipeline_full;
+		u16 flipline, vmin, vmax;
+	} vrr;
 };
 
 enum intel_pipe_crc_source {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index dd093ae5b8bb..a275303c0c5c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2948,6 +2948,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	if (!HAS_DDI(dev_priv))
 		intel_dp_set_clock(encoder, pipe_config);
 
+	intel_vrr_compute_config(pipe_config, conn_state);
 	intel_psr_compute_config(intel_dp, pipe_config);
 	intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp,
 				     constant_n);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 869e41aa8396..466663be90f5 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -30,3 +30,73 @@ bool intel_vrr_is_capable(struct drm_connector *connector)
 		info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
 }
 
+void
+intel_vrr_check_modeset(struct intel_atomic_state *state)
+{
+	int i;
+	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
+	struct intel_crtc *crtc;
+
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		if (new_crtc_state->uapi.vrr_enabled !=
+		    old_crtc_state->uapi.vrr_enabled)
+			new_crtc_state->uapi.mode_changed = true;
+	}
+}
+
+void
+intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
+			 struct drm_connector_state *conn_state)
+{
+	struct intel_connector *connector =
+		to_intel_connector(conn_state->connector);
+	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	const struct drm_display_info *info = &connector->base.display_info;
+	int vmin, vmax;
+
+	if (!intel_vrr_is_capable(&connector->base))
+		return;
+
+	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
+		return;
+
+	if (!crtc_state->uapi.vrr_enabled)
+		return;
+
+	vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
+			    adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq);
+	vmax = adjusted_mode->crtc_clock * 1000 /
+		(adjusted_mode->crtc_htotal * info->monitor_range.min_vfreq);
+
+	vmin = max_t(int, vmin, adjusted_mode->crtc_vtotal);
+	vmax = max_t(int, vmax, adjusted_mode->crtc_vtotal);
+
+	if (vmin >= vmax)
+		return;
+
+	/*
+	 * flipline determines the min vblank length the hardware will
+	 * generate, and flipline>=vmin+1, hence we reduce vmin by one
+	 * to make sure we can get the actual min vblank length.
+	 */
+	crtc_state->vrr.vmin = vmin - 1;
+	crtc_state->vrr.vmax = vmax;
+	crtc_state->vrr.enable = true;
+
+	crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1;
+
+	/*
+	 * FIXME: s/4/framestart_delay+1/ to get consistent
+	 * earliest/latest points for register latching regardless
+	 * of the framestart_delay used?
+	 *
+	 * FIXME: this really needs the extra scanline to provide consistent
+	 * behaviour for all framestart_delay values. Otherwise with
+	 * framestart_delay==3 we will end up extending the min vblank by
+	 * one extra line.
+	 */
+	crtc_state->vrr.pipeline_full =
+		min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1);
+}
+
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 3700acec5d09..67c477d6d1a4 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -9,7 +9,15 @@
 #include <linux/types.h>
 
 struct drm_connector;
+struct drm_connector_state;
+struct intel_atomic_state;
+struct intel_crtc;
+struct intel_crtc_state;
+struct intel_dp;
 
 bool intel_vrr_is_capable(struct drm_connector *connector);
+void intel_vrr_check_modeset(struct intel_atomic_state *state);
+void intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
+			      struct drm_connector_state *conn_state);
 
 #endif /* __INTEL_VRR_H__ */
-- 
2.19.1

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[Intel-gfx] [PATCH v4 07/18] drm/i915/display/dp: Do not enable PSR if VRR is enabled

[Manasi Navare]

Even though our HW supports PSR + VRR, the available panels
do not work reliably with PSR and VRR together. So if user
requested VRR and is supported by HW enable that and do not
enable PSR in that case.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index c24ae69426cf..a653543e4164 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -811,6 +811,13 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 		&crtc_state->hw.adjusted_mode;
 	int psr_setup_time;
 
+	/*
+	 * Current PSR panels dont work reliably with VRR enabled
+	 * So if VRR is enabled, do not enable PSR.
+	 */
+	if (crtc_state->vrr.enable)
+		return;
+
 	if (!CAN_PSR(dev_priv))
 		return;
 
-- 
2.19.1

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[Intel-gfx] [PATCH v4 08/18] drm/i915/display: VRR + DRRS cannot be enabled together

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

If VRR is enabled, DRRS cannot be enabled, so make this check
in atomic check.
---
 drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a275303c0c5c..869a9d291e1b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2845,6 +2845,9 @@ intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
+	if (pipe_config->vrr.enable)
+		return;
+
 	/*
 	 * DRRS and PSR can't be enable together, so giving preference to PSR
 	 * as it allows more power-savings by complete shutting down display,
-- 
2.19.1

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[Intel-gfx] [PATCH v4 09/18] drm/i915: Rename VRR_CTL reg fields

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Give the pipeline full line count bits more descriptive names

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 249a81575b9d..307c613cbc57 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4346,13 +4346,13 @@ enum {
 #define _TRANS_VRR_CTL_B		0x61420
 #define _TRANS_VRR_CTL_C		0x62420
 #define _TRANS_VRR_CTL_D		0x63420
-#define TRANS_VRR_CTL(trans)		_MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
-#define   VRR_CTL_VRR_ENABLE		REG_BIT(31)
-#define   VRR_CTL_IGN_MAX_SHIFT		REG_BIT(30)
-#define   VRR_CTL_FLIP_LINE_EN		REG_BIT(29)
-#define   VRR_CTL_LINE_COUNT_MASK	REG_GENMASK(10, 3)
-#define   VRR_CTL_LINE_COUNT(x)		REG_FIELD_PREP(VRR_CTL_LINE_COUNT_MASK, (x))
-#define   VRR_CTL_SW_FULLLINE_COUNT	REG_BIT(0)
+#define TRANS_VRR_CTL(trans)			_MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
+#define   VRR_CTL_VRR_ENABLE			REG_BIT(31)
+#define   VRR_CTL_IGN_MAX_SHIFT			REG_BIT(30)
+#define   VRR_CTL_FLIP_LINE_EN			REG_BIT(29)
+#define   VRR_CTL_PIPELINE_FULL_MASK		REG_GENMASK(10, 3)
+#define   VRR_CTL_PIPELINE_FULL(x)		REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
+#define   VRR_CTL_PIPELINE_FULL_OVERRIDE	REG_BIT(0)
 
 #define _TRANS_VRR_VMAX_A		0x60424
 #define _TRANS_VRR_VMAX_B		0x61424
-- 
2.19.1

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[Intel-gfx] [PATCH v4 10/18] drm/i915/display/vrr: Configure and enable VRR in modeset enable

[Manasi Navare]

This patch computes the VRR parameters from VRR crtc states
and configures them in VRR registers during CRTC enable in
the modeset enable sequence.

v2:
* Remove initialization to 0 (Jani N)
* Use correct pipe %c (Jani N)

v3:
* Remove debug prints (Ville)
* Use cpu_trans instead of pipe for TRANS_VRR regs (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |  3 +++
 drivers/gpu/drm/i915/display/intel_vrr.c | 21 +++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h |  3 +++
 3 files changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 49cf76a9b4c6..b442f06e9800 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -50,6 +50,7 @@
 #include "intel_sprite.h"
 #include "intel_tc.h"
 #include "intel_vdsc.h"
+#include "intel_vrr.h"
 
 struct ddi_buf_trans {
 	u32 trans1;	/* balance leg enable, de-emph level */
@@ -4313,6 +4314,8 @@ static void intel_enable_ddi(struct intel_atomic_state *state,
 	if (!crtc_state->bigjoiner_slave)
 		intel_ddi_enable_transcoder_func(encoder, crtc_state);
 
+	intel_vrr_enable(encoder, crtc_state);
+
 	intel_enable_pipe(crtc_state);
 
 	intel_crtc_vblank_on(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 466663be90f5..e7fb297e8d23 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -100,3 +100,24 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 		min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1);
 }
 
+void intel_vrr_enable(struct intel_encoder *encoder,
+		      const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 trans_vrr_ctl;
+
+	if (!crtc_state->vrr.enable)
+		return;
+
+	trans_vrr_ctl = VRR_CTL_VRR_ENABLE |
+		VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
+		VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) |
+		VRR_CTL_PIPELINE_FULL_OVERRIDE;
+
+	intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
+	intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
+	intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl);
+	intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1);
+	intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 67c477d6d1a4..80c33fbd0639 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -14,10 +14,13 @@ struct intel_atomic_state;
 struct intel_crtc;
 struct intel_crtc_state;
 struct intel_dp;
+struct intel_encoder;
 
 bool intel_vrr_is_capable(struct drm_connector *connector);
 void intel_vrr_check_modeset(struct intel_atomic_state *state);
 void intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 			      struct drm_connector_state *conn_state);
+void intel_vrr_enable(struct intel_encoder *encoder,
+		      const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_VRR_H__ */
-- 
2.19.1

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[Intel-gfx] [PATCH v4 11/18] drm/i915/display/vrr: Send VRR push to flip the frame

[Manasi Navare]

VRR achieves vblank stretching using the HW PUSH functionality.
So once the VRR is enabled during modeset then for each flip
request from userspace, in the atomic tail pipe_update_end()
we need to set the VRR push bit in HW for it to terminate
the vblank at configured flipline or anytime after flipline
or latest at the Vmax.

The HW clears the PUSH bit after the double buffer updates
are completed.

v2:
* Move send push to after irq en (Manasi)
* Call send push unconditionally (Jani N)

v3:
* Stall w.r.t Vrr vmax (Manasi, Gary Smith)

v4:
* Remove the rmw (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Gary Smith <gary.k.smith@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/display/intel_sprite.c |  4 ++++
 drivers/gpu/drm/i915/display/intel_vrr.c    | 13 +++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h    |  1 +
 3 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index ced6af7cdc84..0e82d1629d2d 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -50,6 +50,7 @@
 #include "intel_dsi.h"
 #include "intel_sprite.h"
 #include "i9xx_plane.h"
+#include "intel_vrr.h"
 
 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
 			     int usecs)
@@ -266,6 +267,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 
 	local_irq_enable();
 
+	/* Send VRR Push to terminate Vblank */
+	intel_vrr_send_push(new_crtc_state);
+
 	if (intel_vgpu_active(dev_priv))
 		return;
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index e7fb297e8d23..1b26806d3416 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -121,3 +121,16 @@ void intel_vrr_enable(struct intel_encoder *encoder,
 	intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1);
 	intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN);
 }
+
+void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if (!crtc_state->vrr.enable)
+		return;
+
+	intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder),
+		       TRANS_PUSH_EN | TRANS_PUSH_SEND);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 80c33fbd0639..1b7c53b5604a 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -22,5 +22,6 @@ void intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 			      struct drm_connector_state *conn_state);
 void intel_vrr_enable(struct intel_encoder *encoder,
 		      const struct intel_crtc_state *crtc_state);
+void intel_vrr_send_push(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_VRR_H__ */
-- 
2.19.1

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[Intel-gfx] [PATCH v4 12/18] drm/i915/display/vrr: Disable VRR in modeset disable path

[Manasi Navare]

This patch disables the VRR enable and VRR PUSH
bits in the HW during commit modeset disable sequence.

Thsi disable will happen when the port is disabled
or when the userspace sets VRR prop to false and
requests to disable VRR.

v2:
* Use intel_de_rmw (Jani N)

v3:
* Remove rmw (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |  2 ++
 drivers/gpu/drm/i915/display/intel_vrr.c | 13 +++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h |  1 +
 3 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b442f06e9800..16b55f49aa54 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4063,6 +4063,8 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
 
 		intel_disable_pipe(old_crtc_state);
 
+		intel_vrr_disable(old_crtc_state);
+
 		intel_ddi_disable_transcoder_func(old_crtc_state);
 
 		intel_dsc_disable(old_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 1b26806d3416..501c8d9142da 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -134,3 +134,16 @@ void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
 	intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder),
 		       TRANS_PUSH_EN | TRANS_PUSH_SEND);
 }
+
+void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
+
+	if (!old_crtc_state->vrr.enable)
+		return;
+
+	intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0);
+	intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 1b7c53b5604a..43379c2bd4d9 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -23,5 +23,6 @@ void intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 void intel_vrr_enable(struct intel_encoder *encoder,
 		      const struct intel_crtc_state *crtc_state);
 void intel_vrr_send_push(const struct intel_crtc_state *crtc_state);
+void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state);
 
 #endif /* __INTEL_VRR_H__ */
-- 
2.19.1

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[Intel-gfx] [PATCH v4 13/18] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink

[Manasi Navare]

If VRR is enabled, the sink should ignore MSA parameters
and regenerate incoming video stream without depending
on these parameters. Hence set the MSA_TIMING_PAR_IGNORE_EN
bit if VRR is enabled.
Reset this bit on VRR disable.

v2:
* ACtually set the dpcd msa ignore bit (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      | 19 +++++++++++++++++++
 .../drm/i915/display/intel_dp_link_training.c |  2 +-
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 16b55f49aa54..e2961d8fac99 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3556,6 +3556,22 @@ i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
 		return DP_TP_STATUS(encoder->port);
 }
 
+static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,
+							  const struct intel_crtc_state *crtc_state,
+							  bool enable)
+{
+	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+	if (!crtc_state->vrr.enable)
+		return;
+
+	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
+			       enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
+		drm_dbg_kms(&i915->drm,
+			    "Failed to set MSA_TIMING_PAR_IGNORE %s in the sink\n",
+			    enable ? "enable" : "disable");
+}
+
 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
 					const struct intel_crtc_state *crtc_state)
 {
@@ -4354,6 +4370,9 @@ static void intel_disable_ddi_dp(struct intel_atomic_state *state,
 	/* Disable the decompression in DP Sink */
 	intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
 					      false);
+	/* Disable Ignore_MSA bit in DP Sink */
+	intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
+						      false);
 }
 
 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index d8c6d7054d11..e4e6d18ef0a2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -434,7 +434,7 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
 		drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
 				  &rate_select, 1);
 
-	link_config[0] = 0;
+	link_config[0] = crtc_state->vrr.enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
 	link_config[1] = DP_SET_ANSI_8B10B;
 	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
 
-- 
2.19.1

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[Intel-gfx] [PATCH v4 14/18] drm/i915/display: Add HW state readout for VRR

[Manasi Navare]

This functions gets the VRR config from the VRR registers
to match the crtc state variables for VRR.

v2:
* Rebase (Manasi)
* Use HAS_VRR (Jani N)

v3:
* Get pipeline_full, flipline (Ville)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  3 +++
 drivers/gpu/drm/i915/display/intel_vrr.c     | 20 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h     |  3 +++
 3 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 22bda7a55cc0..a1c011033803 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10987,6 +10987,9 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
 		intel_get_transcoder_timings(crtc, pipe_config);
 	}
 
+	if (HAS_VRR(dev_priv))
+		intel_vrr_get_config(crtc, pipe_config);
+
 	intel_get_pipe_src_size(crtc, pipe_config);
 
 	if (IS_HASWELL(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 501c8d9142da..5dc6d578760a 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -147,3 +147,23 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 	intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0);
 	intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0);
 }
+
+void intel_vrr_get_config(struct intel_crtc *crtc,
+			  struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 trans_vrr_ctl;
+
+	trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));
+	crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
+	if (!crtc_state->vrr.enable)
+		return;
+
+	if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE)
+		crtc_state->vrr.pipeline_full = REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
+	if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN)
+		crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;
+	crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1;
+	crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 43379c2bd4d9..7610051edad2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -15,6 +15,7 @@ struct intel_crtc;
 struct intel_crtc_state;
 struct intel_dp;
 struct intel_encoder;
+struct intel_crtc;
 
 bool intel_vrr_is_capable(struct drm_connector *connector);
 void intel_vrr_check_modeset(struct intel_atomic_state *state);
@@ -24,5 +25,7 @@ void intel_vrr_enable(struct intel_encoder *encoder,
 		      const struct intel_crtc_state *crtc_state);
 void intel_vrr_send_push(const struct intel_crtc_state *crtc_state);
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state);
+void intel_vrr_get_config(struct intel_crtc *crtc,
+			  struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_VRR_H__ */
-- 
2.19.1

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[Intel-gfx] [PATCH v4 15/18] drm/i915/display: Helpers for VRR vblank min and max start

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

With VRR the earliest the registers can get latched are at
flipline decision boundary, calculate that as vrr_vmin_vblank_start()
and the latest the regsiters can get latched are vmax decision boundary
calculate that as vrr_vmax_vblank_start()

Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 36 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h |  2 ++
 2 files changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5dc6d578760a..9a18c36e4a9a 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -45,6 +45,42 @@ intel_vrr_check_modeset(struct intel_atomic_state *state)
 	}
 }
 
+/*
+ * Without VRR registers get latched at:
+ *  vblank_start
+ *
+ * With VRR the earliest registers can get latched is:
+ *  intel_vrr_vmin_vblank_start(), which if we want to maintain
+ *  the correct min vtotal is >=vblank_start+1
+ *
+ * The latest point registers can get latched is the vmax decision boundary:
+ *  intel_vrr_vmax_vblank_start()
+ *
+ * Between those two points the vblank exit starts (and hence registers get
+ * latched) ASAP after a push is sent.
+ *
+ * framestart_delay is programmable 0-3.
+ */
+static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+	/* TODO: Not sure why the hw imposes the extra scanline?, also check on TGL */
+	return crtc_state->vrr.pipeline_full + i915->framestart_delay + 2;
+}
+
+int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
+{
+	/* Min vblank actually determined by flipline that is always >=vmin+1 */
+	return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state);
+}
+
+int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
+{
+	return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state);
+}
+
 void
 intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 			 struct drm_connector_state *conn_state)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 7610051edad2..d8b6b45557ca 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -27,5 +27,7 @@ void intel_vrr_send_push(const struct intel_crtc_state *crtc_state);
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state);
 void intel_vrr_get_config(struct intel_crtc *crtc,
 			  struct intel_crtc_state *crtc_state);
+int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state);
+int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_VRR_H__ */
-- 
2.19.1

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[Intel-gfx] [PATCH v4 16/18] drm/i915: Add vrr state dump

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Dump vrr state alongside everything else.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a1c011033803..4ed279f034be 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12371,6 +12371,13 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
 		intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
 
+	drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
+		    yesno(pipe_config->vrr.enable),
+		    pipe_config->vrr.vmin, pipe_config->vrr.vmax,
+		    pipe_config->vrr.pipeline_full, pipe_config->vrr.flipline,
+		    intel_vrr_vmin_vblank_start(pipe_config),
+		    intel_vrr_vmax_vblank_start(pipe_config));
+
 	drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
 	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
 	drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
-- 
2.19.1

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[Intel-gfx] [PATCH v4 17/18] drm/i915: Fix vblank timestamps with VRR

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

To get sensible vblank timestamping behaviour we need to feed
the vmax based timings to the vblank code, otherwise it'll chop
off the scanline counter when it exceeds the minumum vtotal.

Additionally with VRR we have three cases to consider when we
generate the vblank timestamp:
1) we are in vertical active
  -> nothing special needs to be done, just return the current
     scanout position and the core will calculate the timestamp
     corresponding to the past time when the current vertical
     active started
2) we are in vertical blank and no push has been sent
  -> the hardware will keep extending the vblank presumably
     to its maximum length, so we make the timestmap match the
     expected time when the max length vblank will end. Since
     the timings used for this are now based on vmax nothing
     special actually needs to be done
3) we are in vblank and a push has been sent so the vblank is
   about to terminate
  -> presumably we want the timestmap to accurately reflect
     when the vblank will terminate, so we use the sampled
     frame timestamp vs. current timestamp to guesstimate
     how far along the vblank exit we are, and then we
     adjust the reported scanout position accordingly so
     that the core will see that the vblank is close to
     ending.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c    | 17 ++++++++++++-----
 .../gpu/drm/i915/display/intel_display_types.h  |  4 ++++
 drivers/gpu/drm/i915/display/intel_vrr.c        |  4 ++++
 drivers/gpu/drm/i915/i915_irq.c                 | 15 ++++++++++++++-
 4 files changed, 34 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4ed279f034be..d989baa44c37 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13835,10 +13835,17 @@ intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->hw.adjusted_mode;
+	struct drm_display_mode adjusted_mode =
+		crtc_state->hw.adjusted_mode;
+
+	if (crtc_state->vrr.enable) {
+		adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;
+		adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;
+		adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
+		crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
+	}
 
-	drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
+	drm_calc_timestamping_constants(&crtc->base, &adjusted_mode);
 
 	crtc->mode_flags = crtc_state->mode_flags;
 
@@ -13872,8 +13879,8 @@ intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
 	if (IS_GEN(dev_priv, 2)) {
 		int vtotal;
 
-		vtotal = adjusted_mode->crtc_vtotal;
-		if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
+		vtotal = adjusted_mode.crtc_vtotal;
+		if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
 			vtotal /= 2;
 
 		crtc->scanline_offset = vtotal - 1;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index aa0842028414..3fee613617f1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -679,6 +679,8 @@ struct intel_crtc_scaler_state {
 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */
 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
+/* Do tricks to make vblank timestamps sane with VRR? */
+#define I915_MODE_FLAG_VRR (1<<6)
 
 struct intel_wm_level {
 	bool enable;
@@ -1186,6 +1188,8 @@ struct intel_crtc {
 	/* I915_MODE_FLAG_* */
 	u8 mode_flags;
 
+	u16 vmax_vblank_start;
+
 	struct intel_display_power_domain_set enabled_power_domains;
 	struct intel_overlay *overlay;
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 9a18c36e4a9a..a494d3ecb1b5 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -134,6 +134,8 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 	 */
 	crtc_state->vrr.pipeline_full =
 		min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1);
+
+	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 }
 
 void intel_vrr_enable(struct intel_encoder *encoder,
@@ -202,4 +204,6 @@ void intel_vrr_get_config(struct intel_crtc *crtc,
 		crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;
 	crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1;
 	crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1;
+
+	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 }
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8505ceca87d5..e81afcb2f43e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -893,7 +893,20 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
 	if (stime)
 		*stime = ktime_get();
 
-	if (use_scanline_counter) {
+	if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
+		int scanlines = intel_crtc_scanlines_since_frame_timestamp(crtc);
+
+		position = __intel_get_crtc_scanline(crtc);
+
+		/*
+		 * Already exiting vblank? If so, shift our position
+		 * so it looks like we're already apporaching the full
+		 * vblank end. This should make the generated timestamp
+		 * more or less match when the active portion will start.
+		 */
+		if (position >= vbl_start && scanlines < position)
+			position = min(crtc->vmax_vblank_start + scanlines, vtotal - 1);
+	} if (use_scanline_counter) {
 		/* No obvious pixelcount register. Only query vertical
 		 * scanout position from Display scan line register.
 		 */
-- 
2.19.1

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[Intel-gfx] [PATCH v4 18/18] drm/i915: Fix vblank evasion with vrr

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

With vrr enabled the hardware no longer latches the registers
automagically at vblank start. The point at which it will do the
latching even when no push has been sent is the vmax decision
boundary. That is the thing we need to evade to avoid our
register latching to get split between two frames.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/display/intel_sprite.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 0e82d1629d2d..530ce0497559 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -101,7 +101,10 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
 	if (new_crtc_state->uapi.async_flip)
 		return;
 
-	vblank_start = intel_mode_vblank_start(adjusted_mode);
+	if (new_crtc_state->vrr.enable)
+		vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
+	else
+		vblank_start = intel_mode_vblank_start(adjusted_mode);
 
 	/* FIXME needs to be calibrated sensibly */
 	min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
-- 
2.19.1

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for VRR/Adaptive Sync Enabling on DP/eDP for TGL+

[Patchwork]

== Series Details ==

Series: VRR/Adaptive Sync Enabling on DP/eDP for TGL+
URL   : https://patchwork.freedesktop.org/series/85831/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
9d81944ab3b3 drm/i915/display/vrr: Create VRR file and add VRR capability check
-:36: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#36: 
new file mode 100644

-:41: WARNING:SPDX_LICENSE_TAG: Improper SPDX comment style for 'drivers/gpu/drm/i915/display/intel_vrr.c', please use '//' instead
#41: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:1:
+/* SPDX-License-Identifier: MIT */

-:41: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#41: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:1:
+/* SPDX-License-Identifier: MIT */

-:82: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line
#82: FILE: drivers/gpu/drm/i915/display/intel_vrr.h:4:
+ * Copyright © 2019 Intel Corporation
+*/

total: 0 errors, 4 warnings, 0 checks, 62 lines checked
be5b431abcca drm/i915/display/dp: Attach and set drm connector VRR property
e42f3141b758 drm/i915: Store framestart_delay in dev_priv
7caaca7f5a5d drm/i915: Extract intel_mode_vblank_start()
762167321220 drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp()
a07503674c3c drm/i915/display/dp: Compute VRR state in atomic_check
6bea0561c8ab drm/i915/display/dp: Do not enable PSR if VRR is enabled
0061e69b29f3 drm/i915/display: VRR + DRRS cannot be enabled together
-:22: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 0 warnings, 0 checks, 9 lines checked
5729930e732b drm/i915: Rename VRR_CTL reg fields
1e53166817ac drm/i915/display/vrr: Configure and enable VRR in modeset enable
31bb5d8efd39 drm/i915/display/vrr: Send VRR push to flip the frame
259a9c3dcc00 drm/i915/display/vrr: Disable VRR in modeset disable path
510a51a72bed drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink
b857d16e4dd6 drm/i915/display: Add HW state readout for VRR
-:55: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#55: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:164:
+		crtc_state->vrr.pipeline_full = REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);

-:57: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#57: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:166:
+		crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;

total: 0 errors, 2 warnings, 0 checks, 46 lines checked
6185d7835cbe drm/i915/display: Helpers for VRR vblank min and max start
6a48576a1fa4 drm/i915: Add vrr state dump
96df6e91917c drm/i915: Fix vblank timestamps with VRR
-:11: WARNING:TYPO_SPELLING: 'minumum' may be misspelled - perhaps 'minimum'?
#11: 
off the scanline counter when it exceeds the minumum vtotal.
                                             ^^^^^^^

-:83: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#83: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:683:
+#define I915_MODE_FLAG_VRR (1<<6)
                              ^

-:138: ERROR:TRAILING_STATEMENTS: trailing statements should be on next line (or did you mean 'else if'?)
#138: FILE: drivers/gpu/drm/i915/i915_irq.c:909:
+	} if (use_scanline_counter) {

total: 1 errors, 1 warnings, 1 checks, 81 lines checked
ac9c147c77da drm/i915: Fix vblank evasion with vrr


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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for VRR/Adaptive Sync Enabling on DP/eDP for TGL+

[Patchwork]

== Series Details ==

Series: VRR/Adaptive Sync Enabling on DP/eDP for TGL+
URL   : https://patchwork.freedesktop.org/series/85831/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1329:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:843:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:843:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:869:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block


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[Intel-gfx] ✗ Fi.CI.BAT: failure for VRR/Adaptive Sync Enabling on DP/eDP for TGL+

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 7619 bytes --]

== Series Details ==

Series: VRR/Adaptive Sync Enabling on DP/eDP for TGL+
URL   : https://patchwork.freedesktop.org/series/85831/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9603 -> Patchwork_19345
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_19345 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19345, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19345/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_19345:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-icl-u2:          [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9603/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19345/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@prime_vgem@basic-userptr:
    - {fi-ehl-1}:         [PASS][3] -> [DMESG-WARN][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9603/fi-ehl-1/igt@prime_vgem@basic-userptr.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19345/fi-ehl-1/igt@prime_vgem@basic-userptr.html

  * igt@runner@aborted:
    - {fi-tgl-dsi}:       NOTRUN -> [FAIL][5]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19345/fi-tgl-dsi/igt@runner@aborted.html

  
Known issues
------------

  Here are the changes found in Patchwork_19345 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@read:
    - fi-tgl-y:           [PASS][6] -> [DMESG-WARN][7] ([i915#402]) +2 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9603/fi-tgl-y/igt@fbdev@read.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19345/fi-tgl-y/igt@fbdev@read.html

  * igt@gem_exec_suspend@basic-s3:
    - fi-tgl-y:           [PASS][8] -> [DMESG-WARN][9] ([i915#2411] / [i915#402])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9603/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19345/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-guc:         [PASS][10] -> [FAIL][11] ([i915#579])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9603/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19345/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-tgl-y:           [PASS][12] -> [DMESG-FAIL][13] ([i915#2601])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9603/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19345/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - fi-snb-2600:        NOTRUN -> [SKIP][14] ([fdo#109271]) +30 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19345/fi-snb-2600/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@hdmi-crc-fast:
    - fi-snb-2600:        NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19345/fi-snb-2600/igt@kms_chamelium@hdmi-crc-fast.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-snb-2600:        [DMESG-WARN][16] ([i915#2772]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9603/fi-snb-2600/igt@gem_exec_suspend@basic-s3.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19345/fi-snb-2600/igt@gem_exec_suspend@basic-s3.html

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-kbl-soraka:      [DMESG-FAIL][18] ([i915#2291] / [i915#541]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9603/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19345/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html

  * igt@prime_vgem@basic-userptr:
    - fi-tgl-y:           [DMESG-WARN][20] ([i915#402]) -> [PASS][21] +2 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9603/fi-tgl-y/igt@prime_vgem@basic-userptr.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19345/fi-tgl-y/igt@prime_vgem@basic-userptr.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
  [i915#2601]: https://gitlab.freedesktop.org/drm/intel/issues/2601
  [i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724
  [i915#2772]: https://gitlab.freedesktop.org/drm/intel/issues/2772
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
  [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579


Participating hosts (43 -> 38)
------------------------------

  Missing    (5): fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-cml-drallion fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_9603 -> Patchwork_19345

  CI-20190529: 20190529
  CI_DRM_9603: 4e758db4f1c2fd3dcfa7bf1cd33a0863978f555c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5957: 2a2b3418f7458dfa1fac255cc5c71603f617690a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19345: ac9c147c77da7f5d478f76e0e192bb0c3d747ef6 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ac9c147c77da drm/i915: Fix vblank evasion with vrr
96df6e91917c drm/i915: Fix vblank timestamps with VRR
6a48576a1fa4 drm/i915: Add vrr state dump
6185d7835cbe drm/i915/display: Helpers for VRR vblank min and max start
b857d16e4dd6 drm/i915/display: Add HW state readout for VRR
510a51a72bed drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink
259a9c3dcc00 drm/i915/display/vrr: Disable VRR in modeset disable path
31bb5d8efd39 drm/i915/display/vrr: Send VRR push to flip the frame
1e53166817ac drm/i915/display/vrr: Configure and enable VRR in modeset enable
5729930e732b drm/i915: Rename VRR_CTL reg fields
0061e69b29f3 drm/i915/display: VRR + DRRS cannot be enabled together
6bea0561c8ab drm/i915/display/dp: Do not enable PSR if VRR is enabled
a07503674c3c drm/i915/display/dp: Compute VRR state in atomic_check
762167321220 drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp()
7caaca7f5a5d drm/i915: Extract intel_mode_vblank_start()
e42f3141b758 drm/i915: Store framestart_delay in dev_priv
be5b431abcca drm/i915/display/dp: Attach and set drm connector VRR property
9d81944ab3b3 drm/i915/display/vrr: Create VRR file and add VRR capability check

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19345/index.html

[-- Attachment #1.2: Type: text/html, Size: 8721 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

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Re: [Intel-gfx] [PATCH v4 08/18] drm/i915/display: VRR + DRRS cannot be enabled together

[Ville Syrjälä]

On Wed, Jan 13, 2021 at 02:09:25PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> If VRR is enabled, DRRS cannot be enabled, so make this check
> in atomic check.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

if we want to keep this as a separete patch.

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index a275303c0c5c..869a9d291e1b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2845,6 +2845,9 @@ intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
>  	struct intel_connector *intel_connector = intel_dp->attached_connector;
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
> +	if (pipe_config->vrr.enable)
> +		return;
> +
>  	/*
>  	 * DRRS and PSR can't be enable together, so giving preference to PSR
>  	 * as it allows more power-savings by complete shutting down display,
> -- 
> 2.19.1

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v4 00/18] VRR/Adaptive Sync Enabling on DP/eDP for TGL+

[Ville Syrjälä]

On Wed, Jan 13, 2021 at 02:09:17PM -0800, Manasi Navare wrote:
> This series address review comments from Ville
> and incorporates some suggested fixes plus his
> patches.
> 
> Aditya Swarup (1):
>   drm/i915/display/dp: Attach and set drm connector VRR property
> 
> Manasi Navare (8):
>   drm/i915/display/vrr: Create VRR file and add VRR capability check
>   drm/i915/display/dp: Compute VRR state in atomic_check
>   drm/i915/display/dp: Do not enable PSR if VRR is enabled
>   drm/i915/display/vrr: Configure and enable VRR in modeset enable
>   drm/i915/display/vrr: Send VRR push to flip the frame
>   drm/i915/display/vrr: Disable VRR in modeset disable path
>   drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink
>   drm/i915/display: Add HW state readout for VRR

All of the above is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> 
> Ville Syrjälä (9):
>   drm/i915: Store framestart_delay in dev_priv
>   drm/i915: Extract intel_mode_vblank_start()
>   drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp()
>   drm/i915/display: VRR + DRRS cannot be enabled together
>   drm/i915: Rename VRR_CTL reg fields
>   drm/i915/display: Helpers for VRR vblank min and max start
>   drm/i915: Add vrr state dump
>   drm/i915: Fix vblank timestamps with VRR
>   drm/i915: Fix vblank evasion with vrr
> 
>  drivers/gpu/drm/i915/Makefile                 |   1 +
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  24 ++
>  drivers/gpu/drm/i915/display/intel_display.c  |  58 +++--
>  .../drm/i915/display/intel_display_types.h    |  11 +
>  drivers/gpu/drm/i915/display/intel_dp.c       |  12 +
>  .../drm/i915/display/intel_dp_link_training.c |   2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c      |   7 +
>  drivers/gpu/drm/i915/display/intel_sprite.c   |  21 +-
>  drivers/gpu/drm/i915/display/intel_vrr.c      | 209 ++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_vrr.h      |  33 +++
>  drivers/gpu/drm/i915/i915_drv.h               |   4 +
>  drivers/gpu/drm/i915/i915_irq.c               |  53 +++--
>  drivers/gpu/drm/i915/i915_reg.h               |  14 +-
>  13 files changed, 408 insertions(+), 41 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.c
>  create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.h
> 
> -- 
> 2.19.1
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v4 15/18] drm/i915/display: Helpers for VRR vblank min and max start

[Ville Syrjälä]

On Wed, Jan 13, 2021 at 02:09:32PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> With VRR the earliest the registers can get latched are at
> flipline decision boundary, calculate that as vrr_vmin_vblank_start()
> and the latest the regsiters can get latched are vmax decision boundary
> calculate that as vrr_vmax_vblank_start()
> 
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c | 36 ++++++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_vrr.h |  2 ++
>  2 files changed, 38 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 5dc6d578760a..9a18c36e4a9a 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -45,6 +45,42 @@ intel_vrr_check_modeset(struct intel_atomic_state *state)
>  	}
>  }
>  
> +/*
> + * Without VRR registers get latched at:
> + *  vblank_start
> + *
> + * With VRR the earliest registers can get latched is:
> + *  intel_vrr_vmin_vblank_start(), which if we want to maintain
> + *  the correct min vtotal is >=vblank_start+1
> + *
> + * The latest point registers can get latched is the vmax decision boundary:
> + *  intel_vrr_vmax_vblank_start()
> + *
> + * Between those two points the vblank exit starts (and hence registers get
> + * latched) ASAP after a push is sent.
> + *
> + * framestart_delay is programmable 0-3.
> + */
> +static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +
> +	/* TODO: Not sure why the hw imposes the extra scanline?, also check on TGL */

We can now drop the TGL TODO(s) since I tested it and confirmed it
follows the same rules.

> +	return crtc_state->vrr.pipeline_full + i915->framestart_delay + 2;
> +}
> +
> +int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
> +{
> +	/* Min vblank actually determined by flipline that is always >=vmin+1 */
> +	return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state);
> +}
> +
> +int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
> +{
> +	return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state);
> +}
> +
>  void
>  intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>  			 struct drm_connector_state *conn_state)
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index 7610051edad2..d8b6b45557ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -27,5 +27,7 @@ void intel_vrr_send_push(const struct intel_crtc_state *crtc_state);
>  void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state);
>  void intel_vrr_get_config(struct intel_crtc *crtc,
>  			  struct intel_crtc_state *crtc_state);
> +int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state);
> +int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state);
>  
>  #endif /* __INTEL_VRR_H__ */
> -- 
> 2.19.1

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v4 03/18] drm/i915: Store framestart_delay in dev_priv

[Navare, Manasi]

On Wed, Jan 13, 2021 at 02:09:20PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The vrr calculations will need to know the framestart delay value
> we use. Currently we program it always to zero, but should that change
> we probably want to stash it somewhere.
> 
> Could stick it into the crtc_state I suppose, but since we never
> change it let's just stuff it into dev_priv for now.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++++---------
>  drivers/gpu/drm/i915/i915_drv.h              |  2 ++
>  2 files changed, 14 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 0189d379a55e..67a55cfa5354 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1610,7 +1610,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
>  		val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
>  		/* Configure frame start delay to match the CPU */
>  		val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> -		val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
> +		val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay);
>  		intel_de_write(dev_priv, reg, val);
>  	}
>  
> @@ -1621,7 +1621,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
>  	if (HAS_PCH_IBX(dev_priv)) {
>  		/* Configure frame start delay to match the CPU */
>  		val &= ~TRANS_FRAME_START_DELAY_MASK;
> -		val |= TRANS_FRAME_START_DELAY(0);
> +		val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay);
>  
>  		/*
>  		 * Make the BPC in transcoder be consistent with
> @@ -1666,7 +1666,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
>  	val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
>  	/* Configure frame start delay to match the CPU */
>  	val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> -	val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
> +	val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay);
>  	intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
>  
>  	val = TRANS_ENABLE;
> @@ -6679,7 +6679,7 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
>  
>  	val = intel_de_read(dev_priv, reg);
>  	val &= ~HSW_FRAME_START_DELAY_MASK;
> -	val |= HSW_FRAME_START_DELAY(0);
> +	val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay);
>  	intel_de_write(dev_priv, reg, val);
>  }
>  
> @@ -8741,7 +8741,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
>  
>  	pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
>  
> -	pipeconf |= PIPECONF_FRAME_START_DELAY(0);
> +	pipeconf |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay);
>  
>  	intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
>  	intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
> @@ -9850,7 +9850,7 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
>  
>  	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
>  
> -	val |= PIPECONF_FRAME_START_DELAY(0);
> +	val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay);
>  
>  	intel_de_write(dev_priv, PIPECONF(pipe), val);
>  	intel_de_posting_read(dev_priv, PIPECONF(pipe));
> @@ -17153,6 +17153,8 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
>  	i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
>  					WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
>  
> +	i915->framestart_delay = 0; /* 0-3 */

Should we change this to default to 1 and then since its 0 based use framestart_delay - 1 everywhere?

Manasi

> +
>  	intel_mode_config_init(i915);
>  
>  	ret = intel_cdclk_init(i915);
> @@ -17487,7 +17489,7 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
>  
>  		val = intel_de_read(dev_priv, reg);
>  		val &= ~HSW_FRAME_START_DELAY_MASK;
> -		val |= HSW_FRAME_START_DELAY(0);
> +		val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay);
>  		intel_de_write(dev_priv, reg, val);
>  	} else {
>  		i915_reg_t reg = PIPECONF(cpu_transcoder);
> @@ -17495,7 +17497,7 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
>  
>  		val = intel_de_read(dev_priv, reg);
>  		val &= ~PIPECONF_FRAME_START_DELAY_MASK;
> -		val |= PIPECONF_FRAME_START_DELAY(0);
> +		val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay);
>  		intel_de_write(dev_priv, reg, val);
>  	}
>  
> @@ -17508,7 +17510,7 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
>  
>  		val = intel_de_read(dev_priv, reg);
>  		val &= ~TRANS_FRAME_START_DELAY_MASK;
> -		val |= TRANS_FRAME_START_DELAY(0);
> +		val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay);
>  		intel_de_write(dev_priv, reg, val);
>  	} else {
>  		enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
> @@ -17517,7 +17519,7 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
>  
>  		val = intel_de_read(dev_priv, reg);
>  		val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> -		val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
> +		val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay);
>  		intel_de_write(dev_priv, reg, val);
>  	}
>  }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 15e016194685..94a27e72b0a8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1182,6 +1182,8 @@ struct drm_i915_private {
>  		struct file *mmap_singleton;
>  	} gem;
>  
> +	u8 framestart_delay;
> +
>  	u8 pch_ssc_use;
>  
>  	/* For i915gm/i945gm vblank irq workaround */
> -- 
> 2.19.1
> 
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Re: [Intel-gfx] [PATCH v4 04/18] drm/i915: Extract intel_mode_vblank_start()

[Navare, Manasi]

On Wed, Jan 13, 2021 at 02:09:21PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We want to calculate the vblank_start for vblank evasion
> differently for vrr. To make that nicer lets first extract
> the current non-vrr case to a helper.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_sprite.c | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index cf3589fd0ddb..ced6af7cdc84 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -62,6 +62,16 @@ int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
>  			    1000 * adjusted_mode->crtc_htotal);
>  }
>  
> +static int intel_mode_vblank_start(const struct drm_display_mode *mode)
> +{
> +	int vblank_start = mode->crtc_vblank_start;
> +
> +	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> +		vblank_start = DIV_ROUND_UP(vblank_start, 2);
> +
> +	return vblank_start;
> +}
> +
>  /**
>   * intel_pipe_update_start() - start update of a set of display registers
>   * @new_crtc_state: the new crtc state
> @@ -90,9 +100,7 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
>  	if (new_crtc_state->uapi.async_flip)
>  		return;
>  
> -	vblank_start = adjusted_mode->crtc_vblank_start;
> -	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
> -		vblank_start = DIV_ROUND_UP(vblank_start, 2);
> +	vblank_start = intel_mode_vblank_start(adjusted_mode);
>  
>  	/* FIXME needs to be calibrated sensibly */
>  	min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
> -- 
> 2.19.1
> 
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Re: [Intel-gfx] [PATCH v4 05/18] drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp()

[Navare, Manasi]

On Wed, Jan 13, 2021 at 02:09:22PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Extract intel_crtc_scanlines_since_frame_timestamp() from
> __intel_get_crtc_scanline_from_timestamp(). We'll reuse this
> for VRR vblank timestamps.

I dont see the intel_crtc_scanlines_since_frame_timestamp() getting used
later in the series.
Should this be moved to the intel display poller rest of the patches you might have?

Manasi

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 38 +++++++++++++++++++++------------
>  1 file changed, 24 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index dd1971040bbc..8505ceca87d5 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -718,25 +718,15 @@ u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
>  	return intel_uncore_read(&dev_priv->uncore, PIPE_FRMCOUNT_G4X(pipe));
>  }
>  
> -/*
> - * On certain encoders on certain platforms, pipe
> - * scanline register will not work to get the scanline,
> - * since the timings are driven from the PORT or issues
> - * with scanline register updates.
> - * This function will use Framestamp and current
> - * timestamp registers to calculate the scanline.
> - */
> -static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
> +static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct drm_vblank_crtc *vblank =
>  		&crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
>  	const struct drm_display_mode *mode = &vblank->hwmode;
> -	u32 vblank_start = mode->crtc_vblank_start;
> -	u32 vtotal = mode->crtc_vtotal;
>  	u32 htotal = mode->crtc_htotal;
>  	u32 clock = mode->crtc_clock;
> -	u32 scanline, scan_prev_time, scan_curr_time, scan_post_time;
> +	u32 scan_prev_time, scan_curr_time, scan_post_time;
>  
>  	/*
>  	 * To avoid the race condition where we might cross into the
> @@ -763,8 +753,28 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
>  						  PIPE_FRMTMSTMP(crtc->pipe));
>  	} while (scan_post_time != scan_prev_time);
>  
> -	scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
> -					clock), 1000 * htotal);
> +	return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
> +				   clock), 1000 * htotal);
> +}
> +
> +/*
> + * On certain encoders on certain platforms, pipe
> + * scanline register will not work to get the scanline,
> + * since the timings are driven from the PORT or issues
> + * with scanline register updates.
> + * This function will use Framestamp and current
> + * timestamp registers to calculate the scanline.
> + */
> +static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
> +{
> +	struct drm_vblank_crtc *vblank =
> +		&crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
> +	const struct drm_display_mode *mode = &vblank->hwmode;
> +	u32 vblank_start = mode->crtc_vblank_start;
> +	u32 vtotal = mode->crtc_vtotal;
> +	u32 scanline;
> +
> +	scanline = intel_crtc_scanlines_since_frame_timestamp(crtc);
>  	scanline = min(scanline, vtotal - 1);
>  	scanline = (scanline + vblank_start) % vtotal;
>  
> -- 
> 2.19.1
> 
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Re: [Intel-gfx] [PATCH v4 08/18] drm/i915/display: VRR + DRRS cannot be enabled together

[Navare, Manasi]

On Thu, Jan 14, 2021 at 07:15:03PM +0200, Ville Syrjälä wrote:
> On Wed, Jan 13, 2021 at 02:09:25PM -0800, Manasi Navare wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > If VRR is enabled, DRRS cannot be enabled, so make this check
> > in atomic check.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> if we want to keep this as a separete patch.

Yes will add your sign off to this
and with that

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index a275303c0c5c..869a9d291e1b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2845,6 +2845,9 @@ intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
> >  	struct intel_connector *intel_connector = intel_dp->attached_connector;
> >  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >  
> > +	if (pipe_config->vrr.enable)
> > +		return;
> > +
> >  	/*
> >  	 * DRRS and PSR can't be enable together, so giving preference to PSR
> >  	 * as it allows more power-savings by complete shutting down display,
> > -- 
> > 2.19.1
> 
> -- 
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH v4 09/18] drm/i915: Rename VRR_CTL reg fields

[Navare, Manasi]

On Wed, Jan 13, 2021 at 02:09:26PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Give the pipeline full line count bits more descriptive names
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 249a81575b9d..307c613cbc57 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4346,13 +4346,13 @@ enum {
>  #define _TRANS_VRR_CTL_B		0x61420
>  #define _TRANS_VRR_CTL_C		0x62420
>  #define _TRANS_VRR_CTL_D		0x63420
> -#define TRANS_VRR_CTL(trans)		_MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
> -#define   VRR_CTL_VRR_ENABLE		REG_BIT(31)
> -#define   VRR_CTL_IGN_MAX_SHIFT		REG_BIT(30)
> -#define   VRR_CTL_FLIP_LINE_EN		REG_BIT(29)
> -#define   VRR_CTL_LINE_COUNT_MASK	REG_GENMASK(10, 3)
> -#define   VRR_CTL_LINE_COUNT(x)		REG_FIELD_PREP(VRR_CTL_LINE_COUNT_MASK, (x))
> -#define   VRR_CTL_SW_FULLLINE_COUNT	REG_BIT(0)
> +#define TRANS_VRR_CTL(trans)			_MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
> +#define   VRR_CTL_VRR_ENABLE			REG_BIT(31)
> +#define   VRR_CTL_IGN_MAX_SHIFT			REG_BIT(30)
> +#define   VRR_CTL_FLIP_LINE_EN			REG_BIT(29)
> +#define   VRR_CTL_PIPELINE_FULL_MASK		REG_GENMASK(10, 3)
> +#define   VRR_CTL_PIPELINE_FULL(x)		REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
> +#define   VRR_CTL_PIPELINE_FULL_OVERRIDE	REG_BIT(0)
>  
>  #define _TRANS_VRR_VMAX_A		0x60424
>  #define _TRANS_VRR_VMAX_B		0x61424
> -- 
> 2.19.1
> 
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Re: [Intel-gfx] [PATCH v4 15/18] drm/i915/display: Helpers for VRR vblank min and max start

[Navare, Manasi]

Yes will drop that TODO

Also,

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi


On Tue, Jan 19, 2021 at 09:07:56PM +0200, Ville Syrjälä wrote:
> On Wed, Jan 13, 2021 at 02:09:32PM -0800, Manasi Navare wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > With VRR the earliest the registers can get latched are at
> > flipline decision boundary, calculate that as vrr_vmin_vblank_start()
> > and the latest the regsiters can get latched are vmax decision boundary
> > calculate that as vrr_vmax_vblank_start()
> > 
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_vrr.c | 36 ++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/display/intel_vrr.h |  2 ++
> >  2 files changed, 38 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index 5dc6d578760a..9a18c36e4a9a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -45,6 +45,42 @@ intel_vrr_check_modeset(struct intel_atomic_state *state)
> >  	}
> >  }
> >  
> > +/*
> > + * Without VRR registers get latched at:
> > + *  vblank_start
> > + *
> > + * With VRR the earliest registers can get latched is:
> > + *  intel_vrr_vmin_vblank_start(), which if we want to maintain
> > + *  the correct min vtotal is >=vblank_start+1
> > + *
> > + * The latest point registers can get latched is the vmax decision boundary:
> > + *  intel_vrr_vmax_vblank_start()
> > + *
> > + * Between those two points the vblank exit starts (and hence registers get
> > + * latched) ASAP after a push is sent.
> > + *
> > + * framestart_delay is programmable 0-3.
> > + */
> > +static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
> > +{
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > +
> > +	/* TODO: Not sure why the hw imposes the extra scanline?, also check on TGL */
> 
> We can now drop the TGL TODO(s) since I tested it and confirmed it
> follows the same rules.
> 
> > +	return crtc_state->vrr.pipeline_full + i915->framestart_delay + 2;
> > +}
> > +
> > +int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
> > +{
> > +	/* Min vblank actually determined by flipline that is always >=vmin+1 */
> > +	return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state);
> > +}
> > +
> > +int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
> > +{
> > +	return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state);
> > +}
> > +
> >  void
> >  intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> >  			 struct drm_connector_state *conn_state)
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> > index 7610051edad2..d8b6b45557ca 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> > @@ -27,5 +27,7 @@ void intel_vrr_send_push(const struct intel_crtc_state *crtc_state);
> >  void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state);
> >  void intel_vrr_get_config(struct intel_crtc *crtc,
> >  			  struct intel_crtc_state *crtc_state);
> > +int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state);
> > +int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state);
> >  
> >  #endif /* __INTEL_VRR_H__ */
> > -- 
> > 2.19.1
> 
> -- 
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH v4 16/18] drm/i915: Add vrr state dump

[Navare, Manasi]

On Wed, Jan 13, 2021 at 02:09:33PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Dump vrr state alongside everything else.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a1c011033803..4ed279f034be 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12371,6 +12371,13 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
>  	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
>  		intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
>  
> +	drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
> +		    yesno(pipe_config->vrr.enable),
> +		    pipe_config->vrr.vmin, pipe_config->vrr.vmax,
> +		    pipe_config->vrr.pipeline_full, pipe_config->vrr.flipline,
> +		    intel_vrr_vmin_vblank_start(pipe_config),
> +		    intel_vrr_vmax_vblank_start(pipe_config));
> +
>  	drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
>  	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
>  	drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
> -- 
> 2.19.1
> 
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Re: [Intel-gfx] [PATCH v4 17/18] drm/i915: Fix vblank timestamps with VRR

[Navare, Manasi]

On Wed, Jan 13, 2021 at 02:09:34PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> To get sensible vblank timestamping behaviour we need to feed
> the vmax based timings to the vblank code, otherwise it'll chop
> off the scanline counter when it exceeds the minumum vtotal.
> 
> Additionally with VRR we have three cases to consider when we
> generate the vblank timestamp:
> 1) we are in vertical active
>   -> nothing special needs to be done, just return the current
>      scanout position and the core will calculate the timestamp
>      corresponding to the past time when the current vertical
>      active started
> 2) we are in vertical blank and no push has been sent
>   -> the hardware will keep extending the vblank presumably
>      to its maximum length, so we make the timestmap match the
>      expected time when the max length vblank will end. Since
>      the timings used for this are now based on vmax nothing
>      special actually needs to be done
> 3) we are in vblank and a push has been sent so the vblank is
>    about to terminate
>   -> presumably we want the timestmap to accurately reflect
>      when the vblank will terminate, so we use the sampled
>      frame timestamp vs. current timestamp to guesstimate
>      how far along the vblank exit we are, and then we
>      adjust the reported scanout position accordingly so
>      that the core will see that the vblank is close to
>      ending.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_display.c    | 17 ++++++++++++-----
>  .../gpu/drm/i915/display/intel_display_types.h  |  4 ++++
>  drivers/gpu/drm/i915/display/intel_vrr.c        |  4 ++++
>  drivers/gpu/drm/i915/i915_irq.c                 | 15 ++++++++++++++-
>  4 files changed, 34 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 4ed279f034be..d989baa44c37 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13835,10 +13835,17 @@ intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->hw.adjusted_mode;
> +	struct drm_display_mode adjusted_mode =
> +		crtc_state->hw.adjusted_mode;
> +
> +	if (crtc_state->vrr.enable) {
> +		adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;
> +		adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;
> +		adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
> +		crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
> +	}
>  
> -	drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
> +	drm_calc_timestamping_constants(&crtc->base, &adjusted_mode);
>  
>  	crtc->mode_flags = crtc_state->mode_flags;
>  
> @@ -13872,8 +13879,8 @@ intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
>  	if (IS_GEN(dev_priv, 2)) {
>  		int vtotal;
>  
> -		vtotal = adjusted_mode->crtc_vtotal;
> -		if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
> +		vtotal = adjusted_mode.crtc_vtotal;
> +		if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
>  			vtotal /= 2;
>  
>  		crtc->scanline_offset = vtotal - 1;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index aa0842028414..3fee613617f1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -679,6 +679,8 @@ struct intel_crtc_scaler_state {
>  #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
>  /* Flag to indicate mipi dsi periodic command mode where we do not get TE */
>  #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
> +/* Do tricks to make vblank timestamps sane with VRR? */
> +#define I915_MODE_FLAG_VRR (1<<6)
>  
>  struct intel_wm_level {
>  	bool enable;
> @@ -1186,6 +1188,8 @@ struct intel_crtc {
>  	/* I915_MODE_FLAG_* */
>  	u8 mode_flags;
>  
> +	u16 vmax_vblank_start;
> +
>  	struct intel_display_power_domain_set enabled_power_domains;
>  	struct intel_overlay *overlay;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 9a18c36e4a9a..a494d3ecb1b5 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -134,6 +134,8 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>  	 */
>  	crtc_state->vrr.pipeline_full =
>  		min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1);
> +
> +	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>  }
>  
>  void intel_vrr_enable(struct intel_encoder *encoder,
> @@ -202,4 +204,6 @@ void intel_vrr_get_config(struct intel_crtc *crtc,
>  		crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;
>  	crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1;
>  	crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1;
> +
> +	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>  }
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 8505ceca87d5..e81afcb2f43e 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -893,7 +893,20 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
>  	if (stime)
>  		*stime = ktime_get();
>  
> -	if (use_scanline_counter) {
> +	if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
> +		int scanlines = intel_crtc_scanlines_since_frame_timestamp(crtc);
> +
> +		position = __intel_get_crtc_scanline(crtc);
> +
> +		/*
> +		 * Already exiting vblank? If so, shift our position
> +		 * so it looks like we're already apporaching the full
> +		 * vblank end. This should make the generated timestamp
> +		 * more or less match when the active portion will start.
> +		 */
> +		if (position >= vbl_start && scanlines < position)
> +			position = min(crtc->vmax_vblank_start + scanlines, vtotal - 1);
> +	} if (use_scanline_counter) {
>  		/* No obvious pixelcount register. Only query vertical
>  		 * scanout position from Display scan line register.
>  		 */
> -- 
> 2.19.1
> 
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Re: [Intel-gfx] [PATCH v4 18/18] drm/i915: Fix vblank evasion with vrr

[Navare, Manasi]

On Wed, Jan 13, 2021 at 02:09:35PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> With vrr enabled the hardware no longer latches the registers
> automagically at vblank start. The point at which it will do the
> latching even when no push has been sent is the vmax decision
> boundary. That is the thing we need to evade to avoid our
> register latching to get split between two frames.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>

Makes sense to us vmax vblank start here with vrr enable

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_sprite.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 0e82d1629d2d..530ce0497559 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -101,7 +101,10 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
>  	if (new_crtc_state->uapi.async_flip)
>  		return;
>  
> -	vblank_start = intel_mode_vblank_start(adjusted_mode);
> +	if (new_crtc_state->vrr.enable)
> +		vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
> +	else
> +		vblank_start = intel_mode_vblank_start(adjusted_mode);
>  
>  	/* FIXME needs to be calibrated sensibly */
>  	min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
> -- 
> 2.19.1
> 
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Re: [Intel-gfx] [PATCH v4 05/18] drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp()

[Navare, Manasi]

On Thu, Jan 21, 2021 at 02:52:11PM -0800, Navare, Manasi wrote:
> On Wed, Jan 13, 2021 at 02:09:22PM -0800, Manasi Navare wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Extract intel_crtc_scanlines_since_frame_timestamp() from
> > __intel_get_crtc_scanline_from_timestamp(). We'll reuse this
> > for VRR vblank timestamps.
> 
> I dont see the intel_crtc_scanlines_since_frame_timestamp() getting used
> later in the series.
> Should this be moved to the intel display poller rest of the patches you might have?
> 
> Manasi

Oh actually I did find where its being used to calculate the vblank timestamps

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> 
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_irq.c | 38 +++++++++++++++++++++------------
> >  1 file changed, 24 insertions(+), 14 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index dd1971040bbc..8505ceca87d5 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -718,25 +718,15 @@ u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
> >  	return intel_uncore_read(&dev_priv->uncore, PIPE_FRMCOUNT_G4X(pipe));
> >  }
> >  
> > -/*
> > - * On certain encoders on certain platforms, pipe
> > - * scanline register will not work to get the scanline,
> > - * since the timings are driven from the PORT or issues
> > - * with scanline register updates.
> > - * This function will use Framestamp and current
> > - * timestamp registers to calculate the scanline.
> > - */
> > -static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
> > +static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  	struct drm_vblank_crtc *vblank =
> >  		&crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
> >  	const struct drm_display_mode *mode = &vblank->hwmode;
> > -	u32 vblank_start = mode->crtc_vblank_start;
> > -	u32 vtotal = mode->crtc_vtotal;
> >  	u32 htotal = mode->crtc_htotal;
> >  	u32 clock = mode->crtc_clock;
> > -	u32 scanline, scan_prev_time, scan_curr_time, scan_post_time;
> > +	u32 scan_prev_time, scan_curr_time, scan_post_time;
> >  
> >  	/*
> >  	 * To avoid the race condition where we might cross into the
> > @@ -763,8 +753,28 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
> >  						  PIPE_FRMTMSTMP(crtc->pipe));
> >  	} while (scan_post_time != scan_prev_time);
> >  
> > -	scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
> > -					clock), 1000 * htotal);
> > +	return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
> > +				   clock), 1000 * htotal);
> > +}
> > +
> > +/*
> > + * On certain encoders on certain platforms, pipe
> > + * scanline register will not work to get the scanline,
> > + * since the timings are driven from the PORT or issues
> > + * with scanline register updates.
> > + * This function will use Framestamp and current
> > + * timestamp registers to calculate the scanline.
> > + */
> > +static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
> > +{
> > +	struct drm_vblank_crtc *vblank =
> > +		&crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
> > +	const struct drm_display_mode *mode = &vblank->hwmode;
> > +	u32 vblank_start = mode->crtc_vblank_start;
> > +	u32 vtotal = mode->crtc_vtotal;
> > +	u32 scanline;
> > +
> > +	scanline = intel_crtc_scanlines_since_frame_timestamp(crtc);
> >  	scanline = min(scanline, vtotal - 1);
> >  	scanline = (scanline + vblank_start) % vtotal;
> >  
> > -- 
> > 2.19.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
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Re: [Intel-gfx] [PATCH v4 03/18] drm/i915: Store framestart_delay in dev_priv

[Ville Syrjälä]

On Thu, Jan 21, 2021 at 02:32:48PM -0800, Navare, Manasi wrote:
> 
> 
> On Wed, Jan 13, 2021 at 02:09:20PM -0800, Manasi Navare wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The vrr calculations will need to know the framestart delay value
> > we use. Currently we program it always to zero, but should that change
> > we probably want to stash it somewhere.
> > 
> > Could stick it into the crtc_state I suppose, but since we never
> > change it let's just stuff it into dev_priv for now.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++++---------
> >  drivers/gpu/drm/i915/i915_drv.h              |  2 ++
> >  2 files changed, 14 insertions(+), 10 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 0189d379a55e..67a55cfa5354 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1610,7 +1610,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
> >  		val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> >  		/* Configure frame start delay to match the CPU */
> >  		val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> > -		val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
> > +		val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay);
> >  		intel_de_write(dev_priv, reg, val);
> >  	}
> >  
> > @@ -1621,7 +1621,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
> >  	if (HAS_PCH_IBX(dev_priv)) {
> >  		/* Configure frame start delay to match the CPU */
> >  		val &= ~TRANS_FRAME_START_DELAY_MASK;
> > -		val |= TRANS_FRAME_START_DELAY(0);
> > +		val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay);
> >  
> >  		/*
> >  		 * Make the BPC in transcoder be consistent with
> > @@ -1666,7 +1666,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
> >  	val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> >  	/* Configure frame start delay to match the CPU */
> >  	val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> > -	val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
> > +	val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay);
> >  	intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
> >  
> >  	val = TRANS_ENABLE;
> > @@ -6679,7 +6679,7 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
> >  
> >  	val = intel_de_read(dev_priv, reg);
> >  	val &= ~HSW_FRAME_START_DELAY_MASK;
> > -	val |= HSW_FRAME_START_DELAY(0);
> > +	val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay);
> >  	intel_de_write(dev_priv, reg, val);
> >  }
> >  
> > @@ -8741,7 +8741,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
> >  
> >  	pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> >  
> > -	pipeconf |= PIPECONF_FRAME_START_DELAY(0);
> > +	pipeconf |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay);
> >  
> >  	intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
> >  	intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
> > @@ -9850,7 +9850,7 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
> >  
> >  	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> >  
> > -	val |= PIPECONF_FRAME_START_DELAY(0);
> > +	val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay);
> >  
> >  	intel_de_write(dev_priv, PIPECONF(pipe), val);
> >  	intel_de_posting_read(dev_priv, PIPECONF(pipe));
> > @@ -17153,6 +17153,8 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
> >  	i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
> >  					WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
> >  
> > +	i915->framestart_delay = 0; /* 0-3 */
> 
> Should we change this to default to 1 and then since its 0 based use framestart_delay - 1 everywhere?

Yeah, since the hw folks seem to like the 1-4 definition we should
probably do the same just so we're always talking the same language.

> 
> Manasi
> 
> > +
> >  	intel_mode_config_init(i915);
> >  
> >  	ret = intel_cdclk_init(i915);
> > @@ -17487,7 +17489,7 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
> >  
> >  		val = intel_de_read(dev_priv, reg);
> >  		val &= ~HSW_FRAME_START_DELAY_MASK;
> > -		val |= HSW_FRAME_START_DELAY(0);
> > +		val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay);
> >  		intel_de_write(dev_priv, reg, val);
> >  	} else {
> >  		i915_reg_t reg = PIPECONF(cpu_transcoder);
> > @@ -17495,7 +17497,7 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
> >  
> >  		val = intel_de_read(dev_priv, reg);
> >  		val &= ~PIPECONF_FRAME_START_DELAY_MASK;
> > -		val |= PIPECONF_FRAME_START_DELAY(0);
> > +		val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay);
> >  		intel_de_write(dev_priv, reg, val);
> >  	}
> >  
> > @@ -17508,7 +17510,7 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
> >  
> >  		val = intel_de_read(dev_priv, reg);
> >  		val &= ~TRANS_FRAME_START_DELAY_MASK;
> > -		val |= TRANS_FRAME_START_DELAY(0);
> > +		val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay);
> >  		intel_de_write(dev_priv, reg, val);
> >  	} else {
> >  		enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
> > @@ -17517,7 +17519,7 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
> >  
> >  		val = intel_de_read(dev_priv, reg);
> >  		val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> > -		val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
> > +		val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay);
> >  		intel_de_write(dev_priv, reg, val);
> >  	}
> >  }
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 15e016194685..94a27e72b0a8 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1182,6 +1182,8 @@ struct drm_i915_private {
> >  		struct file *mmap_singleton;
> >  	} gem;
> >  
> > +	u8 framestart_delay;
> > +
> >  	u8 pch_ssc_use;
> >  
> >  	/* For i915gm/i945gm vblank irq workaround */
> > -- 
> > 2.19.1
> > 
> > _______________________________________________
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> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
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-- 
Ville Syrjälä
Intel
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