* [Intel-gfx] [PATCH 02/10] drm/i915/gt: Skip over completed active execlists, again
2021-01-20 12:21 [Intel-gfx] [PATCH 01/10] drm/i915/gt: Do not suspend bonded requests if one hangs Chris Wilson
@ 2021-01-20 12:21 ` Chris Wilson
2021-01-21 15:23 ` Andi Shyti
2021-01-20 12:21 ` [Intel-gfx] [PATCH 03/10] drm/i915: Strip out internal priorities Chris Wilson
` (12 subsequent siblings)
13 siblings, 1 reply; 27+ messages in thread
From: Chris Wilson @ 2021-01-20 12:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Now that we are careful to always force-restore contexts upon rewinding
(where necessary), we can restore our optimisation to skip over
completed active execlists when dequeuing.
Referenecs: 35f3fd8182ba ("drm/i915/execlists: Workaround switching back to a completed context")
References: 8ab3a3812aa9 ("drm/i915/gt: Incrementally check for rewinding")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
.../drm/i915/gt/intel_execlists_submission.c | 34 +++++++++----------
1 file changed, 16 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 524c8b54d220..ac1be7a632d3 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1224,12 +1224,20 @@ static void set_preempt_timeout(struct intel_engine_cs *engine,
active_preempt_timeout(engine, rq));
}
+static bool completed(const struct i915_request *rq)
+{
+ if (i915_request_has_sentinel(rq))
+ return false;
+
+ return __i915_request_is_complete(rq);
+}
+
static void execlists_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
struct i915_request **port = execlists->pending;
struct i915_request ** const last_port = port + execlists->port_mask;
- struct i915_request *last = *execlists->active;
+ struct i915_request *last, * const *active;
struct virtual_engine *ve;
struct rb_node *rb;
bool submit = false;
@@ -1266,21 +1274,13 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
* i.e. we will retrigger preemption following the ack in case
* of trouble.
*
- * In theory we can skip over completed contexts that have not
- * yet been processed by events (as those events are in flight):
- *
- * while ((last = *active) && i915_request_completed(last))
- * active++;
- *
- * However, the GPU cannot handle this as it will ultimately
- * find itself trying to jump back into a context it has just
- * completed and barf.
*/
+ active = execlists->active;
+ while ((last = *active) && completed(last))
+ active++;
if (last) {
- if (__i915_request_is_complete(last)) {
- goto check_secondary;
- } else if (need_preempt(engine, last)) {
+ if (need_preempt(engine, last)) {
ENGINE_TRACE(engine,
"preempting last=%llx:%lld, prio=%d, hint=%d\n",
last->fence.context,
@@ -1359,9 +1359,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
* we hopefully coalesce several updates into a single
* submission.
*/
-check_secondary:
- if (!list_is_last(&last->sched.link,
- &engine->active.requests)) {
+ if (active[1]) {
/*
* Even if ELSP[1] is occupied and not worthy
* of timeslices, our queue might be.
@@ -1562,7 +1560,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
* of ordered contexts.
*/
if (submit &&
- memcmp(execlists->active,
+ memcmp(active,
execlists->pending,
(port - execlists->pending) * sizeof(*port))) {
*port = NULL;
@@ -1570,7 +1568,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
execlists_schedule_in(*port, port - execlists->pending);
WRITE_ONCE(execlists->yield, -1);
- set_preempt_timeout(engine, *execlists->active);
+ set_preempt_timeout(engine, *active);
execlists_submit_ports(engine);
} else {
ring_set_paused(engine, 0);
--
2.20.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 02/10] drm/i915/gt: Skip over completed active execlists, again
2021-01-20 12:21 ` [Intel-gfx] [PATCH 02/10] drm/i915/gt: Skip over completed active execlists, again Chris Wilson
@ 2021-01-21 15:23 ` Andi Shyti
0 siblings, 0 replies; 27+ messages in thread
From: Andi Shyti @ 2021-01-21 15:23 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
Hi Chris,
> Now that we are careful to always force-restore contexts upon rewinding
> (where necessary), we can restore our optimisation to skip over
> completed active execlists when dequeuing.
>
> Referenecs: 35f3fd8182ba ("drm/i915/execlists: Workaround switching back to a completed context")
> References: 8ab3a3812aa9 ("drm/i915/gt: Incrementally check for rewinding")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> .../drm/i915/gt/intel_execlists_submission.c | 34 +++++++++----------
> 1 file changed, 16 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 524c8b54d220..ac1be7a632d3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -1224,12 +1224,20 @@ static void set_preempt_timeout(struct intel_engine_cs *engine,
> active_preempt_timeout(engine, rq));
> }
>
> +static bool completed(const struct i915_request *rq)
> +{
> + if (i915_request_has_sentinel(rq))
> + return false;
> +
> + return __i915_request_is_complete(rq);
> +}
> +
> static void execlists_dequeue(struct intel_engine_cs *engine)
> {
> struct intel_engine_execlists * const execlists = &engine->execlists;
> struct i915_request **port = execlists->pending;
> struct i915_request ** const last_port = port + execlists->port_mask;
> - struct i915_request *last = *execlists->active;
> + struct i915_request *last, * const *active;
> struct virtual_engine *ve;
> struct rb_node *rb;
> bool submit = false;
> @@ -1266,21 +1274,13 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
> * i.e. we will retrigger preemption following the ack in case
> * of trouble.
> *
> - * In theory we can skip over completed contexts that have not
> - * yet been processed by events (as those events are in flight):
> - *
> - * while ((last = *active) && i915_request_completed(last))
> - * active++;
> - *
> - * However, the GPU cannot handle this as it will ultimately
> - * find itself trying to jump back into a context it has just
> - * completed and barf.
> */
> + active = execlists->active;
> + while ((last = *active) && completed(last))
> + active++;
looks reasonable to me...
Reviewed-by: Andi Shyti <andi.shyti@intel.com>
Thanks,
Andi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 03/10] drm/i915: Strip out internal priorities
2021-01-20 12:21 [Intel-gfx] [PATCH 01/10] drm/i915/gt: Do not suspend bonded requests if one hangs Chris Wilson
2021-01-20 12:21 ` [Intel-gfx] [PATCH 02/10] drm/i915/gt: Skip over completed active execlists, again Chris Wilson
@ 2021-01-20 12:21 ` Chris Wilson
2021-01-21 15:23 ` Andi Shyti
2021-01-20 12:21 ` [Intel-gfx] [PATCH 04/10] drm/i915: Remove I915_USER_PRIORITY_SHIFT Chris Wilson
` (11 subsequent siblings)
13 siblings, 1 reply; 27+ messages in thread
From: Chris Wilson @ 2021-01-20 12:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Since we are not using any internal priority levels, and in the next few
patches will introduce a new index for which the optimisation is not so
lear cut, discard the small table within the priolist.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 2 +-
.../drm/i915/gt/intel_execlists_submission.c | 22 ++------
drivers/gpu/drm/i915/gt/selftest_execlists.c | 1 -
drivers/gpu/drm/i915/gt/selftest_lrc.c | 1 -
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 +--
drivers/gpu/drm/i915/i915_priolist_types.h | 8 +--
drivers/gpu/drm/i915/i915_scheduler.c | 51 +++----------------
drivers/gpu/drm/i915/i915_scheduler.h | 16 ++----
8 files changed, 20 insertions(+), 87 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index d7be2b9339f9..1732a42e9075 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -125,7 +125,7 @@ static void heartbeat(struct work_struct *wrk)
* low latency and no jitter] the chance to naturally
* complete before being preempted.
*/
- attr.priority = I915_PRIORITY_MASK;
+ attr.priority = 0;
if (rq->sched.attr.priority >= attr.priority)
attr.priority |= I915_USER_PRIORITY(I915_PRIORITY_HEARTBEAT);
if (rq->sched.attr.priority >= attr.priority)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index ac1be7a632d3..b31ce0d60028 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -274,22 +274,13 @@ static int effective_prio(const struct i915_request *rq)
static int queue_prio(const struct intel_engine_execlists *execlists)
{
- struct i915_priolist *p;
struct rb_node *rb;
rb = rb_first_cached(&execlists->queue);
if (!rb)
return INT_MIN;
- /*
- * As the priolist[] are inverted, with the highest priority in [0],
- * we have to flip the index value to become priority.
- */
- p = to_priolist(rb);
- if (!I915_USER_PRIORITY_SHIFT)
- return p->priority;
-
- return ((p->priority + 1) << I915_USER_PRIORITY_SHIFT) - ffs(p->used);
+ return to_priolist(rb)->priority;
}
static int virtual_prio(const struct intel_engine_execlists *el)
@@ -1452,9 +1443,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
while ((rb = rb_first_cached(&execlists->queue))) {
struct i915_priolist *p = to_priolist(rb);
struct i915_request *rq, *rn;
- int i;
- priolist_for_each_request_consume(rq, rn, p, i) {
+ priolist_for_each_request_consume(rq, rn, p) {
bool merge = true;
/*
@@ -2968,9 +2958,8 @@ static void execlists_reset_cancel(struct intel_engine_cs *engine)
/* Flush the queued requests to the timeline list (for retiring). */
while ((rb = rb_first_cached(&execlists->queue))) {
struct i915_priolist *p = to_priolist(rb);
- int i;
- priolist_for_each_request_consume(rq, rn, p, i) {
+ priolist_for_each_request_consume(rq, rn, p) {
i915_request_mark_eio(rq);
__i915_request_submit(rq);
}
@@ -3244,7 +3233,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
static struct list_head *virtual_queue(struct virtual_engine *ve)
{
- return &ve->base.execlists.default_priolist.requests[0];
+ return &ve->base.execlists.default_priolist.requests;
}
static void rcu_virtual_context_destroy(struct work_struct *wrk)
@@ -3840,9 +3829,8 @@ void intel_execlists_show_requests(struct intel_engine_cs *engine,
count = 0;
for (rb = rb_first_cached(&execlists->queue); rb; rb = rb_next(rb)) {
struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
- int i;
- priolist_for_each_request(rq, p, i) {
+ priolist_for_each_request(rq, p) {
if (count++ < max - 1)
show_request(m, rq, "\t\t", 0);
else
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 264b5ebdb021..6bce45f63f37 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -1081,7 +1081,6 @@ create_rewinder(struct intel_context *ce,
intel_ring_advance(rq, cs);
- rq->sched.attr.priority = I915_PRIORITY_MASK;
err = 0;
err:
i915_request_get(rq);
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 920979a89413..693a7e2d67c9 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -733,7 +733,6 @@ create_timestamp(struct intel_context *ce, void *slot, int idx)
intel_ring_advance(rq, cs);
- rq->sched.attr.priority = I915_PRIORITY_MASK;
err = 0;
err:
i915_request_get(rq);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 23dc0aeaa0ab..3124d8794d87 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -206,9 +206,8 @@ static void __guc_dequeue(struct intel_engine_cs *engine)
while ((rb = rb_first_cached(&execlists->queue))) {
struct i915_priolist *p = to_priolist(rb);
struct i915_request *rq, *rn;
- int i;
- priolist_for_each_request_consume(rq, rn, p, i) {
+ priolist_for_each_request_consume(rq, rn, p) {
if (last && rq->context != last->context) {
if (port == last_port)
goto done;
@@ -361,9 +360,8 @@ static void guc_reset_cancel(struct intel_engine_cs *engine)
/* Flush the queued requests to the timeline list (for retiring). */
while ((rb = rb_first_cached(&execlists->queue))) {
struct i915_priolist *p = to_priolist(rb);
- int i;
- priolist_for_each_request_consume(rq, rn, p, i) {
+ priolist_for_each_request_consume(rq, rn, p) {
list_del_init(&rq->sched.link);
__i915_request_submit(rq);
dma_fence_set_error(&rq->fence, -EIO);
diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h b/drivers/gpu/drm/i915/i915_priolist_types.h
index 8aa7866ec6b6..9a7657bb002e 100644
--- a/drivers/gpu/drm/i915/i915_priolist_types.h
+++ b/drivers/gpu/drm/i915/i915_priolist_types.h
@@ -27,11 +27,8 @@ enum {
#define I915_USER_PRIORITY_SHIFT 0
#define I915_USER_PRIORITY(x) ((x) << I915_USER_PRIORITY_SHIFT)
-#define I915_PRIORITY_COUNT BIT(I915_USER_PRIORITY_SHIFT)
-#define I915_PRIORITY_MASK (I915_PRIORITY_COUNT - 1)
-
/* Smallest priority value that cannot be bumped. */
-#define I915_PRIORITY_INVALID (INT_MIN | (u8)I915_PRIORITY_MASK)
+#define I915_PRIORITY_INVALID (INT_MIN)
/*
* Requests containing performance queries must not be preempted by
@@ -45,9 +42,8 @@ enum {
#define I915_PRIORITY_BARRIER (I915_PRIORITY_UNPREEMPTABLE - 1)
struct i915_priolist {
- struct list_head requests[I915_PRIORITY_COUNT];
+ struct list_head requests;
struct rb_node node;
- unsigned long used;
int priority;
};
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c
index 7144239f08df..d9f4cafe5a74 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -43,7 +43,7 @@ static inline struct i915_priolist *to_priolist(struct rb_node *rb)
static void assert_priolists(struct intel_engine_execlists * const execlists)
{
struct rb_node *rb;
- long last_prio, i;
+ long last_prio;
if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
return;
@@ -57,14 +57,6 @@ static void assert_priolists(struct intel_engine_execlists * const execlists)
GEM_BUG_ON(p->priority > last_prio);
last_prio = p->priority;
-
- GEM_BUG_ON(!p->used);
- for (i = 0; i < ARRAY_SIZE(p->requests); i++) {
- if (list_empty(&p->requests[i]))
- continue;
-
- GEM_BUG_ON(!(p->used & BIT(i)));
- }
}
}
@@ -75,13 +67,10 @@ i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio)
struct i915_priolist *p;
struct rb_node **parent, *rb;
bool first = true;
- int idx, i;
lockdep_assert_held(&engine->active.lock);
assert_priolists(execlists);
- /* buckets sorted from highest [in slot 0] to lowest priority */
- idx = I915_PRIORITY_COUNT - (prio & I915_PRIORITY_MASK) - 1;
prio >>= I915_USER_PRIORITY_SHIFT;
if (unlikely(execlists->no_priolist))
prio = I915_PRIORITY_NORMAL;
@@ -99,7 +88,7 @@ i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio)
parent = &rb->rb_right;
first = false;
} else {
- goto out;
+ return &p->requests;
}
}
@@ -125,15 +114,12 @@ i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio)
}
p->priority = prio;
- for (i = 0; i < ARRAY_SIZE(p->requests); i++)
- INIT_LIST_HEAD(&p->requests[i]);
+ INIT_LIST_HEAD(&p->requests);
+
rb_link_node(&p->node, rb, parent);
rb_insert_color_cached(&p->node, &execlists->queue, first);
- p->used = 0;
-out:
- p->used |= BIT(idx);
- return &p->requests[idx];
+ return &p->requests;
}
void __i915_priolist_free(struct i915_priolist *p)
@@ -363,30 +349,6 @@ void i915_schedule(struct i915_request *rq, const struct i915_sched_attr *attr)
spin_unlock_irq(&schedule_lock);
}
-static void __bump_priority(struct i915_sched_node *node, unsigned int bump)
-{
- struct i915_sched_attr attr = node->attr;
-
- if (attr.priority & bump)
- return;
-
- attr.priority |= bump;
- __i915_schedule(node, &attr);
-}
-
-void i915_schedule_bump_priority(struct i915_request *rq, unsigned int bump)
-{
- unsigned long flags;
-
- GEM_BUG_ON(bump & ~I915_PRIORITY_MASK);
- if (READ_ONCE(rq->sched.attr.priority) & bump)
- return;
-
- spin_lock_irqsave(&schedule_lock, flags);
- __bump_priority(&rq->sched, bump);
- spin_unlock_irqrestore(&schedule_lock, flags);
-}
-
void i915_sched_node_init(struct i915_sched_node *node)
{
INIT_LIST_HEAD(&node->signalers_list);
@@ -553,8 +515,7 @@ int __init i915_global_scheduler_init(void)
if (!global.slab_dependencies)
return -ENOMEM;
- global.slab_priorities = KMEM_CACHE(i915_priolist,
- SLAB_HWCACHE_ALIGN);
+ global.slab_priorities = KMEM_CACHE(i915_priolist, 0);
if (!global.slab_priorities)
goto err_priorities;
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h
index 4501e5ac2637..858a0938f47a 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -15,17 +15,11 @@
struct drm_printer;
-#define priolist_for_each_request(it, plist, idx) \
- for (idx = 0; idx < ARRAY_SIZE((plist)->requests); idx++) \
- list_for_each_entry(it, &(plist)->requests[idx], sched.link)
+#define priolist_for_each_request(it, plist) \
+ list_for_each_entry(it, &(plist)->requests, sched.link)
-#define priolist_for_each_request_consume(it, n, plist, idx) \
- for (; \
- (plist)->used ? (idx = __ffs((plist)->used)), 1 : 0; \
- (plist)->used &= ~BIT(idx)) \
- list_for_each_entry_safe(it, n, \
- &(plist)->requests[idx], \
- sched.link)
+#define priolist_for_each_request_consume(it, n, plist) \
+ list_for_each_entry_safe(it, n, &(plist)->requests, sched.link)
void i915_sched_node_init(struct i915_sched_node *node);
void i915_sched_node_reinit(struct i915_sched_node *node);
@@ -44,8 +38,6 @@ void i915_sched_node_fini(struct i915_sched_node *node);
void i915_schedule(struct i915_request *request,
const struct i915_sched_attr *attr);
-void i915_schedule_bump_priority(struct i915_request *rq, unsigned int bump);
-
struct list_head *
i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 03/10] drm/i915: Strip out internal priorities
2021-01-20 12:21 ` [Intel-gfx] [PATCH 03/10] drm/i915: Strip out internal priorities Chris Wilson
@ 2021-01-21 15:23 ` Andi Shyti
2021-01-21 15:30 ` Chris Wilson
0 siblings, 1 reply; 27+ messages in thread
From: Andi Shyti @ 2021-01-21 15:23 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
Hi Chris,
> -static void __bump_priority(struct i915_sched_node *node, unsigned int bump)
> -{
> - struct i915_sched_attr attr = node->attr;
> -
> - if (attr.priority & bump)
> - return;
> -
> - attr.priority |= bump;
> - __i915_schedule(node, &attr);
> -}
> -
> -void i915_schedule_bump_priority(struct i915_request *rq, unsigned int bump)
> -{
> - unsigned long flags;
> -
> - GEM_BUG_ON(bump & ~I915_PRIORITY_MASK);
> - if (READ_ONCE(rq->sched.attr.priority) & bump)
> - return;
> -
> - spin_lock_irqsave(&schedule_lock, flags);
> - __bump_priority(&rq->sched, bump);
> - spin_unlock_irqrestore(&schedule_lock, flags);
> -}
was, indeed, this function used anywhere else?
Reviewed-by: Andi Shyti <andi.shyti@intel.com>
Andi
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^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 03/10] drm/i915: Strip out internal priorities
2021-01-21 15:23 ` Andi Shyti
@ 2021-01-21 15:30 ` Chris Wilson
0 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2021-01-21 15:30 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
Quoting Andi Shyti (2021-01-21 15:23:51)
> Hi Chris,
>
> > -static void __bump_priority(struct i915_sched_node *node, unsigned int bump)
> > -{
> > - struct i915_sched_attr attr = node->attr;
> > -
> > - if (attr.priority & bump)
> > - return;
> > -
> > - attr.priority |= bump;
> > - __i915_schedule(node, &attr);
> > -}
> > -
> > -void i915_schedule_bump_priority(struct i915_request *rq, unsigned int bump)
> > -{
> > - unsigned long flags;
> > -
> > - GEM_BUG_ON(bump & ~I915_PRIORITY_MASK);
> > - if (READ_ONCE(rq->sched.attr.priority) & bump)
> > - return;
> > -
> > - spin_lock_irqsave(&schedule_lock, flags);
> > - __bump_priority(&rq->sched, bump);
> > - spin_unlock_irqrestore(&schedule_lock, flags);
> > -}
>
> was, indeed, this function used anywhere else?
Completely overlooked that we had removed the last user a while back.
In my excuse, these have been sitting around for sometime since removing
the no-semaphore boosting.
-Chris
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 04/10] drm/i915: Remove I915_USER_PRIORITY_SHIFT
2021-01-20 12:21 [Intel-gfx] [PATCH 01/10] drm/i915/gt: Do not suspend bonded requests if one hangs Chris Wilson
2021-01-20 12:21 ` [Intel-gfx] [PATCH 02/10] drm/i915/gt: Skip over completed active execlists, again Chris Wilson
2021-01-20 12:21 ` [Intel-gfx] [PATCH 03/10] drm/i915: Strip out internal priorities Chris Wilson
@ 2021-01-20 12:21 ` Chris Wilson
2021-01-21 15:25 ` Andi Shyti
2021-01-20 12:22 ` [Intel-gfx] [PATCH 05/10] drm/i915: Replace engine->schedule() with a known request operation Chris Wilson
` (10 subsequent siblings)
13 siblings, 1 reply; 27+ messages in thread
From: Chris Wilson @ 2021-01-20 12:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
As we do not have any internal priority levels, the priority can be set
directed from the user values.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 +--
.../i915/gem/selftests/i915_gem_object_blt.c | 4 +-
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 10 ++---
drivers/gpu/drm/i915/gt/selftest_execlists.c | 44 +++++++------------
drivers/gpu/drm/i915/i915_priolist_types.h | 3 --
drivers/gpu/drm/i915/i915_scheduler.c | 1 -
7 files changed, 24 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7373f54b216e..6f04f85812fe 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13543,9 +13543,7 @@ int
intel_prepare_plane_fb(struct drm_plane *_plane,
struct drm_plane_state *_new_plane_state)
{
- struct i915_sched_attr attr = {
- .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
- };
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
struct intel_plane *plane = to_intel_plane(_plane);
struct intel_plane_state *new_plane_state =
to_intel_plane_state(_new_plane_state);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 4d2f40cf237b..61a7360c4d9a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -679,7 +679,7 @@ __create_context(struct drm_i915_private *i915)
kref_init(&ctx->ref);
ctx->i915 = i915;
- ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_NORMAL);
+ ctx->sched.priority = I915_PRIORITY_NORMAL;
mutex_init(&ctx->mutex);
INIT_LIST_HEAD(&ctx->link);
@@ -1959,7 +1959,7 @@ static int set_priority(struct i915_gem_context *ctx,
!capable(CAP_SYS_NICE))
return -EPERM;
- ctx->sched.priority = I915_USER_PRIORITY(priority);
+ ctx->sched.priority = priority;
context_apply_all(ctx, __apply_priority, ctx);
return 0;
@@ -2463,7 +2463,7 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
case I915_CONTEXT_PARAM_PRIORITY:
args->size = 0;
- args->value = ctx->sched.priority >> I915_USER_PRIORITY_SHIFT;
+ args->value = ctx->sched.priority;
break;
case I915_CONTEXT_PARAM_SSEU:
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
index 23b6e11bbc3e..c4c04fb97d14 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
@@ -220,7 +220,7 @@ static int igt_fill_blt_thread(void *arg)
return PTR_ERR(ctx);
prio = i915_prandom_u32_max_state(I915_PRIORITY_MAX, prng);
- ctx->sched.priority = I915_USER_PRIORITY(prio);
+ ctx->sched.priority = prio;
}
ce = i915_gem_context_get_engine(ctx, 0);
@@ -338,7 +338,7 @@ static int igt_copy_blt_thread(void *arg)
return PTR_ERR(ctx);
prio = i915_prandom_u32_max_state(I915_PRIORITY_MAX, prng);
- ctx->sched.priority = I915_USER_PRIORITY(prio);
+ ctx->sched.priority = prio;
}
ce = i915_gem_context_get_engine(ctx, 0);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index 1732a42e9075..ed03c08737f5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -81,9 +81,7 @@ static void show_heartbeat(const struct i915_request *rq,
static void heartbeat(struct work_struct *wrk)
{
- struct i915_sched_attr attr = {
- .priority = I915_USER_PRIORITY(I915_PRIORITY_MIN),
- };
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_MIN };
struct intel_engine_cs *engine =
container_of(wrk, typeof(*engine), heartbeat.work.work);
struct intel_context *ce = engine->kernel_context;
@@ -127,7 +125,7 @@ static void heartbeat(struct work_struct *wrk)
*/
attr.priority = 0;
if (rq->sched.attr.priority >= attr.priority)
- attr.priority |= I915_USER_PRIORITY(I915_PRIORITY_HEARTBEAT);
+ attr.priority = I915_PRIORITY_HEARTBEAT;
if (rq->sched.attr.priority >= attr.priority)
attr.priority = I915_PRIORITY_BARRIER;
@@ -285,9 +283,7 @@ int intel_engine_pulse(struct intel_engine_cs *engine)
int intel_engine_flush_barriers(struct intel_engine_cs *engine)
{
- struct i915_sched_attr attr = {
- .priority = I915_USER_PRIORITY(I915_PRIORITY_MIN),
- };
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_MIN };
struct intel_context *ce = engine->kernel_context;
struct i915_request *rq;
int err;
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 6bce45f63f37..7240a61ccb78 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -321,7 +321,7 @@ static int live_unlite_switch(void *arg)
static int live_unlite_preempt(void *arg)
{
- return live_unlite_restore(arg, I915_USER_PRIORITY(I915_PRIORITY_MAX));
+ return live_unlite_restore(arg, I915_PRIORITY_MAX);
}
static int live_unlite_ring(void *arg)
@@ -1311,9 +1311,7 @@ static int live_timeslice_queue(void *arg)
goto err_pin;
for_each_engine(engine, gt, id) {
- struct i915_sched_attr attr = {
- .priority = I915_USER_PRIORITY(I915_PRIORITY_MAX),
- };
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX };
struct i915_request *rq, *nop;
if (!intel_engine_has_preemption(engine))
@@ -1528,14 +1526,12 @@ static int live_busywait_preempt(void *arg)
ctx_hi = kernel_context(gt->i915);
if (!ctx_hi)
return -ENOMEM;
- ctx_hi->sched.priority =
- I915_USER_PRIORITY(I915_CONTEXT_MAX_USER_PRIORITY);
+ ctx_hi->sched.priority = I915_CONTEXT_MAX_USER_PRIORITY;
ctx_lo = kernel_context(gt->i915);
if (!ctx_lo)
goto err_ctx_hi;
- ctx_lo->sched.priority =
- I915_USER_PRIORITY(I915_CONTEXT_MIN_USER_PRIORITY);
+ ctx_lo->sched.priority = I915_CONTEXT_MIN_USER_PRIORITY;
obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
if (IS_ERR(obj)) {
@@ -1732,14 +1728,12 @@ static int live_preempt(void *arg)
ctx_hi = kernel_context(gt->i915);
if (!ctx_hi)
goto err_spin_lo;
- ctx_hi->sched.priority =
- I915_USER_PRIORITY(I915_CONTEXT_MAX_USER_PRIORITY);
+ ctx_hi->sched.priority = I915_CONTEXT_MAX_USER_PRIORITY;
ctx_lo = kernel_context(gt->i915);
if (!ctx_lo)
goto err_ctx_hi;
- ctx_lo->sched.priority =
- I915_USER_PRIORITY(I915_CONTEXT_MIN_USER_PRIORITY);
+ ctx_lo->sched.priority = I915_CONTEXT_MIN_USER_PRIORITY;
for_each_engine(engine, gt, id) {
struct igt_live_test t;
@@ -1832,7 +1826,7 @@ static int live_late_preempt(void *arg)
goto err_ctx_hi;
/* Make sure ctx_lo stays before ctx_hi until we trigger preemption. */
- ctx_lo->sched.priority = I915_USER_PRIORITY(1);
+ ctx_lo->sched.priority = 1;
for_each_engine(engine, gt, id) {
struct igt_live_test t;
@@ -1873,7 +1867,7 @@ static int live_late_preempt(void *arg)
goto err_wedged;
}
- attr.priority = I915_USER_PRIORITY(I915_PRIORITY_MAX);
+ attr.priority = I915_PRIORITY_MAX;
engine->schedule(rq, &attr);
if (!igt_wait_for_spinner(&spin_hi, rq)) {
@@ -1954,7 +1948,7 @@ static int live_nopreempt(void *arg)
return -ENOMEM;
if (preempt_client_init(gt, &b))
goto err_client_a;
- b.ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_MAX);
+ b.ctx->sched.priority = I915_PRIORITY_MAX;
for_each_engine(engine, gt, id) {
struct i915_request *rq_a, *rq_b;
@@ -2419,11 +2413,9 @@ static int live_preempt_cancel(void *arg)
static int live_suppress_self_preempt(void *arg)
{
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX };
struct intel_gt *gt = arg;
struct intel_engine_cs *engine;
- struct i915_sched_attr attr = {
- .priority = I915_USER_PRIORITY(I915_PRIORITY_MAX)
- };
struct preempt_client a, b;
enum intel_engine_id id;
int err = -ENOMEM;
@@ -2554,9 +2546,7 @@ static int live_chain_preempt(void *arg)
goto err_client_hi;
for_each_engine(engine, gt, id) {
- struct i915_sched_attr attr = {
- .priority = I915_USER_PRIORITY(I915_PRIORITY_MAX),
- };
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX };
struct igt_live_test t;
struct i915_request *rq;
int ring_size, count, i;
@@ -2975,9 +2965,7 @@ static int live_preempt_gang(void *arg)
return -EIO;
do {
- struct i915_sched_attr attr = {
- .priority = I915_USER_PRIORITY(prio++),
- };
+ struct i915_sched_attr attr = { .priority = prio++ };
err = create_gang(engine, &rq);
if (err)
@@ -3013,7 +3001,7 @@ static int live_preempt_gang(void *arg)
drm_info_printer(engine->i915->drm.dev);
pr_err("Failed to flush chain of %d requests, at %d\n",
- prio, rq_prio(rq) >> I915_USER_PRIORITY_SHIFT);
+ prio, rq_prio(rq));
intel_engine_dump(engine, &p,
"%s\n", engine->name);
@@ -3383,14 +3371,12 @@ static int live_preempt_timeout(void *arg)
ctx_hi = kernel_context(gt->i915);
if (!ctx_hi)
goto err_spin_lo;
- ctx_hi->sched.priority =
- I915_USER_PRIORITY(I915_CONTEXT_MAX_USER_PRIORITY);
+ ctx_hi->sched.priority = I915_CONTEXT_MAX_USER_PRIORITY;
ctx_lo = kernel_context(gt->i915);
if (!ctx_lo)
goto err_ctx_hi;
- ctx_lo->sched.priority =
- I915_USER_PRIORITY(I915_CONTEXT_MIN_USER_PRIORITY);
+ ctx_lo->sched.priority = I915_CONTEXT_MIN_USER_PRIORITY;
for_each_engine(engine, gt, id) {
unsigned long saved_timeout;
diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h b/drivers/gpu/drm/i915/i915_priolist_types.h
index 9a7657bb002e..bc2fa84f98a8 100644
--- a/drivers/gpu/drm/i915/i915_priolist_types.h
+++ b/drivers/gpu/drm/i915/i915_priolist_types.h
@@ -24,9 +24,6 @@ enum {
I915_PRIORITY_DISPLAY,
};
-#define I915_USER_PRIORITY_SHIFT 0
-#define I915_USER_PRIORITY(x) ((x) << I915_USER_PRIORITY_SHIFT)
-
/* Smallest priority value that cannot be bumped. */
#define I915_PRIORITY_INVALID (INT_MIN)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c
index d9f4cafe5a74..efa638c3acc7 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -71,7 +71,6 @@ i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio)
lockdep_assert_held(&engine->active.lock);
assert_priolists(execlists);
- prio >>= I915_USER_PRIORITY_SHIFT;
if (unlikely(execlists->no_priolist))
prio = I915_PRIORITY_NORMAL;
--
2.20.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 05/10] drm/i915: Replace engine->schedule() with a known request operation
2021-01-20 12:21 [Intel-gfx] [PATCH 01/10] drm/i915/gt: Do not suspend bonded requests if one hangs Chris Wilson
` (2 preceding siblings ...)
2021-01-20 12:21 ` [Intel-gfx] [PATCH 04/10] drm/i915: Remove I915_USER_PRIORITY_SHIFT Chris Wilson
@ 2021-01-20 12:22 ` Chris Wilson
2021-01-21 15:49 ` Andi Shyti
2021-01-20 12:22 ` [Intel-gfx] [PATCH 06/10] drm/i915: Teach the i915_dependency to use a double-lock Chris Wilson
` (9 subsequent siblings)
13 siblings, 1 reply; 27+ messages in thread
From: Chris Wilson @ 2021-01-20 12:22 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Looking to the future, we want to set the scheduling attributes
explicitly and so replace the generic engine->schedule() with the more
direct i915_request_set_priority()
What it loses in removing the 'schedule' name from the function, it
gains in having an explicit entry point with a stated goal.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 ++-
drivers/gpu/drm/i915/gem/i915_gem_object.h | 5 ++-
drivers/gpu/drm/i915/gem/i915_gem_wait.c | 29 +++++-----------
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 --
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 4 +--
drivers/gpu/drm/i915/gt/intel_engine_types.h | 29 ++++++++--------
drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
.../drm/i915/gt/intel_execlists_submission.c | 3 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 33 +++++--------------
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 11 +++----
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 -
drivers/gpu/drm/i915/i915_request.c | 10 +++---
drivers/gpu/drm/i915/i915_scheduler.c | 15 +++++----
drivers/gpu/drm/i915/i915_scheduler.h | 3 +-
14 files changed, 59 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6f04f85812fe..265344d98cbb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13543,7 +13543,6 @@ int
intel_prepare_plane_fb(struct drm_plane *_plane,
struct drm_plane_state *_new_plane_state)
{
- struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
struct intel_plane *plane = to_intel_plane(_plane);
struct intel_plane_state *new_plane_state =
to_intel_plane_state(_new_plane_state);
@@ -13584,7 +13583,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane,
if (new_plane_state->uapi.fence) { /* explicit fencing */
i915_gem_fence_wait_priority(new_plane_state->uapi.fence,
- &attr);
+ I915_PRIORITY_DISPLAY);
ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
new_plane_state->uapi.fence,
i915_fence_timeout(dev_priv),
@@ -13606,7 +13605,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane,
if (ret)
return ret;
- i915_gem_object_wait_priority(obj, 0, &attr);
+ i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
if (!new_plane_state->uapi.fence) { /* implicit fencing */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index b6a16ab85956..92d174017dbf 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -500,15 +500,14 @@ static inline void __start_cpu_write(struct drm_i915_gem_object *obj)
obj->cache_dirty = true;
}
-void i915_gem_fence_wait_priority(struct dma_fence *fence,
- const struct i915_sched_attr *attr);
+void i915_gem_fence_wait_priority(struct dma_fence *fence, int prio);
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
unsigned int flags,
long timeout);
int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
unsigned int flags,
- const struct i915_sched_attr *attr);
+ int prio);
void __i915_gem_object_flush_frontbuffer(struct drm_i915_gem_object *obj,
enum fb_op_origin origin);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_wait.c b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
index 4b9856d5ba14..d79bf16083bd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_wait.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
@@ -91,22 +91,12 @@ i915_gem_object_wait_reservation(struct dma_resv *resv,
return timeout;
}
-static void fence_set_priority(struct dma_fence *fence,
- const struct i915_sched_attr *attr)
+static void fence_set_priority(struct dma_fence *fence, int prio)
{
- struct i915_request *rq;
- struct intel_engine_cs *engine;
-
if (dma_fence_is_signaled(fence) || !dma_fence_is_i915(fence))
return;
- rq = to_request(fence);
- engine = rq->engine;
-
- rcu_read_lock(); /* RCU serialisation for set-wedged protection */
- if (engine->schedule)
- engine->schedule(rq, attr);
- rcu_read_unlock();
+ i915_request_set_priority(to_request(fence), prio);
}
static inline bool __dma_fence_is_chain(const struct dma_fence *fence)
@@ -114,8 +104,7 @@ static inline bool __dma_fence_is_chain(const struct dma_fence *fence)
return fence->ops == &dma_fence_chain_ops;
}
-void i915_gem_fence_wait_priority(struct dma_fence *fence,
- const struct i915_sched_attr *attr)
+void i915_gem_fence_wait_priority(struct dma_fence *fence, int prio)
{
if (dma_fence_is_signaled(fence))
return;
@@ -128,19 +117,19 @@ void i915_gem_fence_wait_priority(struct dma_fence *fence,
int i;
for (i = 0; i < array->num_fences; i++)
- fence_set_priority(array->fences[i], attr);
+ fence_set_priority(array->fences[i], prio);
} else if (__dma_fence_is_chain(fence)) {
struct dma_fence *iter;
/* The chain is ordered; if we boost the last, we boost all */
dma_fence_chain_for_each(iter, fence) {
fence_set_priority(to_dma_fence_chain(iter)->fence,
- attr);
+ prio);
break;
}
dma_fence_put(iter);
} else {
- fence_set_priority(fence, attr);
+ fence_set_priority(fence, prio);
}
local_bh_enable(); /* kick the tasklets if queues were reprioritised */
@@ -149,7 +138,7 @@ void i915_gem_fence_wait_priority(struct dma_fence *fence,
int
i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
unsigned int flags,
- const struct i915_sched_attr *attr)
+ int prio)
{
struct dma_fence *excl;
@@ -164,7 +153,7 @@ i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
return ret;
for (i = 0; i < count; i++) {
- i915_gem_fence_wait_priority(shared[i], attr);
+ i915_gem_fence_wait_priority(shared[i], prio);
dma_fence_put(shared[i]);
}
@@ -174,7 +163,7 @@ i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
}
if (excl) {
- i915_gem_fence_wait_priority(excl, attr);
+ i915_gem_fence_wait_priority(excl, prio);
dma_fence_put(excl);
}
return 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index fb1b1d096975..af4f90be39cd 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -338,9 +338,6 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
if (engine->context_size)
DRIVER_CAPS(i915)->has_logical_contexts = true;
- /* Nothing to do here, execute in order of dependencies */
- engine->schedule = NULL;
-
ewma__engine_latency_init(&engine->latency);
seqcount_init(&engine->stats.lock);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index ed03c08737f5..bccbb932a315 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -115,7 +115,7 @@ static void heartbeat(struct work_struct *wrk)
* but all other contexts, including the kernel
* context are stuck waiting for the signal.
*/
- } else if (engine->schedule &&
+ } else if (intel_engine_has_scheduler(engine) &&
rq->sched.attr.priority < I915_PRIORITY_BARRIER) {
/*
* Gradually raise the priority of the heartbeat to
@@ -130,7 +130,7 @@ static void heartbeat(struct work_struct *wrk)
attr.priority = I915_PRIORITY_BARRIER;
local_bh_disable();
- engine->schedule(rq, &attr);
+ i915_request_set_priority(rq, attr.priority);
local_bh_enable();
} else {
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index d2346b425547..d482674ceb60 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -454,14 +454,6 @@ struct intel_engine_cs {
void (*bond_execute)(struct i915_request *rq,
struct dma_fence *signal);
- /*
- * Call when the priority on a request has changed and it and its
- * dependencies may need rescheduling. Note the request itself may
- * not be ready to run!
- */
- void (*schedule)(struct i915_request *request,
- const struct i915_sched_attr *attr);
-
void (*release)(struct intel_engine_cs *engine);
struct intel_engine_execlists execlists;
@@ -479,13 +471,14 @@ struct intel_engine_cs {
#define I915_ENGINE_USING_CMD_PARSER BIT(0)
#define I915_ENGINE_SUPPORTS_STATS BIT(1)
-#define I915_ENGINE_HAS_PREEMPTION BIT(2)
-#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
-#define I915_ENGINE_HAS_TIMESLICES BIT(4)
-#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(5)
-#define I915_ENGINE_IS_VIRTUAL BIT(6)
-#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(7)
-#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(8)
+#define I915_ENGINE_HAS_SCHEDULER BIT(2)
+#define I915_ENGINE_HAS_PREEMPTION BIT(3)
+#define I915_ENGINE_HAS_SEMAPHORES BIT(4)
+#define I915_ENGINE_HAS_TIMESLICES BIT(5)
+#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(6)
+#define I915_ENGINE_IS_VIRTUAL BIT(7)
+#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(8)
+#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(9)
unsigned int flags;
/*
@@ -573,6 +566,12 @@ intel_engine_supports_stats(const struct intel_engine_cs *engine)
return engine->flags & I915_ENGINE_SUPPORTS_STATS;
}
+static inline bool
+intel_engine_has_scheduler(const struct intel_engine_cs *engine)
+{
+ return engine->flags & I915_ENGINE_HAS_SCHEDULER;
+}
+
static inline bool
intel_engine_has_preemption(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 34e6096f196e..6b5a4fdc14a0 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -108,7 +108,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915)
for_each_uabi_engine(engine, i915) { /* all engines must agree! */
int i;
- if (engine->schedule)
+ if (intel_engine_has_scheduler(engine))
enabled |= (I915_SCHEDULER_CAP_ENABLED |
I915_SCHEDULER_CAP_PRIORITY);
else
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index b31ce0d60028..2e4c069238ad 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3060,7 +3060,6 @@ static bool can_preempt(struct intel_engine_cs *engine)
static void execlists_set_default_submission(struct intel_engine_cs *engine)
{
engine->submit_request = execlists_submit_request;
- engine->schedule = i915_schedule;
engine->execlists.tasklet.func = execlists_submission_tasklet;
engine->reset.prepare = execlists_reset_prepare;
@@ -3071,6 +3070,7 @@ static void execlists_set_default_submission(struct intel_engine_cs *engine)
engine->park = execlists_park;
engine->unpark = NULL;
+ engine->flags |= I915_ENGINE_HAS_SCHEDULER;
engine->flags |= I915_ENGINE_SUPPORTS_STATS;
if (!intel_vgpu_active(engine->i915)) {
engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
@@ -3633,7 +3633,6 @@ intel_execlists_create_virtual(struct intel_engine_cs **siblings,
ve->base.cops = &virtual_context_ops;
ve->base.request_alloc = execlists_request_alloc;
- ve->base.schedule = i915_schedule;
ve->base.submit_request = virtual_submit_request;
ve->base.bond_execute = virtual_bond_execute;
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 7240a61ccb78..993916811dc6 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -269,12 +269,8 @@ static int live_unlite_restore(struct intel_gt *gt, int prio)
i915_request_put(rq[0]);
if (prio) {
- struct i915_sched_attr attr = {
- .priority = prio,
- };
-
/* Alternatively preempt the spinner with ce[1] */
- engine->schedule(rq[1], &attr);
+ i915_request_set_priority(rq[1], prio);
}
/* And switch back to ce[0] for good measure */
@@ -874,9 +870,6 @@ release_queue(struct intel_engine_cs *engine,
struct i915_vma *vma,
int idx, int prio)
{
- struct i915_sched_attr attr = {
- .priority = prio,
- };
struct i915_request *rq;
u32 *cs;
@@ -901,7 +894,7 @@ release_queue(struct intel_engine_cs *engine,
i915_request_add(rq);
local_bh_disable();
- engine->schedule(rq, &attr);
+ i915_request_set_priority(rq, prio);
local_bh_enable(); /* kick tasklet */
i915_request_put(rq);
@@ -1311,7 +1304,6 @@ static int live_timeslice_queue(void *arg)
goto err_pin;
for_each_engine(engine, gt, id) {
- struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX };
struct i915_request *rq, *nop;
if (!intel_engine_has_preemption(engine))
@@ -1326,7 +1318,7 @@ static int live_timeslice_queue(void *arg)
err = PTR_ERR(rq);
goto err_heartbeat;
}
- engine->schedule(rq, &attr);
+ i915_request_set_priority(rq, I915_PRIORITY_MAX);
err = wait_for_submit(engine, rq, HZ / 2);
if (err) {
pr_err("%s: Timed out trying to submit semaphores\n",
@@ -1807,7 +1799,6 @@ static int live_late_preempt(void *arg)
struct i915_gem_context *ctx_hi, *ctx_lo;
struct igt_spinner spin_hi, spin_lo;
struct intel_engine_cs *engine;
- struct i915_sched_attr attr = {};
enum intel_engine_id id;
int err = -ENOMEM;
@@ -1867,8 +1858,7 @@ static int live_late_preempt(void *arg)
goto err_wedged;
}
- attr.priority = I915_PRIORITY_MAX;
- engine->schedule(rq, &attr);
+ i915_request_set_priority(rq, I915_PRIORITY_MAX);
if (!igt_wait_for_spinner(&spin_hi, rq)) {
pr_err("High priority context failed to preempt the low priority context\n");
@@ -2413,7 +2403,6 @@ static int live_preempt_cancel(void *arg)
static int live_suppress_self_preempt(void *arg)
{
- struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX };
struct intel_gt *gt = arg;
struct intel_engine_cs *engine;
struct preempt_client a, b;
@@ -2481,7 +2470,7 @@ static int live_suppress_self_preempt(void *arg)
i915_request_add(rq_b);
GEM_BUG_ON(i915_request_completed(rq_a));
- engine->schedule(rq_a, &attr);
+ i915_request_set_priority(rq_a, I915_PRIORITY_MAX);
igt_spinner_end(&a.spin);
if (!igt_wait_for_spinner(&b.spin, rq_b)) {
@@ -2546,7 +2535,6 @@ static int live_chain_preempt(void *arg)
goto err_client_hi;
for_each_engine(engine, gt, id) {
- struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX };
struct igt_live_test t;
struct i915_request *rq;
int ring_size, count, i;
@@ -2613,7 +2601,7 @@ static int live_chain_preempt(void *arg)
i915_request_get(rq);
i915_request_add(rq);
- engine->schedule(rq, &attr);
+ i915_request_set_priority(rq, I915_PRIORITY_MAX);
igt_spinner_end(&hi.spin);
if (i915_request_wait(rq, 0, HZ / 5) < 0) {
@@ -2965,14 +2953,12 @@ static int live_preempt_gang(void *arg)
return -EIO;
do {
- struct i915_sched_attr attr = { .priority = prio++ };
-
err = create_gang(engine, &rq);
if (err)
break;
/* Submit each spinner at increasing priority */
- engine->schedule(rq, &attr);
+ i915_request_set_priority(rq, prio++);
} while (prio <= I915_PRIORITY_MAX &&
!__igt_timeout(end_time, NULL));
pr_debug("%s: Preempt chain of %d requests\n",
@@ -3193,9 +3179,6 @@ static int preempt_user(struct intel_engine_cs *engine,
struct i915_vma *global,
int id)
{
- struct i915_sched_attr attr = {
- .priority = I915_PRIORITY_MAX
- };
struct i915_request *rq;
int err = 0;
u32 *cs;
@@ -3220,7 +3203,7 @@ static int preempt_user(struct intel_engine_cs *engine,
i915_request_get(rq);
i915_request_add(rq);
- engine->schedule(rq, &attr);
+ i915_request_set_priority(rq, I915_PRIORITY_MAX);
if (i915_request_wait(rq, 0, HZ / 2) < 0)
err = -ETIME;
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 463bb6a700c8..ac3923c9be4b 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -877,12 +877,11 @@ static int active_engine(void *data)
rq[idx] = i915_request_get(new);
i915_request_add(new);
- if (engine->schedule && arg->flags & TEST_PRIORITY) {
- struct i915_sched_attr attr = {
- .priority =
- i915_prandom_u32_max_state(512, &prng),
- };
- engine->schedule(rq[idx], &attr);
+ if (intel_engine_has_scheduler(engine) &&
+ arg->flags & TEST_PRIORITY) {
+ int prio = i915_prandom_u32_max_state(512, &prng);
+
+ i915_request_set_priority(rq[idx], prio);
}
err = active_request_put(old);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 3124d8794d87..53cf68e240c3 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -607,7 +607,6 @@ static int guc_resume(struct intel_engine_cs *engine)
static void guc_set_default_submission(struct intel_engine_cs *engine)
{
engine->submit_request = guc_submit_request;
- engine->schedule = i915_schedule;
engine->execlists.tasklet.func = guc_submission_tasklet;
engine->reset.prepare = guc_reset_prepare;
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index 22e39d938f17..abda565dfe62 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1218,7 +1218,7 @@ __i915_request_await_execution(struct i915_request *to,
}
/* Couple the dependency tree for PI on this exposed to->fence */
- if (to->engine->schedule) {
+ if (intel_engine_has_scheduler(to->engine)) {
err = i915_sched_node_add_dependency(&to->sched,
&from->sched,
I915_DEPENDENCY_WEAK);
@@ -1359,7 +1359,7 @@ i915_request_await_request(struct i915_request *to, struct i915_request *from)
return 0;
}
- if (to->engine->schedule) {
+ if (intel_engine_has_scheduler(to->engine)) {
ret = i915_sched_node_add_dependency(&to->sched,
&from->sched,
I915_DEPENDENCY_EXTERNAL);
@@ -1546,7 +1546,7 @@ __i915_request_add_to_timeline(struct i915_request *rq)
__i915_sw_fence_await_dma_fence(&rq->submit,
&prev->fence,
&rq->dmaq);
- if (rq->engine->schedule)
+ if (intel_engine_has_scheduler(rq->engine))
__i915_sched_node_add_dependency(&rq->sched,
&prev->sched,
&rq->dep,
@@ -1618,8 +1618,8 @@ void __i915_request_queue(struct i915_request *rq,
* decide whether to preempt the entire chain so that it is ready to
* run at the earliest possible convenience.
*/
- if (attr && rq->engine->schedule)
- rq->engine->schedule(rq, attr);
+ if (attr)
+ i915_request_set_priority(rq, attr->priority);
local_bh_disable();
__i915_request_queue_bh(rq);
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c
index efa638c3acc7..dbdd4128f13d 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -216,10 +216,8 @@ static void kick_submission(struct intel_engine_cs *engine,
rcu_read_unlock();
}
-static void __i915_schedule(struct i915_sched_node *node,
- const struct i915_sched_attr *attr)
+static void __i915_schedule(struct i915_sched_node *node, int prio)
{
- const int prio = max(attr->priority, node->attr.priority);
struct intel_engine_cs *engine;
struct i915_dependency *dep, *p;
struct i915_dependency stack;
@@ -233,6 +231,8 @@ static void __i915_schedule(struct i915_sched_node *node,
if (node_signaled(node))
return;
+ prio = max(prio, node->attr.priority);
+
stack.signaler = node;
list_add(&stack.dfs_link, &dfs);
@@ -286,7 +286,7 @@ static void __i915_schedule(struct i915_sched_node *node,
*/
if (node->attr.priority == I915_PRIORITY_INVALID) {
GEM_BUG_ON(!list_empty(&node->link));
- node->attr = *attr;
+ node->attr.priority = prio;
if (stack.dfs_link.next == stack.dfs_link.prev)
return;
@@ -341,10 +341,13 @@ static void __i915_schedule(struct i915_sched_node *node,
spin_unlock(&engine->active.lock);
}
-void i915_schedule(struct i915_request *rq, const struct i915_sched_attr *attr)
+void i915_request_set_priority(struct i915_request *rq, int prio)
{
+ if (!intel_engine_has_scheduler(rq->engine))
+ return;
+
spin_lock_irq(&schedule_lock);
- __i915_schedule(&rq->sched, attr);
+ __i915_schedule(&rq->sched, prio);
spin_unlock_irq(&schedule_lock);
}
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h
index 858a0938f47a..ccee506c9a26 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -35,8 +35,7 @@ int i915_sched_node_add_dependency(struct i915_sched_node *node,
void i915_sched_node_fini(struct i915_sched_node *node);
-void i915_schedule(struct i915_request *request,
- const struct i915_sched_attr *attr);
+void i915_request_set_priority(struct i915_request *request, int prio);
struct list_head *
i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio);
--
2.20.1
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^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 05/10] drm/i915: Replace engine->schedule() with a known request operation
2021-01-20 12:22 ` [Intel-gfx] [PATCH 05/10] drm/i915: Replace engine->schedule() with a known request operation Chris Wilson
@ 2021-01-21 15:49 ` Andi Shyti
2021-01-21 16:25 ` Chris Wilson
0 siblings, 1 reply; 27+ messages in thread
From: Andi Shyti @ 2021-01-21 15:49 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
Hi Chris,
On Wed, Jan 20, 2021 at 12:22:00PM +0000, Chris Wilson wrote:
> Looking to the future, we want to set the scheduling attributes
> explicitly and so replace the generic engine->schedule() with the more
> direct i915_request_set_priority()
>
> What it loses in removing the 'schedule' name from the function, it
> gains in having an explicit entry point with a stated goal.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 ++-
> drivers/gpu/drm/i915/gem/i915_gem_object.h | 5 ++-
> drivers/gpu/drm/i915/gem/i915_gem_wait.c | 29 +++++-----------
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 --
> .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 4 +--
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 29 ++++++++--------
> drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
> .../drm/i915/gt/intel_execlists_submission.c | 3 +-
> drivers/gpu/drm/i915/gt/selftest_execlists.c | 33 +++++--------------
> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 11 +++----
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 -
> drivers/gpu/drm/i915/i915_request.c | 10 +++---
> drivers/gpu/drm/i915/i915_scheduler.c | 15 +++++----
> drivers/gpu/drm/i915/i915_scheduler.h | 3 +-
> 14 files changed, 59 insertions(+), 94 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6f04f85812fe..265344d98cbb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13543,7 +13543,6 @@ int
> intel_prepare_plane_fb(struct drm_plane *_plane,
> struct drm_plane_state *_new_plane_state)
> {
> - struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
do we still need the 'i915_scheduler_types' type?
Andi
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^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 05/10] drm/i915: Replace engine->schedule() with a known request operation
2021-01-21 15:49 ` Andi Shyti
@ 2021-01-21 16:25 ` Chris Wilson
0 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2021-01-21 16:25 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
Quoting Andi Shyti (2021-01-21 15:49:49)
> Hi Chris,
>
> On Wed, Jan 20, 2021 at 12:22:00PM +0000, Chris Wilson wrote:
> > Looking to the future, we want to set the scheduling attributes
> > explicitly and so replace the generic engine->schedule() with the more
> > direct i915_request_set_priority()
> >
> > What it loses in removing the 'schedule' name from the function, it
> > gains in having an explicit entry point with a stated goal.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 5 ++-
> > drivers/gpu/drm/i915/gem/i915_gem_object.h | 5 ++-
> > drivers/gpu/drm/i915/gem/i915_gem_wait.c | 29 +++++-----------
> > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 --
> > .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 4 +--
> > drivers/gpu/drm/i915/gt/intel_engine_types.h | 29 ++++++++--------
> > drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
> > .../drm/i915/gt/intel_execlists_submission.c | 3 +-
> > drivers/gpu/drm/i915/gt/selftest_execlists.c | 33 +++++--------------
> > drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 11 +++----
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 -
> > drivers/gpu/drm/i915/i915_request.c | 10 +++---
> > drivers/gpu/drm/i915/i915_scheduler.c | 15 +++++----
> > drivers/gpu/drm/i915/i915_scheduler.h | 3 +-
> > 14 files changed, 59 insertions(+), 94 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 6f04f85812fe..265344d98cbb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -13543,7 +13543,6 @@ int
> > intel_prepare_plane_fb(struct drm_plane *_plane,
> > struct drm_plane_state *_new_plane_state)
> > {
> > - struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
>
> do we still need the 'i915_scheduler_types' type?
Not for the foreseeable future.
It's been a long time since I put frequency in the scheduling attr, and
if asked to revive it today, I would make it a specific
i915_request_set_frequency.
-Chris
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 06/10] drm/i915: Teach the i915_dependency to use a double-lock
2021-01-20 12:21 [Intel-gfx] [PATCH 01/10] drm/i915/gt: Do not suspend bonded requests if one hangs Chris Wilson
` (3 preceding siblings ...)
2021-01-20 12:22 ` [Intel-gfx] [PATCH 05/10] drm/i915: Replace engine->schedule() with a known request operation Chris Wilson
@ 2021-01-20 12:22 ` Chris Wilson
2021-01-20 12:22 ` [Intel-gfx] [PATCH 07/10] drm/i915: Restructure priority inheritance Chris Wilson
` (8 subsequent siblings)
13 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2021-01-20 12:22 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Currently, we construct and teardown the i915_dependency chains using a
global spinlock. As the lists are entirely local, it should be possible
to use an double-lock with an explicit nesting [signaler -> waiter,
always] and so avoid the costly convenience of a global spinlock.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_request.c | 2 +-
drivers/gpu/drm/i915/i915_scheduler.c | 65 +++++++++++++--------
drivers/gpu/drm/i915/i915_scheduler.h | 2 +-
drivers/gpu/drm/i915/i915_scheduler_types.h | 2 +
4 files changed, 46 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index abda565dfe62..df2ab39b394d 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -330,7 +330,7 @@ bool i915_request_retire(struct i915_request *rq)
intel_context_unpin(rq->context);
free_capture_list(rq);
- i915_sched_node_fini(&rq->sched);
+ i915_sched_node_retire(&rq->sched);
i915_request_put(rq);
return true;
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c
index dbdd4128f13d..96fe1e22dad7 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -19,6 +19,17 @@ static struct i915_global_scheduler {
static DEFINE_SPINLOCK(schedule_lock);
+static struct i915_sched_node *node_get(struct i915_sched_node *node)
+{
+ i915_request_get(container_of(node, struct i915_request, sched));
+ return node;
+}
+
+static void node_put(struct i915_sched_node *node)
+{
+ i915_request_put(container_of(node, struct i915_request, sched));
+}
+
static const struct i915_request *
node_to_request(const struct i915_sched_node *node)
{
@@ -353,6 +364,8 @@ void i915_request_set_priority(struct i915_request *rq, int prio)
void i915_sched_node_init(struct i915_sched_node *node)
{
+ spin_lock_init(&node->lock);
+
INIT_LIST_HEAD(&node->signalers_list);
INIT_LIST_HEAD(&node->waiters_list);
INIT_LIST_HEAD(&node->link);
@@ -377,10 +390,17 @@ i915_dependency_alloc(void)
return kmem_cache_alloc(global.slab_dependencies, GFP_KERNEL);
}
+static void
+rcu_dependency_free(struct rcu_head *rcu)
+{
+ kmem_cache_free(global.slab_dependencies,
+ container_of(rcu, typeof(struct i915_dependency), rcu));
+}
+
static void
i915_dependency_free(struct i915_dependency *dep)
{
- kmem_cache_free(global.slab_dependencies, dep);
+ call_rcu(&dep->rcu, rcu_dependency_free);
}
bool __i915_sched_node_add_dependency(struct i915_sched_node *node,
@@ -390,24 +410,27 @@ bool __i915_sched_node_add_dependency(struct i915_sched_node *node,
{
bool ret = false;
- spin_lock_irq(&schedule_lock);
+ /* The signal->lock is always the outer lock in this double-lock. */
+ spin_lock(&signal->lock);
if (!node_signaled(signal)) {
INIT_LIST_HEAD(&dep->dfs_link);
dep->signaler = signal;
- dep->waiter = node;
+ dep->waiter = node_get(node);
dep->flags = flags;
/* All set, now publish. Beware the lockless walkers. */
+ spin_lock_nested(&node->lock, SINGLE_DEPTH_NESTING);
list_add_rcu(&dep->signal_link, &node->signalers_list);
list_add_rcu(&dep->wait_link, &signal->waiters_list);
+ spin_unlock(&node->lock);
/* Propagate the chains */
node->flags |= signal->flags;
ret = true;
}
- spin_unlock_irq(&schedule_lock);
+ spin_unlock(&signal->lock);
return ret;
}
@@ -429,39 +452,36 @@ int i915_sched_node_add_dependency(struct i915_sched_node *node,
return 0;
}
-void i915_sched_node_fini(struct i915_sched_node *node)
+void i915_sched_node_retire(struct i915_sched_node *node)
{
struct i915_dependency *dep, *tmp;
- spin_lock_irq(&schedule_lock);
-
/*
* Everyone we depended upon (the fences we wait to be signaled)
* should retire before us and remove themselves from our list.
* However, retirement is run independently on each timeline and
- * so we may be called out-of-order.
+ * so we may be called out-of-order. As we need to avoid taking
+ * the signaler's lock, just mark up our completion and be wary
+ * in traversing the signalers->waiters_list.
*/
- list_for_each_entry_safe(dep, tmp, &node->signalers_list, signal_link) {
- GEM_BUG_ON(!list_empty(&dep->dfs_link));
-
- list_del_rcu(&dep->wait_link);
- if (dep->flags & I915_DEPENDENCY_ALLOC)
- i915_dependency_free(dep);
- }
- INIT_LIST_HEAD(&node->signalers_list);
/* Remove ourselves from everyone who depends upon us */
+ spin_lock(&node->lock);
list_for_each_entry_safe(dep, tmp, &node->waiters_list, wait_link) {
- GEM_BUG_ON(dep->signaler != node);
- GEM_BUG_ON(!list_empty(&dep->dfs_link));
+ struct i915_sched_node *w = dep->waiter;
+ GEM_BUG_ON(dep->signaler != node);
+
+ spin_lock_nested(&w->lock, SINGLE_DEPTH_NESTING);
list_del_rcu(&dep->signal_link);
+ spin_unlock(&w->lock);
+ node_put(w);
+
if (dep->flags & I915_DEPENDENCY_ALLOC)
i915_dependency_free(dep);
}
- INIT_LIST_HEAD(&node->waiters_list);
-
- spin_unlock_irq(&schedule_lock);
+ INIT_LIST_HEAD_RCU(&node->waiters_list);
+ spin_unlock(&node->lock);
}
void i915_request_show_with_schedule(struct drm_printer *m,
@@ -512,8 +532,7 @@ static struct i915_global_scheduler global = { {
int __init i915_global_scheduler_init(void)
{
global.slab_dependencies = KMEM_CACHE(i915_dependency,
- SLAB_HWCACHE_ALIGN |
- SLAB_TYPESAFE_BY_RCU);
+ SLAB_HWCACHE_ALIGN);
if (!global.slab_dependencies)
return -ENOMEM;
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h
index ccee506c9a26..a045be784c67 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -33,7 +33,7 @@ int i915_sched_node_add_dependency(struct i915_sched_node *node,
struct i915_sched_node *signal,
unsigned long flags);
-void i915_sched_node_fini(struct i915_sched_node *node);
+void i915_sched_node_retire(struct i915_sched_node *node);
void i915_request_set_priority(struct i915_request *request, int prio);
diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h
index 343ed44d5ed4..623bf41fcf35 100644
--- a/drivers/gpu/drm/i915/i915_scheduler_types.h
+++ b/drivers/gpu/drm/i915/i915_scheduler_types.h
@@ -60,6 +60,7 @@ struct i915_sched_attr {
* others.
*/
struct i915_sched_node {
+ spinlock_t lock; /* protect the lists */
struct list_head signalers_list; /* those before us, we depend upon */
struct list_head waiters_list; /* those after us, they depend upon us */
struct list_head link;
@@ -75,6 +76,7 @@ struct i915_dependency {
struct list_head signal_link;
struct list_head wait_link;
struct list_head dfs_link;
+ struct rcu_head rcu;
unsigned long flags;
#define I915_DEPENDENCY_ALLOC BIT(0)
#define I915_DEPENDENCY_EXTERNAL BIT(1)
--
2.20.1
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 07/10] drm/i915: Restructure priority inheritance
2021-01-20 12:21 [Intel-gfx] [PATCH 01/10] drm/i915/gt: Do not suspend bonded requests if one hangs Chris Wilson
` (4 preceding siblings ...)
2021-01-20 12:22 ` [Intel-gfx] [PATCH 06/10] drm/i915: Teach the i915_dependency to use a double-lock Chris Wilson
@ 2021-01-20 12:22 ` Chris Wilson
2021-01-26 17:18 ` Andi Shyti
2021-01-20 12:22 ` [Intel-gfx] [PATCH 08/10] drm/i915/selftests: Measure set-priority duration Chris Wilson
` (7 subsequent siblings)
13 siblings, 1 reply; 27+ messages in thread
From: Chris Wilson @ 2021-01-20 12:22 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
In anticipation of wanting to be able to call pi from underneath an
engine's active.lock, rework the priority inheritance to primarily work
along an engine's priority queue, delegating any other engine that the
chain may traverse to a worker. This reduces the global spinlock from
governing the multi-entire priority inheritance depth-first search, to a
smaller lock on each engine around a single list on that engine.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 +
drivers/gpu/drm/i915/i915_scheduler.c | 346 ++++++++++++-------
drivers/gpu/drm/i915/i915_scheduler.h | 2 +
drivers/gpu/drm/i915/i915_scheduler_types.h | 19 +-
5 files changed, 234 insertions(+), 138 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index af4f90be39cd..8e7bc0c28af2 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -595,6 +595,8 @@ void intel_engine_init_execlists(struct intel_engine_cs *engine)
execlists->queue_priority_hint = INT_MIN;
execlists->queue = RB_ROOT_CACHED;
+
+ i915_sched_init_ipi(&execlists->ipi);
}
static void cleanup_status_page(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index d482674ceb60..1258b1f795a7 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -21,6 +21,7 @@
#include "i915_gem.h"
#include "i915_pmu.h"
#include "i915_priolist_types.h"
+#include "i915_scheduler_types.h"
#include "i915_selftest.h"
#include "intel_breadcrumbs_types.h"
#include "intel_sseu.h"
@@ -258,6 +259,8 @@ struct intel_engine_execlists {
struct rb_root_cached queue;
struct rb_root_cached virtual;
+ struct i915_sched_ipi ipi;
+
/**
* @csb_write: control register for Context Switch buffer
*
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c
index 96fe1e22dad7..0ecf71a6afd4 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -17,8 +17,6 @@ static struct i915_global_scheduler {
struct kmem_cache *slab_priorities;
} global;
-static DEFINE_SPINLOCK(schedule_lock);
-
static struct i915_sched_node *node_get(struct i915_sched_node *node)
{
i915_request_get(container_of(node, struct i915_request, sched));
@@ -30,17 +28,116 @@ static void node_put(struct i915_sched_node *node)
i915_request_put(container_of(node, struct i915_request, sched));
}
+static inline int rq_prio(const struct i915_request *rq)
+{
+ return READ_ONCE(rq->sched.attr.priority);
+}
+
+static int ipi_get_prio(struct i915_request *rq)
+{
+ if (READ_ONCE(rq->sched.ipi_priority) == I915_PRIORITY_INVALID)
+ return I915_PRIORITY_INVALID;
+
+ return xchg(&rq->sched.ipi_priority, I915_PRIORITY_INVALID);
+}
+
+static void ipi_schedule(struct work_struct *wrk)
+{
+ struct i915_sched_ipi *ipi = container_of(wrk, typeof(*ipi), work);
+ struct i915_request *rq = xchg(&ipi->list, NULL);
+
+ do {
+ struct i915_request *rn = xchg(&rq->sched.ipi_link, NULL);
+ int prio;
+
+ prio = ipi_get_prio(rq);
+
+ /*
+ * For cross-engine scheduling to work we rely on one of two
+ * things:
+ *
+ * a) The requests are using dma-fence fences and so will not
+ * be scheduled until the previous engine is completed, and
+ * so we cannot cross back onto the original engine and end up
+ * queuing an earlier request after the first (due to the
+ * interrupted DFS).
+ *
+ * b) The requests are using semaphores and so may be already
+ * be in flight, in which case if we cross back onto the same
+ * engine, we will already have put the interrupted DFS into
+ * the priolist, and the continuation will now be queued
+ * afterwards [out-of-order]. However, since we are using
+ * semaphores in this case, we also perform yield on semaphore
+ * waits and so will reorder the requests back into the correct
+ * sequence. This occurrence (of promoting a request chain
+ * that crosses the engines using semaphores back unto itself)
+ * should be unlikely enough that it probably does not matter...
+ */
+ local_bh_disable();
+ i915_request_set_priority(rq, prio);
+ local_bh_enable();
+
+ i915_request_put(rq);
+ rq = ptr_mask_bits(rn, 1);
+ } while (rq);
+}
+
+void i915_sched_init_ipi(struct i915_sched_ipi *ipi)
+{
+ INIT_WORK(&ipi->work, ipi_schedule);
+ ipi->list = NULL;
+}
+
+static void __ipi_add(struct i915_request *rq)
+{
+#define STUB ((struct i915_request *)1)
+ struct intel_engine_cs *engine = READ_ONCE(rq->engine);
+ struct i915_request *first;
+
+ if (!i915_request_get_rcu(rq))
+ return;
+
+ if (__i915_request_is_complete(rq) ||
+ cmpxchg(&rq->sched.ipi_link, NULL, STUB)) { /* already queued */
+ i915_request_put(rq);
+ return;
+ }
+
+ first = READ_ONCE(engine->execlists.ipi.list);
+ do
+ rq->sched.ipi_link = ptr_pack_bits(first, 1, 1);
+ while (!try_cmpxchg(&engine->execlists.ipi.list, &first, rq));
+
+ if (!first)
+ queue_work(system_unbound_wq, &engine->execlists.ipi.work);
+}
+
+/*
+ * Virtual engines complicate acquiring the engine timeline lock,
+ * as their rq->engine pointer is not stable until under that
+ * engine lock. The simple ploy we use is to take the lock then
+ * check that the rq still belongs to the newly locked engine.
+ */
+#define lock_engine_irqsave(rq, flags) ({ \
+ struct i915_request * const rq__ = (rq); \
+ struct intel_engine_cs *engine__ = READ_ONCE(rq__->engine); \
+\
+ spin_lock_irqsave(&engine__->active.lock, (flags)); \
+ while (engine__ != READ_ONCE((rq__)->engine)) { \
+ spin_unlock(&engine__->active.lock); \
+ engine__ = READ_ONCE(rq__->engine); \
+ spin_lock(&engine__->active.lock); \
+ } \
+\
+ engine__; \
+})
+
static const struct i915_request *
node_to_request(const struct i915_sched_node *node)
{
return container_of(node, const struct i915_request, sched);
}
-static inline bool node_started(const struct i915_sched_node *node)
-{
- return i915_request_started(node_to_request(node));
-}
-
static inline bool node_signaled(const struct i915_sched_node *node)
{
return i915_request_completed(node_to_request(node));
@@ -137,42 +234,6 @@ void __i915_priolist_free(struct i915_priolist *p)
kmem_cache_free(global.slab_priorities, p);
}
-struct sched_cache {
- struct list_head *priolist;
-};
-
-static struct intel_engine_cs *
-sched_lock_engine(const struct i915_sched_node *node,
- struct intel_engine_cs *locked,
- struct sched_cache *cache)
-{
- const struct i915_request *rq = node_to_request(node);
- struct intel_engine_cs *engine;
-
- GEM_BUG_ON(!locked);
-
- /*
- * Virtual engines complicate acquiring the engine timeline lock,
- * as their rq->engine pointer is not stable until under that
- * engine lock. The simple ploy we use is to take the lock then
- * check that the rq still belongs to the newly locked engine.
- */
- while (locked != (engine = READ_ONCE(rq->engine))) {
- spin_unlock(&locked->active.lock);
- memset(cache, 0, sizeof(*cache));
- spin_lock(&engine->active.lock);
- locked = engine;
- }
-
- GEM_BUG_ON(locked != engine);
- return locked;
-}
-
-static inline int rq_prio(const struct i915_request *rq)
-{
- return rq->sched.attr.priority;
-}
-
static inline bool need_preempt(int prio, int active)
{
/*
@@ -198,19 +259,17 @@ static void kick_submission(struct intel_engine_cs *engine,
if (prio <= engine->execlists.queue_priority_hint)
return;
- rcu_read_lock();
-
/* Nothing currently active? We're overdue for a submission! */
inflight = execlists_active(&engine->execlists);
if (!inflight)
- goto unlock;
+ return;
/*
* If we are already the currently executing context, don't
* bother evaluating if we should preempt ourselves.
*/
if (inflight->context == rq->context)
- goto unlock;
+ return;
ENGINE_TRACE(engine,
"bumping queue-priority-hint:%d for rq:%llx:%lld, inflight:%llx:%lld prio %d\n",
@@ -222,30 +281,28 @@ static void kick_submission(struct intel_engine_cs *engine,
engine->execlists.queue_priority_hint = prio;
if (need_preempt(prio, rq_prio(inflight)))
tasklet_hi_schedule(&engine->execlists.tasklet);
-
-unlock:
- rcu_read_unlock();
}
-static void __i915_schedule(struct i915_sched_node *node, int prio)
+static void ipi_priority(struct i915_request *rq, int prio)
{
- struct intel_engine_cs *engine;
- struct i915_dependency *dep, *p;
- struct i915_dependency stack;
- struct sched_cache cache;
+ int old = READ_ONCE(rq->sched.ipi_priority);
+
+ do {
+ if (prio <= old)
+ return;
+ } while (!try_cmpxchg(&rq->sched.ipi_priority, &old, prio));
+
+ __ipi_add(rq);
+}
+
+static void __i915_request_set_priority(struct i915_request *rq, int prio)
+{
+ struct intel_engine_cs *engine = rq->engine;
+ struct i915_request *rn;
+ struct list_head *plist;
LIST_HEAD(dfs);
- /* Needed in order to use the temporary link inside i915_dependency */
- lockdep_assert_held(&schedule_lock);
- GEM_BUG_ON(prio == I915_PRIORITY_INVALID);
-
- if (node_signaled(node))
- return;
-
- prio = max(prio, node->attr.priority);
-
- stack.signaler = node;
- list_add(&stack.dfs_link, &dfs);
+ list_add(&rq->sched.dfs, &dfs);
/*
* Recursively bump all dependent priorities to match the new request.
@@ -265,66 +322,41 @@ static void __i915_schedule(struct i915_sched_node *node, int prio)
* end result is a topological list of requests in reverse order, the
* last element in the list is the request we must execute first.
*/
- list_for_each_entry(dep, &dfs, dfs_link) {
- struct i915_sched_node *node = dep->signaler;
+ list_for_each_entry(rq, &dfs, sched.dfs) {
+ struct i915_dependency *p;
- /* If we are already flying, we know we have no signalers */
- if (node_started(node))
- continue;
+ /* Also release any children on this engine that are ready */
+ GEM_BUG_ON(rq->engine != engine);
- /*
- * Within an engine, there can be no cycle, but we may
- * refer to the same dependency chain multiple times
- * (redundant dependencies are not eliminated) and across
- * engines.
- */
- list_for_each_entry(p, &node->signalers_list, signal_link) {
- GEM_BUG_ON(p == dep); /* no cycles! */
+ for_each_signaler(p, rq) {
+ struct i915_request *s =
+ container_of(p->signaler, typeof(*s), sched);
- if (node_signaled(p->signaler))
+ GEM_BUG_ON(s == rq);
+
+ if (rq_prio(s) >= prio)
continue;
- if (prio > READ_ONCE(p->signaler->attr.priority))
- list_move_tail(&p->dfs_link, &dfs);
+ if (__i915_request_is_complete(s))
+ continue;
+
+ if (s->engine != rq->engine) {
+ ipi_priority(s, prio);
+ continue;
+ }
+
+ list_move_tail(&s->sched.dfs, &dfs);
}
}
- /*
- * If we didn't need to bump any existing priorities, and we haven't
- * yet submitted this request (i.e. there is no potential race with
- * execlists_submit_request()), we can set our own priority and skip
- * acquiring the engine locks.
- */
- if (node->attr.priority == I915_PRIORITY_INVALID) {
- GEM_BUG_ON(!list_empty(&node->link));
- node->attr.priority = prio;
+ plist = i915_sched_lookup_priolist(engine, prio);
- if (stack.dfs_link.next == stack.dfs_link.prev)
- return;
+ /* Fifo and depth-first replacement ensure our deps execute first */
+ list_for_each_entry_safe_reverse(rq, rn, &dfs, sched.dfs) {
+ GEM_BUG_ON(rq->engine != engine);
- __list_del_entry(&stack.dfs_link);
- }
-
- memset(&cache, 0, sizeof(cache));
- engine = node_to_request(node)->engine;
- spin_lock(&engine->active.lock);
-
- /* Fifo and depth-first replacement ensure our deps execute before us */
- engine = sched_lock_engine(node, engine, &cache);
- list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) {
- INIT_LIST_HEAD(&dep->dfs_link);
-
- node = dep->signaler;
- engine = sched_lock_engine(node, engine, &cache);
- lockdep_assert_held(&engine->active.lock);
-
- /* Recheck after acquiring the engine->timeline.lock */
- if (prio <= node->attr.priority || node_signaled(node))
- continue;
-
- GEM_BUG_ON(node_to_request(node)->engine != engine);
-
- WRITE_ONCE(node->attr.priority, prio);
+ INIT_LIST_HEAD(&rq->sched.dfs);
+ WRITE_ONCE(rq->sched.attr.priority, prio);
/*
* Once the request is ready, it will be placed into the
@@ -334,32 +366,75 @@ static void __i915_schedule(struct i915_sched_node *node, int prio)
* any preemption required, be dealt with upon submission.
* See engine->submit_request()
*/
- if (list_empty(&node->link))
+ if (!i915_request_is_ready(rq))
continue;
- if (i915_request_in_priority_queue(node_to_request(node))) {
- if (!cache.priolist)
- cache.priolist =
- i915_sched_lookup_priolist(engine,
- prio);
- list_move_tail(&node->link, cache.priolist);
- }
+ if (i915_request_in_priority_queue(rq))
+ list_move_tail(&rq->sched.link, plist);
- /* Defer (tasklet) submission until after all of our updates. */
- kick_submission(engine, node_to_request(node), prio);
+ /* Defer (tasklet) submission until after all updates. */
+ kick_submission(engine, rq, prio);
}
-
- spin_unlock(&engine->active.lock);
}
void i915_request_set_priority(struct i915_request *rq, int prio)
{
- if (!intel_engine_has_scheduler(rq->engine))
+ struct intel_engine_cs *engine;
+ unsigned long flags;
+
+ if (prio <= rq_prio(rq))
return;
- spin_lock_irq(&schedule_lock);
- __i915_schedule(&rq->sched, prio);
- spin_unlock_irq(&schedule_lock);
+ /*
+ * If we are setting the priority before being submitted, see if we
+ * can quickly adjust our own priority in-situ and avoid taking
+ * the contended engine->active.lock. If we need priority inheritance,
+ * take the slow route.
+ */
+ if (rq_prio(rq) == I915_PRIORITY_INVALID) {
+ struct i915_dependency *p;
+
+ rcu_read_lock();
+ for_each_signaler(p, rq) {
+ struct i915_request *s =
+ container_of(p->signaler, typeof(*s), sched);
+
+ if (rq_prio(s) >= prio)
+ continue;
+
+ if (__i915_request_is_complete(s))
+ continue;
+
+ break;
+ }
+ rcu_read_unlock();
+
+ if (&p->signal_link == &rq->sched.signalers_list &&
+ cmpxchg(&rq->sched.attr.priority,
+ I915_PRIORITY_INVALID,
+ prio) == I915_PRIORITY_INVALID)
+ return;
+ }
+
+ engine = lock_engine_irqsave(rq, flags);
+ if (prio <= rq_prio(rq))
+ goto unlock;
+
+ if (__i915_request_is_complete(rq))
+ goto unlock;
+
+ if (!intel_engine_has_scheduler(engine)) {
+ rq->sched.attr.priority = prio;
+ goto unlock;
+ }
+
+ rcu_read_lock();
+ __i915_request_set_priority(rq, prio);
+ rcu_read_unlock();
+ GEM_BUG_ON(rq_prio(rq) != prio);
+
+unlock:
+ spin_unlock_irqrestore(&engine->active.lock, flags);
}
void i915_sched_node_init(struct i915_sched_node *node)
@@ -369,6 +444,9 @@ void i915_sched_node_init(struct i915_sched_node *node)
INIT_LIST_HEAD(&node->signalers_list);
INIT_LIST_HEAD(&node->waiters_list);
INIT_LIST_HEAD(&node->link);
+ INIT_LIST_HEAD(&node->dfs);
+
+ node->ipi_link = NULL;
i915_sched_node_reinit(node);
}
@@ -379,6 +457,9 @@ void i915_sched_node_reinit(struct i915_sched_node *node)
node->semaphores = 0;
node->flags = 0;
+ GEM_BUG_ON(node->ipi_link);
+ node->ipi_priority = I915_PRIORITY_INVALID;
+
GEM_BUG_ON(!list_empty(&node->signalers_list));
GEM_BUG_ON(!list_empty(&node->waiters_list));
GEM_BUG_ON(!list_empty(&node->link));
@@ -414,7 +495,6 @@ bool __i915_sched_node_add_dependency(struct i915_sched_node *node,
spin_lock(&signal->lock);
if (!node_signaled(signal)) {
- INIT_LIST_HEAD(&dep->dfs_link);
dep->signaler = signal;
dep->waiter = node_get(node);
dep->flags = flags;
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h
index a045be784c67..5be7f90e7896 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -35,6 +35,8 @@ int i915_sched_node_add_dependency(struct i915_sched_node *node,
void i915_sched_node_retire(struct i915_sched_node *node);
+void i915_sched_init_ipi(struct i915_sched_ipi *ipi);
+
void i915_request_set_priority(struct i915_request *request, int prio);
struct list_head *
diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h
index 623bf41fcf35..5a84d59134ee 100644
--- a/drivers/gpu/drm/i915/i915_scheduler_types.h
+++ b/drivers/gpu/drm/i915/i915_scheduler_types.h
@@ -8,8 +8,8 @@
#define _I915_SCHEDULER_TYPES_H_
#include <linux/list.h>
+#include <linux/workqueue.h>
-#include "gt/intel_engine_types.h"
#include "i915_priolist_types.h"
struct drm_i915_private;
@@ -61,13 +61,23 @@ struct i915_sched_attr {
*/
struct i915_sched_node {
spinlock_t lock; /* protect the lists */
+
struct list_head signalers_list; /* those before us, we depend upon */
struct list_head waiters_list; /* those after us, they depend upon us */
- struct list_head link;
+ struct list_head link; /* guarded by engine->active.lock */
+ struct list_head dfs; /* guarded by engine->active.lock */
struct i915_sched_attr attr;
- unsigned int flags;
+ unsigned long flags;
#define I915_SCHED_HAS_EXTERNAL_CHAIN BIT(0)
- intel_engine_mask_t semaphores;
+ unsigned long semaphores;
+
+ struct i915_request *ipi_link;
+ int ipi_priority;
+};
+
+struct i915_sched_ipi {
+ struct i915_request *list;
+ struct work_struct work;
};
struct i915_dependency {
@@ -75,7 +85,6 @@ struct i915_dependency {
struct i915_sched_node *waiter;
struct list_head signal_link;
struct list_head wait_link;
- struct list_head dfs_link;
struct rcu_head rcu;
unsigned long flags;
#define I915_DEPENDENCY_ALLOC BIT(0)
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 07/10] drm/i915: Restructure priority inheritance
2021-01-20 12:22 ` [Intel-gfx] [PATCH 07/10] drm/i915: Restructure priority inheritance Chris Wilson
@ 2021-01-26 17:18 ` Andi Shyti
2021-01-26 19:03 ` Chris Wilson
0 siblings, 1 reply; 27+ messages in thread
From: Andi Shyti @ 2021-01-26 17:18 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
Hi Chris,
> + local_bh_disable();
> + i915_request_set_priority(rq, prio);
> + local_bh_enable();
> +
> + i915_request_put(rq);
> + rq = ptr_mask_bits(rn, 1);
why are you using ptr_mask_bits here?
> + } while (rq);
> +}
> +
> +void i915_sched_init_ipi(struct i915_sched_ipi *ipi)
> +{
> + INIT_WORK(&ipi->work, ipi_schedule);
> + ipi->list = NULL;
> +}
> +
> +static void __ipi_add(struct i915_request *rq)
> +{
> +#define STUB ((struct i915_request *)1)
> + struct intel_engine_cs *engine = READ_ONCE(rq->engine);
> + struct i915_request *first;
> +
> + if (!i915_request_get_rcu(rq))
> + return;
> +
> + if (__i915_request_is_complete(rq) ||
> + cmpxchg(&rq->sched.ipi_link, NULL, STUB)) { /* already queued */
> + i915_request_put(rq);
> + return;
> + }
> +
> + first = READ_ONCE(engine->execlists.ipi.list);
> + do
> + rq->sched.ipi_link = ptr_pack_bits(first, 1, 1);
... and why ptr_pack_bits here?
do they make any difference?
Andi
> @@ -265,66 +322,41 @@ static void __i915_schedule(struct i915_sched_node *node, int prio)
> * end result is a topological list of requests in reverse order, the
> * last element in the list is the request we must execute first.
> */
> - list_for_each_entry(dep, &dfs, dfs_link) {
> - struct i915_sched_node *node = dep->signaler;
> + list_for_each_entry(rq, &dfs, sched.dfs) {
> + struct i915_dependency *p;
>
> - /* If we are already flying, we know we have no signalers */
> - if (node_started(node))
> - continue;
> + /* Also release any children on this engine that are ready */
> + GEM_BUG_ON(rq->engine != engine);
>
> - /*
> - * Within an engine, there can be no cycle, but we may
> - * refer to the same dependency chain multiple times
> - * (redundant dependencies are not eliminated) and across
> - * engines.
> - */
> - list_for_each_entry(p, &node->signalers_list, signal_link) {
> - GEM_BUG_ON(p == dep); /* no cycles! */
> + for_each_signaler(p, rq) {
> + struct i915_request *s =
> + container_of(p->signaler, typeof(*s), sched);
>
> - if (node_signaled(p->signaler))
> + GEM_BUG_ON(s == rq);
> +
> + if (rq_prio(s) >= prio)
> continue;
>
> - if (prio > READ_ONCE(p->signaler->attr.priority))
> - list_move_tail(&p->dfs_link, &dfs);
> + if (__i915_request_is_complete(s))
> + continue;
> +
> + if (s->engine != rq->engine) {
> + ipi_priority(s, prio);
> + continue;
> + }
> +
> + list_move_tail(&s->sched.dfs, &dfs);
> }
> }
>
> - /*
> - * If we didn't need to bump any existing priorities, and we haven't
> - * yet submitted this request (i.e. there is no potential race with
> - * execlists_submit_request()), we can set our own priority and skip
> - * acquiring the engine locks.
> - */
> - if (node->attr.priority == I915_PRIORITY_INVALID) {
> - GEM_BUG_ON(!list_empty(&node->link));
> - node->attr.priority = prio;
> + plist = i915_sched_lookup_priolist(engine, prio);
>
> - if (stack.dfs_link.next == stack.dfs_link.prev)
> - return;
> + /* Fifo and depth-first replacement ensure our deps execute first */
> + list_for_each_entry_safe_reverse(rq, rn, &dfs, sched.dfs) {
> + GEM_BUG_ON(rq->engine != engine);
>
> - __list_del_entry(&stack.dfs_link);
> - }
> -
> - memset(&cache, 0, sizeof(cache));
> - engine = node_to_request(node)->engine;
> - spin_lock(&engine->active.lock);
> -
> - /* Fifo and depth-first replacement ensure our deps execute before us */
> - engine = sched_lock_engine(node, engine, &cache);
> - list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) {
> - INIT_LIST_HEAD(&dep->dfs_link);
> -
> - node = dep->signaler;
> - engine = sched_lock_engine(node, engine, &cache);
> - lockdep_assert_held(&engine->active.lock);
> -
> - /* Recheck after acquiring the engine->timeline.lock */
> - if (prio <= node->attr.priority || node_signaled(node))
> - continue;
> -
> - GEM_BUG_ON(node_to_request(node)->engine != engine);
> -
> - WRITE_ONCE(node->attr.priority, prio);
> + INIT_LIST_HEAD(&rq->sched.dfs);
> + WRITE_ONCE(rq->sched.attr.priority, prio);
>
> /*
> * Once the request is ready, it will be placed into the
> @@ -334,32 +366,75 @@ static void __i915_schedule(struct i915_sched_node *node, int prio)
> * any preemption required, be dealt with upon submission.
> * See engine->submit_request()
> */
> - if (list_empty(&node->link))
> + if (!i915_request_is_ready(rq))
> continue;
>
> - if (i915_request_in_priority_queue(node_to_request(node))) {
> - if (!cache.priolist)
> - cache.priolist =
> - i915_sched_lookup_priolist(engine,
> - prio);
> - list_move_tail(&node->link, cache.priolist);
> - }
> + if (i915_request_in_priority_queue(rq))
> + list_move_tail(&rq->sched.link, plist);
>
> - /* Defer (tasklet) submission until after all of our updates. */
> - kick_submission(engine, node_to_request(node), prio);
> + /* Defer (tasklet) submission until after all updates. */
> + kick_submission(engine, rq, prio);
> }
> -
> - spin_unlock(&engine->active.lock);
> }
>
> void i915_request_set_priority(struct i915_request *rq, int prio)
> {
> - if (!intel_engine_has_scheduler(rq->engine))
> + struct intel_engine_cs *engine;
> + unsigned long flags;
> +
> + if (prio <= rq_prio(rq))
> return;
>
> - spin_lock_irq(&schedule_lock);
> - __i915_schedule(&rq->sched, prio);
> - spin_unlock_irq(&schedule_lock);
> + /*
> + * If we are setting the priority before being submitted, see if we
> + * can quickly adjust our own priority in-situ and avoid taking
> + * the contended engine->active.lock. If we need priority inheritance,
> + * take the slow route.
> + */
> + if (rq_prio(rq) == I915_PRIORITY_INVALID) {
> + struct i915_dependency *p;
> +
> + rcu_read_lock();
> + for_each_signaler(p, rq) {
> + struct i915_request *s =
> + container_of(p->signaler, typeof(*s), sched);
> +
> + if (rq_prio(s) >= prio)
> + continue;
> +
> + if (__i915_request_is_complete(s))
> + continue;
> +
> + break;
> + }
> + rcu_read_unlock();
> +
> + if (&p->signal_link == &rq->sched.signalers_list &&
> + cmpxchg(&rq->sched.attr.priority,
> + I915_PRIORITY_INVALID,
> + prio) == I915_PRIORITY_INVALID)
> + return;
> + }
> +
> + engine = lock_engine_irqsave(rq, flags);
> + if (prio <= rq_prio(rq))
> + goto unlock;
> +
> + if (__i915_request_is_complete(rq))
> + goto unlock;
> +
> + if (!intel_engine_has_scheduler(engine)) {
> + rq->sched.attr.priority = prio;
> + goto unlock;
> + }
> +
> + rcu_read_lock();
> + __i915_request_set_priority(rq, prio);
> + rcu_read_unlock();
> + GEM_BUG_ON(rq_prio(rq) != prio);
> +
> +unlock:
> + spin_unlock_irqrestore(&engine->active.lock, flags);
> }
>
> void i915_sched_node_init(struct i915_sched_node *node)
> @@ -369,6 +444,9 @@ void i915_sched_node_init(struct i915_sched_node *node)
> INIT_LIST_HEAD(&node->signalers_list);
> INIT_LIST_HEAD(&node->waiters_list);
> INIT_LIST_HEAD(&node->link);
> + INIT_LIST_HEAD(&node->dfs);
> +
> + node->ipi_link = NULL;
>
> i915_sched_node_reinit(node);
> }
> @@ -379,6 +457,9 @@ void i915_sched_node_reinit(struct i915_sched_node *node)
> node->semaphores = 0;
> node->flags = 0;
>
> + GEM_BUG_ON(node->ipi_link);
> + node->ipi_priority = I915_PRIORITY_INVALID;
> +
> GEM_BUG_ON(!list_empty(&node->signalers_list));
> GEM_BUG_ON(!list_empty(&node->waiters_list));
> GEM_BUG_ON(!list_empty(&node->link));
> @@ -414,7 +495,6 @@ bool __i915_sched_node_add_dependency(struct i915_sched_node *node,
> spin_lock(&signal->lock);
>
> if (!node_signaled(signal)) {
> - INIT_LIST_HEAD(&dep->dfs_link);
> dep->signaler = signal;
> dep->waiter = node_get(node);
> dep->flags = flags;
> diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h
> index a045be784c67..5be7f90e7896 100644
> --- a/drivers/gpu/drm/i915/i915_scheduler.h
> +++ b/drivers/gpu/drm/i915/i915_scheduler.h
> @@ -35,6 +35,8 @@ int i915_sched_node_add_dependency(struct i915_sched_node *node,
>
> void i915_sched_node_retire(struct i915_sched_node *node);
>
> +void i915_sched_init_ipi(struct i915_sched_ipi *ipi);
> +
> void i915_request_set_priority(struct i915_request *request, int prio);
>
> struct list_head *
> diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h
> index 623bf41fcf35..5a84d59134ee 100644
> --- a/drivers/gpu/drm/i915/i915_scheduler_types.h
> +++ b/drivers/gpu/drm/i915/i915_scheduler_types.h
> @@ -8,8 +8,8 @@
> #define _I915_SCHEDULER_TYPES_H_
>
> #include <linux/list.h>
> +#include <linux/workqueue.h>
>
> -#include "gt/intel_engine_types.h"
> #include "i915_priolist_types.h"
>
> struct drm_i915_private;
> @@ -61,13 +61,23 @@ struct i915_sched_attr {
> */
> struct i915_sched_node {
> spinlock_t lock; /* protect the lists */
> +
> struct list_head signalers_list; /* those before us, we depend upon */
> struct list_head waiters_list; /* those after us, they depend upon us */
> - struct list_head link;
> + struct list_head link; /* guarded by engine->active.lock */
> + struct list_head dfs; /* guarded by engine->active.lock */
> struct i915_sched_attr attr;
> - unsigned int flags;
> + unsigned long flags;
> #define I915_SCHED_HAS_EXTERNAL_CHAIN BIT(0)
> - intel_engine_mask_t semaphores;
> + unsigned long semaphores;
> +
> + struct i915_request *ipi_link;
> + int ipi_priority;
> +};
> +
> +struct i915_sched_ipi {
> + struct i915_request *list;
> + struct work_struct work;
> };
>
> struct i915_dependency {
> @@ -75,7 +85,6 @@ struct i915_dependency {
> struct i915_sched_node *waiter;
> struct list_head signal_link;
> struct list_head wait_link;
> - struct list_head dfs_link;
> struct rcu_head rcu;
> unsigned long flags;
> #define I915_DEPENDENCY_ALLOC BIT(0)
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 07/10] drm/i915: Restructure priority inheritance
2021-01-26 17:18 ` Andi Shyti
@ 2021-01-26 19:03 ` Chris Wilson
0 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2021-01-26 19:03 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
Quoting Andi Shyti (2021-01-26 17:18:22)
> Hi Chris,
>
> > + local_bh_disable();
> > + i915_request_set_priority(rq, prio);
> > + local_bh_enable();
> > +
> > + i915_request_put(rq);
> > + rq = ptr_mask_bits(rn, 1);
>
> why are you using ptr_mask_bits here?
>
> > + } while (rq);
> > +}
> > +
> > +void i915_sched_init_ipi(struct i915_sched_ipi *ipi)
> > +{
> > + INIT_WORK(&ipi->work, ipi_schedule);
> > + ipi->list = NULL;
> > +}
> > +
> > +static void __ipi_add(struct i915_request *rq)
> > +{
> > +#define STUB ((struct i915_request *)1)
> > + struct intel_engine_cs *engine = READ_ONCE(rq->engine);
> > + struct i915_request *first;
> > +
> > + if (!i915_request_get_rcu(rq))
> > + return;
> > +
> > + if (__i915_request_is_complete(rq) ||
> > + cmpxchg(&rq->sched.ipi_link, NULL, STUB)) { /* already queued */
> > + i915_request_put(rq);
> > + return;
> > + }
> > +
> > + first = READ_ONCE(engine->execlists.ipi.list);
> > + do
> > + rq->sched.ipi_link = ptr_pack_bits(first, 1, 1);
>
> ... and why ptr_pack_bits here?
>
> do they make any difference?
We are using bit0 to differentiate against NULL. So we use the special
value of (void*)1 to mark when the elements is active, but pointing to
nothing.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 08/10] drm/i915/selftests: Measure set-priority duration
2021-01-20 12:21 [Intel-gfx] [PATCH 01/10] drm/i915/gt: Do not suspend bonded requests if one hangs Chris Wilson
` (5 preceding siblings ...)
2021-01-20 12:22 ` [Intel-gfx] [PATCH 07/10] drm/i915: Restructure priority inheritance Chris Wilson
@ 2021-01-20 12:22 ` Chris Wilson
2021-01-26 18:05 ` Andi Shyti
2021-01-20 12:22 ` [Intel-gfx] [PATCH 09/10] drm/i915/selftests: Exercise priority inheritance around an engine loop Chris Wilson
` (6 subsequent siblings)
13 siblings, 1 reply; 27+ messages in thread
From: Chris Wilson @ 2021-01-20 12:22 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
As a topological sort, we expect it to run in linear graph time,
O(V+E). In removing the recursion, it is no longer a DFS but rather a
BFS, and performs as O(VE). Let's demonstrate how bad this is with a few
examples, and build a few test cases to verify a potential fix.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_scheduler.c | 4 +
.../drm/i915/selftests/i915_live_selftests.h | 1 +
.../drm/i915/selftests/i915_perf_selftests.h | 1 +
.../gpu/drm/i915/selftests/i915_scheduler.c | 679 ++++++++++++++++++
4 files changed, 685 insertions(+)
create mode 100644 drivers/gpu/drm/i915/selftests/i915_scheduler.c
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c
index 0ecf71a6afd4..4802c9b1081d 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -592,6 +592,10 @@ void i915_request_show_with_schedule(struct drm_printer *m,
rcu_read_unlock();
}
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftests/i915_scheduler.c"
+#endif
+
static void i915_global_scheduler_shrink(void)
{
kmem_cache_shrink(global.slab_dependencies);
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index a92c0e9b7e6b..2200a5baa68e 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -26,6 +26,7 @@ selftest(gt_mocs, intel_mocs_live_selftests)
selftest(gt_pm, intel_gt_pm_live_selftests)
selftest(gt_heartbeat, intel_heartbeat_live_selftests)
selftest(requests, i915_request_live_selftests)
+selftest(scheduler, i915_scheduler_live_selftests)
selftest(active, i915_active_live_selftests)
selftest(objects, i915_gem_object_live_selftests)
selftest(mman, i915_gem_mman_live_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
index c2389f8a257d..137e35283fee 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
@@ -17,5 +17,6 @@
*/
selftest(engine_cs, intel_engine_cs_perf_selftests)
selftest(request, i915_request_perf_selftests)
+selftest(scheduler, i915_scheduler_perf_selftests)
selftest(blt, i915_gem_object_blt_perf_selftests)
selftest(region, intel_memory_region_perf_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_scheduler.c b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
new file mode 100644
index 000000000000..cb67de304aeb
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
@@ -0,0 +1,679 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "i915_selftest.h"
+
+#include "gt/intel_context.h"
+#include "gt/intel_gpu_commands.h"
+#include "gt/selftest_engine_heartbeat.h"
+#include "selftests/igt_spinner.h"
+#include "selftests/i915_random.h"
+
+static void scheduling_disable(struct intel_engine_cs *engine)
+{
+ engine->props.preempt_timeout_ms = 0;
+ engine->props.timeslice_duration_ms = 0;
+
+ st_engine_heartbeat_disable(engine);
+}
+
+static void scheduling_enable(struct intel_engine_cs *engine)
+{
+ st_engine_heartbeat_enable(engine);
+
+ engine->props.preempt_timeout_ms =
+ engine->defaults.preempt_timeout_ms;
+ engine->props.timeslice_duration_ms =
+ engine->defaults.timeslice_duration_ms;
+}
+
+static int first_engine(struct drm_i915_private *i915,
+ int (*chain)(struct intel_engine_cs *engine,
+ unsigned long param,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v,
+ unsigned long e)),
+ unsigned long param,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ struct intel_engine_cs *engine;
+
+ for_each_uabi_engine(engine, i915) {
+ if (!intel_engine_has_scheduler(engine))
+ continue;
+
+ return chain(engine, param, fn);
+ }
+
+ return 0;
+}
+
+static int all_engines(struct drm_i915_private *i915,
+ int (*chain)(struct intel_engine_cs *engine,
+ unsigned long param,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v,
+ unsigned long e)),
+ unsigned long param,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ struct intel_engine_cs *engine;
+ int err;
+
+ for_each_uabi_engine(engine, i915) {
+ if (!intel_engine_has_scheduler(engine))
+ continue;
+
+ err = chain(engine, param, fn);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static bool check_context_order(struct intel_engine_cs *engine)
+{
+ u64 last_seqno, last_context;
+ unsigned long count;
+ bool result = false;
+ struct rb_node *rb;
+ int last_prio;
+
+ /* We expect the execution order to follow ascending fence-context */
+ spin_lock_irq(&engine->active.lock);
+
+ count = 0;
+ last_context = 0;
+ last_seqno = 0;
+ last_prio = 0;
+ for (rb = rb_first_cached(&engine->execlists.queue); rb; rb = rb_next(rb)) {
+ struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
+ struct i915_request *rq;
+
+ priolist_for_each_request(rq, p) {
+ if (rq->fence.context < last_context ||
+ (rq->fence.context == last_context &&
+ rq->fence.seqno < last_seqno)) {
+ pr_err("[%lu] %llx:%lld [prio:%d] after %llx:%lld [prio:%d]\n",
+ count,
+ rq->fence.context,
+ rq->fence.seqno,
+ rq_prio(rq),
+ last_context,
+ last_seqno,
+ last_prio);
+ goto out_unlock;
+ }
+
+ last_context = rq->fence.context;
+ last_seqno = rq->fence.seqno;
+ last_prio = rq_prio(rq);
+ count++;
+ }
+ }
+ result = true;
+out_unlock:
+ spin_unlock_irq(&engine->active.lock);
+
+ return result;
+}
+
+static int __single_chain(struct intel_engine_cs *engine, unsigned long length,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ struct intel_context *ce;
+ struct igt_spinner spin;
+ struct i915_request *rq;
+ unsigned long count;
+ unsigned long min;
+ int err = 0;
+
+ if (!intel_engine_can_store_dword(engine))
+ return 0;
+
+ scheduling_disable(engine);
+
+ if (igt_spinner_init(&spin, engine->gt)) {
+ err = -ENOMEM;
+ goto err_heartbeat;
+ }
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce)) {
+ err = PTR_ERR(ce);
+ goto err_spin;
+ }
+ ce->ring = __intel_context_ring_size(SZ_512K);
+
+ rq = igt_spinner_create_request(&spin, ce, MI_NOOP);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_context;
+ }
+ i915_request_add(rq);
+ min = ce->ring->size - ce->ring->space;
+
+ count = 1;
+ while (count < length && ce->ring->space > min) {
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+ i915_request_add(rq);
+ count++;
+ }
+ intel_engine_flush_submission(engine);
+
+ tasklet_disable(&engine->execlists.tasklet);
+ local_bh_disable();
+ if (fn(rq, count, count - 1) && !check_context_order(engine))
+ err = -EINVAL;
+ local_bh_enable();
+ tasklet_enable(&engine->execlists.tasklet);
+
+ igt_spinner_end(&spin);
+err_context:
+ intel_context_put(ce);
+err_spin:
+ igt_spinner_fini(&spin);
+err_heartbeat:
+ scheduling_enable(engine);
+ return err;
+}
+
+static int __wide_chain(struct intel_engine_cs *engine, unsigned long width,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ struct intel_context **ce;
+ struct i915_request **rq;
+ struct igt_spinner spin;
+ unsigned long count;
+ unsigned long i, j;
+ int err = 0;
+
+ if (!intel_engine_can_store_dword(engine))
+ return 0;
+
+ scheduling_disable(engine);
+
+ if (igt_spinner_init(&spin, engine->gt)) {
+ err = -ENOMEM;
+ goto err_heartbeat;
+ }
+
+ ce = kmalloc_array(width, sizeof(*ce), GFP_KERNEL);
+ if (!ce) {
+ err = -ENOMEM;
+ goto err_spin;
+ }
+
+ for (i = 0; i < width; i++) {
+ ce[i] = intel_context_create(engine);
+ if (IS_ERR(ce[i])) {
+ err = PTR_ERR(ce[i]);
+ width = i;
+ goto err_context;
+ }
+ }
+
+ rq = kmalloc_array(width, sizeof(*rq), GFP_KERNEL);
+ if (!rq) {
+ err = -ENOMEM;
+ goto err_context;
+ }
+
+ rq[0] = igt_spinner_create_request(&spin, ce[0], MI_NOOP);
+ if (IS_ERR(rq[0])) {
+ err = PTR_ERR(rq[0]);
+ goto err_free;
+ }
+ i915_request_add(rq[0]);
+
+ count = 0;
+ for (i = 1; i < width; i++) {
+ GEM_BUG_ON(i915_request_completed(rq[0]));
+
+ rq[i] = intel_context_create_request(ce[i]);
+ if (IS_ERR(rq[i])) {
+ err = PTR_ERR(rq[i]);
+ break;
+ }
+ for (j = 0; j < i; j++) {
+ err = i915_request_await_dma_fence(rq[i],
+ &rq[j]->fence);
+ if (err)
+ break;
+ count++;
+ }
+ i915_request_add(rq[i]);
+ }
+ intel_engine_flush_submission(engine);
+
+ tasklet_disable(&engine->execlists.tasklet);
+ local_bh_disable();
+ if (fn(rq[i - 1], i, count) && !check_context_order(engine))
+ err = -EINVAL;
+ local_bh_enable();
+ tasklet_enable(&engine->execlists.tasklet);
+
+ igt_spinner_end(&spin);
+err_free:
+ kfree(rq);
+err_context:
+ for (i = 0; i < width; i++)
+ intel_context_put(ce[i]);
+ kfree(ce);
+err_spin:
+ igt_spinner_fini(&spin);
+err_heartbeat:
+ scheduling_enable(engine);
+ return err;
+}
+
+static int __inv_chain(struct intel_engine_cs *engine, unsigned long width,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ struct intel_context **ce;
+ struct i915_request **rq;
+ struct igt_spinner spin;
+ unsigned long count;
+ unsigned long i, j;
+ int err = 0;
+
+ if (!intel_engine_can_store_dword(engine))
+ return 0;
+
+ scheduling_disable(engine);
+
+ if (igt_spinner_init(&spin, engine->gt)) {
+ err = -ENOMEM;
+ goto err_heartbeat;
+ }
+
+ ce = kmalloc_array(width, sizeof(*ce), GFP_KERNEL);
+ if (!ce) {
+ err = -ENOMEM;
+ goto err_spin;
+ }
+
+ for (i = 0; i < width; i++) {
+ ce[i] = intel_context_create(engine);
+ if (IS_ERR(ce[i])) {
+ err = PTR_ERR(ce[i]);
+ width = i;
+ goto err_context;
+ }
+ }
+
+ rq = kmalloc_array(width, sizeof(*rq), GFP_KERNEL);
+ if (!rq) {
+ err = -ENOMEM;
+ goto err_context;
+ }
+
+ rq[0] = igt_spinner_create_request(&spin, ce[0], MI_NOOP);
+ if (IS_ERR(rq[0])) {
+ err = PTR_ERR(rq[0]);
+ goto err_free;
+ }
+ i915_request_add(rq[0]);
+
+ count = 0;
+ for (i = 1; i < width; i++) {
+ GEM_BUG_ON(i915_request_completed(rq[0]));
+
+ rq[i] = intel_context_create_request(ce[i]);
+ if (IS_ERR(rq[i])) {
+ err = PTR_ERR(rq[i]);
+ break;
+ }
+ for (j = i; j > 0; j--) {
+ err = i915_request_await_dma_fence(rq[i],
+ &rq[j - 1]->fence);
+ if (err)
+ break;
+ count++;
+ }
+ i915_request_add(rq[i]);
+ }
+ intel_engine_flush_submission(engine);
+
+ tasklet_disable(&engine->execlists.tasklet);
+ local_bh_disable();
+ if (fn(rq[i - 1], i, count) && !check_context_order(engine))
+ err = -EINVAL;
+ local_bh_enable();
+ tasklet_enable(&engine->execlists.tasklet);
+
+ igt_spinner_end(&spin);
+err_free:
+ kfree(rq);
+err_context:
+ for (i = 0; i < width; i++)
+ intel_context_put(ce[i]);
+ kfree(ce);
+err_spin:
+ igt_spinner_fini(&spin);
+err_heartbeat:
+ scheduling_enable(engine);
+ return err;
+}
+
+static int __sparse_chain(struct intel_engine_cs *engine, unsigned long width,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ struct intel_context **ce;
+ struct i915_request **rq;
+ struct igt_spinner spin;
+ I915_RND_STATE(prng);
+ unsigned long count;
+ unsigned long i, j;
+ int err = 0;
+
+ if (!intel_engine_can_store_dword(engine))
+ return 0;
+
+ scheduling_disable(engine);
+
+ if (igt_spinner_init(&spin, engine->gt)) {
+ err = -ENOMEM;
+ goto err_heartbeat;
+ }
+
+ ce = kmalloc_array(width, sizeof(*ce), GFP_KERNEL);
+ if (!ce) {
+ err = -ENOMEM;
+ goto err_spin;
+ }
+
+ for (i = 0; i < width; i++) {
+ ce[i] = intel_context_create(engine);
+ if (IS_ERR(ce[i])) {
+ err = PTR_ERR(ce[i]);
+ width = i;
+ goto err_context;
+ }
+ }
+
+ rq = kmalloc_array(width, sizeof(*rq), GFP_KERNEL);
+ if (!rq) {
+ err = -ENOMEM;
+ goto err_context;
+ }
+
+ rq[0] = igt_spinner_create_request(&spin, ce[0], MI_NOOP);
+ if (IS_ERR(rq[0])) {
+ err = PTR_ERR(rq[0]);
+ goto err_free;
+ }
+ i915_request_add(rq[0]);
+
+ count = 0;
+ for (i = 1; i < width; i++) {
+ GEM_BUG_ON(i915_request_completed(rq[0]));
+
+ rq[i] = intel_context_create_request(ce[i]);
+ if (IS_ERR(rq[i])) {
+ err = PTR_ERR(rq[i]);
+ break;
+ }
+
+ if (err == 0 && i > 1) {
+ j = i915_prandom_u32_max_state(i - 1, &prng);
+ err = i915_request_await_dma_fence(rq[i],
+ &rq[j]->fence);
+ count++;
+ }
+
+ if (err == 0) {
+ err = i915_request_await_dma_fence(rq[i],
+ &rq[i - 1]->fence);
+ count++;
+ }
+
+ if (err == 0 && i > 2) {
+ j = i915_prandom_u32_max_state(i - 2, &prng);
+ err = i915_request_await_dma_fence(rq[i],
+ &rq[j]->fence);
+ count++;
+ }
+
+ i915_request_add(rq[i]);
+ if (err)
+ break;
+ }
+ intel_engine_flush_submission(engine);
+
+ tasklet_disable(&engine->execlists.tasklet);
+ local_bh_disable();
+ if (fn(rq[i - 1], i, count) && !check_context_order(engine))
+ err = -EINVAL;
+ local_bh_enable();
+ tasklet_enable(&engine->execlists.tasklet);
+
+ igt_spinner_end(&spin);
+err_free:
+ kfree(rq);
+err_context:
+ for (i = 0; i < width; i++)
+ intel_context_put(ce[i]);
+ kfree(ce);
+err_spin:
+ igt_spinner_fini(&spin);
+err_heartbeat:
+ scheduling_enable(engine);
+ return err;
+}
+
+static int igt_schedule_chains(struct drm_i915_private *i915,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ static int (* const chains[])(struct intel_engine_cs *engine,
+ unsigned long length,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e)) = {
+ __single_chain,
+ __wide_chain,
+ __inv_chain,
+ __sparse_chain,
+ };
+ int n, err;
+
+ for (n = 0; n < ARRAY_SIZE(chains); n++) {
+ err = all_engines(i915, chains[n], 17, fn);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static bool igt_priority(struct i915_request *rq,
+ unsigned long v, unsigned long e)
+{
+ i915_request_set_priority(rq, I915_PRIORITY_BARRIER);
+ GEM_BUG_ON(rq_prio(rq) != I915_PRIORITY_BARRIER);
+ return true;
+}
+
+static int igt_priority_chains(void *arg)
+{
+ return igt_schedule_chains(arg, igt_priority);
+}
+
+int i915_scheduler_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(igt_priority_chains),
+ };
+
+ return i915_subtests(tests, i915);
+}
+
+static int chains(struct drm_i915_private *i915,
+ int (*chain)(struct drm_i915_private *i915,
+ unsigned long length,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e)),
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ unsigned long x[] = { 1, 4, 16, 64, 128, 256, 512, 1024, 4096 };
+ int i, err;
+
+ for (i = 0; i < ARRAY_SIZE(x); i++) {
+ IGT_TIMEOUT(end_time);
+
+ err = chain(i915, x[i], fn);
+ if (err)
+ return err;
+
+ if (__igt_timeout(end_time, NULL))
+ break;
+ }
+
+ return 0;
+}
+
+static int single_chain(struct drm_i915_private *i915,
+ unsigned long length,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ return first_engine(i915, __single_chain, length, fn);
+}
+
+static int single(struct drm_i915_private *i915,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ return chains(i915, single_chain, fn);
+}
+
+static int wide_chain(struct drm_i915_private *i915,
+ unsigned long width,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ return first_engine(i915, __wide_chain, width, fn);
+}
+
+static int wide(struct drm_i915_private *i915,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ return chains(i915, wide_chain, fn);
+}
+
+static int inv_chain(struct drm_i915_private *i915,
+ unsigned long width,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ return first_engine(i915, __inv_chain, width, fn);
+}
+
+static int inv(struct drm_i915_private *i915,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ return chains(i915, inv_chain, fn);
+}
+
+static int sparse_chain(struct drm_i915_private *i915,
+ unsigned long width,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ return first_engine(i915, __sparse_chain, width, fn);
+}
+
+static int sparse(struct drm_i915_private *i915,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ return chains(i915, sparse_chain, fn);
+}
+
+static void report(const char *what, unsigned long v, unsigned long e, u64 dt)
+{
+ pr_info("(%4lu, %7lu), %s:%10lluns\n", v, e, what, dt);
+}
+
+static u64 __set_priority(struct i915_request *rq, int prio)
+{
+ u64 dt;
+
+ preempt_disable();
+ dt = ktime_get_raw_fast_ns();
+ i915_request_set_priority(rq, prio);
+ dt = ktime_get_raw_fast_ns() - dt;
+ preempt_enable();
+
+ return dt;
+}
+
+static bool set_priority(struct i915_request *rq,
+ unsigned long v, unsigned long e)
+{
+ report("set-priority", v, e, __set_priority(rq, I915_PRIORITY_BARRIER));
+ return true;
+}
+
+static int single_priority(void *arg)
+{
+ return single(arg, set_priority);
+}
+
+static int wide_priority(void *arg)
+{
+ return wide(arg, set_priority);
+}
+
+static int inv_priority(void *arg)
+{
+ return inv(arg, set_priority);
+}
+
+static int sparse_priority(void *arg)
+{
+ return sparse(arg, set_priority);
+}
+
+int i915_scheduler_perf_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(single_priority),
+ SUBTEST(wide_priority),
+ SUBTEST(inv_priority),
+ SUBTEST(sparse_priority),
+ };
+ static const struct {
+ const char *name;
+ size_t sz;
+ } types[] = {
+#define T(t) { #t, sizeof(struct t) }
+ T(i915_priolist),
+ T(i915_sched_attr),
+ T(i915_sched_node),
+#undef T
+ {}
+ };
+ typeof(*types) *t;
+
+ for (t = types; t->name; t++)
+ pr_info("sizeof(%s): %zd\n", t->name, t->sz);
+
+ return i915_subtests(tests, i915);
+}
--
2.20.1
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^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 08/10] drm/i915/selftests: Measure set-priority duration
2021-01-20 12:22 ` [Intel-gfx] [PATCH 08/10] drm/i915/selftests: Measure set-priority duration Chris Wilson
@ 2021-01-26 18:05 ` Andi Shyti
2021-01-26 21:16 ` Chris Wilson
0 siblings, 1 reply; 27+ messages in thread
From: Andi Shyti @ 2021-01-26 18:05 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Wed, Jan 20, 2021 at 12:22:03PM +0000, Chris Wilson wrote:
> As a topological sort, we expect it to run in linear graph time,
> O(V+E). In removing the recursion, it is no longer a DFS but rather a
> BFS, and performs as O(VE). Let's demonstrate how bad this is with a few
> examples, and build a few test cases to verify a potential fix.
very noble purpose, but...
[...]
> +static int sparse(struct drm_i915_private *i915,
> + bool (*fn)(struct i915_request *rq,
> + unsigned long v, unsigned long e))
> +{
> + return chains(i915, sparse_chain, fn);
> +}
... this is quite an intricate web of functions calling each
other.
Is there any simplier way to do this? This is that kind of code
that if you go on holiday for a few days you forget what you
wrote.
I do need three drawing boards and 24 fingers for keeping track
of what's happening here. :)
> +
> +static void report(const char *what, unsigned long v, unsigned long e, u64 dt)
> +{
> + pr_info("(%4lu, %7lu), %s:%10lluns\n", v, e, what, dt);
> +}
> +
> +static u64 __set_priority(struct i915_request *rq, int prio)
> +{
> + u64 dt;
> +
> + preempt_disable();
> + dt = ktime_get_raw_fast_ns();
> + i915_request_set_priority(rq, prio);
> + dt = ktime_get_raw_fast_ns() - dt;
> + preempt_enable();
> +
> + return dt;
> +}
> +
> +static bool set_priority(struct i915_request *rq,
> + unsigned long v, unsigned long e)
> +{
> + report("set-priority", v, e, __set_priority(rq, I915_PRIORITY_BARRIER));
can't we pr_info directly here and spare a function?
> + return true;
> +}
> +
> +static int single_priority(void *arg)
> +{
> + return single(arg, set_priority);
> +}
> +
> +static int wide_priority(void *arg)
> +{
> + return wide(arg, set_priority);
> +}
> +
> +static int inv_priority(void *arg)
> +{
> + return inv(arg, set_priority);
> +}
> +
> +static int sparse_priority(void *arg)
> +{
> + return sparse(arg, set_priority);
> +}
> +
> +int i915_scheduler_perf_selftests(struct drm_i915_private *i915)
> +{
> + static const struct i915_subtest tests[] = {
> + SUBTEST(single_priority),
> + SUBTEST(wide_priority),
> + SUBTEST(inv_priority),
> + SUBTEST(sparse_priority),
> + };
> + static const struct {
> + const char *name;
> + size_t sz;
> + } types[] = {
> +#define T(t) { #t, sizeof(struct t) }
> + T(i915_priolist),
> + T(i915_sched_attr),
> + T(i915_sched_node),
> +#undef T
is this really making the code better? Is it a big deal to
clearly use
{ i915_priolist, sizeof(i915_priolist) },
{ i915_sched_attr, sizeof(i915_sched_attr) },
{ i915_sched_node, sizeof(i915_sched_node) },
> + {}
> + };
> + typeof(*types) *t;
> +
> + for (t = types; t->name; t++)
> + pr_info("sizeof(%s): %zd\n", t->name, t->sz);
> +
> + return i915_subtests(tests, i915);
> +}
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Andi
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^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 08/10] drm/i915/selftests: Measure set-priority duration
2021-01-26 18:05 ` Andi Shyti
@ 2021-01-26 21:16 ` Chris Wilson
0 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2021-01-26 21:16 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
Quoting Andi Shyti (2021-01-26 18:05:38)
> On Wed, Jan 20, 2021 at 12:22:03PM +0000, Chris Wilson wrote:
> > As a topological sort, we expect it to run in linear graph time,
> > O(V+E). In removing the recursion, it is no longer a DFS but rather a
> > BFS, and performs as O(VE). Let's demonstrate how bad this is with a few
> > examples, and build a few test cases to verify a potential fix.
>
> very noble purpose, but...
>
> [...]
>
> > +static int sparse(struct drm_i915_private *i915,
> > + bool (*fn)(struct i915_request *rq,
> > + unsigned long v, unsigned long e))
> > +{
> > + return chains(i915, sparse_chain, fn);
> > +}
>
> ... this is quite an intricate web of functions calling each
> other.
>
> Is there any simplier way to do this? This is that kind of code
> that if you go on holiday for a few days you forget what you
> wrote.
This was to remove duplication, and there's more tests to come in this
group that use the same framework and only differ in the final step.
> I do need three drawing boards and 24 fingers for keeping track
> of what's happening here. :)
>
> > +
> > +static void report(const char *what, unsigned long v, unsigned long e, u64 dt)
> > +{
> > + pr_info("(%4lu, %7lu), %s:%10lluns\n", v, e, what, dt);
> > +}
> > +
> > +static u64 __set_priority(struct i915_request *rq, int prio)
> > +{
> > + u64 dt;
> > +
> > + preempt_disable();
> > + dt = ktime_get_raw_fast_ns();
> > + i915_request_set_priority(rq, prio);
> > + dt = ktime_get_raw_fast_ns() - dt;
> > + preempt_enable();
> > +
> > + return dt;
> > +}
> > +
> > +static bool set_priority(struct i915_request *rq,
> > + unsigned long v, unsigned long e)
> > +{
> > + report("set-priority", v, e, __set_priority(rq, I915_PRIORITY_BARRIER));
>
> can't we pr_info directly here and spare a function?
It will be reused later.
> > + return true;
> > +}
> > +
> > +static int single_priority(void *arg)
> > +{
> > + return single(arg, set_priority);
> > +}
> > +
> > +static int wide_priority(void *arg)
> > +{
> > + return wide(arg, set_priority);
> > +}
> > +
> > +static int inv_priority(void *arg)
> > +{
> > + return inv(arg, set_priority);
> > +}
> > +
> > +static int sparse_priority(void *arg)
> > +{
> > + return sparse(arg, set_priority);
> > +}
> > +
> > +int i915_scheduler_perf_selftests(struct drm_i915_private *i915)
> > +{
> > + static const struct i915_subtest tests[] = {
> > + SUBTEST(single_priority),
> > + SUBTEST(wide_priority),
> > + SUBTEST(inv_priority),
> > + SUBTEST(sparse_priority),
> > + };
> > + static const struct {
> > + const char *name;
> > + size_t sz;
> > + } types[] = {
> > +#define T(t) { #t, sizeof(struct t) }
> > + T(i915_priolist),
> > + T(i915_sched_attr),
> > + T(i915_sched_node),
> > +#undef T
>
> is this really making the code better? Is it a big deal to
> clearly use
>
> { i915_priolist, sizeof(i915_priolist) },
> { i915_sched_attr, sizeof(i915_sched_attr) },
> { i915_sched_node, sizeof(i915_sched_node) },
Duplication and more typing, you even left out the struct in
sizeof(struct T) :)
Did this save me more time to add stuff than it took to write #define T?
-Chris
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 09/10] drm/i915/selftests: Exercise priority inheritance around an engine loop
2021-01-20 12:21 [Intel-gfx] [PATCH 01/10] drm/i915/gt: Do not suspend bonded requests if one hangs Chris Wilson
` (6 preceding siblings ...)
2021-01-20 12:22 ` [Intel-gfx] [PATCH 08/10] drm/i915/selftests: Measure set-priority duration Chris Wilson
@ 2021-01-20 12:22 ` Chris Wilson
2021-01-20 12:22 ` [Intel-gfx] [PATCH 10/10] drm/i915: Improve DFS for priority inheritance Chris Wilson
` (5 subsequent siblings)
13 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2021-01-20 12:22 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Exercise rescheduling priority inheritance around a sequence of requests
that wrap around all the engines.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
.../gpu/drm/i915/selftests/i915_scheduler.c | 219 ++++++++++++++++++
1 file changed, 219 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_scheduler.c b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
index cb67de304aeb..e6910f4c429d 100644
--- a/drivers/gpu/drm/i915/selftests/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
@@ -7,6 +7,7 @@
#include "gt/intel_context.h"
#include "gt/intel_gpu_commands.h"
+#include "gt/intel_ring.h"
#include "gt/selftest_engine_heartbeat.h"
#include "selftests/igt_spinner.h"
#include "selftests/i915_random.h"
@@ -512,10 +513,228 @@ static int igt_priority_chains(void *arg)
return igt_schedule_chains(arg, igt_priority);
}
+static struct i915_request *
+__write_timestamp(struct intel_engine_cs *engine,
+ struct drm_i915_gem_object *obj,
+ int slot,
+ struct i915_request *prev)
+{
+ struct i915_request *rq = ERR_PTR(-EINVAL);
+ struct intel_context *ce;
+ struct i915_vma *vma;
+ int err = 0;
+ u32 *cs;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return ERR_CAST(ce);
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out_ce;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto out_ce;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_unpin;
+ }
+
+ i915_vma_lock(vma);
+ err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+ i915_vma_unlock(vma);
+ if (err)
+ goto out_request;
+
+ if (prev) {
+ err = i915_request_await_dma_fence(rq, &prev->fence);
+ if (err)
+ goto out_request;
+ }
+
+ if (engine->emit_init_breadcrumb) {
+ err = engine->emit_init_breadcrumb(rq);
+ if (err)
+ goto out_request;
+ }
+
+ cs = intel_ring_begin(rq, 4);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto out_request;
+ }
+
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8;
+ *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base));
+ *cs++ = lower_32_bits(vma->node.start) + sizeof(u32) * slot;
+ *cs++ = upper_32_bits(vma->node.start);
+ intel_ring_advance(rq, cs);
+
+ i915_request_get(rq);
+out_request:
+ i915_request_add(rq);
+out_unpin:
+ i915_vma_unpin(vma);
+out_ce:
+ intel_context_put(ce);
+ i915_request_put(prev);
+ return err ? ERR_PTR(err) : rq;
+}
+
+static struct i915_request *create_spinner(struct drm_i915_private *i915,
+ struct igt_spinner *spin)
+{
+ struct intel_engine_cs *engine;
+
+ for_each_uabi_engine(engine, i915) {
+ struct intel_context *ce;
+ struct i915_request *rq;
+
+ if (igt_spinner_init(spin, engine->gt))
+ return ERR_PTR(-ENOMEM);
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return ERR_CAST(ce);
+
+ rq = igt_spinner_create_request(spin, ce, MI_NOOP);
+ intel_context_put(ce);
+ if (rq == ERR_PTR(-ENODEV))
+ continue;
+ if (IS_ERR(rq))
+ return rq;
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+ return rq;
+ }
+
+ return ERR_PTR(-ENODEV);
+}
+
+static int __igt_schedule_cycle(struct drm_i915_private *i915,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ struct intel_engine_cs *engine;
+ struct drm_i915_gem_object *obj;
+ struct igt_spinner spin;
+ struct i915_request *rq;
+ unsigned long count, n;
+ u32 *time, last;
+ int err;
+
+ /*
+ * Queue a bunch of ordered requests (each waiting on the previous)
+ * around the engines a couple of times. Each request will write
+ * the timestamp it executes at into the scratch, with the expectation
+ * that the timestamp will be in our desired execution order.
+ */
+
+ if (INTEL_GEN(i915) < 8)
+ return 0;
+
+ obj = i915_gem_object_create_internal(i915, SZ_64K);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ time = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ if (IS_ERR(time)) {
+ err = PTR_ERR(time);
+ goto out_obj;
+ }
+
+ rq = create_spinner(i915, &spin);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_obj;
+ }
+
+ err = 0;
+ count = 0;
+ for_each_uabi_engine(engine, i915) {
+ if (!intel_engine_has_scheduler(engine))
+ continue;
+
+ rq = __write_timestamp(engine, obj, count, rq);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ count++;
+ }
+ for_each_uabi_engine(engine, i915) {
+ if (!intel_engine_has_scheduler(engine))
+ continue;
+
+ rq = __write_timestamp(engine, obj, count, rq);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ count++;
+ }
+ GEM_BUG_ON(count * sizeof(u32) > obj->base.size);
+ if (err || !count)
+ goto out_spin;
+
+ fn(rq, count + 1, count);
+ igt_spinner_end(&spin);
+
+ if (i915_request_wait(rq, 0, HZ / 2) < 0) {
+ err = -ETIME;
+ goto out_request;
+ }
+
+ last = time[0];
+ for (n = 1; n < count; n++) {
+ if (i915_seqno_passed(last, time[n])) {
+ pr_err("Timestamp[%lu] %x before previous %x\n",
+ n, time[n], last);
+ err = -EINVAL;
+ break;
+ }
+ last = time[n];
+ }
+
+out_request:
+ i915_request_put(rq);
+out_spin:
+ igt_spinner_fini(&spin);
+out_obj:
+ i915_gem_object_put(obj);
+ return 0;
+}
+
+static bool noop(struct i915_request *rq, unsigned long v, unsigned long e)
+{
+ return true;
+}
+
+static int igt_schedule_cycle(void *arg)
+{
+ return __igt_schedule_cycle(arg, noop);
+}
+
+static int igt_priority_cycle(void *arg)
+{
+ return __igt_schedule_cycle(arg, igt_priority);
+}
+
int i915_scheduler_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(igt_priority_chains),
+
+ SUBTEST(igt_schedule_cycle),
+ SUBTEST(igt_priority_cycle),
};
return i915_subtests(tests, i915);
--
2.20.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 10/10] drm/i915: Improve DFS for priority inheritance
2021-01-20 12:21 [Intel-gfx] [PATCH 01/10] drm/i915/gt: Do not suspend bonded requests if one hangs Chris Wilson
` (7 preceding siblings ...)
2021-01-20 12:22 ` [Intel-gfx] [PATCH 09/10] drm/i915/selftests: Exercise priority inheritance around an engine loop Chris Wilson
@ 2021-01-20 12:22 ` Chris Wilson
2021-01-26 17:34 ` Andi Shyti
2021-01-20 19:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/10] drm/i915/gt: Do not suspend bonded requests if one hangs Patchwork
` (4 subsequent siblings)
13 siblings, 1 reply; 27+ messages in thread
From: Chris Wilson @ 2021-01-20 12:22 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
The core of the scheduling algorithm is that we compute the topological
order of the fence DAG. Knowing that we have a DAG, we should be able to
use a DFS to compute the topological sort in linear time. However,
during the conversion of the recursive algorithm into an iterative one,
the memoization of how far we had progressed down a branch was
forgotten. The result was that instead of running in linear time, it was
running in geometric time and could easily run for a few hundred
milliseconds given a wide enough graph, not the microseconds as required.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_scheduler.c | 58 ++++++++++++++++-----------
1 file changed, 34 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c
index 4802c9b1081d..9139a91f0aa3 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -234,6 +234,26 @@ void __i915_priolist_free(struct i915_priolist *p)
kmem_cache_free(global.slab_priorities, p);
}
+static struct i915_request *
+stack_push(struct i915_request *rq,
+ struct i915_request *stack,
+ struct list_head *pos)
+{
+ stack->sched.dfs.prev = pos;
+ rq->sched.dfs.next = (struct list_head *)stack;
+ return rq;
+}
+
+static struct i915_request *
+stack_pop(struct i915_request *rq,
+ struct list_head **pos)
+{
+ rq = (struct i915_request *)rq->sched.dfs.next;
+ if (rq)
+ *pos = rq->sched.dfs.prev;
+ return rq;
+}
+
static inline bool need_preempt(int prio, int active)
{
/*
@@ -298,11 +318,10 @@ static void ipi_priority(struct i915_request *rq, int prio)
static void __i915_request_set_priority(struct i915_request *rq, int prio)
{
struct intel_engine_cs *engine = rq->engine;
- struct i915_request *rn;
+ struct list_head *pos = &rq->sched.signalers_list;
struct list_head *plist;
- LIST_HEAD(dfs);
- list_add(&rq->sched.dfs, &dfs);
+ plist = i915_sched_lookup_priolist(engine, prio);
/*
* Recursively bump all dependent priorities to match the new request.
@@ -322,40 +341,31 @@ static void __i915_request_set_priority(struct i915_request *rq, int prio)
* end result is a topological list of requests in reverse order, the
* last element in the list is the request we must execute first.
*/
- list_for_each_entry(rq, &dfs, sched.dfs) {
- struct i915_dependency *p;
-
- /* Also release any children on this engine that are ready */
- GEM_BUG_ON(rq->engine != engine);
-
- for_each_signaler(p, rq) {
+ rq->sched.dfs.next = NULL;
+ do {
+ list_for_each_continue(pos, &rq->sched.signalers_list) {
+ struct i915_dependency *p =
+ list_entry(pos, typeof(*p), signal_link);
struct i915_request *s =
container_of(p->signaler, typeof(*s), sched);
- GEM_BUG_ON(s == rq);
-
if (rq_prio(s) >= prio)
continue;
if (__i915_request_is_complete(s))
continue;
- if (s->engine != rq->engine) {
+ if (s->engine != engine) {
ipi_priority(s, prio);
continue;
}
- list_move_tail(&s->sched.dfs, &dfs);
+ /* Remember our position along this branch */
+ rq = stack_push(s, rq, pos);
+ pos = &rq->sched.signalers_list;
}
- }
- plist = i915_sched_lookup_priolist(engine, prio);
-
- /* Fifo and depth-first replacement ensure our deps execute first */
- list_for_each_entry_safe_reverse(rq, rn, &dfs, sched.dfs) {
- GEM_BUG_ON(rq->engine != engine);
-
- INIT_LIST_HEAD(&rq->sched.dfs);
+ RQ_TRACE(rq, "set-priority:%d\n", prio);
WRITE_ONCE(rq->sched.attr.priority, prio);
/*
@@ -369,12 +379,13 @@ static void __i915_request_set_priority(struct i915_request *rq, int prio)
if (!i915_request_is_ready(rq))
continue;
+ GEM_BUG_ON(rq->engine != engine);
if (i915_request_in_priority_queue(rq))
list_move_tail(&rq->sched.link, plist);
/* Defer (tasklet) submission until after all updates. */
kick_submission(engine, rq, prio);
- }
+ } while ((rq = stack_pop(rq, &pos)));
}
void i915_request_set_priority(struct i915_request *rq, int prio)
@@ -444,7 +455,6 @@ void i915_sched_node_init(struct i915_sched_node *node)
INIT_LIST_HEAD(&node->signalers_list);
INIT_LIST_HEAD(&node->waiters_list);
INIT_LIST_HEAD(&node->link);
- INIT_LIST_HEAD(&node->dfs);
node->ipi_link = NULL;
--
2.20.1
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^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 10/10] drm/i915: Improve DFS for priority inheritance
2021-01-20 12:22 ` [Intel-gfx] [PATCH 10/10] drm/i915: Improve DFS for priority inheritance Chris Wilson
@ 2021-01-26 17:34 ` Andi Shyti
2021-01-26 21:20 ` Chris Wilson
0 siblings, 1 reply; 27+ messages in thread
From: Andi Shyti @ 2021-01-26 17:34 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
Hi Chris,
On Wed, Jan 20, 2021 at 12:22:05PM +0000, Chris Wilson wrote:
> The core of the scheduling algorithm is that we compute the topological
> order of the fence DAG. Knowing that we have a DAG, we should be able to
> use a DFS to compute the topological sort in linear time. However,
> during the conversion of the recursive algorithm into an iterative one,
> the memoization of how far we had progressed down a branch was
memoization?
> forgotten. The result was that instead of running in linear time, it was
> running in geometric time and could easily run for a few hundred
> milliseconds given a wide enough graph, not the microseconds as required.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
I have seen this patch long time ago... I'm r-b'eing starting
from the last patch :)
Reviewed-by: Andi Shyti <andi.shyti@intel.com>
Andi
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^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 10/10] drm/i915: Improve DFS for priority inheritance
2021-01-26 17:34 ` Andi Shyti
@ 2021-01-26 21:20 ` Chris Wilson
0 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2021-01-26 21:20 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
Quoting Andi Shyti (2021-01-26 17:34:48)
> Hi Chris,
>
> On Wed, Jan 20, 2021 at 12:22:05PM +0000, Chris Wilson wrote:
> > The core of the scheduling algorithm is that we compute the topological
> > order of the fence DAG. Knowing that we have a DAG, we should be able to
> > use a DFS to compute the topological sort in linear time. However,
> > during the conversion of the recursive algorithm into an iterative one,
> > the memoization of how far we had progressed down a branch was
>
> memoization?
I too believe it was originally misspelt ;) But that's the accepted term
for this technique of storing partial results in dynamic programming.
(The field is full of self-glorified terms.)
https://en.wikipedia.org/wiki/Memoization
-Chris
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/10] drm/i915/gt: Do not suspend bonded requests if one hangs
2021-01-20 12:21 [Intel-gfx] [PATCH 01/10] drm/i915/gt: Do not suspend bonded requests if one hangs Chris Wilson
` (8 preceding siblings ...)
2021-01-20 12:22 ` [Intel-gfx] [PATCH 10/10] drm/i915: Improve DFS for priority inheritance Chris Wilson
@ 2021-01-20 19:22 ` Patchwork
2021-01-20 19:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
13 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2021-01-20 19:22 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/10] drm/i915/gt: Do not suspend bonded requests if one hangs
URL : https://patchwork.freedesktop.org/series/86088/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ed0915405628 drm/i915/gt: Do not suspend bonded requests if one hangs
89f5522aeb8f drm/i915/gt: Skip over completed active execlists, again
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#10:
Referenecs: 35f3fd8182ba ("drm/i915/execlists: Workaround switching back to a completed context")
-:10: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 35f3fd8182ba ("drm/i915/execlists: Workaround switching back to a completed context")'
#10:
Referenecs: 35f3fd8182ba ("drm/i915/execlists: Workaround switching back to a completed context")
-:11: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 8ab3a3812aa9 ("drm/i915/gt: Incrementally check for rewinding")'
#11:
References: 8ab3a3812aa9 ("drm/i915/gt: Incrementally check for rewinding")
total: 2 errors, 1 warnings, 0 checks, 72 lines checked
7e2e3df4ad78 drm/i915: Strip out internal priorities
ab6bc4b70663 drm/i915: Remove I915_USER_PRIORITY_SHIFT
d02f5b7f8431 drm/i915: Replace engine->schedule() with a known request operation
af4debc42274 drm/i915: Teach the i915_dependency to use a double-lock
a440718dfe78 drm/i915: Restructure priority inheritance
d1f21b1a4125 drm/i915/selftests: Measure set-priority duration
-:52: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#52:
new file mode 100644
-:434: WARNING:LINE_SPACING: Missing a blank line after declarations
#434: FILE: drivers/gpu/drm/i915/selftests/i915_scheduler.c:378:
+ struct igt_spinner spin;
+ I915_RND_STATE(prng);
total: 0 errors, 2 warnings, 0 checks, 702 lines checked
242ea7da8ef4 drm/i915/selftests: Exercise priority inheritance around an engine loop
9bf36381a2f6 drm/i915: Improve DFS for priority inheritance
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/10] drm/i915/gt: Do not suspend bonded requests if one hangs
2021-01-20 12:21 [Intel-gfx] [PATCH 01/10] drm/i915/gt: Do not suspend bonded requests if one hangs Chris Wilson
` (9 preceding siblings ...)
2021-01-20 19:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/10] drm/i915/gt: Do not suspend bonded requests if one hangs Patchwork
@ 2021-01-20 19:23 ` Patchwork
2021-01-20 19:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2021-01-20 19:23 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/10] drm/i915/gt: Do not suspend bonded requests if one hangs
URL : https://patchwork.freedesktop.org/series/86088/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1328:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/selftests/i915_syncmap.c:80:54: warning: dubious: x | !y
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/gt: Do not suspend bonded requests if one hangs
2021-01-20 12:21 [Intel-gfx] [PATCH 01/10] drm/i915/gt: Do not suspend bonded requests if one hangs Chris Wilson
` (10 preceding siblings ...)
2021-01-20 19:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-01-20 19:51 ` Patchwork
2021-01-20 23:04 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-01-21 15:19 ` [Intel-gfx] [PATCH 01/10] " Andi Shyti
13 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2021-01-20 19:51 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 5348 bytes --]
== Series Details ==
Series: series starting with [01/10] drm/i915/gt: Do not suspend bonded requests if one hangs
URL : https://patchwork.freedesktop.org/series/86088/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9650 -> Patchwork_19427
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/index.html
New tests
---------
New tests have been introduced between CI_DRM_9650 and Patchwork_19427:
### New IGT tests (1) ###
* igt@i915_selftest@live@scheduler:
- Statuses : 32 pass(s)
- Exec time: [0.56, 7.42] s
Known issues
------------
Here are the changes found in Patchwork_19427 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-snb-2520m: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/fi-snb-2520m/igt@amdgpu/amd_prime@i915-to-amd.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600: NOTRUN -> [SKIP][2] ([fdo#109271]) +30 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/fi-snb-2600/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/fi-snb-2600/igt@kms_chamelium@hdmi-crc-fast.html
* igt@prime_self_import@basic-with_one_bo:
- fi-tgl-y: [PASS][4] -> [DMESG-WARN][5] ([i915#402]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@prime_self_import@basic-with_one_bo.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/fi-tgl-y/igt@prime_self_import@basic-with_one_bo.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][6] ([i915#1602] / [i915#2029] / [i915#2369])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/fi-bdw-5557u/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-snb-2600: [DMESG-WARN][7] ([i915#2772]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2600/igt@gem_exec_suspend@basic-s3.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/fi-snb-2600/igt@gem_exec_suspend@basic-s3.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2520m: [INCOMPLETE][9] -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2520m/igt@i915_selftest@live@hangcheck.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/fi-snb-2520m/igt@i915_selftest@live@hangcheck.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2772]: https://gitlab.freedesktop.org/drm/intel/issues/2772
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 38)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9650 -> Patchwork_19427
CI-20190529: 20190529
CI_DRM_9650: 3f989d1bb4cfd91e25549f9fd7a750412581dcc4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5960: ace82fcd5f3623f8dde7c220a825873dc53dfae4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19427: 9bf36381a2f6b8f0a1ed4b4955b3a6970d2d94bc @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9bf36381a2f6 drm/i915: Improve DFS for priority inheritance
242ea7da8ef4 drm/i915/selftests: Exercise priority inheritance around an engine loop
d1f21b1a4125 drm/i915/selftests: Measure set-priority duration
a440718dfe78 drm/i915: Restructure priority inheritance
af4debc42274 drm/i915: Teach the i915_dependency to use a double-lock
d02f5b7f8431 drm/i915: Replace engine->schedule() with a known request operation
ab6bc4b70663 drm/i915: Remove I915_USER_PRIORITY_SHIFT
7e2e3df4ad78 drm/i915: Strip out internal priorities
89f5522aeb8f drm/i915/gt: Skip over completed active execlists, again
ed0915405628 drm/i915/gt: Do not suspend bonded requests if one hangs
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/index.html
[-- Attachment #1.2: Type: text/html, Size: 6303 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [01/10] drm/i915/gt: Do not suspend bonded requests if one hangs
2021-01-20 12:21 [Intel-gfx] [PATCH 01/10] drm/i915/gt: Do not suspend bonded requests if one hangs Chris Wilson
` (11 preceding siblings ...)
2021-01-20 19:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-01-20 23:04 ` Patchwork
2021-01-21 15:19 ` [Intel-gfx] [PATCH 01/10] " Andi Shyti
13 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2021-01-20 23:04 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 24693 bytes --]
== Series Details ==
Series: series starting with [01/10] drm/i915/gt: Do not suspend bonded requests if one hangs
URL : https://patchwork.freedesktop.org/series/86088/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9650_full -> Patchwork_19427_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
New tests
---------
New tests have been introduced between CI_DRM_9650_full and Patchwork_19427_full:
### New IGT tests (2) ###
* igt@i915_selftest@live@scheduler:
- Statuses : 8 pass(s)
- Exec time: [0.47, 6.58] s
* igt@i915_selftest@perf@scheduler:
- Statuses : 8 pass(s)
- Exec time: [0.62, 10.95] s
Known issues
------------
Here are the changes found in Patchwork_19427_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@legacy-engines-hostile-preempt:
- shard-hsw: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-hsw4/igt@gem_ctx_persistence@legacy-engines-hostile-preempt.html
* igt@gem_exec_capture@pi@rcs0:
- shard-skl: [PASS][2] -> [INCOMPLETE][3] ([i915#2369])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl3/igt@gem_exec_capture@pi@rcs0.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl5/igt@gem_exec_capture@pi@rcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][4] ([i915#2842])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-iclb4/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-kbl: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl4/igt@gem_exec_fair@basic-none@vecs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-kbl4/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [PASS][7] -> [SKIP][8] ([fdo#109271]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs1.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb8/igt@gem_exec_fair@basic-pace@vecs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-tglb7/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][11] ([i915#2389]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-iclb4/igt@gem_exec_reloc@basic-wide-active@vcs1.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-apl: [PASS][12] -> [DMESG-WARN][13] ([i915#1610])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-apl2/igt@gem_exec_schedule@u-fairslice@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-apl8/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-skl: [PASS][14] -> [FAIL][15] ([i915#644])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl5/igt@gem_ppgtt@flink-and-close-vma-leak.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl2/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gen3_mixed_blits:
- shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271]) +29 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-kbl3/igt@gen3_mixed_blits.html
* igt@gen9_exec_parse@allowed-all:
- shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1436] / [i915#716])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl6/igt@gen9_exec_parse@allowed-all.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl10/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#658])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-kbl3/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_selftest@live@hangcheck:
- shard-hsw: NOTRUN -> [INCOMPLETE][20] ([i915#2782])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-hsw2/igt@i915_selftest@live@hangcheck.html
* igt@kms_async_flips@test-time-stamp:
- shard-tglb: [PASS][21] -> [FAIL][22] ([i915#2574])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb2/igt@kms_async_flips@test-time-stamp.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-tglb2/igt@kms_async_flips@test-time-stamp.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180:
- shard-skl: NOTRUN -> [SKIP][23] ([fdo#109271] / [fdo#111304])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl7/igt@kms_ccs@pipe-c-crc-primary-rotation-180.html
* igt@kms_chamelium@hdmi-hpd-with-enabled-mode:
- shard-kbl: NOTRUN -> [SKIP][24] ([fdo#109271] / [fdo#111827]) +3 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-kbl3/igt@kms_chamelium@hdmi-hpd-with-enabled-mode.html
* igt@kms_chamelium@vga-frame-dump:
- shard-snb: NOTRUN -> [SKIP][25] ([fdo#109271] / [fdo#111827])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-snb6/igt@kms_chamelium@vga-frame-dump.html
* igt@kms_color@pipe-a-ctm-0-75:
- shard-skl: [PASS][26] -> [DMESG-WARN][27] ([i915#1982]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl5/igt@kms_color@pipe-a-ctm-0-75.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl6/igt@kms_color@pipe-a-ctm-0-75.html
* igt@kms_color_chamelium@pipe-a-ctm-green-to-red:
- shard-glk: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) +2 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-glk3/igt@kms_color_chamelium@pipe-a-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-c-ctm-limited-range:
- shard-hsw: NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +8 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-hsw4/igt@kms_color_chamelium@pipe-c-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-d-ctm-green-to-red:
- shard-skl: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +5 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl3/igt@kms_color_chamelium@pipe-d-ctm-green-to-red.html
* igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen:
- shard-skl: NOTRUN -> [FAIL][31] ([i915#54])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-128x128-random:
- shard-skl: [PASS][32] -> [FAIL][33] ([i915#54]) +7 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl6/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html
* igt@kms_cursor_edge_walk@pipe-b-128x128-left-edge:
- shard-snb: [PASS][34] -> [SKIP][35] ([fdo#109271])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-snb6/igt@kms_cursor_edge_walk@pipe-b-128x128-left-edge.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-snb7/igt@kms_cursor_edge_walk@pipe-b-128x128-left-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-skl: NOTRUN -> [FAIL][36] ([i915#2346])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@ac-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][37] -> [FAIL][38] ([i915#2122])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-glk1/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ac-hdmi-a1-hdmi-a2.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-glk6/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip@bo-too-big@a-hdmi-a1:
- shard-glk: [PASS][39] -> [DMESG-WARN][40] ([i915#118] / [i915#95])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-glk8/igt@kms_flip@bo-too-big@a-hdmi-a1.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-glk5/igt@kms_flip@bo-too-big@a-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-tglb: [PASS][41] -> [FAIL][42] ([i915#2598])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-tglb6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-skl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#2672])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-skl: NOTRUN -> [SKIP][44] ([fdo#109271]) +57 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt:
- shard-glk: NOTRUN -> [SKIP][45] ([fdo#109271]) +11 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-glk3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-skl: NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#533])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl2/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- shard-glk: [PASS][47] -> [FAIL][48] ([i915#53])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-glk8/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-glk5/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-skl: [PASS][49] -> [INCOMPLETE][50] ([i915#198])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl8/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: NOTRUN -> [FAIL][51] ([fdo#108145] / [i915#265]) +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_scaling@scaler-with-rotation:
- shard-snb: NOTRUN -> [SKIP][52] ([fdo#109271])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-snb7/igt@kms_plane_scaling@scaler-with-rotation.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
- shard-skl: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#658])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
* igt@kms_psr@primary_page_flip:
- shard-hsw: NOTRUN -> [SKIP][54] ([fdo#109271]) +111 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-hsw4/igt@kms_psr@primary_page_flip.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-kbl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#533])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-kbl3/igt@kms_vblank@pipe-d-wait-idle.html
* igt@sysfs_heartbeat_interval@mixed@rcs0:
- shard-skl: [PASS][56] -> [FAIL][57] ([i915#1731]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl9/igt@sysfs_heartbeat_interval@mixed@rcs0.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl10/igt@sysfs_heartbeat_interval@mixed@rcs0.html
#### Possible fixes ####
* igt@drm_import_export@prime:
- shard-kbl: [INCOMPLETE][58] -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl7/igt@drm_import_export@prime.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-kbl3/igt@drm_import_export@prime.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [FAIL][60] ([i915#2842]) -> [PASS][61] +2 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb8/igt@gem_exec_fair@basic-pace@bcs0.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-tglb7/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [FAIL][62] ([i915#2842]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl6/igt@gem_exec_fair@basic-pace@vecs0.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-glk: [DMESG-WARN][64] ([i915#1610]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-glk9/igt@gem_exec_schedule@u-fairslice@rcs0.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-glk3/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy@gtt:
- shard-hsw: [INCOMPLETE][66] -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-hsw8/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy@gtt.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-hsw6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy@gtt.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [DMESG-WARN][68] ([i915#1436] / [i915#1982] / [i915#716]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl4/igt@gen9_exec_parse@allowed-single.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl7/igt@gen9_exec_parse@allowed-single.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-snb: [INCOMPLETE][70] ([i915#2880]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-snb7/igt@i915_module_load@reload-with-fault-injection.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-snb6/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][72] ([i915#454]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-iclb1/igt@i915_pm_dc@dc6-psr.html
* igt@i915_suspend@sysfs-reader:
- shard-skl: [INCOMPLETE][74] ([i915#146] / [i915#198]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl2/igt@i915_suspend@sysfs-reader.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl3/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding:
- shard-skl: [FAIL][76] ([i915#54]) -> [PASS][77] +6 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-skl: [FAIL][78] ([i915#2346]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [FAIL][80] ([i915#2346] / [i915#533]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-tglb: [FAIL][82] ([i915#2346]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb6/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-tglb2/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [FAIL][84] ([i915#79]) -> [PASS][85] +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@plain-flip-fb-recreate@c-edp1:
- shard-skl: [FAIL][86] ([i915#2122]) -> [PASS][87] +2 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl10/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl1/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu:
- shard-skl: [DMESG-WARN][88] ([i915#1982]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [SKIP][90] ([fdo#109441]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-iclb7/igt@kms_psr@psr2_basic.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-iclb2/igt@kms_psr@psr2_basic.html
#### Warnings ####
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5:
- shard-iclb: [SKIP][92] ([i915#658]) -> [SKIP][93] ([i915#2920])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-iclb7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-iclb: [SKIP][94] ([i915#2920]) -> [SKIP][95] ([i915#658]) +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-iclb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][96], [FAIL][97]) ([i915#2295] / [i915#2505] / [i915#2722]) -> [FAIL][98] ([i915#2295])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl6/igt@runner@aborted.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl7/igt@runner@aborted.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-kbl7/igt@runner@aborted.html
- shard-apl: [FAIL][99] ([i915#2295]) -> ([FAIL][100], [FAIL][101]) ([i915#1610] / [i915#2295] / [i915#2426])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-apl2/igt@runner@aborted.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-apl1/igt@runner@aborted.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-apl8/igt@runner@aborted.html
- shard-glk: ([FAIL][102], [FAIL][103]) ([i915#2295] / [i915#2426] / [k.org#202321]) -> [FAIL][104] ([i915#2295] / [k.org#202321])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-glk4/igt@runner@aborted.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-glk9/igt@runner@aborted.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-glk4/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111304]: https://bugs.freedesktop.org/show_bug.cgi?id=111304
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#2574]: https://gitlab.freedesktop.org/drm/intel/issues/2574
[i915#2598]: https://gitlab.freedesktop.org/drm/intel/issues/2598
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2880]: https://gitlab.freedesktop.org/drm/intel/issues/2880
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9650 -> Patchwork_19427
CI-20190529: 20190529
CI_DRM_9650: 3f989d1bb4cfd91e25549f9fd7a750412581dcc4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5960: ace82fcd5f3623f8dde7c220a825873dc53dfae4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19427: 9bf36381a2f6b8f0a1ed4b4955b3a6970d2d94bc @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/index.html
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^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 01/10] drm/i915/gt: Do not suspend bonded requests if one hangs
2021-01-20 12:21 [Intel-gfx] [PATCH 01/10] drm/i915/gt: Do not suspend bonded requests if one hangs Chris Wilson
` (12 preceding siblings ...)
2021-01-20 23:04 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2021-01-21 15:19 ` Andi Shyti
13 siblings, 0 replies; 27+ messages in thread
From: Andi Shyti @ 2021-01-21 15:19 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
Hi Chris,
On Wed, Jan 20, 2021 at 12:21:56PM +0000, Chris Wilson wrote:
> Treat the dependency between bonded requests as weak and leave the
> remainder of the pair on the GPU if one hangs.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Andi Shyti <andi.shyti@intel.com>
Thanks,
Andi
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^ permalink raw reply [flat|nested] 27+ messages in thread