From: Daniel Vetter <daniel@ffwll.ch>
To: Matthew Brost <matthew.brost@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
daniel.vetter@ffwll.ch
Subject: Re: [Intel-gfx] [PATCH 17/22] drm/i915/guc: Move guc_blocked fence to struct guc_state
Date: Tue, 17 Aug 2021 12:10:25 +0200 [thread overview]
Message-ID: <YRuLEUQ27bNMbBsT@phenom.ffwll.local> (raw)
In-Reply-To: <20210816135139.10060-18-matthew.brost@intel.com>
On Mon, Aug 16, 2021 at 06:51:34AM -0700, Matthew Brost wrote:
> Move guc_blocked fence to struct guc_state as the lock which protects
> the fence lives there.
>
> s/ce->guc_blocked/ce->guc_state.blocked_fence/g
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
General comment, but latest when your combine your count state with a wait
queue you're very far into "reinventing a mutex/semaphore, badly" land.
I think we really need to look into why we can't just protect this all
with a mutex and make sure the awkward transition states are never visible
to anyone else.
-Daniel
> ---
> drivers/gpu/drm/i915/gt/intel_context.c | 5 +++--
> drivers/gpu/drm/i915/gt/intel_context_types.h | 5 ++---
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +++++++++---------
> 3 files changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
> index 745e84c72c90..0e48939ec85f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context.c
> +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> @@ -405,8 +405,9 @@ intel_context_init(struct intel_context *ce, struct intel_engine_cs *engine)
> * Initialize fence to be complete as this is expected to be complete
> * unless there is a pending schedule disable outstanding.
> */
> - i915_sw_fence_init(&ce->guc_blocked, sw_fence_dummy_notify);
> - i915_sw_fence_commit(&ce->guc_blocked);
> + i915_sw_fence_init(&ce->guc_state.blocked_fence,
> + sw_fence_dummy_notify);
> + i915_sw_fence_commit(&ce->guc_state.blocked_fence);
>
> i915_active_init(&ce->active,
> __intel_context_active, __intel_context_retire, 0);
> diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h
> index 3a73f3117873..c06171ee8792 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> @@ -167,6 +167,8 @@ struct intel_context {
> * fence related to GuC submission
> */
> struct list_head fences;
> + /* GuC context blocked fence */
> + struct i915_sw_fence blocked_fence;
> } guc_state;
>
> struct {
> @@ -190,9 +192,6 @@ struct intel_context {
> */
> struct list_head guc_id_link;
>
> - /* GuC context blocked fence */
> - struct i915_sw_fence guc_blocked;
> -
> /*
> * GuC priority management
> */
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 9ae4633aa7cb..7aa16371908a 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1482,24 +1482,24 @@ static void guc_blocked_fence_complete(struct intel_context *ce)
> {
> lockdep_assert_held(&ce->guc_state.lock);
>
> - if (!i915_sw_fence_done(&ce->guc_blocked))
> - i915_sw_fence_complete(&ce->guc_blocked);
> + if (!i915_sw_fence_done(&ce->guc_state.blocked_fence))
> + i915_sw_fence_complete(&ce->guc_state.blocked_fence);
> }
>
> static void guc_blocked_fence_reinit(struct intel_context *ce)
> {
> lockdep_assert_held(&ce->guc_state.lock);
> - GEM_BUG_ON(!i915_sw_fence_done(&ce->guc_blocked));
> + GEM_BUG_ON(!i915_sw_fence_done(&ce->guc_state.blocked_fence));
>
> /*
> * This fence is always complete unless a pending schedule disable is
> * outstanding. We arm the fence here and complete it when we receive
> * the pending schedule disable complete message.
> */
> - i915_sw_fence_fini(&ce->guc_blocked);
> - i915_sw_fence_reinit(&ce->guc_blocked);
> - i915_sw_fence_await(&ce->guc_blocked);
> - i915_sw_fence_commit(&ce->guc_blocked);
> + i915_sw_fence_fini(&ce->guc_state.blocked_fence);
> + i915_sw_fence_reinit(&ce->guc_state.blocked_fence);
> + i915_sw_fence_await(&ce->guc_state.blocked_fence);
> + i915_sw_fence_commit(&ce->guc_state.blocked_fence);
> }
>
> static u16 prep_context_pending_disable(struct intel_context *ce)
> @@ -1539,7 +1539,7 @@ static struct i915_sw_fence *guc_context_block(struct intel_context *ce)
> if (enabled)
> clr_context_enabled(ce);
> spin_unlock_irqrestore(&ce->guc_state.lock, flags);
> - return &ce->guc_blocked;
> + return &ce->guc_state.blocked_fence;
> }
>
> /*
> @@ -1555,7 +1555,7 @@ static struct i915_sw_fence *guc_context_block(struct intel_context *ce)
> with_intel_runtime_pm(runtime_pm, wakeref)
> __guc_context_sched_disable(guc, ce, guc_id);
>
> - return &ce->guc_blocked;
> + return &ce->guc_state.blocked_fence;
> }
>
> static void guc_context_unblock(struct intel_context *ce)
> --
> 2.32.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
next prev parent reply other threads:[~2021-08-17 10:10 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-16 13:51 [Intel-gfx] [PATCH 00/22] Clean up GuC CI failures, simplify locking, and kernel DOC Matthew Brost
2021-08-16 13:51 ` [Intel-gfx] [PATCH 01/22] drm/i915/guc: Fix blocked context accounting Matthew Brost
2021-08-16 13:51 ` [Intel-gfx] [PATCH 02/22] drm/i915/guc: Fix outstanding G2H accounting Matthew Brost
2021-08-17 9:39 ` Daniel Vetter
2021-08-17 18:17 ` Matthew Brost
2021-08-16 13:51 ` [Intel-gfx] [PATCH 03/22] drm/i915/guc: Unwind context requests in reverse order Matthew Brost
2021-08-16 13:51 ` [Intel-gfx] [PATCH 04/22] drm/i915/guc: Don't drop ce->guc_active.lock when unwinding context Matthew Brost
2021-08-16 13:51 ` [Intel-gfx] [PATCH 05/22] drm/i915/guc: Workaround reset G2H is received after schedule done G2H Matthew Brost
2021-08-17 9:32 ` Daniel Vetter
2021-08-17 15:03 ` Matthew Brost
2021-08-16 13:51 ` [Intel-gfx] [PATCH 06/22] drm/i915/execlists: Do not propagate errors to dependent fences Matthew Brost
2021-08-17 9:21 ` Daniel Vetter
2021-08-17 15:08 ` Matthew Brost
2021-08-17 15:49 ` Daniel Vetter
2021-08-16 13:51 ` [Intel-gfx] [PATCH 07/22] drm/i915/selftests: Add a cancel request selftest that triggers a reset Matthew Brost
2021-08-16 13:51 ` [Intel-gfx] [PATCH 08/22] drm/i915/guc: Don't enable scheduling on a banned context, guc_id invalid, not registered Matthew Brost
2021-08-17 9:47 ` Daniel Vetter
2021-08-17 9:57 ` Daniel Vetter
2021-08-17 16:44 ` Matthew Brost
2021-08-16 13:51 ` [Intel-gfx] [PATCH 09/22] drm/i915/selftests: Fix memory corruption in live_lrc_isolation Matthew Brost
2021-08-16 13:51 ` [Intel-gfx] [PATCH 10/22] drm/i915/selftests: Add initial GuC selftest for scrubbing lost G2H Matthew Brost
2021-08-16 13:51 ` [Intel-gfx] [PATCH 11/22] drm/i915/guc: Take context ref when cancelling request Matthew Brost
2021-08-16 13:51 ` [Intel-gfx] [PATCH 12/22] drm/i915/guc: Don't touch guc_state.sched_state without a lock Matthew Brost
2021-08-17 7:21 ` kernel test robot
2021-08-16 13:51 ` [Intel-gfx] [PATCH 13/22] drm/i915/guc: Reset LRC descriptor if register returns -ENODEV Matthew Brost
2021-08-16 13:51 ` [Intel-gfx] [PATCH 14/22] drm/i915: Allocate error capture in atomic context Matthew Brost
2021-08-17 10:06 ` Daniel Vetter
2021-08-17 16:12 ` Matthew Brost
2021-08-16 13:51 ` [Intel-gfx] [PATCH 15/22] drm/i915/guc: Flush G2H work queue during reset Matthew Brost
2021-08-17 10:06 ` Daniel Vetter
2021-08-16 13:51 ` [Intel-gfx] [PATCH 16/22] drm/i915/guc: Release submit fence from an IRQ Matthew Brost
2021-08-17 10:08 ` Daniel Vetter
2021-08-16 13:51 ` [Intel-gfx] [PATCH 17/22] drm/i915/guc: Move guc_blocked fence to struct guc_state Matthew Brost
2021-08-17 10:10 ` Daniel Vetter [this message]
2021-08-16 13:51 ` [Intel-gfx] [PATCH 18/22] drm/i915/guc: Rework and simplify locking Matthew Brost
2021-08-17 10:15 ` Daniel Vetter
2021-08-17 15:30 ` Matthew Brost
2021-08-16 13:51 ` [Intel-gfx] [PATCH 19/22] drm/i915/guc: Proper xarray usage for contexts_lookup Matthew Brost
2021-08-17 10:27 ` Daniel Vetter
2021-08-17 15:26 ` Matthew Brost
2021-08-17 17:13 ` Daniel Vetter
2021-08-17 17:13 ` Matthew Brost
2021-08-16 13:51 ` [Intel-gfx] [PATCH 20/22] drm/i915/guc: Drop pin count check trick between sched_disable and re-pin Matthew Brost
2021-08-16 13:51 ` [Intel-gfx] [PATCH 21/22] drm/i915/guc: Move GuC priority fields in context under guc_active Matthew Brost
2021-08-16 13:51 ` [Intel-gfx] [PATCH 22/22] drm/i915/guc: Add GuC kernel doc Matthew Brost
2021-08-17 11:11 ` Daniel Vetter
2021-08-17 16:36 ` Matthew Brost
2021-08-17 17:20 ` Daniel Vetter
2021-08-17 17:27 ` Michal Wajdeczko
2021-08-17 17:34 ` Daniel Vetter
2021-08-17 20:41 ` Michal Wajdeczko
2021-08-17 21:49 ` Daniel Vetter
2021-08-17 12:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Clean up GuC CI failures, simplify locking, and kernel DOC (rev2) Patchwork
2021-08-17 12:51 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-17 13:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-08-17 14:39 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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