* [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select
@ 2023-12-01 13:41 Jani Nikula
2023-12-01 14:41 ` Ville Syrjälä
` (2 more replies)
0 siblings, 3 replies; 12+ messages in thread
From: Jani Nikula @ 2023-12-01 13:41 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
The eDP 1.5 spec adds a clarification for eDP 1.4x:
> For eDP v1.4x, if the Source device chooses the Main-Link rate by way
> of DPCD 00100h, the Sink device shall ignore DPCD 00115h[2:0].
We write 0 to DP_LINK_BW_SET (DPCD 100h) even when using
DP_LINK_RATE_SET (DPCD 114h). Stop doing that, as it can cause the panel
to ignore the rate set method.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9081
Tested-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../drm/i915/display/intel_dp_link_training.c | 23 +++++++++++--------
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index dbc1b66c8ee4..6336a39030a4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -650,19 +650,22 @@ intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
u8 link_bw, u8 rate_select)
{
- u8 link_config[2];
+ u8 lane_count = crtc_state->lane_count;
- /* Write the link configuration data */
- link_config[0] = link_bw;
- link_config[1] = crtc_state->lane_count;
if (crtc_state->enhanced_framing)
- link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
- drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
+ lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+
+ if (link_bw) {
+ /* eDP 1.3 and earlier link bw set method. */
+ u8 link_config[] = { link_bw, lane_count };
- /* eDP 1.4 rate select method. */
- if (!link_bw)
- drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
- &rate_select, 1);
+ drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config,
+ ARRAY_SIZE(link_config));
+ } else {
+ /* eDP 1.4 rate select method. */
+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count);
+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET, rate_select);
+ }
}
/*
--
2.39.2
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select
2023-12-01 13:41 [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select Jani Nikula
@ 2023-12-01 14:41 ` Ville Syrjälä
2023-12-04 9:57 ` Jani Nikula
2023-12-01 23:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2023-12-03 4:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2 siblings, 1 reply; 12+ messages in thread
From: Ville Syrjälä @ 2023-12-01 14:41 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Fri, Dec 01, 2023 at 03:41:41PM +0200, Jani Nikula wrote:
> The eDP 1.5 spec adds a clarification for eDP 1.4x:
>
> > For eDP v1.4x, if the Source device chooses the Main-Link rate by way
> > of DPCD 00100h, the Sink device shall ignore DPCD 00115h[2:0].
>
> We write 0 to DP_LINK_BW_SET (DPCD 100h) even when using
> DP_LINK_RATE_SET (DPCD 114h). Stop doing that, as it can cause the panel
> to ignore the rate set method.
What a terrible way to specify this :( This means the device must
hav some internal state to keep track of whethe BW_SET was ever
written.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9081
> Tested-by: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../drm/i915/display/intel_dp_link_training.c | 23 +++++++++++--------
> 1 file changed, 13 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index dbc1b66c8ee4..6336a39030a4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -650,19 +650,22 @@ intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state,
> u8 link_bw, u8 rate_select)
> {
> - u8 link_config[2];
> + u8 lane_count = crtc_state->lane_count;
>
> - /* Write the link configuration data */
> - link_config[0] = link_bw;
> - link_config[1] = crtc_state->lane_count;
> if (crtc_state->enhanced_framing)
> - link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
> + lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> +
> + if (link_bw) {
> + /* eDP 1.3 and earlier link bw set method. */
> + u8 link_config[] = { link_bw, lane_count };
>
> - /* eDP 1.4 rate select method. */
> - if (!link_bw)
> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> - &rate_select, 1);
> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config,
> + ARRAY_SIZE(link_config));
> + } else {
> + /* eDP 1.4 rate select method. */
> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count);
> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET, rate_select);
Doesn't look there's anything in the spec that specifies when the device
is supposed to reset its internal state to stop ignoring DP_LINK_RATE_SET.
Do we know when this panel does it? When VDD is removed?
> + }
> }
>
> /*
> --
> 2.39.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select
2023-12-01 13:41 [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select Jani Nikula
2023-12-01 14:41 ` Ville Syrjälä
@ 2023-12-01 23:53 ` Patchwork
2023-12-03 4:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2023-12-01 23:53 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 13114 bytes --]
== Series Details ==
Series: drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select
URL : https://patchwork.freedesktop.org/series/127194/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13961 -> Patchwork_127194v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/index.html
Participating hosts (36 -> 35)
------------------------------
Additional (2): bat-dg2-8 bat-dg1-5
Missing (3): bat-mtlp-8 fi-snb-2520m fi-pnv-d510
Known issues
------------
Here are the changes found in Patchwork_127194v1 that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- fi-bsw-n3050: [PASS][1] -> [FAIL][2] ([i915#8293])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/fi-bsw-n3050/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/fi-bsw-n3050/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s0@smem:
- bat-jsl-1: NOTRUN -> [INCOMPLETE][3] ([i915#9275])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-jsl-1/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_lmem_swapping@verify-random:
- bat-jsl-1: NOTRUN -> [SKIP][4] ([i915#4613]) +2 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-jsl-1/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap@basic:
- bat-dg1-5: NOTRUN -> [SKIP][5] ([i915#4083])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg1-5/igt@gem_mmap@basic.html
- bat-dg2-8: NOTRUN -> [SKIP][6] ([i915#4083])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg2-8/igt@gem_mmap@basic.html
* igt@gem_mmap_gtt@basic:
- bat-dg2-8: NOTRUN -> [SKIP][7] ([i915#4077]) +2 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg2-8/igt@gem_mmap_gtt@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg1-5: NOTRUN -> [SKIP][8] ([i915#4077]) +2 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg1-5/igt@gem_tiled_fence_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg1-5: NOTRUN -> [SKIP][9] ([i915#4079]) +1 other test skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg1-5/igt@gem_tiled_pread_basic.html
- bat-dg2-8: NOTRUN -> [SKIP][10] ([i915#4079]) +1 other test skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg2-8/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-5: NOTRUN -> [SKIP][11] ([i915#6621])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg1-5/igt@i915_pm_rps@basic-api.html
- bat-dg2-8: NOTRUN -> [SKIP][12] ([i915#6621])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg2-8/igt@i915_pm_rps@basic-api.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-dg2-8: NOTRUN -> [SKIP][13] ([i915#6645])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg2-8/igt@i915_suspend@basic-s3-without-i915.html
- bat-jsl-1: NOTRUN -> [FAIL][14] ([fdo#103375])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-jsl-1/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-8: NOTRUN -> [SKIP][15] ([i915#5190])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg2-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- bat-dg1-5: NOTRUN -> [SKIP][16] ([i915#4212]) +7 other tests skip
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg1-5/igt@kms_addfb_basic@basic-x-tiled-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-8: NOTRUN -> [SKIP][17] ([i915#4215] / [i915#5190])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg2-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
- bat-dg1-5: NOTRUN -> [SKIP][18] ([i915#4215])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg1-5/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-8: NOTRUN -> [SKIP][19] ([i915#4212]) +6 other tests skip
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg2-8/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-8: NOTRUN -> [SKIP][20] ([i915#4212] / [i915#5608])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg2-8/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-8: NOTRUN -> [SKIP][21] ([i915#4103] / [i915#4213] / [i915#5608]) +1 other test skip
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg2-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-dg1-5: NOTRUN -> [SKIP][22] ([i915#4103] / [i915#4213]) +1 other test skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg1-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-dg1-5: NOTRUN -> [SKIP][23] ([i915#3555] / [i915#3840])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg1-5/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-8: NOTRUN -> [SKIP][24] ([fdo#109285])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg2-8/igt@kms_force_connector_basic@force-load-detect.html
- bat-dg1-5: NOTRUN -> [SKIP][25] ([fdo#109285])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg1-5/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-8: NOTRUN -> [SKIP][26] ([i915#5274])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg2-8/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_hdmi_inject@inject-audio:
- bat-dg1-5: NOTRUN -> [SKIP][27] ([i915#433])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg1-5/igt@kms_hdmi_inject@inject-audio.html
- fi-kbl-guc: [PASS][28] -> [FAIL][29] ([IGT#3])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-adlp-9: NOTRUN -> [SKIP][30] ([i915#1845] / [i915#3546]) +3 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-adlp-9/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg1-5: NOTRUN -> [SKIP][31] ([i915#3555])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg1-5/igt@kms_setmode@basic-clone-single-crtc.html
- bat-dg2-8: NOTRUN -> [SKIP][32] ([i915#3555] / [i915#4098])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg2-8/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-dg2-8: NOTRUN -> [SKIP][33] ([i915#3708])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg2-8/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-dg2-8: NOTRUN -> [SKIP][34] ([i915#3708] / [i915#4077]) +1 other test skip
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg2-8/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- bat-dg1-5: NOTRUN -> [SKIP][35] ([i915#3708]) +3 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg1-5/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-gtt:
- bat-dg1-5: NOTRUN -> [SKIP][36] ([i915#3708] / [i915#4077]) +1 other test skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg1-5/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@basic-write:
- bat-dg2-8: NOTRUN -> [SKIP][37] ([i915#3291] / [i915#3708]) +2 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-dg2-8/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- bat-jsl-3: [INCOMPLETE][38] ([i915#9275]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/bat-jsl-3/igt@gem_exec_suspend@basic-s0@smem.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-jsl-3/igt@gem_exec_suspend@basic-s0@smem.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][40] ([i915#5334]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-jsl-3: [FAIL][42] ([fdo#103375]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/bat-jsl-3/igt@i915_suspend@basic-s3-without-i915.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-jsl-3/igt@i915_suspend@basic-s3-without-i915.html
#### Warnings ####
* igt@gem_lmem_swapping@basic:
- bat-jsl-1: [INCOMPLETE][44] -> [SKIP][45] ([i915#4613])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/bat-jsl-1/igt@gem_lmem_swapping@basic.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/bat-jsl-1/igt@gem_lmem_swapping@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#9275]: https://gitlab.freedesktop.org/drm/intel/issues/9275
[i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
[i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
[i915#9736]: https://gitlab.freedesktop.org/drm/intel/issues/9736
Build changes
-------------
* Linux: CI_DRM_13961 -> Patchwork_127194v1
CI-20190529: 20190529
CI_DRM_13961: b663cf8fc774c07996684d82bf09df14a7a21688 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7614: c7298ec108dc1c861c9a2593e973648ad9b420b4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_127194v1: b663cf8fc774c07996684d82bf09df14a7a21688 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
bcc5dc2b4b88 drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/index.html
[-- Attachment #2: Type: text/html, Size: 15940 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select
2023-12-01 13:41 [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select Jani Nikula
2023-12-01 14:41 ` Ville Syrjälä
2023-12-01 23:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
@ 2023-12-03 4:46 ` Patchwork
2 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2023-12-03 4:46 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 55650 bytes --]
== Series Details ==
Series: drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select
URL : https://patchwork.freedesktop.org/series/127194/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13961_full -> Patchwork_127194v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-mtlp0
Known issues
------------
Here are the changes found in Patchwork_127194v1_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-glk: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [FAIL][27], [PASS][28], [FAIL][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) ([i915#8293])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk1/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk2/boot.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk2/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk2/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk3/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk3/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk3/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk4/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk4/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk4/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk5/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk5/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk5/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk6/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk6/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk6/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk7/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk7/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk7/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk8/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk8/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk8/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk9/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk9/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk9/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk5/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk5/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk6/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk6/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk7/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk7/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk7/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk8/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk8/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk8/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk9/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk9/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk9/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk4/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk4/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk4/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk3/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk3/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk3/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk2/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk2/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk2/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk1/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk1/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk1/boot.html
### IGT changes ###
#### Issues hit ####
* igt@drm_fdinfo@busy-idle@bcs0:
- shard-dg2: NOTRUN -> [SKIP][51] ([i915#8414]) +9 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@drm_fdinfo@busy-idle@bcs0.html
* igt@drm_fdinfo@isolation@bcs0:
- shard-dg1: NOTRUN -> [SKIP][52] ([i915#8414]) +4 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@drm_fdinfo@isolation@bcs0.html
* igt@drm_fdinfo@virtual-busy-all:
- shard-mtlp: NOTRUN -> [SKIP][53] ([i915#8414])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@drm_fdinfo@virtual-busy-all.html
* igt@gem_busy@semaphore:
- shard-mtlp: NOTRUN -> [SKIP][54] ([i915#3936])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@gem_busy@semaphore.html
* igt@gem_caching@read-writes:
- shard-mtlp: NOTRUN -> [SKIP][55] ([i915#4873])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@gem_caching@read-writes.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglu: [PASS][56] -> [FAIL][57] ([i915#6268])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-tglu-7/igt@gem_ctx_exec@basic-nohangcheck.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-tglu-3/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_persistence@heartbeat-hostile:
- shard-dg2: NOTRUN -> [SKIP][58] ([i915#8555])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-11/igt@gem_ctx_persistence@heartbeat-hostile.html
* igt@gem_ctx_sseu@engines:
- shard-mtlp: NOTRUN -> [SKIP][59] ([i915#280])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-3/igt@gem_ctx_sseu@engines.html
* igt@gem_eio@hibernate:
- shard-dg2: NOTRUN -> [ABORT][60] ([i915#7975] / [i915#8213])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@gem_eio@hibernate.html
* igt@gem_exec_balancer@hog:
- shard-dg2: NOTRUN -> [SKIP][61] ([i915#4812])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-10/igt@gem_exec_balancer@hog.html
* igt@gem_exec_capture@capture-invisible@lmem0:
- shard-dg2: NOTRUN -> [SKIP][62] ([i915#6334]) +1 other test skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@gem_exec_capture@capture-invisible@lmem0.html
* igt@gem_exec_fair@basic-none-share:
- shard-dg1: NOTRUN -> [SKIP][63] ([i915#3539] / [i915#4852])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@gem_exec_fair@basic-none-share.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][64] -> [FAIL][65] ([i915#2842])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_flush@basic-wb-prw-default:
- shard-dg2: NOTRUN -> [SKIP][66] ([i915#3539] / [i915#4852]) +1 other test skip
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@gem_exec_flush@basic-wb-prw-default.html
* igt@gem_exec_reloc@basic-gtt-cpu-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][67] ([i915#3281]) +6 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@gem_exec_reloc@basic-gtt-cpu-noreloc.html
* igt@gem_exec_reloc@basic-wc:
- shard-dg1: NOTRUN -> [SKIP][68] ([i915#3281]) +1 other test skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@gem_exec_reloc@basic-wc.html
* igt@gem_exec_reloc@basic-write-gtt-active:
- shard-dg2: NOTRUN -> [SKIP][69] ([i915#3281]) +4 other tests skip
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@gem_exec_reloc@basic-write-gtt-active.html
* igt@gem_exec_schedule@preempt-queue:
- shard-dg1: NOTRUN -> [SKIP][70] ([i915#4812]) +1 other test skip
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@gem_exec_schedule@preempt-queue.html
* igt@gem_exec_schedule@preempt-queue-chain:
- shard-dg2: NOTRUN -> [SKIP][71] ([i915#4537] / [i915#4812])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@gem_exec_schedule@preempt-queue-chain.html
* igt@gem_exec_schedule@reorder-wide:
- shard-mtlp: NOTRUN -> [SKIP][72] ([i915#4537] / [i915#4812])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-5/igt@gem_exec_schedule@reorder-wide.html
* igt@gem_fenced_exec_thrash@no-spare-fences:
- shard-dg2: NOTRUN -> [SKIP][73] ([i915#4860])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-11/igt@gem_fenced_exec_thrash@no-spare-fences.html
* igt@gem_lmem_swapping@massive-random:
- shard-mtlp: NOTRUN -> [SKIP][74] ([i915#4613]) +2 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-5/igt@gem_lmem_swapping@massive-random.html
* igt@gem_mmap@bad-object:
- shard-dg1: NOTRUN -> [SKIP][75] ([i915#4083]) +4 other tests skip
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@gem_mmap@bad-object.html
* igt@gem_mmap_gtt@basic:
- shard-dg1: NOTRUN -> [SKIP][76] ([i915#4077]) +3 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@gem_mmap_gtt@basic.html
* igt@gem_mmap_gtt@close-race:
- shard-mtlp: NOTRUN -> [SKIP][77] ([i915#4077]) +9 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-3/igt@gem_mmap_gtt@close-race.html
* igt@gem_mmap_wc@bad-size:
- shard-dg2: NOTRUN -> [SKIP][78] ([i915#4083]) +1 other test skip
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@gem_mmap_wc@bad-size.html
* igt@gem_pread@snoop:
- shard-dg2: NOTRUN -> [SKIP][79] ([i915#3282]) +5 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-10/igt@gem_pread@snoop.html
- shard-dg1: NOTRUN -> [SKIP][80] ([i915#3282]) +1 other test skip
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-19/igt@gem_pread@snoop.html
* igt@gem_pwrite@basic-random:
- shard-mtlp: NOTRUN -> [SKIP][81] ([i915#3282]) +2 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-5/igt@gem_pwrite@basic-random.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-dg1: NOTRUN -> [SKIP][82] ([i915#4270])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_pxp@reject-modify-context-protection-off-2:
- shard-mtlp: NOTRUN -> [SKIP][83] ([i915#4270])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@gem_pxp@reject-modify-context-protection-off-2.html
* igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs:
- shard-mtlp: NOTRUN -> [SKIP][84] ([i915#8428]) +2 other tests skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-3/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs.html
* igt@gem_tiled_partial_pwrite_pread@reads:
- shard-dg2: NOTRUN -> [SKIP][85] ([i915#4077]) +3 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-11/igt@gem_tiled_partial_pwrite_pread@reads.html
* igt@gem_userptr_blits@unsync-overlap:
- shard-mtlp: NOTRUN -> [SKIP][86] ([i915#3297]) +2 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@gem_userptr_blits@unsync-overlap.html
* igt@gen7_exec_parse@basic-offset:
- shard-dg2: NOTRUN -> [SKIP][87] ([fdo#109289])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@gen7_exec_parse@basic-offset.html
* igt@gen9_exec_parse@batch-without-end:
- shard-dg2: NOTRUN -> [SKIP][88] ([i915#2856])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@gen9_exec_parse@batch-without-end.html
* igt@gen9_exec_parse@bb-start-far:
- shard-mtlp: NOTRUN -> [SKIP][89] ([i915#2856]) +2 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-3/igt@gen9_exec_parse@bb-start-far.html
* igt@gen9_exec_parse@shadow-peek:
- shard-dg1: NOTRUN -> [SKIP][90] ([i915#2527])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@gen9_exec_parse@shadow-peek.html
* igt@i915_fb_tiling:
- shard-dg1: NOTRUN -> [SKIP][91] ([i915#4881])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@i915_fb_tiling.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg2: [PASS][92] -> [WARN][93] ([i915#7356])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-dg2-6/igt@i915_module_load@reload-with-fault-injection.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-11/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_freq_mult@media-freq@gt0:
- shard-dg1: NOTRUN -> [SKIP][94] ([i915#6590])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-19/igt@i915_pm_freq_mult@media-freq@gt0.html
* igt@i915_pm_rpm@gem-mmap-type@gtt-smem0:
- shard-mtlp: NOTRUN -> [SKIP][95] ([i915#8431])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-3/igt@i915_pm_rpm@gem-mmap-type@gtt-smem0.html
* igt@i915_pm_rps@min-max-config-loaded:
- shard-mtlp: NOTRUN -> [SKIP][96] ([i915#6621])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-5/igt@i915_pm_rps@min-max-config-loaded.html
* igt@i915_pm_rps@thresholds-idle-park@gt0:
- shard-mtlp: NOTRUN -> [SKIP][97] ([i915#8925])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@i915_pm_rps@thresholds-idle-park@gt0.html
* igt@i915_pm_rps@thresholds-idle-park@gt1:
- shard-mtlp: NOTRUN -> [SKIP][98] ([i915#3555] / [i915#8925])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@i915_pm_rps@thresholds-idle-park@gt1.html
* igt@i915_query@query-topology-unsupported:
- shard-mtlp: NOTRUN -> [SKIP][99] ([fdo#109302])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-5/igt@i915_query@query-topology-unsupported.html
* igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
- shard-dg1: NOTRUN -> [SKIP][100] ([i915#4212])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling.html
* igt@kms_addfb_basic@bo-too-small-due-to-tiling:
- shard-mtlp: NOTRUN -> [SKIP][101] ([i915#4212])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-3/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
* igt@kms_async_flips@crc@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [FAIL][102] ([i915#8247]) +1 other test fail
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-5/igt@kms_async_flips@crc@pipe-b-edp-1.html
* igt@kms_async_flips@crc@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [DMESG-FAIL][103] ([i915#8561]) +1 other test dmesg-fail
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-5/igt@kms_async_flips@crc@pipe-d-edp-1.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-mtlp: NOTRUN -> [SKIP][104] ([i915#3555] / [i915#4098])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-5/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-mtlp: NOTRUN -> [SKIP][105] ([i915#1769] / [i915#3555])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@kms_atomic_transition@plane-all-modeset-transition.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-180:
- shard-mtlp: [PASS][106] -> [FAIL][107] ([i915#5138]) +1 other test fail
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-mtlp-8/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-2/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-180:
- shard-dg1: NOTRUN -> [SKIP][108] ([i915#4538] / [i915#5286])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@kms_big_fb@4-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@linear-32bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][109] ([fdo#111614]) +1 other test skip
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-11/igt@kms_big_fb@linear-32bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-90:
- shard-mtlp: NOTRUN -> [SKIP][110] ([fdo#111614]) +3 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-3/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- shard-dg2: NOTRUN -> [SKIP][111] ([i915#5190]) +7 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-tglu: [PASS][112] -> [FAIL][113] ([i915#3743]) +2 other tests fail
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-tglu-4/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-tglu-8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-mtlp: NOTRUN -> [SKIP][114] ([fdo#111615]) +5 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][115] ([i915#4538] / [i915#5190]) +1 other test skip
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-addfb-size-overflow:
- shard-mtlp: NOTRUN -> [SKIP][116] ([i915#6187])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-3/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-dg1: NOTRUN -> [SKIP][117] ([i915#4538]) +1 other test skip
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_chamelium_audio@hdmi-audio-edid:
- shard-mtlp: NOTRUN -> [SKIP][118] ([i915#7828]) +5 other tests skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@kms_chamelium_audio@hdmi-audio-edid.html
* igt@kms_chamelium_color@ctm-limited-range:
- shard-dg1: NOTRUN -> [SKIP][119] ([fdo#111827])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@kms_chamelium_color@ctm-limited-range.html
* igt@kms_chamelium_color@ctm-negative:
- shard-dg2: NOTRUN -> [SKIP][120] ([fdo#111827]) +2 other tests skip
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@kms_chamelium_color@ctm-negative.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- shard-dg2: NOTRUN -> [SKIP][121] ([i915#7828])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
- shard-dg1: NOTRUN -> [SKIP][122] ([i915#7828])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html
* igt@kms_content_protection@atomic-dpms@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [TIMEOUT][123] ([i915#7173])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-11/igt@kms_content_protection@atomic-dpms@pipe-a-dp-4.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-mtlp: NOTRUN -> [SKIP][124] ([i915#3299])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-3/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_cursor_crc@cursor-offscreen-512x170:
- shard-mtlp: NOTRUN -> [SKIP][125] ([i915#3359])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@kms_cursor_crc@cursor-offscreen-512x170.html
* igt@kms_cursor_crc@cursor-offscreen-512x512:
- shard-dg2: NOTRUN -> [SKIP][126] ([i915#3359])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@kms_cursor_crc@cursor-offscreen-512x512.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-dg1: NOTRUN -> [SKIP][127] ([i915#3359])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
- shard-mtlp: NOTRUN -> [SKIP][128] ([i915#3546]) +1 other test skip
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-3/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- shard-dg1: NOTRUN -> [SKIP][129] ([i915#4103] / [i915#4213])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
- shard-glk: [PASS][130] -> [FAIL][131] ([i915#8248])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk3/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk4/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-dg2: NOTRUN -> [SKIP][132] ([fdo#109274] / [i915#5354])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@single-move@all-pipes:
- shard-mtlp: [PASS][133] -> [DMESG-WARN][134] ([i915#2017])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-mtlp-5/igt@kms_cursor_legacy@single-move@all-pipes.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-4/igt@kms_cursor_legacy@single-move@all-pipes.html
* igt@kms_draw_crc@draw-method-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][135] ([i915#8812])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@kms_draw_crc@draw-method-mmap-wc.html
* igt@kms_dsc@dsc-basic:
- shard-dg2: NOTRUN -> [SKIP][136] ([i915#3555] / [i915#3840] / [i915#4098])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@kms_dsc@dsc-basic.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-mtlp: NOTRUN -> [SKIP][137] ([i915#3840] / [i915#9688])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_fbcon_fbt@psr:
- shard-dg1: NOTRUN -> [SKIP][138] ([i915#3469])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@kms_fbcon_fbt@psr.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-dg2: NOTRUN -> [SKIP][139] ([i915#3469])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@2x-blocking-wf_vblank:
- shard-snb: NOTRUN -> [SKIP][140] ([fdo#109271]) +1 other test skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-snb6/igt@kms_flip@2x-blocking-wf_vblank.html
* igt@kms_flip@2x-flip-vs-dpms:
- shard-mtlp: NOTRUN -> [SKIP][141] ([i915#3637]) +4 other tests skip
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@kms_flip@2x-flip-vs-dpms.html
* igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible:
- shard-dg2: NOTRUN -> [SKIP][142] ([fdo#109274]) +2 other tests skip
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][143] ([i915#2672]) +5 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-10/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
- shard-dg1: NOTRUN -> [SKIP][144] ([i915#2587] / [i915#2672]) +1 other test skip
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-19/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][145] ([i915#2672])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][146] ([i915#3555] / [i915#8810])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][147] ([i915#2672] / [i915#3555])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][148] ([i915#2672] / [i915#3555])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_force_connector_basic@prune-stale-modes:
- shard-dg2: NOTRUN -> [SKIP][149] ([i915#5274])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt:
- shard-dg2: NOTRUN -> [FAIL][150] ([i915#6880])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][151] ([i915#8708]) +4 other tests skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-19/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][152] ([i915#8708]) +5 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][153] ([i915#3458]) +6 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt:
- shard-dg1: NOTRUN -> [SKIP][154] ([fdo#111825]) +11 other tests skip
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu:
- shard-dg1: NOTRUN -> [SKIP][155] ([i915#3458]) +3 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt:
- shard-dg2: NOTRUN -> [SKIP][156] ([i915#5354]) +12 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][157] ([i915#8708]) +4 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
- shard-mtlp: NOTRUN -> [SKIP][158] ([i915#1825]) +18 other tests skip
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-dg2: NOTRUN -> [SKIP][159] ([i915#3555] / [i915#8228])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-2/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_invalid_mode@clock-too-high@pipe-c-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][160] ([i915#9457]) +2 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-3/igt@kms_invalid_mode@clock-too-high@pipe-c-edp-1.html
* igt@kms_plane_lowres@tiling-none@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][161] ([i915#3582]) +3 other tests skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@kms_plane_lowres@tiling-none@pipe-b-edp-1.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-dg2: NOTRUN -> [SKIP][162] ([i915#6953])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][163] ([i915#5176]) +1 other test skip
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][164] ([i915#5176] / [i915#9423]) +3 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-19/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-hdmi-a-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][165] ([i915#3555] / [i915#5235]) +1 other test skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-d-edp-1.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][166] ([i915#5235]) +3 other tests skip
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-hdmi-a-4.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][167] ([i915#5235]) +11 other tests skip
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][168] ([i915#5235]) +5 other tests skip
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-edp-1.html
* igt@kms_prime@basic-modeset-hybrid:
- shard-mtlp: NOTRUN -> [SKIP][169] ([i915#6524])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-3/igt@kms_prime@basic-modeset-hybrid.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-dg2: NOTRUN -> [SKIP][170] ([i915#9683]) +1 other test skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_sprite_blt:
- shard-dg2: NOTRUN -> [SKIP][171] ([i915#9673] / [i915#9732]) +1 other test skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-dg2: NOTRUN -> [SKIP][172] ([i915#9673] / [i915#9736])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-11/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-mtlp: NOTRUN -> [SKIP][173] ([i915#4235]) +1 other test skip
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_rotation_crc@primary-rotation-90:
- shard-dg2: NOTRUN -> [SKIP][174] ([i915#4235])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@kms_rotation_crc@primary-rotation-90.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-dg2: NOTRUN -> [SKIP][175] ([i915#4235] / [i915#5190])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-11/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_scaling_modes@scaling-mode-none:
- shard-dg2: NOTRUN -> [SKIP][176] ([i915#3555]) +2 other tests skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@kms_scaling_modes@scaling-mode-none.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-dg1: NOTRUN -> [SKIP][177] ([i915#8623])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-19/igt@kms_tiled_display@basic-test-pattern.html
- shard-dg2: NOTRUN -> [SKIP][178] ([i915#8623]) +1 other test skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-10/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [FAIL][179] ([i915#9196])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html
* igt@kms_vrr@flip-suspend:
- shard-dg1: NOTRUN -> [SKIP][180] ([i915#3555])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@kms_vrr@flip-suspend.html
* igt@kms_writeback@writeback-check-output:
- shard-dg2: NOTRUN -> [SKIP][181] ([i915#2437])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id:
- shard-mtlp: NOTRUN -> [SKIP][182] ([i915#2437])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@kms_writeback@writeback-fb-id.html
* igt@perf@gen8-unprivileged-single-ctx-counters:
- shard-dg2: NOTRUN -> [SKIP][183] ([i915#2436])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@perf@gen8-unprivileged-single-ctx-counters.html
* igt@perf@global-sseu-config-invalid:
- shard-mtlp: NOTRUN -> [SKIP][184] ([i915#7387])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@perf@global-sseu-config-invalid.html
* igt@perf@unprivileged-single-ctx-counters:
- shard-mtlp: NOTRUN -> [SKIP][185] ([fdo#109289])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@perf@unprivileged-single-ctx-counters.html
* igt@perf_pmu@busy-double-start@vecs1:
- shard-dg2: NOTRUN -> [FAIL][186] ([i915#4349]) +3 other tests fail
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@perf_pmu@busy-double-start@vecs1.html
* igt@perf_pmu@module-unload:
- shard-dg2: NOTRUN -> [FAIL][187] ([i915#5793])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@perf_pmu@module-unload.html
* igt@prime_vgem@basic-gtt:
- shard-dg2: NOTRUN -> [SKIP][188] ([i915#3708] / [i915#4077])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@fence-read-hang:
- shard-mtlp: NOTRUN -> [SKIP][189] ([i915#3708])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-8/igt@prime_vgem@fence-read-hang.html
* igt@v3d/v3d_submit_csd@job-perfmon:
- shard-dg2: NOTRUN -> [SKIP][190] ([i915#2575]) +4 other tests skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-5/igt@v3d/v3d_submit_csd@job-perfmon.html
* igt@v3d/v3d_wait_bo@map-bo-0ns:
- shard-mtlp: NOTRUN -> [SKIP][191] ([i915#2575]) +6 other tests skip
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-3/igt@v3d/v3d_wait_bo@map-bo-0ns.html
* igt@v3d/v3d_wait_bo@unused-bo-0ns:
- shard-dg1: NOTRUN -> [SKIP][192] ([i915#2575]) +2 other tests skip
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-16/igt@v3d/v3d_wait_bo@unused-bo-0ns.html
* igt@vc4/vc4_mmap@mmap-bo:
- shard-dg2: NOTRUN -> [SKIP][193] ([i915#7711]) +2 other tests skip
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-10/igt@vc4/vc4_mmap@mmap-bo.html
- shard-dg1: NOTRUN -> [SKIP][194] ([i915#7711]) +3 other tests skip
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg1-19/igt@vc4/vc4_mmap@mmap-bo.html
* igt@vc4/vc4_purgeable_bo@mark-unpurgeable-twice:
- shard-mtlp: NOTRUN -> [SKIP][195] ([i915#7711]) +3 other tests skip
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-3/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-twice.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglu: [FAIL][196] ([i915#2842]) -> [PASS][197]
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-tglu-3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-tglu-8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_suspend@basic-s4-devices@lmem0:
- shard-dg2: [ABORT][198] ([i915#7975] / [i915#8213]) -> [PASS][199]
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-dg2-1/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-11/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-tglu: [FAIL][200] ([i915#3743]) -> [PASS][201] +1 other test pass
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-tglu-3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-tglu-8/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic:
- shard-mtlp: [INCOMPLETE][202] -> [PASS][203]
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-mtlp-4/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-5/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [FAIL][204] ([i915#2346]) -> [PASS][205]
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-dg2: [FAIL][206] ([i915#6880]) -> [PASS][207] +1 other test pass
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-vga-1:
- shard-snb: [FAIL][208] ([i915#9196]) -> [PASS][209] +1 other test pass
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-snb5/igt@kms_universal_plane@cursor-fb-leak@pipe-a-vga-1.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-snb4/igt@kms_universal_plane@cursor-fb-leak@pipe-a-vga-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1:
- shard-tglu: [FAIL][210] ([i915#9196]) -> [PASS][211]
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-tglu-5/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-tglu-8/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
* igt@perf_pmu@render-node-busy@ccs0:
- shard-mtlp: [FAIL][212] ([i915#4349]) -> [PASS][213]
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-mtlp-2/igt@perf_pmu@render-node-busy@ccs0.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-mtlp-7/igt@perf_pmu@render-node-busy@ccs0.html
#### Warnings ####
* igt@kms_content_protection@type1:
- shard-dg2: [SKIP][214] ([i915#7118] / [i915#7162]) -> [SKIP][215] ([i915#7118])
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-dg2-11/igt@kms_content_protection@type1.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-1/igt@kms_content_protection@type1.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-dg2: [SKIP][216] ([i915#9673] / [i915#9732]) -> [SKIP][217] ([i915#9673])
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-dg2-6/igt@kms_psr@psr2_primary_mmap_gtt.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-11/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-dg2: [SKIP][218] ([i915#9673] / [i915#9732]) -> [SKIP][219] ([i915#9673] / [i915#9736])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-dg2-6/igt@kms_psr@psr2_sprite_mmap_gtt.html
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-11/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_psr@psr2_suspend:
- shard-dg2: [SKIP][220] ([i915#9673] / [i915#9736]) -> [SKIP][221] ([i915#9673] / [i915#9732]) +1 other test skip
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-dg2-11/igt@kms_psr@psr2_suspend.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-2/igt@kms_psr@psr2_suspend.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: [INCOMPLETE][222] ([i915#5493]) -> [CRASH][223] ([i915#9351])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13961/shard-dg2-10/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/shard-dg2-11/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3582]: https://gitlab.freedesktop.org/drm/intel/issues/3582
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5793]: https://gitlab.freedesktop.org/drm/intel/issues/5793
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6187]: https://gitlab.freedesktop.org/drm/intel/issues/6187
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
[i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
[i915#7356]: https://gitlab.freedesktop.org/drm/intel/issues/7356
[i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8248]: https://gitlab.freedesktop.org/drm/intel/issues/8248
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8431]: https://gitlab.freedesktop.org/drm/intel/issues/8431
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
[i915#8561]: https://gitlab.freedesktop.org/drm/intel/issues/8561
[i915#8623]: https://gitlab.freedesktop.org/drm/intel/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
[i915#8812]: https://gitlab.freedesktop.org/drm/intel/issues/8812
[i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
[i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
[i915#9293]: https://gitlab.freedesktop.org/drm/intel/issues/9293
[i915#9337]: https://gitlab.freedesktop.org/drm/intel/issues/9337
[i915#9351]: https://gitlab.freedesktop.org/drm/intel/issues/9351
[i915#9423]: https://gitlab.freedesktop.org/drm/intel/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/intel/issues/9424
[i915#9433]: https://gitlab.freedesktop.org/drm/intel/issues/9433
[i915#9457]: https://gitlab.freedesktop.org/drm/intel/issues/9457
[i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
[i915#9683]: https://gitlab.freedesktop.org/drm/intel/issues/9683
[i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688
[i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
[i915#9736]: https://gitlab.freedesktop.org/drm/intel/issues/9736
Build changes
-------------
* Linux: CI_DRM_13961 -> Patchwork_127194v1
* Piglit: None -> piglit_4509
CI-20190529: 20190529
CI_DRM_13961: b663cf8fc774c07996684d82bf09df14a7a21688 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7614: c7298ec108dc1c861c9a2593e973648ad9b420b4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_127194v1: b663cf8fc774c07996684d82bf09df14a7a21688 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127194v1/index.html
[-- Attachment #2: Type: text/html, Size: 66257 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select
2023-12-01 14:41 ` Ville Syrjälä
@ 2023-12-04 9:57 ` Jani Nikula
2023-12-04 13:59 ` Manna, Animesh
2023-12-04 16:34 ` Shankar, Uma
0 siblings, 2 replies; 12+ messages in thread
From: Jani Nikula @ 2023-12-04 9:57 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, 01 Dec 2023, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Fri, Dec 01, 2023 at 03:41:41PM +0200, Jani Nikula wrote:
>> The eDP 1.5 spec adds a clarification for eDP 1.4x:
>>
>> > For eDP v1.4x, if the Source device chooses the Main-Link rate by way
>> > of DPCD 00100h, the Sink device shall ignore DPCD 00115h[2:0].
>>
>> We write 0 to DP_LINK_BW_SET (DPCD 100h) even when using
>> DP_LINK_RATE_SET (DPCD 114h). Stop doing that, as it can cause the panel
>> to ignore the rate set method.
>
> What a terrible way to specify this :( This means the device must
> hav some internal state to keep track of whethe BW_SET was ever
> written.
Indeed.
Additionally, eDP 1.5 specifies LINK_CONFIGURATION_STATUS (DPCD 0020Ch)
which exposes the internal state as link rate set status, and whether
that status is valid or not.
Overall the spec looks like that's just for status, but the register is
annotated Write/Read so who knows.
>
>>
>> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9081
>> Tested-by: Animesh Manna <animesh.manna@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> .../drm/i915/display/intel_dp_link_training.c | 23 +++++++++++--------
>> 1 file changed, 13 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> index dbc1b66c8ee4..6336a39030a4 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> @@ -650,19 +650,22 @@ intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
>> const struct intel_crtc_state *crtc_state,
>> u8 link_bw, u8 rate_select)
>> {
>> - u8 link_config[2];
>> + u8 lane_count = crtc_state->lane_count;
>>
>> - /* Write the link configuration data */
>> - link_config[0] = link_bw;
>> - link_config[1] = crtc_state->lane_count;
>> if (crtc_state->enhanced_framing)
>> - link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
>> + lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>> +
>> + if (link_bw) {
>> + /* eDP 1.3 and earlier link bw set method. */
>> + u8 link_config[] = { link_bw, lane_count };
>>
>> - /* eDP 1.4 rate select method. */
>> - if (!link_bw)
>> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
>> - &rate_select, 1);
>> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config,
>> + ARRAY_SIZE(link_config));
>> + } else {
>> + /* eDP 1.4 rate select method. */
>> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count);
>> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET, rate_select);
>
> Doesn't look there's anything in the spec that specifies when the device
> is supposed to reset its internal state to stop ignoring DP_LINK_RATE_SET.
> Do we know when this panel does it? When VDD is removed?
No idea. Animesh?
I think it's just crazy writing 0 to explicitly disable DP_LINK_BW_SET
renders DP_LINK_RATE_SET unusable. Pretty sure we've seen panels where
this works as you'd expect.
And the above depends on pre-os using the same logic as us for choosing
DP_LINK_RATE_SET. GOP seems to do that. But if it or some other pre-os
used DP_LINK_BW_SET, we'd fail. With some other panels, writing the 0
might recover from that.
No r-b, so do you have any better ideas?
BR,
Jani.
>
>> + }
>> }
>>
>> /*
>> --
>> 2.39.2
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select
2023-12-04 9:57 ` Jani Nikula
@ 2023-12-04 13:59 ` Manna, Animesh
2023-12-04 16:34 ` Shankar, Uma
1 sibling, 0 replies; 12+ messages in thread
From: Manna, Animesh @ 2023-12-04 13:59 UTC (permalink / raw)
To: Nikula, Jani, Ville Syrjälä; +Cc: intel-gfx
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Monday, December 4, 2023 3:28 PM
> To: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/edp: don't write to
> DP_LINK_BW_SET when using rate select
>
> On Fri, 01 Dec 2023, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Fri, Dec 01, 2023 at 03:41:41PM +0200, Jani Nikula wrote:
> >> The eDP 1.5 spec adds a clarification for eDP 1.4x:
> >>
> >> > For eDP v1.4x, if the Source device chooses the Main-Link rate by
> >> > way of DPCD 00100h, the Sink device shall ignore DPCD 00115h[2:0].
> >>
> >> We write 0 to DP_LINK_BW_SET (DPCD 100h) even when using
> >> DP_LINK_RATE_SET (DPCD 114h). Stop doing that, as it can cause the
> >> panel to ignore the rate set method.
> >
> > What a terrible way to specify this :( This means the device must hav
> > some internal state to keep track of whethe BW_SET was ever written.
>
> Indeed.
>
> Additionally, eDP 1.5 specifies LINK_CONFIGURATION_STATUS (DPCD
> 0020Ch) which exposes the internal state as link rate set status, and whether
> that status is valid or not.
>
> Overall the spec looks like that's just for status, but the register is annotated
> Write/Read so who knows.
>
> >
> >>
> >> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9081
> >> Tested-by: Animesh Manna <animesh.manna@intel.com>
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >> .../drm/i915/display/intel_dp_link_training.c | 23
> >> +++++++++++--------
> >> 1 file changed, 13 insertions(+), 10 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> index dbc1b66c8ee4..6336a39030a4 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> @@ -650,19 +650,22 @@ intel_dp_update_link_bw_set(struct intel_dp
> *intel_dp,
> >> const struct intel_crtc_state *crtc_state,
> >> u8 link_bw, u8 rate_select)
> >> {
> >> - u8 link_config[2];
> >> + u8 lane_count = crtc_state->lane_count;
> >>
> >> - /* Write the link configuration data */
> >> - link_config[0] = link_bw;
> >> - link_config[1] = crtc_state->lane_count;
> >> if (crtc_state->enhanced_framing)
> >> - link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> >> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config,
> 2);
> >> + lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> >> +
> >> + if (link_bw) {
> >> + /* eDP 1.3 and earlier link bw set method. */
> >> + u8 link_config[] = { link_bw, lane_count };
> >>
> >> - /* eDP 1.4 rate select method. */
> >> - if (!link_bw)
> >> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> >> - &rate_select, 1);
> >> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET,
> link_config,
> >> + ARRAY_SIZE(link_config));
> >> + } else {
> >> + /* eDP 1.4 rate select method. */
> >> + drm_dp_dpcd_writeb(&intel_dp->aux,
> DP_LANE_COUNT_SET, lane_count);
> >> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET,
> rate_select);
> >
> > Doesn't look there's anything in the spec that specifies when the
> > device is supposed to reset its internal state to stop ignoring
> DP_LINK_RATE_SET.
> > Do we know when this panel does it? When VDD is removed?
>
> No idea. Animesh?
Hi Jani/Ville,
Tried below experiment and sharing my observation below:
Forcefully changed the value of dpcd 0x100 (LINK_BW_SET) to random value (0x99) in edp_init_connector and later while VDD is on during modeset sequence I can see it is not holding its value rather got reset to default value. This will confirm when VDD is removed panel reset its internal state.
Regards,
Animesh
>
> I think it's just crazy writing 0 to explicitly disable DP_LINK_BW_SET renders
> DP_LINK_RATE_SET unusable. Pretty sure we've seen panels where this
> works as you'd expect.
>
> And the above depends on pre-os using the same logic as us for choosing
> DP_LINK_RATE_SET. GOP seems to do that. But if it or some other pre-os
> used DP_LINK_BW_SET, we'd fail. With some other panels, writing the 0
> might recover from that.
>
> No r-b, so do you have any better ideas?
>
>
> BR,
> Jani.
>
>
> >
> >> + }
> >> }
> >>
> >> /*
> >> --
> >> 2.39.2
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select
2023-12-04 9:57 ` Jani Nikula
2023-12-04 13:59 ` Manna, Animesh
@ 2023-12-04 16:34 ` Shankar, Uma
2023-12-04 16:48 ` Jani Nikula
1 sibling, 1 reply; 12+ messages in thread
From: Shankar, Uma @ 2023-12-04 16:34 UTC (permalink / raw)
To: Nikula, Jani, Ville Syrjälä; +Cc: intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Monday, December 4, 2023 3:28 PM
> To: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET
> when using rate select
>
> On Fri, 01 Dec 2023, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Fri, Dec 01, 2023 at 03:41:41PM +0200, Jani Nikula wrote:
> >> The eDP 1.5 spec adds a clarification for eDP 1.4x:
> >>
> >> > For eDP v1.4x, if the Source device chooses the Main-Link rate by
> >> > way of DPCD 00100h, the Sink device shall ignore DPCD 00115h[2:0].
> >>
> >> We write 0 to DP_LINK_BW_SET (DPCD 100h) even when using
> >> DP_LINK_RATE_SET (DPCD 114h). Stop doing that, as it can cause the
> >> panel to ignore the rate set method.
> >
> > What a terrible way to specify this :( This means the device must hav
> > some internal state to keep track of whethe BW_SET was ever written.
>
> Indeed.
>
> Additionally, eDP 1.5 specifies LINK_CONFIGURATION_STATUS (DPCD 0020Ch)
> which exposes the internal state as link rate set status, and whether that status is
> valid or not.
>
> Overall the spec looks like that's just for status, but the register is annotated
> Write/Read so who knows.
>
> >
> >>
> >> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9081
> >> Tested-by: Animesh Manna <animesh.manna@intel.com>
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >> .../drm/i915/display/intel_dp_link_training.c | 23
> >> +++++++++++--------
> >> 1 file changed, 13 insertions(+), 10 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> index dbc1b66c8ee4..6336a39030a4 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> @@ -650,19 +650,22 @@ intel_dp_update_link_bw_set(struct intel_dp
> *intel_dp,
> >> const struct intel_crtc_state *crtc_state,
> >> u8 link_bw, u8 rate_select)
> >> {
> >> - u8 link_config[2];
> >> + u8 lane_count = crtc_state->lane_count;
> >>
> >> - /* Write the link configuration data */
> >> - link_config[0] = link_bw;
> >> - link_config[1] = crtc_state->lane_count;
> >> if (crtc_state->enhanced_framing)
> >> - link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> >> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
> >> + lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> >> +
> >> + if (link_bw) {
> >> + /* eDP 1.3 and earlier link bw set method. */
> >> + u8 link_config[] = { link_bw, lane_count };
> >>
> >> - /* eDP 1.4 rate select method. */
> >> - if (!link_bw)
> >> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> >> - &rate_select, 1);
> >> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET,
> link_config,
> >> + ARRAY_SIZE(link_config));
> >> + } else {
> >> + /* eDP 1.4 rate select method. */
> >> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET,
> lane_count);
> >> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET,
> rate_select);
> >
> > Doesn't look there's anything in the spec that specifies when the
> > device is supposed to reset its internal state to stop ignoring
> DP_LINK_RATE_SET.
> > Do we know when this panel does it? When VDD is removed?
>
> No idea. Animesh?
>
> I think it's just crazy writing 0 to explicitly disable DP_LINK_BW_SET renders
> DP_LINK_RATE_SET unusable. Pretty sure we've seen panels where this works as
> you'd expect.
>
> And the above depends on pre-os using the same logic as us for choosing
> DP_LINK_RATE_SET. GOP seems to do that. But if it or some other pre-os used
> DP_LINK_BW_SET, we'd fail. With some other panels, writing the 0 might recover
> from that.
The spec does leave it a bit open on this one:
115h: LINK_RATE_SET and TX_GTC_CAPABILITY
• DPCD 00001h = 00h/DPCD 02201h = 00h – Source device shall use this field to choose
the link rate, and the Sink device shall ignore DPCD 00100h
• DPCD 00001h/DPCD 02201h = Valid link rate – Source device may optionally choose
a link rate associated with HBR3, HBR2,HBR, –or– RBR by writing to DPCD 00100h
So the 2nd point here does mentions that sinks can optionally use value of 00100h
if 2201h is not 00. So programming a value to this DPCD is not right unless we program
the right value (not 0).
I feel safe way would be be to go with LINK_BW_SET for DP1.3 and for DP1.4+ always use
LINK_RATE_SET and have it mutually exclusive.
Some TCONs would have ignored and we got lucky but we can't leave it ambiguous, we will be compliant
to spec if we don't write 0x100. So let's go with this change.
Regards,
Uma Shankar
> No r-b, so do you have any better ideas?
>
>
> BR,
> Jani.
>
>
> >
> >> + }
> >> }
> >>
> >> /*
> >> --
> >> 2.39.2
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select
2023-12-04 16:34 ` Shankar, Uma
@ 2023-12-04 16:48 ` Jani Nikula
2023-12-04 16:52 ` Shankar, Uma
0 siblings, 1 reply; 12+ messages in thread
From: Jani Nikula @ 2023-12-04 16:48 UTC (permalink / raw)
To: Shankar, Uma, Ville Syrjälä; +Cc: intel-gfx
On Mon, 04 Dec 2023, "Shankar, Uma" <uma.shankar@intel.com> wrote:
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
>> Nikula
>> Sent: Monday, December 4, 2023 3:28 PM
>> To: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: intel-gfx@lists.freedesktop.org
>> Subject: Re: [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET
>> when using rate select
>>
>> On Fri, 01 Dec 2023, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>> > On Fri, Dec 01, 2023 at 03:41:41PM +0200, Jani Nikula wrote:
>> >> The eDP 1.5 spec adds a clarification for eDP 1.4x:
>> >>
>> >> > For eDP v1.4x, if the Source device chooses the Main-Link rate by
>> >> > way of DPCD 00100h, the Sink device shall ignore DPCD 00115h[2:0].
>> >>
>> >> We write 0 to DP_LINK_BW_SET (DPCD 100h) even when using
>> >> DP_LINK_RATE_SET (DPCD 114h). Stop doing that, as it can cause the
>> >> panel to ignore the rate set method.
>> >
>> > What a terrible way to specify this :( This means the device must hav
>> > some internal state to keep track of whethe BW_SET was ever written.
>>
>> Indeed.
>>
>> Additionally, eDP 1.5 specifies LINK_CONFIGURATION_STATUS (DPCD 0020Ch)
>> which exposes the internal state as link rate set status, and whether that status is
>> valid or not.
>>
>> Overall the spec looks like that's just for status, but the register is annotated
>> Write/Read so who knows.
>>
>> >
>> >>
>> >> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9081
>> >> Tested-by: Animesh Manna <animesh.manna@intel.com>
>> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> >> ---
>> >> .../drm/i915/display/intel_dp_link_training.c | 23
>> >> +++++++++++--------
>> >> 1 file changed, 13 insertions(+), 10 deletions(-)
>> >>
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> >> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> >> index dbc1b66c8ee4..6336a39030a4 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> >> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> >> @@ -650,19 +650,22 @@ intel_dp_update_link_bw_set(struct intel_dp
>> *intel_dp,
>> >> const struct intel_crtc_state *crtc_state,
>> >> u8 link_bw, u8 rate_select)
>> >> {
>> >> - u8 link_config[2];
>> >> + u8 lane_count = crtc_state->lane_count;
>> >>
>> >> - /* Write the link configuration data */
>> >> - link_config[0] = link_bw;
>> >> - link_config[1] = crtc_state->lane_count;
>> >> if (crtc_state->enhanced_framing)
>> >> - link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>> >> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
>> >> + lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>> >> +
>> >> + if (link_bw) {
>> >> + /* eDP 1.3 and earlier link bw set method. */
>> >> + u8 link_config[] = { link_bw, lane_count };
>> >>
>> >> - /* eDP 1.4 rate select method. */
>> >> - if (!link_bw)
>> >> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
>> >> - &rate_select, 1);
>> >> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET,
>> link_config,
>> >> + ARRAY_SIZE(link_config));
>> >> + } else {
>> >> + /* eDP 1.4 rate select method. */
>> >> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET,
>> lane_count);
>> >> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET,
>> rate_select);
>> >
>> > Doesn't look there's anything in the spec that specifies when the
>> > device is supposed to reset its internal state to stop ignoring
>> DP_LINK_RATE_SET.
>> > Do we know when this panel does it? When VDD is removed?
>>
>> No idea. Animesh?
>>
>> I think it's just crazy writing 0 to explicitly disable DP_LINK_BW_SET renders
>> DP_LINK_RATE_SET unusable. Pretty sure we've seen panels where this works as
>> you'd expect.
>>
>> And the above depends on pre-os using the same logic as us for choosing
>> DP_LINK_RATE_SET. GOP seems to do that. But if it or some other pre-os used
>> DP_LINK_BW_SET, we'd fail. With some other panels, writing the 0 might recover
>> from that.
>
> The spec does leave it a bit open on this one:
>
> 115h: LINK_RATE_SET and TX_GTC_CAPABILITY
> • DPCD 00001h = 00h/DPCD 02201h = 00h – Source device shall use this field to choose
> the link rate, and the Sink device shall ignore DPCD 00100h
> • DPCD 00001h/DPCD 02201h = Valid link rate – Source device may optionally choose
> a link rate associated with HBR3, HBR2,HBR, –or– RBR by writing to DPCD 00100h
>
> So the 2nd point here does mentions that sinks can optionally use value of 00100h
> if 2201h is not 00. So programming a value to this DPCD is not right unless we program
> the right value (not 0).
>
> I feel safe way would be be to go with LINK_BW_SET for DP1.3 and for DP1.4+ always use
> LINK_RATE_SET and have it mutually exclusive.
>
> Some TCONs would have ignored and we got lucky but we can't leave it ambiguous, we will be compliant
> to spec if we don't write 0x100. So let's go with this change.
Moreover, there are only four documented valid values for this register,
0x06, 0xa, 0x14, and 0x1e, all other values are reserved. In that sense
it's also wrong to write 0x00.
BR,
Jani.
>
> Regards,
> Uma Shankar
>
>> No r-b, so do you have any better ideas?
>>
>>
>> BR,
>> Jani.
>>
>>
>> >
>> >> + }
>> >> }
>> >>
>> >> /*
>> >> --
>> >> 2.39.2
>>
>> --
>> Jani Nikula, Intel
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select
2023-12-04 16:48 ` Jani Nikula
@ 2023-12-04 16:52 ` Shankar, Uma
2023-12-05 12:00 ` Shankar, Uma
0 siblings, 1 reply; 12+ messages in thread
From: Shankar, Uma @ 2023-12-04 16:52 UTC (permalink / raw)
To: Nikula, Jani, Ville Syrjälä; +Cc: intel-gfx
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Monday, December 4, 2023 10:18 PM
> To: Shankar, Uma <uma.shankar@intel.com>; Ville Syrjälä
> <ville.syrjala@linux.intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET
> when using rate select
>
> On Mon, 04 Dec 2023, "Shankar, Uma" <uma.shankar@intel.com> wrote:
> >> -----Original Message-----
> >> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> >> Of Jani Nikula
> >> Sent: Monday, December 4, 2023 3:28 PM
> >> To: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> Cc: intel-gfx@lists.freedesktop.org
> >> Subject: Re: [Intel-gfx] [PATCH] drm/i915/edp: don't write to
> >> DP_LINK_BW_SET when using rate select
> >>
> >> On Fri, 01 Dec 2023, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> >> > On Fri, Dec 01, 2023 at 03:41:41PM +0200, Jani Nikula wrote:
> >> >> The eDP 1.5 spec adds a clarification for eDP 1.4x:
> >> >>
> >> >> > For eDP v1.4x, if the Source device chooses the Main-Link rate
> >> >> > by way of DPCD 00100h, the Sink device shall ignore DPCD 00115h[2:0].
> >> >>
> >> >> We write 0 to DP_LINK_BW_SET (DPCD 100h) even when using
> >> >> DP_LINK_RATE_SET (DPCD 114h). Stop doing that, as it can cause the
> >> >> panel to ignore the rate set method.
> >> >
> >> > What a terrible way to specify this :( This means the device must
> >> > hav some internal state to keep track of whethe BW_SET was ever written.
> >>
> >> Indeed.
> >>
> >> Additionally, eDP 1.5 specifies LINK_CONFIGURATION_STATUS (DPCD
> >> 0020Ch) which exposes the internal state as link rate set status, and
> >> whether that status is valid or not.
> >>
> >> Overall the spec looks like that's just for status, but the register
> >> is annotated Write/Read so who knows.
> >>
> >> >
> >> >>
> >> >> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9081
> >> >> Tested-by: Animesh Manna <animesh.manna@intel.com>
> >> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> >> ---
> >> >> .../drm/i915/display/intel_dp_link_training.c | 23
> >> >> +++++++++++--------
> >> >> 1 file changed, 13 insertions(+), 10 deletions(-)
> >> >>
> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> >> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> >> index dbc1b66c8ee4..6336a39030a4 100644
> >> >> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> >> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> >> @@ -650,19 +650,22 @@ intel_dp_update_link_bw_set(struct intel_dp
> >> *intel_dp,
> >> >> const struct intel_crtc_state *crtc_state,
> >> >> u8 link_bw, u8 rate_select) {
> >> >> - u8 link_config[2];
> >> >> + u8 lane_count = crtc_state->lane_count;
> >> >>
> >> >> - /* Write the link configuration data */
> >> >> - link_config[0] = link_bw;
> >> >> - link_config[1] = crtc_state->lane_count;
> >> >> if (crtc_state->enhanced_framing)
> >> >> - link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> >> >> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
> >> >> + lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> >> >> +
> >> >> + if (link_bw) {
> >> >> + /* eDP 1.3 and earlier link bw set method. */
> >> >> + u8 link_config[] = { link_bw, lane_count };
> >> >>
> >> >> - /* eDP 1.4 rate select method. */
> >> >> - if (!link_bw)
> >> >> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> >> >> - &rate_select, 1);
> >> >> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET,
> >> link_config,
> >> >> + ARRAY_SIZE(link_config));
> >> >> + } else {
> >> >> + /* eDP 1.4 rate select method. */
> >> >> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET,
> >> lane_count);
> >> >> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET,
> >> rate_select);
> >> >
> >> > Doesn't look there's anything in the spec that specifies when the
> >> > device is supposed to reset its internal state to stop ignoring
> >> DP_LINK_RATE_SET.
> >> > Do we know when this panel does it? When VDD is removed?
> >>
> >> No idea. Animesh?
> >>
> >> I think it's just crazy writing 0 to explicitly disable DP_LINK_BW_SET renders
> >> DP_LINK_RATE_SET unusable. Pretty sure we've seen panels where this works
> as
> >> you'd expect.
> >>
> >> And the above depends on pre-os using the same logic as us for choosing
> >> DP_LINK_RATE_SET. GOP seems to do that. But if it or some other pre-os used
> >> DP_LINK_BW_SET, we'd fail. With some other panels, writing the 0 might
> recover
> >> from that.
> >
> > The spec does leave it a bit open on this one:
> >
> > 115h: LINK_RATE_SET and TX_GTC_CAPABILITY
> > • DPCD 00001h = 00h/DPCD 02201h = 00h – Source device shall use this field to
> choose
> > the link rate, and the Sink device shall ignore DPCD 00100h
> > • DPCD 00001h/DPCD 02201h = Valid link rate – Source device may optionally
> choose
> > a link rate associated with HBR3, HBR2,HBR, –or– RBR by writing to DPCD
> 00100h
> >
> > So the 2nd point here does mentions that sinks can optionally use value of
> 00100h
> > if 2201h is not 00. So programming a value to this DPCD is not right unless we
> program
> > the right value (not 0).
> >
> > I feel safe way would be be to go with LINK_BW_SET for DP1.3 and for DP1.4+
> always use
> > LINK_RATE_SET and have it mutually exclusive.
> >
> > Some TCONs would have ignored and we got lucky but we can't leave it
> ambiguous, we will be compliant
> > to spec if we don't write 0x100. So let's go with this change.
>
> Moreover, there are only four documented valid values for this register,
> 0x06, 0xa, 0x14, and 0x1e, all other values are reserved. In that sense
> it's also wrong to write 0x00.
Yeah, writing 0 is done with an intention to disable it but that’s not the way
to have this option disabled. Infact there is no reason to write to it for DP1.4+
if sink is compliant.
Regards,
Uma Shankar
> BR,
> Jani.
>
>
>
>
> >
> > Regards,
> > Uma Shankar
> >
> >> No r-b, so do you have any better ideas?
> >>
> >>
> >> BR,
> >> Jani.
> >>
> >>
> >> >
> >> >> + }
> >> >> }
> >> >>
> >> >> /*
> >> >> --
> >> >> 2.39.2
> >>
> >> --
> >> Jani Nikula, Intel
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select
2023-12-04 16:52 ` Shankar, Uma
@ 2023-12-05 12:00 ` Shankar, Uma
2023-12-05 12:50 ` Jani Nikula
0 siblings, 1 reply; 12+ messages in thread
From: Shankar, Uma @ 2023-12-05 12:00 UTC (permalink / raw)
To: Nikula, Jani, Ville Syrjälä; +Cc: intel-gfx
> -----Original Message-----
> From: Shankar, Uma
> Sent: Monday, December 4, 2023 10:23 PM
> To: Nikula, Jani <jani.nikula@intel.com>; Ville Syrjälä
> <ville.syrjala@linux.intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET
> when using rate select
>
>
>
> > -----Original Message-----
> > From: Nikula, Jani <jani.nikula@intel.com>
> > Sent: Monday, December 4, 2023 10:18 PM
> > To: Shankar, Uma <uma.shankar@intel.com>; Ville Syrjälä
> > <ville.syrjala@linux.intel.com>
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: RE: [Intel-gfx] [PATCH] drm/i915/edp: don't write to
> > DP_LINK_BW_SET when using rate select
> >
> > On Mon, 04 Dec 2023, "Shankar, Uma" <uma.shankar@intel.com> wrote:
> > >> -----Original Message-----
> > >> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> > >> Of Jani Nikula
> > >> Sent: Monday, December 4, 2023 3:28 PM
> > >> To: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >> Cc: intel-gfx@lists.freedesktop.org
> > >> Subject: Re: [Intel-gfx] [PATCH] drm/i915/edp: don't write to
> > >> DP_LINK_BW_SET when using rate select
> > >>
> > >> On Fri, 01 Dec 2023, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > >> > On Fri, Dec 01, 2023 at 03:41:41PM +0200, Jani Nikula wrote:
> > >> >> The eDP 1.5 spec adds a clarification for eDP 1.4x:
> > >> >>
> > >> >> > For eDP v1.4x, if the Source device chooses the Main-Link rate
> > >> >> > by way of DPCD 00100h, the Sink device shall ignore DPCD 00115h[2:0].
> > >> >>
> > >> >> We write 0 to DP_LINK_BW_SET (DPCD 100h) even when using
> > >> >> DP_LINK_RATE_SET (DPCD 114h). Stop doing that, as it can cause
> > >> >> the panel to ignore the rate set method.
> > >> >
> > >> > What a terrible way to specify this :( This means the device must
> > >> > hav some internal state to keep track of whethe BW_SET was ever written.
> > >>
> > >> Indeed.
> > >>
> > >> Additionally, eDP 1.5 specifies LINK_CONFIGURATION_STATUS (DPCD
> > >> 0020Ch) which exposes the internal state as link rate set status,
> > >> and whether that status is valid or not.
> > >>
> > >> Overall the spec looks like that's just for status, but the
> > >> register is annotated Write/Read so who knows.
> > >>
> > >> >
> > >> >>
> > >> >> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9081
> > >> >> Tested-by: Animesh Manna <animesh.manna@intel.com>
> > >> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> > >> >> ---
> > >> >> .../drm/i915/display/intel_dp_link_training.c | 23
> > >> >> +++++++++++--------
> > >> >> 1 file changed, 13 insertions(+), 10 deletions(-)
> > >> >>
> > >> >> diff --git
> > >> >> a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > >> >> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > >> >> index dbc1b66c8ee4..6336a39030a4 100644
> > >> >> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > >> >> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > >> >> @@ -650,19 +650,22 @@ intel_dp_update_link_bw_set(struct
> > >> >> intel_dp
> > >> *intel_dp,
> > >> >> const struct intel_crtc_state *crtc_state,
> > >> >> u8 link_bw, u8 rate_select) {
> > >> >> - u8 link_config[2];
> > >> >> + u8 lane_count = crtc_state->lane_count;
> > >> >>
> > >> >> - /* Write the link configuration data */
> > >> >> - link_config[0] = link_bw;
> > >> >> - link_config[1] = crtc_state->lane_count;
> > >> >> if (crtc_state->enhanced_framing)
> > >> >> - link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> > >> >> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET,
> > >> >> link_config, 2);
> > >> >> + lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> > >> >> +
> > >> >> + if (link_bw) {
> > >> >> + /* eDP 1.3 and earlier link bw set method. */
> > >> >> + u8 link_config[] = { link_bw, lane_count };
> > >> >>
> > >> >> - /* eDP 1.4 rate select method. */
> > >> >> - if (!link_bw)
> > >> >> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> > >> >> - &rate_select, 1);
> > >> >> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET,
> > >> link_config,
> > >> >> + ARRAY_SIZE(link_config)); } else {
> > >> >> + /* eDP 1.4 rate select method. */
> > >> >> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET,
> > >> lane_count);
> > >> >> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET,
> > >> rate_select);
> > >> >
> > >> > Doesn't look there's anything in the spec that specifies when the
> > >> > device is supposed to reset its internal state to stop ignoring
> > >> DP_LINK_RATE_SET.
> > >> > Do we know when this panel does it? When VDD is removed?
> > >>
> > >> No idea. Animesh?
> > >>
> > >> I think it's just crazy writing 0 to explicitly disable
> > >> DP_LINK_BW_SET renders DP_LINK_RATE_SET unusable. Pretty sure we've
> > >> seen panels where this works
> > as
> > >> you'd expect.
> > >>
> > >> And the above depends on pre-os using the same logic as us for
> > >> choosing DP_LINK_RATE_SET. GOP seems to do that. But if it or some
> > >> other pre-os used DP_LINK_BW_SET, we'd fail. With some other
> > >> panels, writing the 0 might
> > recover
> > >> from that.
> > >
> > > The spec does leave it a bit open on this one:
> > >
> > > 115h: LINK_RATE_SET and TX_GTC_CAPABILITY • DPCD 00001h = 00h/DPCD
> > > 02201h = 00h – Source device shall use this field to
> > choose
> > > the link rate, and the Sink device shall ignore DPCD 00100h • DPCD
> > > 00001h/DPCD 02201h = Valid link rate – Source device may optionally
> > choose
> > > a link rate associated with HBR3, HBR2,HBR, –or– RBR by writing to
> > > DPCD
> > 00100h
> > >
> > > So the 2nd point here does mentions that sinks can optionally use
> > > value of
> > 00100h
> > > if 2201h is not 00. So programming a value to this DPCD is not right
> > > unless we
> > program
> > > the right value (not 0).
> > >
> > > I feel safe way would be be to go with LINK_BW_SET for DP1.3 and for
> > > DP1.4+
> > always use
> > > LINK_RATE_SET and have it mutually exclusive.
> > >
> > > Some TCONs would have ignored and we got lucky but we can't leave it
> > ambiguous, we will be compliant
> > > to spec if we don't write 0x100. So let's go with this change.
> >
> > Moreover, there are only four documented valid values for this
> > register, 0x06, 0xa, 0x14, and 0x1e, all other values are reserved. In
> > that sense it's also wrong to write 0x00.
>
> Yeah, writing 0 is done with an intention to disable it but that’s not the way to
> have this option disabled. Infact there is no reason to write to it for DP1.4+ if sink
> is compliant.
The change looks ok and aligns with spec, its
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Regards,
Uma Shankar
>
> > BR,
> > Jani.
> >
> >
> >
> >
> > >
> > > Regards,
> > > Uma Shankar
> > >
> > >> No r-b, so do you have any better ideas?
> > >>
> > >>
> > >> BR,
> > >> Jani.
> > >>
> > >>
> > >> >
> > >> >> + }
> > >> >> }
> > >> >>
> > >> >> /*
> > >> >> --
> > >> >> 2.39.2
> > >>
> > >> --
> > >> Jani Nikula, Intel
> >
> > --
> > Jani Nikula, Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select
2023-12-05 12:00 ` Shankar, Uma
@ 2023-12-05 12:50 ` Jani Nikula
2023-12-05 15:01 ` Ville Syrjälä
0 siblings, 1 reply; 12+ messages in thread
From: Jani Nikula @ 2023-12-05 12:50 UTC (permalink / raw)
To: Shankar, Uma, Ville Syrjälä; +Cc: intel-gfx
On Tue, 05 Dec 2023, "Shankar, Uma" <uma.shankar@intel.com> wrote:
>> Yeah, writing 0 is done with an intention to disable it but that’s not the way to
>> have this option disabled. Infact there is no reason to write to it for DP1.4+ if sink
>> is compliant.
>
> The change looks ok and aligns with spec, its
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Ville, any further objections or concerns? Okay to merge?
BR,
Jani.
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select
2023-12-05 12:50 ` Jani Nikula
@ 2023-12-05 15:01 ` Ville Syrjälä
0 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjälä @ 2023-12-05 15:01 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Dec 05, 2023 at 02:50:57PM +0200, Jani Nikula wrote:
> On Tue, 05 Dec 2023, "Shankar, Uma" <uma.shankar@intel.com> wrote:
> >> Yeah, writing 0 is done with an intention to disable it but that’s not the way to
> >> have this option disabled. Infact there is no reason to write to it for DP1.4+ if sink
> >> is compliant.
> >
> > The change looks ok and aligns with spec, its
> > Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>
> Ville, any further objections or concerns? Okay to merge?
I guess a small comment on why we're avoiding the BW_SET in there might
be good idea, lest we forget and try to reunify the two branches by
accident. But otherwise seems fine.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2023-12-05 15:02 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-12-01 13:41 [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select Jani Nikula
2023-12-01 14:41 ` Ville Syrjälä
2023-12-04 9:57 ` Jani Nikula
2023-12-04 13:59 ` Manna, Animesh
2023-12-04 16:34 ` Shankar, Uma
2023-12-04 16:48 ` Jani Nikula
2023-12-04 16:52 ` Shankar, Uma
2023-12-05 12:00 ` Shankar, Uma
2023-12-05 12:50 ` Jani Nikula
2023-12-05 15:01 ` Ville Syrjälä
2023-12-01 23:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2023-12-03 4:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).