* [Intel-gfx] [PATCH 1/7] drm/i915: Settle on "adl-x" in WA comments @ 2021-07-08 21:18 José Roberto de Souza 2021-07-08 21:18 ` [Intel-gfx] [PATCH 2/7] drm/i915: Implement Wa_1508744258 José Roberto de Souza ` (9 more replies) 0 siblings, 10 replies; 21+ messages in thread From: José Roberto de Souza @ 2021-07-08 21:18 UTC (permalink / raw) To: intel-gfx; +Cc: Lucas De Marchi From: Lucas De Marchi <lucas.demarchi@intel.com> Most of the places are using this format so lets consolidate it. Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +- drivers/gpu/drm/i915/display/intel_cursor.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 10 +++++----- drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 7 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index df2d8ce4a12f6..71067a62264de 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2878,7 +2878,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; dev_priv->display.calc_voltage_level = tgl_calc_voltage_level; - /* Wa_22011320316:adlp[a0] */ + /* Wa_22011320316:adl-p[a0] */ if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) dev_priv->cdclk.table = adlp_a_step_cdclk_table; else diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index bb61e736de911..f61a25fb87e90 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -383,7 +383,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, if (plane_state->hw.rotation & DRM_MODE_ROTATE_180) cntl |= MCURSOR_ROTATE_180; - /* Wa_22012358565:adlp */ + /* Wa_22012358565:adl-p */ if (DISPLAY_VER(dev_priv) == 13) cntl |= MCURSOR_ARB_SLOTS(1); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 026c28c612f07..65ddb6ca16e67 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -975,7 +975,7 @@ void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state) /* FIXME: assert CPU port conditions for SNB+ */ } - /* Wa_22012358565:adlp */ + /* Wa_22012358565:adl-p */ if (DISPLAY_VER(dev_priv) == 13) intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 0, PIPE_ARB_USE_PROG_SLOTS); diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 9643624fe160d..4dfe1dceb8635 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -545,7 +545,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1); val |= intel_psr2_get_tp_time(intel_dp); - /* Wa_22012278275:adlp */ + /* Wa_22012278275:adl-p */ if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D1)) { static const u8 map[] = { 2, /* 5 lines */ @@ -733,7 +733,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) return; - /* Wa_16011303918:adlp */ + /* Wa_16011303918:adl-p */ if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) return; @@ -965,7 +965,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } - /* Wa_16011303918:adlp */ + /* Wa_16011303918:adl-p */ if (crtc_state->vrr.enable && IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) { drm_dbg_kms(&dev_priv->drm, @@ -1160,7 +1160,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp) intel_dp->psr.psr2_sel_fetch_enabled ? IGNORE_PSR2_HW_TRACKING : 0); - /* Wa_16011168373:adlp */ + /* Wa_16011168373:adl-p */ if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) && intel_dp->psr.psr2_enabled) intel_de_rmw(dev_priv, @@ -1346,7 +1346,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) intel_de_rmw(dev_priv, CHICKEN_PAR1_1, DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0); - /* Wa_16011168373:adlp */ + /* Wa_16011168373:adl-p */ if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) && intel_dp->psr.psr2_enabled) intel_de_rmw(dev_priv, diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index c7263f4ff11d7..628b678d9a71c 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -926,7 +926,7 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, else if (key->flags & I915_SET_COLORKEY_SOURCE) plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; - /* Wa_22012358565:adlp */ + /* Wa_22012358565:adl-p */ if (DISPLAY_VER(dev_priv) == 13) plane_ctl |= adlp_plane_ctl_arb_slots(plane_state); diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index d9a5a445ceecd..e5e3f820074a9 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1078,7 +1078,7 @@ gen12_gt_workarounds_init(struct drm_i915_private *i915, { icl_wa_init_mcr(i915, wal); - /* Wa_14011060649:tgl,rkl,dg1,adls,adl-p */ + /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */ wa_14011060649(i915, wal); } diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 5fdb96e7d2668..0cbb79452fcf9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7356,7 +7356,7 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv) static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) { - /* Wa_1409120013:tgl,rkl,adl_s,dg1 */ + /* Wa_1409120013:tgl,rkl,adl-s,dg1 */ if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, @@ -7367,7 +7367,7 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) | TGL_VRH_GATING_DIS); - /* Wa_14011059788:tgl,rkl,adl_s,dg1,adl-p */ + /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ intel_uncore_rmw(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN, 0, DFR_DISABLE); -- 2.32.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 2/7] drm/i915: Implement Wa_1508744258 2021-07-08 21:18 [Intel-gfx] [PATCH 1/7] drm/i915: Settle on "adl-x" in WA comments José Roberto de Souza @ 2021-07-08 21:18 ` José Roberto de Souza 2021-07-10 5:06 ` Matt Roper 2021-08-12 3:27 ` Timo Aaltonen 2021-07-08 21:18 ` [Intel-gfx] [PATCH 3/7] drm/i915/adl_s: Extend Wa_1406941453 José Roberto de Souza ` (8 subsequent siblings) 9 siblings, 2 replies; 21+ messages in thread From: José Roberto de Souza @ 2021-07-08 21:18 UTC (permalink / raw) To: intel-gfx Same bit was required for Wa_14012131227 in DG1 now it is also required as Wa_1508744258 to TGL, RKL, DG1, ADL-S and ADL-P. Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index e5e3f820074a9..c346229e2be00 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -670,6 +670,13 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, FF_MODE2_GS_TIMER_MASK, FF_MODE2_GS_TIMER_224, 0); + + /* + * Wa_14012131227:dg1 + * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p + */ + wa_masked_en(wal, GEN7_COMMON_SLICE_CHICKEN1, + GEN9_RHWO_OPTIMIZATION_DISABLE); } static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, -- 2.32.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 2/7] drm/i915: Implement Wa_1508744258 2021-07-08 21:18 ` [Intel-gfx] [PATCH 2/7] drm/i915: Implement Wa_1508744258 José Roberto de Souza @ 2021-07-10 5:06 ` Matt Roper 2021-08-12 3:27 ` Timo Aaltonen 1 sibling, 0 replies; 21+ messages in thread From: Matt Roper @ 2021-07-10 5:06 UTC (permalink / raw) To: José Roberto de Souza; +Cc: intel-gfx On Thu, Jul 08, 2021 at 02:18:22PM -0700, José Roberto de Souza wrote: > Same bit was required for Wa_14012131227 in DG1 now it is also This is a DG1-specific number; the general lineage number given here and in the comment should be 22011054531 (and this lineage number does apply to TGL, RKL, ADL-S, ADL-P, and DG1 too). > required as Wa_1508744258 to TGL, RKL, DG1, ADL-S and ADL-P. Technically it's still working its way through the process to become official on RKL, but given that it's already an official workaround under the other number, I think it's safe to assume this one will become official too. > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index e5e3f820074a9..c346229e2be00 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -670,6 +670,13 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, > FF_MODE2_GS_TIMER_MASK, > FF_MODE2_GS_TIMER_224, > 0); > + > + /* > + * Wa_14012131227:dg1 > + * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p > + */ > + wa_masked_en(wal, GEN7_COMMON_SLICE_CHICKEN1, > + GEN9_RHWO_OPTIMIZATION_DISABLE); > } > > static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, > -- > 2.32.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 2/7] drm/i915: Implement Wa_1508744258 2021-07-08 21:18 ` [Intel-gfx] [PATCH 2/7] drm/i915: Implement Wa_1508744258 José Roberto de Souza 2021-07-10 5:06 ` Matt Roper @ 2021-08-12 3:27 ` Timo Aaltonen 2021-08-12 6:29 ` Timo Aaltonen 1 sibling, 1 reply; 21+ messages in thread From: Timo Aaltonen @ 2021-08-12 3:27 UTC (permalink / raw) To: José Roberto de Souza, intel-gfx On 9.7.2021 0.18, José Roberto de Souza wrote: > Same bit was required for Wa_14012131227 in DG1 now it is also > required as Wa_1508744258 to TGL, RKL, DG1, ADL-S and ADL-P. > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index e5e3f820074a9..c346229e2be00 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -670,6 +670,13 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, > FF_MODE2_GS_TIMER_MASK, > FF_MODE2_GS_TIMER_224, > 0); > + > + /* > + * Wa_14012131227:dg1 > + * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p > + */ > + wa_masked_en(wal, GEN7_COMMON_SLICE_CHICKEN1, > + GEN9_RHWO_OPTIMIZATION_DISABLE); > } > > static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, > Hi, I don't see this (or patches 3, 4) in drm-intel-next, are they not needed anymore? -- t ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 2/7] drm/i915: Implement Wa_1508744258 2021-08-12 3:27 ` Timo Aaltonen @ 2021-08-12 6:29 ` Timo Aaltonen 2021-08-12 15:56 ` Souza, Jose 0 siblings, 1 reply; 21+ messages in thread From: Timo Aaltonen @ 2021-08-12 6:29 UTC (permalink / raw) To: José Roberto de Souza, intel-gfx On 12.8.2021 6.27, Timo Aaltonen wrote: > On 9.7.2021 0.18, José Roberto de Souza wrote: >> Same bit was required for Wa_14012131227 in DG1 now it is also >> required as Wa_1508744258 to TGL, RKL, DG1, ADL-S and ADL-P. >> >> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> >> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> >> --- >> drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c >> b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> index e5e3f820074a9..c346229e2be00 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> @@ -670,6 +670,13 @@ static void gen12_ctx_workarounds_init(struct >> intel_engine_cs *engine, >> FF_MODE2_GS_TIMER_MASK, >> FF_MODE2_GS_TIMER_224, >> 0); >> + >> + /* >> + * Wa_14012131227:dg1 >> + * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p >> + */ >> + wa_masked_en(wal, GEN7_COMMON_SLICE_CHICKEN1, >> + GEN9_RHWO_OPTIMIZATION_DISABLE); >> } >> static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, >> > > Hi, I don't see this (or patches 3, 4) in drm-intel-next, are they not > needed anymore? but is in drm-intel-gt-next.. -- t ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 2/7] drm/i915: Implement Wa_1508744258 2021-08-12 6:29 ` Timo Aaltonen @ 2021-08-12 15:56 ` Souza, Jose 0 siblings, 0 replies; 21+ messages in thread From: Souza, Jose @ 2021-08-12 15:56 UTC (permalink / raw) To: tjaalton, intel-gfx On Thu, 2021-08-12 at 09:29 +0300, Timo Aaltonen wrote: > On 12.8.2021 6.27, Timo Aaltonen wrote: > > On 9.7.2021 0.18, José Roberto de Souza wrote: > > > Same bit was required for Wa_14012131227 in DG1 now it is also > > > required as Wa_1508744258 to TGL, RKL, DG1, ADL-S and ADL-P. > > > > > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > > --- > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++ > > > 1 file changed, 7 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > index e5e3f820074a9..c346229e2be00 100644 > > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > @@ -670,6 +670,13 @@ static void gen12_ctx_workarounds_init(struct > > > intel_engine_cs *engine, > > > FF_MODE2_GS_TIMER_MASK, > > > FF_MODE2_GS_TIMER_224, > > > 0); > > > + > > > + /* > > > + * Wa_14012131227:dg1 > > > + * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p > > > + */ > > > + wa_masked_en(wal, GEN7_COMMON_SLICE_CHICKEN1, > > > + GEN9_RHWO_OPTIMIZATION_DISABLE); > > > } > > > static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, > > > > > > > Hi, I don't see this (or patches 3, 4) in drm-intel-next, are they not > > needed anymore? > > but is in drm-intel-gt-next.. Yep, display code can go to drm-intel-next and gt code goes to drm-intel-gt-next > > ^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 3/7] drm/i915/adl_s: Extend Wa_1406941453 2021-07-08 21:18 [Intel-gfx] [PATCH 1/7] drm/i915: Settle on "adl-x" in WA comments José Roberto de Souza 2021-07-08 21:18 ` [Intel-gfx] [PATCH 2/7] drm/i915: Implement Wa_1508744258 José Roberto de Souza @ 2021-07-08 21:18 ` José Roberto de Souza 2021-07-10 5:07 ` Matt Roper 2021-07-08 21:18 ` [Intel-gfx] [PATCH 4/7] drm/i915: Limit maximum number of memory channels José Roberto de Souza ` (7 subsequent siblings) 9 siblings, 1 reply; 21+ messages in thread From: José Roberto de Souza @ 2021-07-08 21:18 UTC (permalink / raw) To: intel-gfx BSpec: 54370 Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index c346229e2be00..72562c233ad20 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1677,8 +1677,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN8_RC_SEMA_IDLE_MSG_DISABLE); } - if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { - /* Wa_1406941453:tgl,rkl,dg1 */ + if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || + IS_ALDERLAKE_S(i915)) { + /* Wa_1406941453:tgl,rkl,dg1,adl-s */ wa_masked_en(wal, GEN10_SAMPLER_MODE, ENABLE_SMALLPL); -- 2.32.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 3/7] drm/i915/adl_s: Extend Wa_1406941453 2021-07-08 21:18 ` [Intel-gfx] [PATCH 3/7] drm/i915/adl_s: Extend Wa_1406941453 José Roberto de Souza @ 2021-07-10 5:07 ` Matt Roper 0 siblings, 0 replies; 21+ messages in thread From: Matt Roper @ 2021-07-10 5:07 UTC (permalink / raw) To: José Roberto de Souza; +Cc: intel-gfx On Thu, Jul 08, 2021 at 02:18:23PM -0700, José Roberto de Souza wrote: > BSpec: 54370 > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index c346229e2be00..72562c233ad20 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1677,8 +1677,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > GEN8_RC_SEMA_IDLE_MSG_DISABLE); > } > > - if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { > - /* Wa_1406941453:tgl,rkl,dg1 */ > + if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || > + IS_ALDERLAKE_S(i915)) { > + /* Wa_1406941453:tgl,rkl,dg1,adl-s */ > wa_masked_en(wal, > GEN10_SAMPLER_MODE, > ENABLE_SMALLPL); > -- > 2.32.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 4/7] drm/i915: Limit maximum number of memory channels 2021-07-08 21:18 [Intel-gfx] [PATCH 1/7] drm/i915: Settle on "adl-x" in WA comments José Roberto de Souza 2021-07-08 21:18 ` [Intel-gfx] [PATCH 2/7] drm/i915: Implement Wa_1508744258 José Roberto de Souza 2021-07-08 21:18 ` [Intel-gfx] [PATCH 3/7] drm/i915/adl_s: Extend Wa_1406941453 José Roberto de Souza @ 2021-07-08 21:18 ` José Roberto de Souza 2021-07-08 21:18 ` [Intel-gfx] [PATCH 5/7] drm/i915: Limit Wa_22010178259 to affected platforms José Roberto de Souza ` (6 subsequent siblings) 9 siblings, 0 replies; 21+ messages in thread From: José Roberto de Souza @ 2021-07-08 21:18 UTC (permalink / raw) To: intel-gfx Alderlake-P PCODE is returning 4 memory channels while it has a maximum of 2. So adding this limit and printing a debug message but the real fix will need to come from PCODE. HSDES: 22013272110 Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/intel_dram.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c index 879b0f007be31..de1d426627ef1 100644 --- a/drivers/gpu/drm/i915/intel_dram.c +++ b/drivers/gpu/drm/i915/intel_dram.c @@ -467,6 +467,10 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv) } dram_info->num_channels = (val & 0xf0) >> 4; + if (dram_info->num_channels > 2) { + drm_info(&dev_priv->drm, "More DRAM channels than expected, setting to max.\n"); + dram_info->num_channels = 2; + } dram_info->num_qgv_points = (val & 0xf00) >> 8; return 0; -- 2.32.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 5/7] drm/i915: Limit Wa_22010178259 to affected platforms 2021-07-08 21:18 [Intel-gfx] [PATCH 1/7] drm/i915: Settle on "adl-x" in WA comments José Roberto de Souza ` (2 preceding siblings ...) 2021-07-08 21:18 ` [Intel-gfx] [PATCH 4/7] drm/i915: Limit maximum number of memory channels José Roberto de Souza @ 2021-07-08 21:18 ` José Roberto de Souza 2021-07-10 5:29 ` Matt Roper 2021-07-08 21:18 ` [Intel-gfx] [PATCH 6/7] drm/i915/display/adl_p: Correctly program MBUS DBOX A credits José Roberto de Souza ` (5 subsequent siblings) 9 siblings, 1 reply; 21+ messages in thread From: José Roberto de Souza @ 2021-07-08 21:18 UTC (permalink / raw) To: intel-gfx This workaround is not needed for platforms with display 13. Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_display_power.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 285380079aab2..6fc766da66054 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -5822,10 +5822,11 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i), table[config].page_mask); - /* Wa_22010178259:tgl,rkl */ - intel_de_rmw(dev_priv, BW_BUDDY_CTL(i), - BW_BUDDY_TLB_REQ_TIMER_MASK, - BW_BUDDY_TLB_REQ_TIMER(0x8)); + /* Wa_22010178259:tgl,dg1,rkl,adl-s */ + if (DISPLAY_VER(dev_priv) == 12) + intel_de_rmw(dev_priv, BW_BUDDY_CTL(i), + BW_BUDDY_TLB_REQ_TIMER_MASK, + BW_BUDDY_TLB_REQ_TIMER(0x8)); } } } -- 2.32.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 5/7] drm/i915: Limit Wa_22010178259 to affected platforms 2021-07-08 21:18 ` [Intel-gfx] [PATCH 5/7] drm/i915: Limit Wa_22010178259 to affected platforms José Roberto de Souza @ 2021-07-10 5:29 ` Matt Roper 0 siblings, 0 replies; 21+ messages in thread From: Matt Roper @ 2021-07-10 5:29 UTC (permalink / raw) To: José Roberto de Souza; +Cc: intel-gfx On Thu, Jul 08, 2021 at 02:18:25PM -0700, José Roberto de Souza wrote: > This workaround is not needed for platforms with display 13. > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display_power.c | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index 285380079aab2..6fc766da66054 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -5822,10 +5822,11 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) > intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i), > table[config].page_mask); > > - /* Wa_22010178259:tgl,rkl */ > - intel_de_rmw(dev_priv, BW_BUDDY_CTL(i), > - BW_BUDDY_TLB_REQ_TIMER_MASK, > - BW_BUDDY_TLB_REQ_TIMER(0x8)); > + /* Wa_22010178259:tgl,dg1,rkl,adl-s */ > + if (DISPLAY_VER(dev_priv) == 12) > + intel_de_rmw(dev_priv, BW_BUDDY_CTL(i), > + BW_BUDDY_TLB_REQ_TIMER_MASK, > + BW_BUDDY_TLB_REQ_TIMER(0x8)); > } > } > } > -- > 2.32.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 6/7] drm/i915/display/adl_p: Correctly program MBUS DBOX A credits 2021-07-08 21:18 [Intel-gfx] [PATCH 1/7] drm/i915: Settle on "adl-x" in WA comments José Roberto de Souza ` (3 preceding siblings ...) 2021-07-08 21:18 ` [Intel-gfx] [PATCH 5/7] drm/i915: Limit Wa_22010178259 to affected platforms José Roberto de Souza @ 2021-07-08 21:18 ` José Roberto de Souza 2021-07-10 5:41 ` Matt Roper 2021-07-08 21:18 ` [Intel-gfx] [PATCH 7/7] drm/i915/display/xelpd: Exetend Wa_14011508470 José Roberto de Souza ` (4 subsequent siblings) 9 siblings, 1 reply; 21+ messages in thread From: José Roberto de Souza @ 2021-07-08 21:18 UTC (permalink / raw) To: intel-gfx Alderlake-P have different values for MBUS DBOX A credits depending if MBUS join is enabled or not. BSpec: 50343 BSpec: 54369 Cc: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 65ddb6ca16e67..fe380896eb99e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3400,13 +3400,17 @@ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); } -static void icl_pipe_mbus_enable(struct intel_crtc *crtc) +static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; u32 val; - val = MBUS_DBOX_A_CREDIT(2); + /* Wa_22010947358:adl-p */ + if (IS_ALDERLAKE_P(dev_priv)) + val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); + else + val = MBUS_DBOX_A_CREDIT(2); if (DISPLAY_VER(dev_priv) >= 12) { val |= MBUS_DBOX_BW_CREDIT(2); @@ -3561,8 +3565,12 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, if (dev_priv->display.initial_watermarks) dev_priv->display.initial_watermarks(state, crtc); - if (DISPLAY_VER(dev_priv) >= 11) - icl_pipe_mbus_enable(crtc); + if (DISPLAY_VER(dev_priv) >= 11) { + const struct intel_dbuf_state *dbuf_state = + intel_atomic_get_new_dbuf_state(state); + + icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus); + } if (new_crtc_state->bigjoiner_slave) intel_crtc_vblank_on(new_crtc_state); -- 2.32.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 6/7] drm/i915/display/adl_p: Correctly program MBUS DBOX A credits 2021-07-08 21:18 ` [Intel-gfx] [PATCH 6/7] drm/i915/display/adl_p: Correctly program MBUS DBOX A credits José Roberto de Souza @ 2021-07-10 5:41 ` Matt Roper 2021-08-03 20:19 ` Souza, Jose 0 siblings, 1 reply; 21+ messages in thread From: Matt Roper @ 2021-07-10 5:41 UTC (permalink / raw) To: José Roberto de Souza; +Cc: intel-gfx On Thu, Jul 08, 2021 at 02:18:26PM -0700, José Roberto de Souza wrote: > Alderlake-P have different values for MBUS DBOX A credits depending > if MBUS join is enabled or not. > > BSpec: 50343 > BSpec: 54369 > Cc: Matt Atwood <matthew.s.atwood@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 16 ++++++++++++---- > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 65ddb6ca16e67..fe380896eb99e 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -3400,13 +3400,17 @@ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, > intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); > } > > -static void icl_pipe_mbus_enable(struct intel_crtc *crtc) > +static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus) > { > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > enum pipe pipe = crtc->pipe; > u32 val; > > - val = MBUS_DBOX_A_CREDIT(2); > + /* Wa_22010947358:adl-p */ > + if (IS_ALDERLAKE_P(dev_priv)) > + val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); > + else > + val = MBUS_DBOX_A_CREDIT(2); If we're in single-pipe / joined-mbus mode, then we'll program the credits to 6. If we later turn on another pipe, reallocate the DDB, and turn off joined-mbus mode, we'll set that other pipe's credits to 4 during the sequence of hsw_crtc_enable() -> icl_pipe_mbus_enable(). But don't we also need to go back re-program the credits down to 4 on the first pipe too (which is already enabled and won't be re-calling hsw_crtc_enable())? I might be missing something; it's been a while since I really looked at any of the dbuf stuff... Matt > > if (DISPLAY_VER(dev_priv) >= 12) { > val |= MBUS_DBOX_BW_CREDIT(2); > @@ -3561,8 +3565,12 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, > if (dev_priv->display.initial_watermarks) > dev_priv->display.initial_watermarks(state, crtc); > > - if (DISPLAY_VER(dev_priv) >= 11) > - icl_pipe_mbus_enable(crtc); > + if (DISPLAY_VER(dev_priv) >= 11) { > + const struct intel_dbuf_state *dbuf_state = > + intel_atomic_get_new_dbuf_state(state); > + > + icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus); > + } > > if (new_crtc_state->bigjoiner_slave) > intel_crtc_vblank_on(new_crtc_state); > -- > 2.32.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 6/7] drm/i915/display/adl_p: Correctly program MBUS DBOX A credits 2021-07-10 5:41 ` Matt Roper @ 2021-08-03 20:19 ` Souza, Jose 2021-08-03 22:39 ` Matt Roper 0 siblings, 1 reply; 21+ messages in thread From: Souza, Jose @ 2021-08-03 20:19 UTC (permalink / raw) To: Roper, Matthew D; +Cc: intel-gfx On Fri, 2021-07-09 at 22:41 -0700, Matt Roper wrote: > On Thu, Jul 08, 2021 at 02:18:26PM -0700, José Roberto de Souza wrote: > > Alderlake-P have different values for MBUS DBOX A credits depending > > if MBUS join is enabled or not. > > > > BSpec: 50343 > > BSpec: 54369 > > Cc: Matt Atwood <matthew.s.atwood@intel.com> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 16 ++++++++++++---- > > 1 file changed, 12 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index 65ddb6ca16e67..fe380896eb99e 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -3400,13 +3400,17 @@ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, > > intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); > > } > > > > -static void icl_pipe_mbus_enable(struct intel_crtc *crtc) > > +static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus) > > { > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > enum pipe pipe = crtc->pipe; > > u32 val; > > > > - val = MBUS_DBOX_A_CREDIT(2); > > + /* Wa_22010947358:adl-p */ > > + if (IS_ALDERLAKE_P(dev_priv)) > > + val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); > > + else > > + val = MBUS_DBOX_A_CREDIT(2); > > If we're in single-pipe / joined-mbus mode, then we'll program the > credits to 6. If we later turn on another pipe, reallocate the DDB, and > turn off joined-mbus mode, we'll set that other pipe's credits to 4 > during the sequence of hsw_crtc_enable() -> icl_pipe_mbus_enable(). But > don't we also need to go back re-program the credits down to 4 on the > first pipe too (which is already enabled and won't be re-calling > hsw_crtc_enable())? > > I might be missing something; it's been a while since I really looked at > any of the dbuf stuff... skl_compute_ddb() is handling this cases, it will force a modeset in all pipes in cases like this. > > > Matt > > > > > if (DISPLAY_VER(dev_priv) >= 12) { > > val |= MBUS_DBOX_BW_CREDIT(2); > > @@ -3561,8 +3565,12 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, > > if (dev_priv->display.initial_watermarks) > > dev_priv->display.initial_watermarks(state, crtc); > > > > - if (DISPLAY_VER(dev_priv) >= 11) > > - icl_pipe_mbus_enable(crtc); > > + if (DISPLAY_VER(dev_priv) >= 11) { > > + const struct intel_dbuf_state *dbuf_state = > > + intel_atomic_get_new_dbuf_state(state); > > + > > + icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus); > > + } > > > > if (new_crtc_state->bigjoiner_slave) > > intel_crtc_vblank_on(new_crtc_state); > > -- > > 2.32.0 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 6/7] drm/i915/display/adl_p: Correctly program MBUS DBOX A credits 2021-08-03 20:19 ` Souza, Jose @ 2021-08-03 22:39 ` Matt Roper 0 siblings, 0 replies; 21+ messages in thread From: Matt Roper @ 2021-08-03 22:39 UTC (permalink / raw) To: Souza, Jose; +Cc: intel-gfx On Tue, Aug 03, 2021 at 01:19:12PM -0700, Souza, Jose wrote: > On Fri, 2021-07-09 at 22:41 -0700, Matt Roper wrote: > > On Thu, Jul 08, 2021 at 02:18:26PM -0700, José Roberto de Souza wrote: > > > Alderlake-P have different values for MBUS DBOX A credits depending > > > if MBUS join is enabled or not. > > > > > > BSpec: 50343 > > > BSpec: 54369 > > > Cc: Matt Atwood <matthew.s.atwood@intel.com> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_display.c | 16 ++++++++++++---- > > > 1 file changed, 12 insertions(+), 4 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > > index 65ddb6ca16e67..fe380896eb99e 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > @@ -3400,13 +3400,17 @@ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, > > > intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); > > > } > > > > > > -static void icl_pipe_mbus_enable(struct intel_crtc *crtc) > > > +static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus) > > > { > > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > > enum pipe pipe = crtc->pipe; > > > u32 val; > > > > > > - val = MBUS_DBOX_A_CREDIT(2); > > > + /* Wa_22010947358:adl-p */ > > > + if (IS_ALDERLAKE_P(dev_priv)) > > > + val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); > > > + else > > > + val = MBUS_DBOX_A_CREDIT(2); > > > > If we're in single-pipe / joined-mbus mode, then we'll program the > > credits to 6. If we later turn on another pipe, reallocate the DDB, and > > turn off joined-mbus mode, we'll set that other pipe's credits to 4 > > during the sequence of hsw_crtc_enable() -> icl_pipe_mbus_enable(). But > > don't we also need to go back re-program the credits down to 4 on the > > first pipe too (which is already enabled and won't be re-calling > > hsw_crtc_enable())? > > > > I might be missing something; it's been a while since I really looked at > > any of the dbuf stuff... > > skl_compute_ddb() is handling this cases, it will force a modeset in all pipes in cases like this. > Ah, that's right. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > > > > > > Matt > > > > > > > > if (DISPLAY_VER(dev_priv) >= 12) { > > > val |= MBUS_DBOX_BW_CREDIT(2); > > > @@ -3561,8 +3565,12 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, > > > if (dev_priv->display.initial_watermarks) > > > dev_priv->display.initial_watermarks(state, crtc); > > > > > > - if (DISPLAY_VER(dev_priv) >= 11) > > > - icl_pipe_mbus_enable(crtc); > > > + if (DISPLAY_VER(dev_priv) >= 11) { > > > + const struct intel_dbuf_state *dbuf_state = > > > + intel_atomic_get_new_dbuf_state(state); > > > + > > > + icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus); > > > + } > > > > > > if (new_crtc_state->bigjoiner_slave) > > > intel_crtc_vblank_on(new_crtc_state); > > > -- > > > 2.32.0 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH 7/7] drm/i915/display/xelpd: Exetend Wa_14011508470 2021-07-08 21:18 [Intel-gfx] [PATCH 1/7] drm/i915: Settle on "adl-x" in WA comments José Roberto de Souza ` (4 preceding siblings ...) 2021-07-08 21:18 ` [Intel-gfx] [PATCH 6/7] drm/i915/display/adl_p: Correctly program MBUS DBOX A credits José Roberto de Souza @ 2021-07-08 21:18 ` José Roberto de Souza 2021-07-10 5:42 ` Matt Roper 2021-07-08 23:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/7] drm/i915: Settle on "adl-x" in WA comments Patchwork ` (3 subsequent siblings) 9 siblings, 1 reply; 21+ messages in thread From: José Roberto de Souza @ 2021-07-08 21:18 UTC (permalink / raw) To: intel-gfx This workaround is also applicable to xelpd display so extending it. Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_display_power.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 6fc766da66054..d92db471411e5 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -5883,8 +5883,8 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, if (resume && intel_dmc_has_payload(dev_priv)) intel_dmc_load_program(dev_priv); - /* Wa_14011508470 */ - if (DISPLAY_VER(dev_priv) == 12) { + /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p */ + if (DISPLAY_VER(dev_priv) >= 12) { val = DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM | DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR; intel_uncore_rmw(&dev_priv->uncore, GEN11_CHICKEN_DCPR_2, 0, val); -- 2.32.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 7/7] drm/i915/display/xelpd: Exetend Wa_14011508470 2021-07-08 21:18 ` [Intel-gfx] [PATCH 7/7] drm/i915/display/xelpd: Exetend Wa_14011508470 José Roberto de Souza @ 2021-07-10 5:42 ` Matt Roper 0 siblings, 0 replies; 21+ messages in thread From: Matt Roper @ 2021-07-10 5:42 UTC (permalink / raw) To: José Roberto de Souza; +Cc: intel-gfx On Thu, Jul 08, 2021 at 02:18:27PM -0700, José Roberto de Souza wrote: > This workaround is also applicable to xelpd display so extending it. > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display_power.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index 6fc766da66054..d92db471411e5 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -5883,8 +5883,8 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, > if (resume && intel_dmc_has_payload(dev_priv)) > intel_dmc_load_program(dev_priv); > > - /* Wa_14011508470 */ > - if (DISPLAY_VER(dev_priv) == 12) { > + /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p */ > + if (DISPLAY_VER(dev_priv) >= 12) { > val = DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM | > DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR; > intel_uncore_rmw(&dev_priv->uncore, GEN11_CHICKEN_DCPR_2, 0, val); > -- > 2.32.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/7] drm/i915: Settle on "adl-x" in WA comments 2021-07-08 21:18 [Intel-gfx] [PATCH 1/7] drm/i915: Settle on "adl-x" in WA comments José Roberto de Souza ` (5 preceding siblings ...) 2021-07-08 21:18 ` [Intel-gfx] [PATCH 7/7] drm/i915/display/xelpd: Exetend Wa_14011508470 José Roberto de Souza @ 2021-07-08 23:32 ` Patchwork 2021-07-08 23:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork ` (2 subsequent siblings) 9 siblings, 0 replies; 21+ messages in thread From: Patchwork @ 2021-07-08 23:32 UTC (permalink / raw) To: José Roberto de Souza; +Cc: intel-gfx == Series Details == Series: series starting with [1/7] drm/i915: Settle on "adl-x" in WA comments URL : https://patchwork.freedesktop.org/series/92342/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1896:21: expected struct i915_vma *[assigned] vma +drivers/gpu/drm/i915/display/intel_display.c:1896:21: got void [noderef] __iomem *[assigned] iomem +drivers/gpu/drm/i915/display/intel_display.c:1896:21: warning: incorrect type in assignment (different address spaces) _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/7] drm/i915: Settle on "adl-x" in WA comments 2021-07-08 21:18 [Intel-gfx] [PATCH 1/7] drm/i915: Settle on "adl-x" in WA comments José Roberto de Souza ` (6 preceding siblings ...) 2021-07-08 23:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/7] drm/i915: Settle on "adl-x" in WA comments Patchwork @ 2021-07-08 23:57 ` Patchwork 2021-07-09 14:30 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-07-10 4:55 ` [Intel-gfx] [PATCH 1/7] " Matt Roper 9 siblings, 0 replies; 21+ messages in thread From: Patchwork @ 2021-07-08 23:57 UTC (permalink / raw) To: José Roberto de Souza; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 1839 bytes --] == Series Details == Series: series starting with [1/7] drm/i915: Settle on "adl-x" in WA comments URL : https://patchwork.freedesktop.org/series/92342/ State : success == Summary == CI Bug Log - changes from CI_DRM_10320 -> Patchwork_20558 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/index.html Known issues ------------ Here are the changes found in Patchwork_20558 that come from known issues: ### IGT changes ### {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 Participating hosts (40 -> 39) ------------------------------ Missing (1): fi-bsw-cyan Build changes ------------- * Linux: CI_DRM_10320 -> Patchwork_20558 CI-20190529: 20190529 CI_DRM_10320: 7d61ab4a59bcbb206324b6a430748b4c15dd8adb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6132: 61fb9cdf2a9132e3618c8b08b9d20fec0c347831 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_20558: 0be142e780934cd09e46b4699fe3f7cd9b7adde0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0be142e78093 drm/i915/display/xelpd: Exetend Wa_14011508470 8d9f68df0f34 drm/i915/display/adl_p: Correctly program MBUS DBOX A credits ccd65a2b8785 drm/i915: Limit Wa_22010178259 to affected platforms 4818897f7082 drm/i915: Limit maximum number of memory channels 1a869323ea02 drm/i915/adl_s: Extend Wa_1406941453 6cea025795d1 drm/i915: Implement Wa_1508744258 78692bfbbdb4 drm/i915: Settle on "adl-x" in WA comments == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/index.html [-- Attachment #1.2: Type: text/html, Size: 2393 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/7] drm/i915: Settle on "adl-x" in WA comments 2021-07-08 21:18 [Intel-gfx] [PATCH 1/7] drm/i915: Settle on "adl-x" in WA comments José Roberto de Souza ` (7 preceding siblings ...) 2021-07-08 23:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2021-07-09 14:30 ` Patchwork 2021-07-10 4:55 ` [Intel-gfx] [PATCH 1/7] " Matt Roper 9 siblings, 0 replies; 21+ messages in thread From: Patchwork @ 2021-07-09 14:30 UTC (permalink / raw) To: José Roberto de Souza; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 30292 bytes --] == Series Details == Series: series starting with [1/7] drm/i915: Settle on "adl-x" in WA comments URL : https://patchwork.freedesktop.org/series/92342/ State : success == Summary == CI Bug Log - changes from CI_DRM_10320_full -> Patchwork_20558_full ==================================================== Summary ------- **SUCCESS** No regressions found. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_20558_full: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@gem_exec_fair@basic-none-solo@rcs0: - {shard-rkl}: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-rkl-2/igt@gem_exec_fair@basic-none-solo@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-rkl-5/igt@gem_exec_fair@basic-none-solo@rcs0.html * igt@gem_exec_whisper@basic-fds-forked-all: - {shard-rkl}: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-rkl-1/igt@gem_exec_whisper@basic-fds-forked-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-rkl-2/igt@gem_exec_whisper@basic-fds-forked-all.html * igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs: - {shard-rkl}: [FAIL][5] ([i915#3678]) -> [SKIP][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-rkl-2/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-rkl-6/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs.html New tests --------- New tests have been introduced between CI_DRM_10320_full and Patchwork_20558_full: ### New IGT tests (2) ### * igt@gem_pread@bench: - Statuses : 6 pass(s) 1 skip(s) - Exec time: [0.0, 12.18] s * igt@i915_selftest@live@gem_migrate: - Statuses : 7 pass(s) - Exec time: [0.53, 5.11] s Known issues ------------ Here are the changes found in Patchwork_20558_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_create@create-clear: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#1888] / [i915#3160]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-glk7/igt@gem_create@create-clear.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-glk4/igt@gem_create@create-clear.html * igt@gem_ctx_persistence@engines-mixed: - shard-snb: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1099]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-snb5/igt@gem_ctx_persistence@engines-mixed.html * igt@gem_ctx_shared@q-in-order: - shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271]) +253 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-snb7/igt@gem_ctx_shared@q-in-order.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][11] -> [TIMEOUT][12] ([i915#2369] / [i915#3063] / [i915#3648]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-tglb2/igt@gem_eio@unwedge-stress.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-tglb3/igt@gem_eio@unwedge-stress.html * igt@gem_exec_fair@basic-deadline: - shard-skl: NOTRUN -> [FAIL][13] ([i915#2846]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-skl5/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-tglb2/igt@gem_exec_fair@basic-none-share@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-tglb2/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: [PASS][16] -> [FAIL][17] ([i915#2842]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-glk5/igt@gem_exec_fair@basic-none@rcs0.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-glk9/igt@gem_exec_fair@basic-none@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-iclb: [PASS][18] -> [FAIL][19] ([i915#2842]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-iclb6/igt@gem_exec_fair@basic-pace@vcs0.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-iclb8/igt@gem_exec_fair@basic-pace@vcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [PASS][20] -> [SKIP][21] ([fdo#109271]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-kbl3/igt@gem_exec_fair@basic-pace@vecs0.html * igt@gem_exec_params@no-vebox: - shard-skl: NOTRUN -> [SKIP][22] ([fdo#109271]) +14 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-skl10/igt@gem_exec_params@no-vebox.html * igt@gem_exec_params@secure-non-master: - shard-tglb: NOTRUN -> [SKIP][23] ([fdo#112283]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-tglb5/igt@gem_exec_params@secure-non-master.html * igt@gem_exec_reloc@basic-wide-active@rcs0: - shard-snb: NOTRUN -> [FAIL][24] ([i915#3633]) +2 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-snb2/igt@gem_exec_reloc@basic-wide-active@rcs0.html * igt@gem_mmap_gtt@big-copy-xy: - shard-glk: [PASS][25] -> [FAIL][26] ([i915#307]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-glk2/igt@gem_mmap_gtt@big-copy-xy.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-glk1/igt@gem_mmap_gtt@big-copy-xy.html * igt@gem_userptr_blits@vma-merge: - shard-kbl: NOTRUN -> [FAIL][27] ([i915#3318]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-kbl1/igt@gem_userptr_blits@vma-merge.html * igt@gen3_render_tiledy_blits: - shard-tglb: NOTRUN -> [SKIP][28] ([fdo#109289]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-tglb5/igt@gen3_render_tiledy_blits.html * igt@gen9_exec_parse@bb-start-out: - shard-tglb: NOTRUN -> [SKIP][29] ([fdo#112306]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-tglb6/igt@gen9_exec_parse@bb-start-out.html - shard-iclb: NOTRUN -> [SKIP][30] ([fdo#112306]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-iclb1/igt@gen9_exec_parse@bb-start-out.html * igt@i915_module_load@reload-with-fault-injection: - shard-skl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-skl9/igt@i915_module_load@reload-with-fault-injection.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-skl8/igt@i915_module_load@reload-with-fault-injection.html * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip: - shard-skl: NOTRUN -> [FAIL][33] ([i915#3722]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-skl6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip: - shard-tglb: NOTRUN -> [SKIP][34] ([fdo#111615]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-tglb5/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html * igt@kms_ccs@pipe-b-crc-primary-rotation-180-yf_tiled_ccs: - shard-tglb: NOTRUN -> [SKIP][35] ([i915#3689]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-tglb5/igt@kms_ccs@pipe-b-crc-primary-rotation-180-yf_tiled_ccs.html * igt@kms_ccs@pipe-d-bad-rotation-90-y_tiled_gen12_rc_ccs_cc: - shard-iclb: NOTRUN -> [SKIP][36] ([fdo#109278]) +3 similar issues [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-iclb1/igt@kms_ccs@pipe-d-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html * igt@kms_chamelium@dp-hpd-enable-disable-mode: - shard-tglb: NOTRUN -> [SKIP][37] ([fdo#109284] / [fdo#111827]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-tglb5/igt@kms_chamelium@dp-hpd-enable-disable-mode.html * igt@kms_chamelium@hdmi-crc-multiple: - shard-skl: NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-skl10/igt@kms_chamelium@hdmi-crc-multiple.html * igt@kms_chamelium@hdmi-edid-change-during-suspend: - shard-apl: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +26 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-apl2/igt@kms_chamelium@hdmi-edid-change-during-suspend.html * igt@kms_chamelium@vga-hpd-without-ddc: - shard-kbl: NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +1 similar issue [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-kbl3/igt@kms_chamelium@vga-hpd-without-ddc.html * igt@kms_color_chamelium@pipe-b-ctm-0-25: - shard-snb: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +8 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-snb7/igt@kms_color_chamelium@pipe-b-ctm-0-25.html * igt@kms_content_protection@legacy: - shard-iclb: NOTRUN -> [SKIP][42] ([fdo#109300] / [fdo#111066]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-iclb1/igt@kms_content_protection@legacy.html - shard-tglb: NOTRUN -> [SKIP][43] ([fdo#111828]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-tglb6/igt@kms_content_protection@legacy.html * igt@kms_content_protection@srm: - shard-apl: NOTRUN -> [TIMEOUT][44] ([i915#1319]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-apl1/igt@kms_content_protection@srm.html * igt@kms_cursor_crc@pipe-a-cursor-32x10-random: - shard-tglb: NOTRUN -> [SKIP][45] ([i915#3359]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-tglb6/igt@kms_cursor_crc@pipe-a-cursor-32x10-random.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][46] -> [DMESG-WARN][47] ([i915#180]) +3 similar issues [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html * igt@kms_cursor_crc@pipe-c-cursor-64x64-random: - shard-skl: [PASS][48] -> [FAIL][49] ([i915#3444]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-skl5/igt@kms_cursor_crc@pipe-c-cursor-64x64-random.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-skl10/igt@kms_cursor_crc@pipe-c-cursor-64x64-random.html * igt@kms_cursor_crc@pipe-d-cursor-32x32-sliding: - shard-kbl: NOTRUN -> [SKIP][50] ([fdo#109271]) +22 similar issues [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-kbl3/igt@kms_cursor_crc@pipe-d-cursor-32x32-sliding.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][51] -> [FAIL][52] ([i915#2346]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_cursor_legacy@pipe-d-torture-bo: - shard-apl: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#533]) +2 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-apl1/igt@kms_cursor_legacy@pipe-d-torture-bo.html * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: [PASS][54] -> [INCOMPLETE][55] ([i915#198]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-skl8/igt@kms_fbcon_fbt@psr-suspend.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-skl8/igt@kms_fbcon_fbt@psr-suspend.html * igt@kms_flip@2x-plain-flip-ts-check: - shard-tglb: NOTRUN -> [SKIP][56] ([fdo#111825]) +6 similar issues [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-tglb6/igt@kms_flip@2x-plain-flip-ts-check.html - shard-iclb: NOTRUN -> [SKIP][57] ([fdo#109274]) +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-iclb1/igt@kms_flip@2x-plain-flip-ts-check.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2: - shard-glk: [PASS][58] -> [FAIL][59] ([i915#79]) +1 similar issue [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-glk4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move: - shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109280]) +2 similar issues [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move.html * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt: - shard-glk: NOTRUN -> [SKIP][61] ([fdo#109271]) +4 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-glk4/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt.html * igt@kms_hdr@static-toggle-dpms: - shard-tglb: NOTRUN -> [SKIP][62] ([i915#1187]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-tglb5/igt@kms_hdr@static-toggle-dpms.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-apl: [PASS][63] -> [DMESG-WARN][64] ([i915#180]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-apl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-apl8/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: - shard-apl: NOTRUN -> [FAIL][65] ([fdo#108145] / [i915#265]) +4 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb: - shard-apl: NOTRUN -> [FAIL][66] ([i915#265]) +1 similar issue [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-apl3/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][67] -> [FAIL][68] ([fdo#108145] / [i915#265]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt@kms_plane_alpha_blend@pipe-c-alpha-basic: - shard-kbl: NOTRUN -> [FAIL][69] ([fdo#108145] / [i915#265]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-kbl1/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max: - shard-skl: NOTRUN -> [FAIL][70] ([fdo#108145] / [i915#265]) [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html * igt@kms_plane_lowres@pipe-d-tiling-x: - shard-tglb: NOTRUN -> [SKIP][71] ([i915#3536]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-tglb6/igt@kms_plane_lowres@pipe-d-tiling-x.html * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5: - shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#658]) +5 similar issues [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-apl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][73] -> [SKIP][74] ([fdo#109642] / [fdo#111068] / [i915#658]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-iclb2/igt@kms_psr2_su@frontbuffer.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-iclb4/igt@kms_psr2_su@frontbuffer.html * igt@kms_psr@psr2_cursor_plane_onoff: - shard-iclb: [PASS][75] -> [SKIP][76] ([fdo#109441]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-iclb6/igt@kms_psr@psr2_cursor_plane_onoff.html * igt@kms_psr@psr2_no_drrs: - shard-iclb: NOTRUN -> [SKIP][77] ([fdo#109441]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-iclb1/igt@kms_psr@psr2_no_drrs.html - shard-tglb: NOTRUN -> [FAIL][78] ([i915#132] / [i915#3467]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-tglb6/igt@kms_psr@psr2_no_drrs.html * igt@kms_vblank@pipe-d-ts-continuation-idle: - shard-apl: NOTRUN -> [SKIP][79] ([fdo#109271]) +302 similar issues [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-apl7/igt@kms_vblank@pipe-d-ts-continuation-idle.html * igt@kms_writeback@writeback-check-output: - shard-apl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#2437]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-apl3/igt@kms_writeback@writeback-check-output.html * igt@prime_nv_test@i915_blt_fill_nv_read: - shard-tglb: NOTRUN -> [SKIP][81] ([fdo#109291]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-tglb6/igt@prime_nv_test@i915_blt_fill_nv_read.html - shard-iclb: NOTRUN -> [SKIP][82] ([fdo#109291]) [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-iclb1/igt@prime_nv_test@i915_blt_fill_nv_read.html * igt@sysfs_clients@fair-7: - shard-apl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#2994]) +5 similar issues [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-apl3/igt@sysfs_clients@fair-7.html * igt@sysfs_clients@split-50: - shard-kbl: NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#2994]) [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-kbl2/igt@sysfs_clients@split-50.html - shard-iclb: NOTRUN -> [SKIP][85] ([i915#2994]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-iclb1/igt@sysfs_clients@split-50.html - shard-tglb: NOTRUN -> [SKIP][86] ([i915#2994]) [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-tglb6/igt@sysfs_clients@split-50.html - shard-skl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#2994]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-skl4/igt@sysfs_clients@split-50.html * igt@vgem_basic@unload: - shard-snb: NOTRUN -> [INCOMPLETE][88] ([i915#3744]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-snb2/igt@vgem_basic@unload.html #### Possible fixes #### * igt@fbdev@unaligned-read: - {shard-rkl}: [SKIP][89] ([i915#2582]) -> [PASS][90] +1 similar issue [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-rkl-5/igt@fbdev@unaligned-read.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-rkl-6/igt@fbdev@unaligned-read.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-glk: [FAIL][91] ([i915#2842]) -> [PASS][92] +1 similar issue [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-glk1/igt@gem_exec_fair@basic-none-rrul@rcs0.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: [FAIL][93] ([i915#2842]) -> [PASS][94] +5 similar issues [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-kbl4/igt@gem_exec_fair@basic-none-solo@rcs0.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-kbl2/igt@gem_exec_fair@basic-none-solo@rcs0.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-tglb: [FAIL][95] ([i915#2842]) -> [PASS][96] +1 similar issue [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-tglb6/igt@gem_exec_fair@basic-pace@bcs0.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-tglb3/igt@gem_exec_fair@basic-pace@bcs0.html * igt@gem_exec_suspend@basic-s3-devices: - {shard-rkl}: [FAIL][97] -> [PASS][98] [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-rkl-6/igt@gem_exec_suspend@basic-s3-devices.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-rkl-5/igt@gem_exec_suspend@basic-s3-devices.html * igt@gem_exec_whisper@basic-queues-all: - shard-glk: [DMESG-WARN][99] ([i915#118] / [i915#95]) -> [PASS][100] +1 similar issue [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-glk3/igt@gem_exec_whisper@basic-queues-all.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-glk4/igt@gem_exec_whisper@basic-queues-all.html * igt@gem_mmap_gtt@cpuset-big-copy-odd: - {shard-rkl}: [FAIL][101] ([i915#307]) -> [PASS][102] [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-rkl-1/igt@gem_mmap_gtt@cpuset-big-copy-odd.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-rkl-1/igt@gem_mmap_gtt@cpuset-big-copy-odd.html * igt@gem_mmap_wc@set-cache-level: - {shard-rkl}: [SKIP][103] ([i915#1850]) -> [PASS][104] [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-rkl-5/igt@gem_mmap_wc@set-cache-level.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-rkl-6/igt@gem_mmap_wc@set-cache-level.html * igt@i915_pm_rpm@drm-resources-equal: - {shard-rkl}: [SKIP][105] ([fdo#109308]) -> [PASS][106] [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-rkl-2/igt@i915_pm_rpm@drm-resources-equal.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-rkl-6/igt@i915_pm_rpm@drm-resources-equal.html * igt@i915_pm_rpm@modeset-lpsp: - {shard-rkl}: [SKIP][107] ([i915#1397]) -> [PASS][108] [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-rkl-5/igt@i915_pm_rpm@modeset-lpsp.html [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp.html * igt@i915_pm_rpm@system-suspend: - shard-skl: [INCOMPLETE][109] ([i915#151]) -> [PASS][110] [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-skl4/igt@i915_pm_rpm@system-suspend.html [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-skl3/igt@i915_pm_rpm@system-suspend.html * igt@i915_selftest@live@gt_pm: - {shard-rkl}: [DMESG-FAIL][111] ([i915#1021]) -> [PASS][112] [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-rkl-5/igt@i915_selftest@live@gt_pm.html [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-rkl-1/igt@i915_selftest@live@gt_pm.html * igt@i915_suspend@sysfs-reader: - shard-kbl: [INCOMPLETE][113] ([i915#155]) -> [PASS][114] [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-kbl2/igt@i915_suspend@sysfs-reader.html [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-kbl1/igt@i915_suspend@sysfs-reader.html * igt@kms_big_fb@linear-64bpp-rotate-0: - shard-iclb: [FAIL][115] -> [PASS][116] [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-iclb4/igt@kms_big_fb@linear-64bpp-rotate-0.html [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-iclb7/igt@kms_big_fb@linear-64bpp-rotate-0.html * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0: - {shard-rkl}: [SKIP][117] ([i915#3721]) -> [PASS][118] +3 similar issues [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-rkl-5/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0.html [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-rkl-6/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0.html * igt@kms_big_fb@x-tiled-64bpp-rotate-180: - {shard-rkl}: [SKIP][119] ([i915#3638]) -> [PASS][120] +2 similar issues [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-rkl-2/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-rkl-6/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html * igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc: - {shard-rkl}: [FAIL][121] ([i915#3678]) -> [PASS][122] +5 similar issues [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-rkl-5/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-rkl-6/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html * igt@kms_color@pipe-c-ctm-0-5: - {shard-rkl}: [SKIP][123] ([i915#1149] / [i915#1849]) -> [PASS][124] +3 similar issues [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-rkl-2/igt@kms_color@pipe-c-ctm-0-5.html [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-rkl-6/igt@kms_color@pipe-c-ctm-0-5.html * igt@kms_cursor_crc@pipe-a-cursor-256x256-rapid-movement: - {shard-rkl}: [SKIP][125] ([fdo#112022]) -> [PASS][126] +15 similar issues [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-rkl-5/igt@kms_cursor_crc@pipe-a-cursor-256x256-rapid-movement.html [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-256x256-rapid-movement.html * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy: - {shard-rkl}: [SKIP][127] ([fdo#111825]) -> [PASS][128] +4 similar issues [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-rkl-5/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html * igt@kms_cursor_legacy@flip-vs-cursor-toggle: - shard-skl: [FAIL][129] ([i915#2346]) -> [PASS][130] [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html * igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled: - {shard-rkl}: [SKIP][131] ([fdo#111314]) -> [PASS][132] +8 similar issues [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-rkl-2/igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled.html [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1: - shard-skl: [FAIL][133] ([i915#79]) -> [PASS][134] [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html * igt@kms_flip@flip-vs-expired-vblank@b-dp1: - shard-kbl: [FAIL][135] ([i915#79]) -> [PASS][136] [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-kbl6/igt@kms_flip@flip-vs-expired-vblank@b-dp1.html [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-kbl3/igt@kms_flip@flip-vs-expired-vblank@b-dp1.html * igt@kms_frontbuffer_tracking@basic: - {shard-rkl}: [SKIP][137] ([i915#1849] / [i915#3180]) -> [PASS][138] +1 similar issue [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-rkl-2/igt@kms_frontbuffer_tracking@basic.html [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-rkl-6/igt@kms_frontbuffer_tracking@basic.html * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt: - shard-skl: [DMESG-WARN][139] ([i915#1982]) -> [PASS][140] +1 similar issue [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-skl2/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-skl2/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes: - shard-apl: [DMESG-WARN][141] ([i915#180]) -> [PASS][142] [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb: - {shard-rkl}: [SKIP][143] ([i915#1849]) -> [PASS][144] +38 similar issues [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10320/shard-rkl-2/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/shard-rkl-6/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][145] ([fdo#108145] / [i91 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20558/index.html [-- Attachment #1.2: Type: text/html, Size: 33551 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH 1/7] drm/i915: Settle on "adl-x" in WA comments 2021-07-08 21:18 [Intel-gfx] [PATCH 1/7] drm/i915: Settle on "adl-x" in WA comments José Roberto de Souza ` (8 preceding siblings ...) 2021-07-09 14:30 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork @ 2021-07-10 4:55 ` Matt Roper 9 siblings, 0 replies; 21+ messages in thread From: Matt Roper @ 2021-07-10 4:55 UTC (permalink / raw) To: José Roberto de Souza; +Cc: intel-gfx, Lucas De Marchi On Thu, Jul 08, 2021 at 02:18:21PM -0700, José Roberto de Souza wrote: > From: Lucas De Marchi <lucas.demarchi@intel.com> > > Most of the places are using this format so lets consolidate it. > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +- > drivers/gpu/drm/i915/display/intel_cursor.c | 2 +- > drivers/gpu/drm/i915/display/intel_display.c | 2 +- > drivers/gpu/drm/i915/display/intel_psr.c | 10 +++++----- > drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- > drivers/gpu/drm/i915/intel_pm.c | 4 ++-- > 7 files changed, 12 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index df2d8ce4a12f6..71067a62264de 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -2878,7 +2878,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) > dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; > dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; > dev_priv->display.calc_voltage_level = tgl_calc_voltage_level; > - /* Wa_22011320316:adlp[a0] */ > + /* Wa_22011320316:adl-p[a0] */ > if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) > dev_priv->cdclk.table = adlp_a_step_cdclk_table; > else > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c > index bb61e736de911..f61a25fb87e90 100644 > --- a/drivers/gpu/drm/i915/display/intel_cursor.c > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c > @@ -383,7 +383,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, > if (plane_state->hw.rotation & DRM_MODE_ROTATE_180) > cntl |= MCURSOR_ROTATE_180; > > - /* Wa_22012358565:adlp */ > + /* Wa_22012358565:adl-p */ > if (DISPLAY_VER(dev_priv) == 13) > cntl |= MCURSOR_ARB_SLOTS(1); > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 026c28c612f07..65ddb6ca16e67 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -975,7 +975,7 @@ void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state) > /* FIXME: assert CPU port conditions for SNB+ */ > } > > - /* Wa_22012358565:adlp */ > + /* Wa_22012358565:adl-p */ > if (DISPLAY_VER(dev_priv) == 13) > intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), > 0, PIPE_ARB_USE_PROG_SLOTS); > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index 9643624fe160d..4dfe1dceb8635 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -545,7 +545,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1); > val |= intel_psr2_get_tp_time(intel_dp); > > - /* Wa_22012278275:adlp */ > + /* Wa_22012278275:adl-p */ > if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D1)) { > static const u8 map[] = { > 2, /* 5 lines */ > @@ -733,7 +733,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, > if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) > return; > > - /* Wa_16011303918:adlp */ > + /* Wa_16011303918:adl-p */ > if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) > return; > > @@ -965,7 +965,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > return false; > } > > - /* Wa_16011303918:adlp */ > + /* Wa_16011303918:adl-p */ > if (crtc_state->vrr.enable && > IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) { > drm_dbg_kms(&dev_priv->drm, > @@ -1160,7 +1160,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp) > intel_dp->psr.psr2_sel_fetch_enabled ? > IGNORE_PSR2_HW_TRACKING : 0); > > - /* Wa_16011168373:adlp */ > + /* Wa_16011168373:adl-p */ > if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) && > intel_dp->psr.psr2_enabled) > intel_de_rmw(dev_priv, > @@ -1346,7 +1346,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) > intel_de_rmw(dev_priv, CHICKEN_PAR1_1, > DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0); > > - /* Wa_16011168373:adlp */ > + /* Wa_16011168373:adl-p */ > if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) && > intel_dp->psr.psr2_enabled) > intel_de_rmw(dev_priv, > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c > index c7263f4ff11d7..628b678d9a71c 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > @@ -926,7 +926,7 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, > else if (key->flags & I915_SET_COLORKEY_SOURCE) > plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; > > - /* Wa_22012358565:adlp */ > + /* Wa_22012358565:adl-p */ > if (DISPLAY_VER(dev_priv) == 13) > plane_ctl |= adlp_plane_ctl_arb_slots(plane_state); > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index d9a5a445ceecd..e5e3f820074a9 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1078,7 +1078,7 @@ gen12_gt_workarounds_init(struct drm_i915_private *i915, > { > icl_wa_init_mcr(i915, wal); > > - /* Wa_14011060649:tgl,rkl,dg1,adls,adl-p */ > + /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */ > wa_14011060649(i915, wal); > } > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 5fdb96e7d2668..0cbb79452fcf9 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -7356,7 +7356,7 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv) > > static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) > { > - /* Wa_1409120013:tgl,rkl,adl_s,dg1 */ > + /* Wa_1409120013:tgl,rkl,adl-s,dg1 */ > if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) || > IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) > intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, > @@ -7367,7 +7367,7 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) > intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) | > TGL_VRH_GATING_DIS); > > - /* Wa_14011059788:tgl,rkl,adl_s,dg1,adl-p */ > + /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ > intel_uncore_rmw(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN, > 0, DFR_DISABLE); > > -- > 2.32.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2021-08-12 15:56 UTC | newest] Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-07-08 21:18 [Intel-gfx] [PATCH 1/7] drm/i915: Settle on "adl-x" in WA comments José Roberto de Souza 2021-07-08 21:18 ` [Intel-gfx] [PATCH 2/7] drm/i915: Implement Wa_1508744258 José Roberto de Souza 2021-07-10 5:06 ` Matt Roper 2021-08-12 3:27 ` Timo Aaltonen 2021-08-12 6:29 ` Timo Aaltonen 2021-08-12 15:56 ` Souza, Jose 2021-07-08 21:18 ` [Intel-gfx] [PATCH 3/7] drm/i915/adl_s: Extend Wa_1406941453 José Roberto de Souza 2021-07-10 5:07 ` Matt Roper 2021-07-08 21:18 ` [Intel-gfx] [PATCH 4/7] drm/i915: Limit maximum number of memory channels José Roberto de Souza 2021-07-08 21:18 ` [Intel-gfx] [PATCH 5/7] drm/i915: Limit Wa_22010178259 to affected platforms José Roberto de Souza 2021-07-10 5:29 ` Matt Roper 2021-07-08 21:18 ` [Intel-gfx] [PATCH 6/7] drm/i915/display/adl_p: Correctly program MBUS DBOX A credits José Roberto de Souza 2021-07-10 5:41 ` Matt Roper 2021-08-03 20:19 ` Souza, Jose 2021-08-03 22:39 ` Matt Roper 2021-07-08 21:18 ` [Intel-gfx] [PATCH 7/7] drm/i915/display/xelpd: Exetend Wa_14011508470 José Roberto de Souza 2021-07-10 5:42 ` Matt Roper 2021-07-08 23:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/7] drm/i915: Settle on "adl-x" in WA comments Patchwork 2021-07-08 23:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-07-09 14:30 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-07-10 4:55 ` [Intel-gfx] [PATCH 1/7] " Matt Roper
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