[Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support

[Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support

[Mitul Golani]

his patch series adds support for DSC fractional compressed bpp
for MTL+. The series starts with some fixes, followed by patches that
lay groundwork to iterate over valid compressed bpps to select the
'best' compressed bpp with optimal link configuration (taken from
upstream series: https://patchwork.freedesktop.org/series/105200/).

The later patches, add changes to accommodate compressed bpp with
fractional part, including changes to QP calculations.
To get the 'best' compressed bpp, we iterate over the valid compressed
bpp values, but with fractional step size 1/16, 1/8, 1/4 or 1/2 as per
sink support.

The last 2 patches add support to depict DSC sink's fractional support,
and debugfs to enforce use of fractional bpp, while choosing an
appropriate compressed bpp.

Ankit Nautiyal (5):
  drm/display/dp: Add helper function to get DSC bpp prescision
  drm/i915/display: Store compressed bpp in U6.4 format
  drm/i915/display: Consider fractional vdsc bpp while computing m_n
    values
  drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
  drm/i915/dp: Iterate over output bpp with fractional step size

Swati Sharma (2):
  drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
  drm/i915/dsc: Allow DSC only with fractional bpp when forced from
    debugfs

Vandita Kulkarni (1):
  drm/i915/dsc/mtl: Add support for fractional bpp

 drivers/gpu/drm/display/drm_dp_helper.c       | 27 ++++++
 drivers/gpu/drm/i915/display/icl_dsi.c        | 11 +--
 drivers/gpu/drm/i915/display/intel_audio.c    | 17 ++--
 drivers/gpu/drm/i915/display/intel_bios.c     |  6 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  6 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  8 +-
 drivers/gpu/drm/i915/display/intel_display.h  |  2 +-
 .../drm/i915/display/intel_display_debugfs.c  | 83 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  4 +-
 drivers/gpu/drm/i915/display/intel_dp.c       | 81 +++++++++++-------
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 32 ++++---
 drivers/gpu/drm/i915/display/intel_fdi.c      |  2 +-
 .../i915/display/intel_fractional_helper.h    | 36 ++++++++
 .../gpu/drm/i915/display/intel_qp_tables.c    |  3 -
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 30 +++++--
 include/drm/display/drm_dp_helper.h           |  1 +
 16 files changed, 275 insertions(+), 74 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_fractional_helper.h

-- 
2.25.1

[Intel-gfx] [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp prescision

[Mitul Golani]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Add helper to get the DSC bits_per_pixel precision for the DP sink.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/display/drm_dp_helper.c | 27 +++++++++++++++++++++++++
 include/drm/display/drm_dp_helper.h     |  1 +
 2 files changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index 8a1b64c57dfd..5c23d5b8fc50 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2323,6 +2323,33 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
 }
 EXPORT_SYMBOL(drm_dp_read_desc);
 
+/**
+ * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
+ * @dsc_dpcd: DSC capabilities from DPCD
+ *
+ * Returns the bpp precision supported by the DP sink.
+ */
+u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+	u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT];
+
+	switch (bpp_increment_dpcd) {
+	case DP_DSC_BITS_PER_PIXEL_1_16:
+		return 16;
+	case DP_DSC_BITS_PER_PIXEL_1_8:
+		return 8;
+	case DP_DSC_BITS_PER_PIXEL_1_4:
+		return 4;
+	case DP_DSC_BITS_PER_PIXEL_1_2:
+		return 2;
+	case DP_DSC_BITS_PER_PIXEL_1_1:
+		return 1;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
+
 /**
  * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
  * supported by the DSC sink.
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index 3369104e2d25..6968d4d87931 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -164,6 +164,7 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 }
 
 /* DP/eDP DSC support */
+u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
 				   bool is_edp);
 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
-- 
2.25.1

[Intel-gfx] [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format

[Mitul Golani]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

DSC parameter bits_per_pixel is stored in U6.4 format.
The 4 bits represent the fractional part of the bpp.
Currently we use compressed_bpp member of dsc structure to store
only the integral part of the bits_per_pixel.
To store the full bits_per_pixel along with the fractional part,
compressed_bpp is changed to store bpp in U6.4 formats. Intergral
part is retrieved by simply right shifting the member compressed_bpp by 4.

v2:
-Use to_bpp_int, to_bpp_frac_dec, to_bpp_x16 helpers while dealing
 with compressed bpp. (Suraj)
-Fix comment styling. (Suraj)

v3:
-Add separate file for 6.4 fixed point helper(Jani, Nikula)
-Add comment for magic values(Suraj)

v4:
-Fix checkpatch caused due to renaming(Suraj)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c        | 11 +++---
 drivers/gpu/drm/i915/display/intel_audio.c    |  3 +-
 drivers/gpu/drm/i915/display/intel_bios.c     |  6 ++--
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  6 ++--
 drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
 .../drm/i915/display/intel_display_types.h    |  3 +-
 drivers/gpu/drm/i915/display/intel_dp.c       | 33 ++++++++++-------
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 26 ++++++++------
 .../i915/display/intel_fractional_helper.h    | 36 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vdsc.c     |  5 +--
 10 files changed, 93 insertions(+), 38 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_fractional_helper.h

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index ad6488e9c2b2..0f7594b6aa1f 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -43,6 +43,7 @@
 #include "intel_de.h"
 #include "intel_dsi.h"
 #include "intel_dsi_vbt.h"
+#include "intel_fractional_helper.h"
 #include "intel_panel.h"
 #include "intel_vdsc.h"
 #include "intel_vdsc_regs.h"
@@ -330,7 +331,7 @@ static int afe_clk(struct intel_encoder *encoder,
 	int bpp;
 
 	if (crtc_state->dsc.compression_enable)
-		bpp = crtc_state->dsc.compressed_bpp;
+		bpp = intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16);
 	else
 		bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 
@@ -860,7 +861,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	 * compressed and non-compressed bpp.
 	 */
 	if (crtc_state->dsc.compression_enable) {
-		mul = crtc_state->dsc.compressed_bpp;
+		mul = intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16);
 		div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 	}
 
@@ -884,7 +885,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 		int bpp, line_time_us, byte_clk_period_ns;
 
 		if (crtc_state->dsc.compression_enable)
-			bpp = crtc_state->dsc.compressed_bpp;
+			bpp = intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16);
 		else
 			bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 
@@ -1451,8 +1452,8 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
 	struct drm_display_mode *adjusted_mode =
 					&pipe_config->hw.adjusted_mode;
 
-	if (pipe_config->dsc.compressed_bpp) {
-		int div = pipe_config->dsc.compressed_bpp;
+	if (pipe_config->dsc.compressed_bpp_x16) {
+		int div = intel_fractional_bpp_from_x16(pipe_config->dsc.compressed_bpp_x16);
 		int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 
 		adjusted_mode->crtc_htotal =
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 19605264a35c..4f1db1581316 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -35,6 +35,7 @@
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
+#include "intel_fractional_helper.h"
 #include "intel_lpe_audio.h"
 
 /**
@@ -528,7 +529,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
 	h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 	h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
 	pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
-	vdsc_bpp = crtc_state->dsc.compressed_bpp;
+	vdsc_bpp = intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16);
 	cdclk = i915->display.cdclk.hw.cdclk;
 	/* fec= 0.972261, using rounding multiplier of 1000000 */
 	fec_coeff = 972261;
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index f735b035436c..3e4a3c62fc8a 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -33,6 +33,7 @@
 #include "i915_reg.h"
 #include "intel_display.h"
 #include "intel_display_types.h"
+#include "intel_fractional_helper.h"
 #include "intel_gmbus.h"
 
 #define _INTEL_BIOS_PRIVATE
@@ -3384,8 +3385,9 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
 
 	crtc_state->pipe_bpp = bpc * 3;
 
-	crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
-					     VBT_DSC_MAX_BPP(dsc->max_bpp));
+	crtc_state->dsc.compressed_bpp_x16 =
+		intel_fractional_bpp_to_x16(min(crtc_state->pipe_bpp,
+						VBT_DSC_MAX_BPP(dsc->max_bpp)));
 
 	/*
 	 * FIXME: This is ugly, and slice count should take DSC engine
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ad5251ba6fe1..b9a07be81dfe 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -34,6 +34,7 @@
 #include "intel_de.h"
 #include "intel_dp.h"
 #include "intel_display_types.h"
+#include "intel_fractional_helper.h"
 #include "intel_mchbar_regs.h"
 #include "intel_pci_config.h"
 #include "intel_pcode.h"
@@ -2567,8 +2568,9 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
 		 * => CDCLK >= compressed_bpp * Pixel clock  / 2 * Bigjoiner Interface bits
 		 */
 		int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
-		int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * pixel_clock) /
-				   (2 * bigjoiner_interface_bits);
+		int min_cdclk_bj =
+			(intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16) *
+			 pixel_clock) / (2 * bigjoiner_interface_bits);
 
 		min_cdclk = max(min_cdclk, min_cdclk_bj);
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 83e1bc858b9f..afcbdd4f105a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5365,7 +5365,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
 	PIPE_CONF_CHECK_I(dsc.compression_enable);
 	PIPE_CONF_CHECK_I(dsc.dsc_split);
-	PIPE_CONF_CHECK_I(dsc.compressed_bpp);
+	PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
 
 	PIPE_CONF_CHECK_BOOL(splitter.enable);
 	PIPE_CONF_CHECK_I(splitter.link_count);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c21064794f32..69bcabec4a29 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1353,7 +1353,8 @@ struct intel_crtc_state {
 	struct {
 		bool compression_enable;
 		bool dsc_split;
-		u16 compressed_bpp;
+		/* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
+		u16 compressed_bpp_x16;
 		u8 slice_count;
 		struct drm_dsc_config config;
 	} dsc;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index aa5f602b56fb..cb647bb38b12 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -64,6 +64,7 @@
 #include "intel_dp_mst.h"
 #include "intel_dpio_phy.h"
 #include "intel_dpll.h"
+#include "intel_fractional_helper.h"
 #include "intel_fifo_underrun.h"
 #include "intel_hdcp.h"
 #include "intel_hdmi.h"
@@ -1863,7 +1864,8 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
 					      valid_dsc_bpp[i],
 					      timeslots);
 		if (ret == 0) {
-			pipe_config->dsc.compressed_bpp = valid_dsc_bpp[i];
+			pipe_config->dsc.compressed_bpp_x16 =
+				intel_fractional_bpp_to_x16(valid_dsc_bpp[i]);
 			return 0;
 		}
 	}
@@ -1901,7 +1903,8 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
 					      compressed_bpp,
 					      timeslots);
 		if (ret == 0) {
-			pipe_config->dsc.compressed_bpp = compressed_bpp;
+			pipe_config->dsc.compressed_bpp_x16 =
+				intel_fractional_bpp_to_x16(compressed_bpp);
 			return 0;
 		}
 	}
@@ -2085,7 +2088,8 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
 	/* Compressed BPP should be less than the Input DSC bpp */
 	dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
 
-	pipe_config->dsc.compressed_bpp = max(dsc_min_bpp, dsc_max_bpp);
+	pipe_config->dsc.compressed_bpp_x16 =
+		intel_fractional_bpp_to_x16(max(dsc_min_bpp, dsc_max_bpp));
 
 	pipe_config->pipe_bpp = pipe_bpp;
 
@@ -2171,18 +2175,19 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
 	if (ret < 0) {
 		drm_dbg_kms(&dev_priv->drm,
-			    "Cannot compute valid DSC parameters for Input Bpp = %d "
-			    "Compressed BPP = %d\n",
+			    "Cannot compute valid DSC parameters for Input Bpp = %d Compressed BPP = %d.%d\n",
 			    pipe_config->pipe_bpp,
-			    pipe_config->dsc.compressed_bpp);
+			    intel_fractional_bpp_from_x16(pipe_config->dsc.compressed_bpp_x16),
+			    intel_fractional_bpp_decimal(pipe_config->dsc.compressed_bpp_x16));
 		return ret;
 	}
 
 	pipe_config->dsc.compression_enable = true;
-	drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
-		    "Compressed Bpp = %d Slice Count = %d\n",
+	drm_dbg_kms(&dev_priv->drm,
+		    "DP DSC computed with Input Bpp = %d Compressed Bpp = %d.%d Slice Count = %d\n",
 		    pipe_config->pipe_bpp,
-		    pipe_config->dsc.compressed_bpp,
+		    intel_fractional_bpp_from_x16(pipe_config->dsc.compressed_bpp_x16),
+		    intel_fractional_bpp_decimal(pipe_config->dsc.compressed_bpp_x16),
 		    pipe_config->dsc.slice_count);
 
 	return 0;
@@ -2261,15 +2266,17 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 
 	if (pipe_config->dsc.compression_enable) {
 		drm_dbg_kms(&i915->drm,
-			    "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
+			    "DP lane count %d clock %d Input bpp %d Compressed bpp %d.%d\n",
 			    pipe_config->lane_count, pipe_config->port_clock,
 			    pipe_config->pipe_bpp,
-			    pipe_config->dsc.compressed_bpp);
+			    intel_fractional_bpp_from_x16(pipe_config->dsc.compressed_bpp_x16),
+			    intel_fractional_bpp_decimal(pipe_config->dsc.compressed_bpp_x16));
 
 		drm_dbg_kms(&i915->drm,
 			    "DP link rate required %i available %i\n",
 			    intel_dp_link_required(adjusted_mode->crtc_clock,
-						   pipe_config->dsc.compressed_bpp),
+						   intel_fractional_bpp_from_x16
+						   (pipe_config->dsc.compressed_bpp_x16)),
 			    intel_dp_max_data_rate(pipe_config->port_clock,
 						   pipe_config->lane_count));
 	} else {
@@ -2702,7 +2709,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 		intel_dp_limited_color_range(pipe_config, conn_state);
 
 	if (pipe_config->dsc.compression_enable)
-		link_bpp = pipe_config->dsc.compressed_bpp;
+		link_bpp = pipe_config->dsc.compressed_bpp_x16;
 	else
 		link_bpp = intel_dp_output_bpp(pipe_config->output_format,
 					       pipe_config->pipe_bpp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 1c7f0b6afe47..7bf0b6e4ac0b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -41,6 +41,7 @@
 #include "intel_dp_hdcp.h"
 #include "intel_dp_mst.h"
 #include "intel_dpio_phy.h"
+#include "intel_fractional_helper.h"
 #include "intel_hdcp.h"
 #include "intel_hotplug.h"
 #include "skl_scaler.h"
@@ -140,7 +141,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
 		if (!dsc)
 			crtc_state->pipe_bpp = bpp;
 		else
-			crtc_state->dsc.compressed_bpp = bpp;
+			crtc_state->dsc.compressed_bpp_x16 = intel_fractional_bpp_to_x16(bpp);
 		drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);
 	}
 
@@ -238,13 +239,14 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
 	if (slots < 0)
 		return slots;
 
-	last_compressed_bpp = crtc_state->dsc.compressed_bpp;
+	last_compressed_bpp = intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16);
 
-	crtc_state->dsc.compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915,
-									last_compressed_bpp,
-									crtc_state->pipe_bpp);
+	crtc_state->dsc.compressed_bpp_x16 =
+		intel_fractional_bpp_to_x16(intel_dp_dsc_nearest_valid_bpp(i915,
+									   last_compressed_bpp,
+									   crtc_state->pipe_bpp));
 
-	if (crtc_state->dsc.compressed_bpp != last_compressed_bpp)
+	if (crtc_state->dsc.compressed_bpp_x16 != intel_fractional_bpp_to_x16(last_compressed_bpp))
 		need_timeslot_recalc = true;
 
 	/*
@@ -252,15 +254,17 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
 	 * the actual compressed bpp we use.
 	 */
 	if (need_timeslot_recalc) {
-		slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
-							     crtc_state->dsc.compressed_bpp,
-							     crtc_state->dsc.compressed_bpp,
-							     limits, conn_state, 2 * 3, true);
+		slots =
+		intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
+						     intel_fractional_bpp_from_x16
+						     (crtc_state->dsc.compressed_bpp_x16),
+		intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16),
+		limits, conn_state, 2 * 3, true);
 		if (slots < 0)
 			return slots;
 	}
 
-	intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
+	intel_link_compute_m_n(intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16),
 			       crtc_state->lane_count,
 			       adjusted_mode->crtc_clock,
 			       crtc_state->port_clock,
diff --git a/drivers/gpu/drm/i915/display/intel_fractional_helper.h b/drivers/gpu/drm/i915/display/intel_fractional_helper.h
new file mode 100644
index 000000000000..0212a9041c8f
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_fractional_helper.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+#ifndef __INTEL_FRACTIONAL_HELPERS_H__
+#define __INTEL_FRACTIONAL_HELPERS_H__
+
+ /*
+  * Convert a U6.4 fixed-point bits-per-pixel (bpp) value to an integer bpp value.
+  */
+static inline int intel_fractional_bpp_from_x16(int bpp_x16)
+{
+	return bpp_x16 >> 4;
+}
+
+/*
+ * Extract the fractional part of a U6.4 fixed-point bpp value based on the
+ * last 4 bits representing fractional bits, obtained by multiplying by 10000
+ * and then dividing by 16, as the bpp value is initially left-shifted by 4
+ * to allocate 4 bits for the fractional part.
+ */
+static inline int intel_fractional_bpp_decimal(int bpp_x16)
+{
+	return (bpp_x16 & 0xf) * 625;
+}
+
+/*
+ * Convert bits-per-pixel (bpp) to a U6.4 fixed-point representation.
+ */
+static inline int intel_fractional_bpp_to_x16(int bpp)
+{
+	return bpp << 4;
+}
+
+#endif /*  __INTEL_FRACTIONAL_HELPERS_H__ */
+
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 5c00f7ccad7f..1bd9391a6f5a 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -15,6 +15,7 @@
 #include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_dsi.h"
+#include "intel_fractional_helper.h"
 #include "intel_qp_tables.h"
 #include "intel_vdsc.h"
 #include "intel_vdsc_regs.h"
@@ -248,7 +249,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
-	u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
+	u16 compressed_bpp = intel_fractional_bpp_from_x16(pipe_config->dsc.compressed_bpp_x16);
 	int err;
 	int ret;
 
@@ -874,7 +875,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
 	if (vdsc_cfg->native_420)
 		vdsc_cfg->bits_per_pixel >>= 1;
 
-	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
+	crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;
 
 	/* PPS 2 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);
-- 
2.25.1

[Intel-gfx] [PATCH 3/8] drm/i915/display: Consider fractional vdsc bpp while computing m_n values

[Mitul Golani]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate this precision while computing m_n values.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 6 +++++-
 drivers/gpu/drm/i915/display/intel_display.h | 2 +-
 drivers/gpu/drm/i915/display/intel_dp.c      | 5 +++--
 drivers/gpu/drm/i915/display/intel_dp_mst.c  | 6 ++++--
 drivers/gpu/drm/i915/display/intel_fdi.c     | 2 +-
 5 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index afcbdd4f105a..b37aeac961f4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2380,10 +2380,14 @@ void
 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
 		       int pixel_clock, int link_clock,
 		       struct intel_link_m_n *m_n,
-		       bool fec_enable)
+		       bool fec_enable,
+		       bool is_dsc_fractional_bpp)
 {
 	u32 data_clock = bits_per_pixel * pixel_clock;
 
+	if (is_dsc_fractional_bpp)
+		data_clock = DIV_ROUND_UP(bits_per_pixel * pixel_clock, 16);
+
 	if (fec_enable)
 		data_clock = intel_dp_mode_to_fec_clock(data_clock);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 49ac8473b988..a4c4ca3cad65 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -398,7 +398,7 @@ u8 intel_calc_active_pipes(struct intel_atomic_state *state,
 void intel_link_compute_m_n(u16 bpp, int nlanes,
 			    int pixel_clock, int link_clock,
 			    struct intel_link_m_n *m_n,
-			    bool fec_enable);
+			    bool fec_enable, bool is_dsc_fractional_bpp);
 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 			      u32 pixel_format, u64 modifier);
 enum drm_mode_status
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index cb647bb38b12..6e09e21909a1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2562,7 +2562,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
 
 	intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock,
 			       pipe_config->port_clock, &pipe_config->dp_m2_n2,
-			       pipe_config->fec_enable);
+			       pipe_config->fec_enable, false);
 
 	/* FIXME: abstract this better */
 	if (pipe_config->splitter.enable)
@@ -2741,7 +2741,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 			       adjusted_mode->crtc_clock,
 			       pipe_config->port_clock,
 			       &pipe_config->dp_m_n,
-			       pipe_config->fec_enable);
+			       pipe_config->fec_enable,
+			       pipe_config->dsc.compression_enable);
 
 	/* FIXME: abstract this better */
 	if (pipe_config->splitter.enable)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 7bf0b6e4ac0b..8f6bd54532cb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -172,7 +172,8 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
 			       adjusted_mode->crtc_clock,
 			       crtc_state->port_clock,
 			       &crtc_state->dp_m_n,
-			       crtc_state->fec_enable);
+			       crtc_state->fec_enable,
+			       false);
 	crtc_state->dp_m_n.tu = slots;
 
 	return 0;
@@ -269,7 +270,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
 			       adjusted_mode->crtc_clock,
 			       crtc_state->port_clock,
 			       &crtc_state->dp_m_n,
-			       crtc_state->fec_enable);
+			       crtc_state->fec_enable,
+			       crtc_state->dsc.compression_enable);
 	crtc_state->dp_m_n.tu = slots;
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index e12b46a84fa1..15fddabf7c2e 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -259,7 +259,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
 	pipe_config->fdi_lanes = lane;
 
 	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
-			       link_bw, &pipe_config->fdi_m_n, false);
+			       link_bw, &pipe_config->fdi_m_n, false, false);
 
 	ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);
 	if (ret == -EDEADLK)
-- 
2.25.1

[Intel-gfx] [PATCH 4/8] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data

[Mitul Golani]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate the precision during calculation of transfer unit data
for hblank_early calculation.

v2:
-Fixed tu_data calculation while dealing with U6.4 format. (Stan)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_audio.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 4f1db1581316..3b08be54ce4f 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -522,25 +522,25 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
 	unsigned int link_clks_available, link_clks_required;
 	unsigned int tu_data, tu_line, link_clks_active;
 	unsigned int h_active, h_total, hblank_delta, pixel_clk;
-	unsigned int fec_coeff, cdclk, vdsc_bpp;
+	unsigned int fec_coeff, cdclk, vdsc_bppx16;
 	unsigned int link_clk, lanes;
 	unsigned int hblank_rise;
 
 	h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 	h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
 	pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
-	vdsc_bpp = intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16);
+	vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16;
 	cdclk = i915->display.cdclk.hw.cdclk;
 	/* fec= 0.972261, using rounding multiplier of 1000000 */
 	fec_coeff = 972261;
 	link_clk = crtc_state->port_clock;
 	lanes = crtc_state->lane_count;
 
-	drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :"
-		    "lanes = %u vdsc_bpp = %u cdclk = %u\n",
-		    h_active, link_clk, lanes, vdsc_bpp, cdclk);
+	drm_dbg_kms(&i915->drm,
+		    "h_active = %u link_clk = %u : lanes = %u vdsc_bppx16 = %u cdclk = %u\n",
+		    h_active, link_clk, lanes, vdsc_bppx16, cdclk);
 
-	if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk))
+	if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk))
 		return 0;
 
 	link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28;
@@ -552,8 +552,8 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
 		hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk),
 						  mul_u32_u32(link_clk, cdclk));
 
-	tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 1000000),
-			    mul_u32_u32(link_clk * lanes, fec_coeff));
+	tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000),
+			    mul_u32_u32(link_clk * lanes * 16, fec_coeff));
 	tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff),
 			    mul_u32_u32(64 * pixel_clk, 1000000));
 	link_clks_active  = (tu_line - 1) * 64 + tu_data;
-- 
2.25.1

[Intel-gfx] [PATCH 5/8] drm/i915/dsc/mtl: Add support for fractional bpp

[Mitul Golani]

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

Consider the fractional bpp while reading the qp values.

v2: Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 .../gpu/drm/i915/display/intel_qp_tables.c    |  3 ---
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 25 +++++++++++++++----
 2 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c b/drivers/gpu/drm/i915/display/intel_qp_tables.c
index 543cdc46aa1d..600c815e37e4 100644
--- a/drivers/gpu/drm/i915/display/intel_qp_tables.c
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
@@ -34,9 +34,6 @@
  * These qp tables are as per the C model
  * and it has the rows pointing to bpps which increment
  * in steps of 0.5
- * We do not support fractional bpps as of today,
- * hence we would skip the fractional bpps during
- * our references for qp calclulations.
  */
 static const u8 rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 1bd9391a6f5a..2c19078fbce8 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -78,8 +78,8 @@ intel_vdsc_set_min_max_qp(struct drm_dsc_config *vdsc_cfg, int buf,
 static void
 calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
 {
+	int bpp = intel_fractional_bpp_from_x16(vdsc_cfg->bits_per_pixel);
 	int bpc = vdsc_cfg->bits_per_component;
-	int bpp = vdsc_cfg->bits_per_pixel >> 4;
 	int qp_bpc_modifier = (bpc - 8) * 2;
 	int uncompressed_bpg_rate;
 	int first_line_bpg_offset;
@@ -149,7 +149,13 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
 		static const s8 ofs_und8[] = {
 			10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
 		};
-
+		/*
+		 * For 420 format since bits_per_pixel (bpp) is set to target bpp * 2,
+		 * QP table values for target bpp 4.0 to 4.4375 (rounded to 4.0) are
+		 * actually for bpp 8 to 8.875 (rounded to 4.0 * 2 i.e 8).
+		 * Similarly values for target bpp 4.5 to 4.8375 (rounded to 4.5)
+		 * are for bpp 9 to 9.875 (rounded to 4.5 * 2 i.e 9), and so on.
+		 */
 		bpp_i  = bpp - 8;
 		for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
 			u8 range_bpg_offset;
@@ -179,6 +185,9 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
 				range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
 		}
 	} else {
+		/* fractional bpp part * 10000 (for precision up to 4 decimal places) */
+		int fractional_bits = intel_fractional_bpp_decimal(vdsc_cfg->bits_per_pixel);
+
 		static const s8 ofs_und6[] = {
 			0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
 		};
@@ -192,7 +201,14 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
 			10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
 		};
 
-		bpp_i  = (2 * (bpp - 6));
+		/*
+		 * QP table rows have values in increment of 0.5.
+		 * So 6.0 bpp to 6.4375 will have index 0, 6.5 to 6.9375 will have index 1,
+		 * and so on.
+		 * 0.5 fractional part with 4 decimal precision becomes 5000
+		 */
+		bpp_i  = ((bpp - 6) + (fractional_bits < 5000 ? 0 : 1));
+
 		for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
 			u8 range_bpg_offset;
 
@@ -280,8 +296,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 	/* Gen 11 does not support VBR */
 	vdsc_cfg->vbr_enable = false;
 
-	/* Gen 11 only supports integral values of bpp */
-	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
+	vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp_x16;
 
 	/*
 	 * According to DSC 1.2 specs in Section 4.1 if native_420 is set
-- 
2.25.1

[Intel-gfx] [PATCH 6/8] drm/i915/dp: Iterate over output bpp with fractional step size

[Mitul Golani]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

This patch adds support to iterate over compressed output bpp as per the
fractional step, supported by DP sink.

v2:
-Avoid ending up with compressed bpp, same as pipe bpp. (Stan)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 38 +++++++++++++++----------
 1 file changed, 23 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6e09e21909a1..d6c29006b816 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1716,15 +1716,15 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
 	return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
 }
 
-static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock,
+static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock,
 					    u32 lane_count, u32 mode_clock,
 					    enum intel_output_format output_format,
 					    int timeslots)
 {
 	u32 available_bw, required_bw;
 
-	available_bw = (link_clock * lane_count * timeslots)  / 8;
-	required_bw = compressed_bpp * (intel_dp_mode_to_fec_clock(mode_clock));
+	available_bw = (link_clock * lane_count * timeslots * 16)  / 8;
+	required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock));
 
 	return available_bw > required_bw;
 }
@@ -1732,7 +1732,7 @@ static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock,
 static int dsc_compute_link_config(struct intel_dp *intel_dp,
 				   struct intel_crtc_state *pipe_config,
 				   struct link_config_limits *limits,
-				   u16 compressed_bpp,
+				   u16 compressed_bppx16,
 				   int timeslots)
 {
 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
@@ -1747,8 +1747,8 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
 		for (lane_count = limits->min_lane_count;
 		     lane_count <= limits->max_lane_count;
 		     lane_count <<= 1) {
-			if (!is_bw_sufficient_for_dsc_config(compressed_bpp, link_rate, lane_count,
-							     adjusted_mode->clock,
+			if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate,
+							     lane_count, adjusted_mode->clock,
 							     pipe_config->output_format,
 							     timeslots))
 				continue;
@@ -1861,7 +1861,7 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
 		ret = dsc_compute_link_config(intel_dp,
 					      pipe_config,
 					      limits,
-					      valid_dsc_bpp[i],
+					      valid_dsc_bpp[i] << 4,
 					      timeslots);
 		if (ret == 0) {
 			pipe_config->dsc.compressed_bpp_x16 =
@@ -1888,23 +1888,31 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
 			      int pipe_bpp,
 			      int timeslots)
 {
-	u16 compressed_bpp;
+	u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd);
+	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	u16 compressed_bppx16;
+	u8 bppx16_step;
 	int ret;
 
+	if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1)
+		bppx16_step = 16;
+	else
+		bppx16_step = 16 / bppx16_incr;
+
 	/* Compressed BPP should be less than the Input DSC bpp */
-	dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
+	dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step);
+	dsc_min_bpp = dsc_min_bpp << 4;
 
-	for (compressed_bpp = dsc_max_bpp;
-	     compressed_bpp >= dsc_min_bpp;
-	     compressed_bpp--) {
+	for (compressed_bppx16 = dsc_max_bpp;
+	     compressed_bppx16 >= dsc_min_bpp;
+	     compressed_bppx16 -= bppx16_step) {
 		ret = dsc_compute_link_config(intel_dp,
 					      pipe_config,
 					      limits,
-					      compressed_bpp,
+					      compressed_bppx16,
 					      timeslots);
 		if (ret == 0) {
-			pipe_config->dsc.compressed_bpp_x16 =
-				intel_fractional_bpp_to_x16(compressed_bpp);
+			pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
 			return 0;
 		}
 	}
-- 
2.25.1

[Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

[Mitul Golani]

From: Swati Sharma <swati2.sharma@intel.com>

DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
to depict sink's precision.
Also, new debugfs entry is created to enforce fractional bpp.
If Force_DSC_Fractional_BPP_en is set then while iterating over
output bpp with fractional step size we will continue if output_bpp is
computed as integer. With this approach, we will be able to validate
DSC with fractional bpp.

v2:
Add drm_modeset_unlock to new line(Suraj)

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 .../drm/i915/display/intel_display_debugfs.c  | 83 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  1 +
 2 files changed, 84 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index f05b52381a83..776ab96def1f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1244,6 +1244,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
 								      DP_DSC_YCbCr420_Native)),
 			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
 								      DP_DSC_YCbCr444)));
+		seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
+			   drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
 		seq_printf(m, "Force_DSC_Enable: %s\n",
 			   str_yes_no(intel_dp->force_dsc_en));
 		if (!intel_dp_is_edp(intel_dp))
@@ -1436,6 +1438,84 @@ static const struct file_operations i915_dsc_output_format_fops = {
 	.write = i915_dsc_output_format_write
 };
 
+static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct drm_device *dev = connector->dev;
+	struct drm_crtc *crtc;
+	struct intel_dp *intel_dp;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	int ret;
+
+	if (!encoder)
+		return -ENODEV;
+
+	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
+	if (ret)
+		return ret;
+
+	crtc = connector->state->crtc;
+	if (connector->status != connector_status_connected || !crtc) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	intel_dp = intel_attached_dp(to_intel_connector(connector));
+	seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
+		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
+
+out:
+	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+	return ret;
+}
+
+static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
+					     const char __user *ubuf,
+					     size_t len, loff_t *offp)
+{
+	struct drm_connector *connector =
+		((struct seq_file *)file->private_data)->private;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	bool dsc_fractional_bpp_enable = false;
+	int ret;
+
+	if (len == 0)
+		return 0;
+
+	drm_dbg(&i915->drm,
+		"Copied %zu bytes from user to force fractional bpp for DSC\n", len);
+
+	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
+	if (ret < 0)
+		return ret;
+
+	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
+		(dsc_fractional_bpp_enable) ? "true" : "false");
+	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
+
+	*offp += len;
+
+	return len;
+}
+
+static int i915_dsc_fractional_bpp_open(struct inode *inode,
+					struct file *file)
+{
+	return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private);
+}
+
+static const struct file_operations i915_dsc_fractional_bpp_fops = {
+	.owner = THIS_MODULE,
+	.open = i915_dsc_fractional_bpp_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = i915_dsc_fractional_bpp_write
+};
+
 /*
  * Returns the Current CRTC's bpc.
  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
@@ -1513,6 +1593,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
 
 		debugfs_create_file("i915_dsc_output_format", 0644, root,
 				    connector, &i915_dsc_output_format_fops);
+
+		debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
+				    connector, &i915_dsc_fractional_bpp_fops);
 	}
 
 	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 69bcabec4a29..27b31cb4c7b4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1797,6 +1797,7 @@ struct intel_dp {
 	/* Display stream compression testing */
 	bool force_dsc_en;
 	int force_dsc_output_format;
+	bool force_dsc_fractional_bpp_en;
 	int force_dsc_bpc;
 
 	bool hobl_failed;
-- 
2.25.1

[Intel-gfx] [PATCH 8/8] drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs

[Mitul Golani]

From: Swati Sharma <swati2.sharma@intel.com>

If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff
compressed bpp is fractional. Continue if the computed compressed bpp
turns out to be a integer.

v2:
-Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)
-Fix comment (Suraj)

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d6c29006b816..354d78593a5f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1906,6 +1906,9 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
 	for (compressed_bppx16 = dsc_max_bpp;
 	     compressed_bppx16 >= dsc_min_bpp;
 	     compressed_bppx16 -= bppx16_step) {
+		if (intel_dp->force_dsc_fractional_bpp_en &&
+		    !intel_fractional_bpp_decimal(compressed_bppx16))
+			continue;
 		ret = dsc_compute_link_config(intel_dp,
 					      pipe_config,
 					      limits,
@@ -1913,6 +1916,10 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
 					      timeslots);
 		if (ret == 0) {
 			pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
+			if (intel_dp->force_dsc_fractional_bpp_en &&
+			    intel_fractional_bpp_decimal(compressed_bppx16))
+				drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n");
+
 			return 0;
 		}
 	}
-- 
2.25.1

Re: [Intel-gfx] [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp prescision

[Kandpal, Suraj]

> Subject: [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp
> prescision
> 
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> Add helper to get the DSC bits_per_pixel precision for the DP sink.
> 

I think you forgot to add my reviewed by that I gave in the last revision 😝
Anyways,

LGTM.

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/display/drm_dp_helper.c | 27 +++++++++++++++++++++++++
>  include/drm/display/drm_dp_helper.h     |  1 +
>  2 files changed, 28 insertions(+)
> 
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
> b/drivers/gpu/drm/display/drm_dp_helper.c
> index 8a1b64c57dfd..5c23d5b8fc50 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -2323,6 +2323,33 @@ int drm_dp_read_desc(struct drm_dp_aux *aux,
> struct drm_dp_desc *desc,  }  EXPORT_SYMBOL(drm_dp_read_desc);
> 
> +/**
> + * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
> + * @dsc_dpcd: DSC capabilities from DPCD
> + *
> + * Returns the bpp precision supported by the DP sink.
> + */
> +u8 drm_dp_dsc_sink_bpp_incr(const u8
> +dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
> +{
> +	u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC -
> +DP_DSC_SUPPORT];
> +
> +	switch (bpp_increment_dpcd) {
> +	case DP_DSC_BITS_PER_PIXEL_1_16:
> +		return 16;
> +	case DP_DSC_BITS_PER_PIXEL_1_8:
> +		return 8;
> +	case DP_DSC_BITS_PER_PIXEL_1_4:
> +		return 4;
> +	case DP_DSC_BITS_PER_PIXEL_1_2:
> +		return 2;
> +	case DP_DSC_BITS_PER_PIXEL_1_1:
> +		return 1;
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
> +
>  /**
>   * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
>   * supported by the DSC sink.
> diff --git a/include/drm/display/drm_dp_helper.h
> b/include/drm/display/drm_dp_helper.h
> index 3369104e2d25..6968d4d87931 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -164,6 +164,7 @@ drm_dp_is_branch(const u8
> dpcd[DP_RECEIVER_CAP_SIZE])  }
> 
>  /* DP/eDP DSC support */
> +u8 drm_dp_dsc_sink_bpp_incr(const u8
> +dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
>  u8 drm_dp_dsc_sink_max_slice_count(const u8
> dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
>  				   bool is_edp);
>  u8 drm_dp_dsc_sink_line_buf_depth(const u8
> dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
> --
> 2.25.1

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC fractional bpp support (rev7)

[Patchwork]

== Series Details ==

Series: Add DSC fractional bpp support (rev7)
URL   : https://patchwork.freedesktop.org/series/111391/
State : warning

== Summary ==

Error: dim checkpatch failed
335c97448415 drm/display/dp: Add helper function to get DSC bpp prescision
1e1010fd7a35 drm/i915/display: Store compressed bpp in U6.4 format
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:339: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#339: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 311 lines checked
346395c16c9e drm/i915/display: Consider fractional vdsc bpp while computing m_n values
931e5062e6b6 drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
df96870bfa53 drm/i915/dsc/mtl: Add support for fractional bpp
dcce55cc2a23 drm/i915/dp: Iterate over output bpp with fractional step size
3ae03ebc7a51 drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
5e2c4525feef drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add DSC fractional bpp support (rev7)

[Patchwork]

== Series Details ==

Series: Add DSC fractional bpp support (rev7)
URL   : https://patchwork.freedesktop.org/series/111391/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for Add DSC fractional bpp support (rev7)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 7633 bytes --]

== Series Details ==

Series: Add DSC fractional bpp support (rev7)
URL   : https://patchwork.freedesktop.org/series/111391/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13623 -> Patchwork_111391v7
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/index.html

Participating hosts (39 -> 39)
------------------------------

  Additional (1): bat-adlm-1 
  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_111391v7 that come from known issues:

### CI changes ###

#### Issues hit ####

  * boot:
    - fi-hsw-4770:        [PASS][1] -> [FAIL][2] ([i915#8293])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/fi-hsw-4770/boot.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/fi-hsw-4770/boot.html

  

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - bat-adlm-1:         NOTRUN -> [SKIP][3] ([i915#3826])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@debugfs_test@basic-hwmon.html

  * igt@fbdev@eof:
    - bat-adlm-1:         NOTRUN -> [SKIP][4] ([i915#2582]) +3 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@fbdev@eof.html

  * igt@fbdev@info:
    - bat-adlm-1:         NOTRUN -> [SKIP][5] ([i915#1849] / [i915#2582])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@fbdev@info.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - bat-adlm-1:         NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_tiled_pread_basic:
    - bat-adlm-1:         NOTRUN -> [SKIP][7] ([i915#3282])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-adlm-1:         NOTRUN -> [SKIP][8] ([i915#6621])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@i915_pm_rps@basic-api.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
    - bat-adlm-1:         NOTRUN -> [SKIP][9] ([i915#1845]) +16 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html

  * igt@kms_flip@basic-plain-flip:
    - bat-adlm-1:         NOTRUN -> [SKIP][10] ([i915#3637]) +3 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@kms_flip@basic-plain-flip.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-adlm-1:         NOTRUN -> [SKIP][11] ([fdo#109285])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_frontbuffer_tracking@basic:
    - bat-adlm-1:         NOTRUN -> [SKIP][12] ([i915#1849])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-adlp-9:         NOTRUN -> [SKIP][13] ([i915#3546]) +2 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlp-9/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  * igt@kms_psr@cursor_plane_move:
    - bat-adlm-1:         NOTRUN -> [SKIP][14] ([i915#1072]) +3 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@kms_psr@cursor_plane_move.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-adlm-1:         NOTRUN -> [SKIP][15] ([i915#3555])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-adlm-1:         NOTRUN -> [SKIP][16] ([i915#1845] / [i915#3708])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-write:
    - bat-adlm-1:         NOTRUN -> [SKIP][17] ([i915#3708]) +2 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-apl-guc:         [DMESG-FAIL][18] ([i915#5334]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@hugepages:
    - bat-mtlp-8:         [DMESG-WARN][20] ([i915#9121]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/bat-mtlp-8/igt@i915_selftest@live@hugepages.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-mtlp-8/igt@i915_selftest@live@hugepages.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
  [i915#9121]: https://gitlab.freedesktop.org/drm/intel/issues/9121


Build changes
-------------

  * Linux: CI_DRM_13623 -> Patchwork_111391v7

  CI-20190529: 20190529
  CI_DRM_13623: eb35627e1c4a3781c161cd04944e403ce6df3e1c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7480: a8d38db9ac258d7fd71b2cf7607e259a864f95be @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111391v7: eb35627e1c4a3781c161cd04944e403ce6df3e1c @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

a2cfcf910bb4 drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs
4b483929aca4 drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
6f8920388246 drm/i915/dp: Iterate over output bpp with fractional step size
40a32e997ac8 drm/i915/dsc/mtl: Add support for fractional bpp
f423235c58d2 drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
41315368a73b drm/i915/display: Consider fractional vdsc bpp while computing m_n values
a7d7b569d208 drm/i915/display: Store compressed bpp in U6.4 format
9340c8f50171 drm/display/dp: Add helper function to get DSC bpp prescision

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/index.html

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[Intel-gfx] ✗ Fi.CI.IGT: failure for Add DSC fractional bpp support (rev7)

[Patchwork]

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== Series Details ==

Series: Add DSC fractional bpp support (rev7)
URL   : https://patchwork.freedesktop.org/series/111391/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13623_full -> Patchwork_111391v7_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_111391v7_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_111391v7_full, please notify your bug team (lgci.bug.filing@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_111391v7_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_flip@flip-vs-suspend@b-hdmi-a1:
    - shard-tglu:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-tglu-4/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-4/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html

  * igt@kms_universal_plane@cursor-fb-leak-pipe-b:
    - shard-apl:          [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-apl2/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-apl1/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html

  
New tests
---------

  New tests have been introduced between CI_DRM_13623_full and Patchwork_111391v7_full:

### New IGT tests (4) ###

  * igt@kms_atomic_transition@plane-primary-toggle-with-vblank-wait@pipe-a-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@kms_atomic_transition@plane-primary-toggle-with-vblank-wait@pipe-b-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@kms_cursor_crc@cursor-offscreen-64x64@pipe-a-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@kms_cursor_crc@cursor-offscreen-64x64@pipe-d-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_111391v7_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@object-reloc-keep-cache:
    - shard-dg2:          NOTRUN -> [SKIP][5] ([i915#8411])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@api_intel_bb@object-reloc-keep-cache.html

  * igt@device_reset@cold-reset-bound:
    - shard-dg2:          NOTRUN -> [SKIP][6] ([i915#7701])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@device_reset@cold-reset-bound.html

  * igt@drm_fdinfo@most-busy-idle-check-all@vecs1:
    - shard-dg2:          NOTRUN -> [SKIP][7] ([i915#8414]) +9 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@drm_fdinfo@most-busy-idle-check-all@vecs1.html

  * igt@drm_fdinfo@virtual-busy-idle-all:
    - shard-mtlp:         NOTRUN -> [SKIP][8] ([i915#8414])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@drm_fdinfo@virtual-busy-idle-all.html

  * igt@feature_discovery@psr1:
    - shard-dg2:          NOTRUN -> [SKIP][9] ([i915#658])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@feature_discovery@psr1.html

  * igt@gem_basic@multigpu-create-close:
    - shard-mtlp:         NOTRUN -> [SKIP][10] ([i915#7697])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@gem_basic@multigpu-create-close.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-dg2:          NOTRUN -> [SKIP][11] ([i915#7697])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - shard-tglu:         [PASS][12] -> [FAIL][13] ([i915#6268])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-tglu-9/igt@gem_ctx_exec@basic-nohangcheck.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-2/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_ctx_param@set-priority-not-supported:
    - shard-dg2:          NOTRUN -> [SKIP][14] ([fdo#109314])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@gem_ctx_param@set-priority-not-supported.html

  * igt@gem_ctx_persistence@heartbeat-hang:
    - shard-dg2:          NOTRUN -> [SKIP][15] ([i915#8555])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@gem_ctx_persistence@heartbeat-hang.html

  * igt@gem_ctx_persistence@processes:
    - shard-snb:          NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#1099]) +1 other test skip
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-snb1/igt@gem_ctx_persistence@processes.html

  * igt@gem_exec_balancer@bonded-pair:
    - shard-dg2:          NOTRUN -> [SKIP][17] ([i915#4771])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@gem_exec_balancer@bonded-pair.html

  * igt@gem_exec_balancer@invalid-bonds:
    - shard-mtlp:         NOTRUN -> [SKIP][18] ([i915#4036])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@gem_exec_balancer@invalid-bonds.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-rkl:          [PASS][19] -> [FAIL][20] ([i915#2842]) +2 other tests fail
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-rkl-4/igt@gem_exec_fair@basic-pace@vecs0.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-rkl-4/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_fair@basic-throttle:
    - shard-dg2:          NOTRUN -> [SKIP][21] ([i915#3539])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@gem_exec_fair@basic-throttle.html

  * igt@gem_exec_flush@basic-wb-prw-default:
    - shard-dg2:          NOTRUN -> [SKIP][22] ([i915#3539] / [i915#4852]) +2 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@gem_exec_flush@basic-wb-prw-default.html

  * igt@gem_exec_reloc@basic-gtt-read:
    - shard-mtlp:         NOTRUN -> [SKIP][23] ([i915#3281]) +2 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@gem_exec_reloc@basic-gtt-read.html

  * igt@gem_exec_reloc@basic-range-active:
    - shard-dg2:          NOTRUN -> [SKIP][24] ([i915#3281]) +4 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@gem_exec_reloc@basic-range-active.html

  * igt@gem_exec_schedule@preempt-queue-contexts:
    - shard-dg2:          NOTRUN -> [SKIP][25] ([i915#4537] / [i915#4812])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@gem_exec_schedule@preempt-queue-contexts.html

  * igt@gem_exec_suspend@basic-s3@smem:
    - shard-mtlp:         [PASS][26] -> [ABORT][27] ([i915#9262]) +2 other tests abort
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-mtlp-4/igt@gem_exec_suspend@basic-s3@smem.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-6/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@gem_exec_suspend@basic-s4-devices@lmem0:
    - shard-dg2:          [PASS][28] -> [ABORT][29] ([i915#7975] / [i915#8213])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-11/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
    - shard-dg1:          [PASS][30] -> [ABORT][31] ([i915#7975] / [i915#8213])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg1-19/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-14/igt@gem_exec_suspend@basic-s4-devices@lmem0.html

  * igt@gem_fenced_exec_thrash@no-spare-fences-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][32] ([i915#4860])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@gem_fenced_exec_thrash@no-spare-fences-interruptible.html

  * igt@gem_lmem_swapping@heavy-multi:
    - shard-tglu:         NOTRUN -> [SKIP][33] ([i915#4613])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@gem_lmem_swapping@heavy-multi.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg1:          [PASS][34] -> [DMESG-WARN][35] ([i915#4936] / [i915#5493])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg1-16/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-19/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@gem_mmap_gtt@close-race:
    - shard-mtlp:         NOTRUN -> [SKIP][36] ([i915#4077]) +2 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@gem_mmap_gtt@close-race.html

  * igt@gem_mmap_gtt@fault-concurrent-y:
    - shard-dg2:          NOTRUN -> [SKIP][37] ([i915#4077]) +4 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@gem_mmap_gtt@fault-concurrent-y.html

  * igt@gem_mmap_wc@close:
    - shard-dg2:          NOTRUN -> [SKIP][38] ([i915#4083]) +7 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@gem_mmap_wc@close.html

  * igt@gem_partial_pwrite_pread@reads-uncached:
    - shard-dg2:          NOTRUN -> [SKIP][39] ([i915#3282]) +3 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@gem_partial_pwrite_pread@reads-uncached.html

  * igt@gem_partial_pwrite_pread@write:
    - shard-mtlp:         NOTRUN -> [SKIP][40] ([i915#3282])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@gem_partial_pwrite_pread@write.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-snb:          NOTRUN -> [WARN][41] ([i915#2658])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-snb1/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
    - shard-mtlp:         NOTRUN -> [SKIP][42] ([i915#4270])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html

  * igt@gem_pxp@regular-baseline-src-copy-readible:
    - shard-dg2:          NOTRUN -> [SKIP][43] ([i915#4270]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@gem_pxp@regular-baseline-src-copy-readible.html

  * igt@gem_render_copy@yf-tiled-ccs-to-y-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][44] ([i915#8428]) +1 other test skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][45] ([i915#4079])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_softpin@evict-snoop-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][46] ([i915#4885])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@gem_softpin@evict-snoop-interruptible.html

  * igt@gem_spin_batch@spin-all-new:
    - shard-dg2:          NOTRUN -> [FAIL][47] ([i915#5889])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@gem_spin_batch@spin-all-new.html

  * igt@gem_userptr_blits@access-control:
    - shard-dg2:          NOTRUN -> [SKIP][48] ([i915#3297])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@gem_userptr_blits@access-control.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy:
    - shard-dg2:          NOTRUN -> [SKIP][49] ([i915#3297] / [i915#4880]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@gem_userptr_blits@map-fixed-invalidate-busy.html

  * igt@gem_userptr_blits@unsync-unmap:
    - shard-tglu:         NOTRUN -> [SKIP][50] ([i915#3297])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@gem_userptr_blits@unsync-unmap.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-tglu:         NOTRUN -> [FAIL][51] ([i915#3318])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@gem_userptr_blits@vma-merge.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-mtlp:         NOTRUN -> [ABORT][52] ([i915#9262])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-5/igt@gem_workarounds@suspend-resume-fd.html

  * igt@gen3_render_linear_blits:
    - shard-dg2:          NOTRUN -> [SKIP][53] ([fdo#109289]) +4 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@gen3_render_linear_blits.html

  * igt@gen9_exec_parse@bb-start-param:
    - shard-dg2:          NOTRUN -> [SKIP][54] ([i915#2856]) +1 other test skip
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@gen9_exec_parse@bb-start-param.html

  * igt@i915_pipe_stress@stress-xrgb8888-untiled:
    - shard-mtlp:         [PASS][55] -> [FAIL][56] ([i915#8691])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-mtlp-1/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-2/igt@i915_pipe_stress@stress-xrgb8888-untiled.html

  * igt@i915_pm_freq_api@freq-suspend@gt0:
    - shard-dg2:          [PASS][57] -> [INCOMPLETE][58] ([i915#8797])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-11/igt@i915_pm_freq_api@freq-suspend@gt0.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@i915_pm_freq_api@freq-suspend@gt0.html

  * igt@i915_pm_rc6_residency@rc6-idle@rcs0:
    - shard-tglu:         NOTRUN -> [WARN][59] ([i915#2681]) +3 other tests warn
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html

  * igt@i915_pm_rpm@modeset-lpsp:
    - shard-dg2:          [PASS][60] -> [SKIP][61] ([i915#1397]) +1 other test skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-10/igt@i915_pm_rpm@modeset-lpsp.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@i915_pm_rpm@modeset-lpsp.html

  * igt@i915_pm_rpm@modeset-lpsp-stress:
    - shard-dg2:          NOTRUN -> [SKIP][62] ([i915#1397])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@i915_pm_rpm@modeset-lpsp-stress.html

  * igt@i915_pm_rps@reset:
    - shard-snb:          [PASS][63] -> [INCOMPLETE][64] ([i915#7790])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-snb5/igt@i915_pm_rps@reset.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-snb5/igt@i915_pm_rps@reset.html

  * igt@i915_pm_rps@thresholds-park@gt0:
    - shard-dg2:          NOTRUN -> [SKIP][65] ([i915#8925])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@i915_pm_rps@thresholds-park@gt0.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-rkl:          [PASS][66] -> [FAIL][67] ([fdo#103375])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-rkl-2/igt@i915_suspend@basic-s3-without-i915.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-rkl-4/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_addfb_basic@clobberred-modifier:
    - shard-dg2:          NOTRUN -> [SKIP][68] ([i915#4212]) +1 other test skip
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_addfb_basic@clobberred-modifier.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-4-y-rc_ccs:
    - shard-dg1:          NOTRUN -> [SKIP][69] ([i915#8502]) +7 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-18/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-4-y-rc_ccs.html

  * igt@kms_async_flips@crc@pipe-a-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [FAIL][70] ([i915#8247]) +3 other tests fail
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_async_flips@crc@pipe-a-hdmi-a-2.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-dg2:          NOTRUN -> [SKIP][71] ([i915#404])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-apl:          NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#1769])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-apl2/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@linear-8bpp-rotate-90:
    - shard-mtlp:         NOTRUN -> [SKIP][73] ([fdo#111614])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_big_fb@linear-8bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-270:
    - shard-dg2:          NOTRUN -> [SKIP][74] ([fdo#111614]) +1 other test skip
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-0:
    - shard-mtlp:         NOTRUN -> [SKIP][75] ([fdo#111615]) +1 other test skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-5/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-270:
    - shard-dg2:          NOTRUN -> [SKIP][76] ([i915#5190]) +8 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-tglu:         [PASS][77] -> [FAIL][78] ([i915#3743]) +1 other test fail
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-tglu-9/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-apl:          NOTRUN -> [SKIP][79] ([fdo#109271]) +22 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-apl2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
    - shard-dg2:          NOTRUN -> [SKIP][80] ([i915#4538] / [i915#5190]) +6 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-tglu:         NOTRUN -> [SKIP][81] ([fdo#111615])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_joiner@2x-modeset:
    - shard-dg2:          NOTRUN -> [SKIP][82] ([i915#2705])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_big_joiner@2x-modeset.html

  * igt@kms_big_joiner@invalid-modeset:
    - shard-mtlp:         NOTRUN -> [SKIP][83] ([i915#2705])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_big_joiner@invalid-modeset.html

  * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs:
    - shard-tglu:         NOTRUN -> [SKIP][84] ([i915#3689] / [i915#3886] / [i915#5354] / [i915#6095])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_dg2_rc_ccs_cc:
    - shard-tglu:         NOTRUN -> [SKIP][85] ([i915#5354] / [i915#6095]) +4 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_dg2_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs:
    - shard-dg2:          NOTRUN -> [SKIP][86] ([i915#3689] / [i915#3886] / [i915#5354]) +7 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-bad-rotation-90-yf_tiled_ccs:
    - shard-dg2:          NOTRUN -> [SKIP][87] ([i915#3689] / [i915#5354]) +11 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_ccs@pipe-b-bad-rotation-90-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][88] ([i915#3886] / [i915#6095]) +1 other test skip
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#3886])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-apl2/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-d-bad-pixel-format-4_tiled_dg2_mc_ccs:
    - shard-tglu:         NOTRUN -> [SKIP][90] ([i915#3689] / [i915#5354] / [i915#6095]) +1 other test skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_ccs@pipe-d-bad-pixel-format-4_tiled_dg2_mc_ccs.html

  * igt@kms_ccs@pipe-d-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][91] ([i915#6095]) +3 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs.html

  * igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][92] ([i915#4087] / [i915#7213]) +2 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-10/igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-1.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][93] ([i915#7213])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-10/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html

  * igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][94] ([i915#4087]) +3 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-10/igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1.html

  * igt@kms_chamelium_color@ctm-0-25:
    - shard-tglu:         NOTRUN -> [SKIP][95] ([fdo#111827])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_chamelium_color@ctm-0-25.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-dg2:          NOTRUN -> [SKIP][96] ([fdo#111827]) +1 other test skip
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k:
    - shard-dg2:          NOTRUN -> [SKIP][97] ([i915#7828]) +7 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html

  * igt@kms_chamelium_frames@dp-crc-fast:
    - shard-tglu:         NOTRUN -> [SKIP][98] ([i915#7828])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_chamelium_frames@dp-crc-fast.html

  * igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
    - shard-mtlp:         NOTRUN -> [SKIP][99] ([i915#7828])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-5/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html

  * igt@kms_color@deep-color:
    - shard-dg2:          NOTRUN -> [SKIP][100] ([i915#3555]) +5 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@kms_color@deep-color.html

  * igt@kms_content_protection@atomic:
    - shard-tglu:         NOTRUN -> [SKIP][101] ([i915#6944] / [i915#7116] / [i915#7118]) +1 other test skip
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-mtlp:         NOTRUN -> [SKIP][102] ([i915#6944])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@srm:
    - shard-dg2:          NOTRUN -> [SKIP][103] ([i915#7118])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@kms_content_protection@srm.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-mtlp:         NOTRUN -> [SKIP][104] ([i915#3359])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-tglu:         NOTRUN -> [SKIP][105] ([i915#3359])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-dg2:          NOTRUN -> [SKIP][106] ([i915#3359])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-tglu:         NOTRUN -> [SKIP][107] ([fdo#109274])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
    - shard-dg2:          NOTRUN -> [SKIP][108] ([fdo#109274] / [i915#5354]) +4 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
    - shard-mtlp:         NOTRUN -> [SKIP][109] ([i915#3546]) +1 other test skip
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-apl:          [PASS][110] -> [FAIL][111] ([i915#2346]) +1 other test fail
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-mtlp:         NOTRUN -> [SKIP][112] ([i915#4213])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-dg2:          NOTRUN -> [SKIP][113] ([i915#4103] / [i915#4213])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dirtyfb@dirtyfb-ioctl@drrs-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [SKIP][114] ([i915#9226] / [i915#9261]) +1 other test skip
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_dirtyfb@dirtyfb-ioctl@drrs-hdmi-a-2.html

  * igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-1:
    - shard-dg1:          NOTRUN -> [SKIP][115] ([i915#9227])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-19/igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-1.html

  * igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [SKIP][116] ([i915#9227])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-2.html

  * igt@kms_dirtyfb@dirtyfb-ioctl@psr-hdmi-a-1:
    - shard-dg1:          NOTRUN -> [SKIP][117] ([i915#9226] / [i915#9261]) +1 other test skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-19/igt@kms_dirtyfb@dirtyfb-ioctl@psr-hdmi-a-1.html

  * igt@kms_dsc@dsc-basic:
    - shard-dg2:          NOTRUN -> [SKIP][118] ([i915#3555] / [i915#3840])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@kms_dsc@dsc-basic.html

  * igt@kms_fence_pin_leak:
    - shard-mtlp:         NOTRUN -> [SKIP][119] ([i915#4881])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_fence_pin_leak.html

  * igt@kms_flip@2x-dpms-vs-vblank-race:
    - shard-tglu:         NOTRUN -> [SKIP][120] ([fdo#109274] / [i915#3637])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_flip@2x-dpms-vs-vblank-race.html

  * igt@kms_flip@2x-flip-vs-fences-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][121] ([i915#8381])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_flip@2x-flip-vs-fences-interruptible.html

  * igt@kms_flip@2x-nonexisting-fb:
    - shard-snb:          NOTRUN -> [SKIP][122] ([fdo#109271]) +116 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-snb2/igt@kms_flip@2x-nonexisting-fb.html

  * igt@kms_flip@2x-plain-flip:
    - shard-dg2:          NOTRUN -> [SKIP][123] ([fdo#109274])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][124] ([i915#2672]) +1 other test skip
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][125] ([i915#3555] / [i915#8810])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt:
    - shard-dg2:          [PASS][126] -> [FAIL][127] ([i915#6880]) +2 other tests fail
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt:
    - shard-dg2:          NOTRUN -> [SKIP][128] ([i915#5354]) +27 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-pwrite:
    - shard-tglu:         NOTRUN -> [SKIP][129] ([fdo#109280]) +4 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][130] ([i915#8708]) +18 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][131] ([i915#3458]) +9 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu:
    - shard-tglu:         NOTRUN -> [SKIP][132] ([fdo#110189]) +5 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][133] ([i915#8708]) +1 other test skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-mtlp:         NOTRUN -> [SKIP][134] ([i915#1825]) +3 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-dg2:          NOTRUN -> [SKIP][135] ([i915#3555] / [i915#8228]) +1 other test skip
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-tglu:         NOTRUN -> [SKIP][136] ([i915#3555]) +1 other test skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-c-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [SKIP][137] ([i915#5176]) +7 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-c-hdmi-a-2.html

  * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-hdmi-a-1:
    - shard-dg1:          NOTRUN -> [SKIP][138] ([i915#5176]) +11 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-19/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][139] ([i915#5176]) +3 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-rkl-4/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][140] ([i915#5235]) +3 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-dp-4:
    - shard-dg2:          NOTRUN -> [SKIP][141] ([i915#5235]) +19 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-11/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-dp-4.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-1:
    - shard-dg1:          NOTRUN -> [SKIP][142] ([i915#5235]) +19 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-19/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-1.html

  * igt@kms_prime@basic-crc-hybrid:
    - shard-dg2:          NOTRUN -> [SKIP][143] ([i915#6524] / [i915#6805])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_prime@basic-crc-hybrid.html

  * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
    - shard-tglu:         NOTRUN -> [SKIP][144] ([i915#658])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-apl:          NOTRUN -> [SKIP][145] ([fdo#109271] / [i915#658])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-apl2/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@primary_page_flip:
    - shard-dg2:          NOTRUN -> [SKIP][146] ([i915#1072]) +5 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_psr@primary_page_flip.html

  * igt@kms_rotation_crc@exhaust-fences:
    - shard-mtlp:         NOTRUN -> [SKIP][147] ([i915#4235])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_rotation_crc@exhaust-fences.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
    - shard-rkl:          [PASS][148] -> [INCOMPLETE][149] ([i915#8875])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-rkl-1/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-rkl-7/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
    - shard-dg2:          NOTRUN -> [SKIP][150] ([i915#4235]) +1 other test skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html

  * igt@kms_selftest@drm_format:
    - shard-apl:          NOTRUN -> [SKIP][151] ([fdo#109271] / [i915#8661])
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-apl2/igt@kms_selftest@drm_format.html

  * igt@kms_universal_plane@cursor-fb-leak-pipe-a:
    - shard-snb:          NOTRUN -> [FAIL][152] ([i915#9196])
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-snb1/igt@kms_universal_plane@cursor-fb-leak-pipe-a.html

  * igt@kms_universal_plane@cursor-fb-leak-pipe-d:
    - shard-dg2:          [PASS][153] -> [FAIL][154] ([i915#9196])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-5/igt@kms_universal_plane@cursor-fb-leak-pipe-d.html
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-10/igt@kms_universal_plane@cursor-fb-leak-pipe-d.html

  * igt@perf@global-sseu-config-invalid:
    - shard-mtlp:         NOTRUN -> [SKIP][155] ([i915#7387])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@perf@global-sseu-config-invalid.html

  * igt@perf_pmu@faulting-read@gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][156] ([i915#8440])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@perf_pmu@faulting-read@gtt.html

  * igt@perf_pmu@most-busy-idle-check-all@rcs0:
    - shard-rkl:          [PASS][157] -> [FAIL][158] ([i915#4349])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-rkl-1/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-rkl-6/igt@perf_pmu@most-busy-idle-check-all@rcs0.html

  * igt@prime_vgem@basic-read:
    - shard-dg2:          NOTRUN -> [SKIP][159] ([i915#3291] / [i915#3708])
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@fence-write-hang:
    - shard-dg2:          NOTRUN -> [SKIP][160] ([i915#3708])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@prime_vgem@fence-write-hang.html

  * igt@v3d/v3d_perfmon@create-perfmon-exceed:
    - shard-mtlp:         NOTRUN -> [SKIP][161] ([i915#2575])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@v3d/v3d_perfmon@create-perfmon-exceed.html

  * igt@v3d/v3d_submit_cl@simple-flush-cache:
    - shard-tglu:         NOTRUN -> [SKIP][162] ([fdo#109315] / [i915#2575]) +1 other test skip
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@v3d/v3d_submit_cl@simple-flush-cache.html

  * igt@v3d/v3d_wait_bo@unused-bo-1ns:
    - shard-dg2:          NOTRUN -> [SKIP][163] ([i915#2575]) +8 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@v3d/v3d_wait_bo@unused-bo-1ns.html

  * igt@vc4/vc4_label_bo@set-bad-name:
    - shard-mtlp:         NOTRUN -> [SKIP][164] ([i915#7711]) +1 other test skip
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@vc4/vc4_label_bo@set-bad-name.html

  * igt@vc4/vc4_label_bo@set-kernel-name:
    - shard-dg2:          NOTRUN -> [SKIP][165] ([i915#7711]) +4 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@vc4/vc4_label_bo@set-kernel-name.html

  * igt@vc4/vc4_purgeable_bo@mark-willneed:
    - shard-tglu:         NOTRUN -> [SKIP][166] ([i915#2575]) +1 other test skip
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@vc4/vc4_purgeable_bo@mark-willneed.html

  
#### Possible fixes ####

  * igt@drm_fdinfo@most-busy-check-all@rcs0:
    - shard-rkl:          [FAIL][167] ([i915#7742]) -> [PASS][168]
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-rkl-1/igt@drm_fdinfo@most-busy-check-all@rcs0.html

  * igt@gem_eio@hibernate:
    - shard-tglu:         [ABORT][169] ([i915#7975] / [i915#8213] / [i915#8398]) -> [PASS][170]
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-tglu-10/igt@gem_eio@hibernate.html
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@gem_eio@hibernate.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-rkl:          [FAIL][171] ([i915#2846]) -> [PASS][172]
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-rkl-2/igt@gem_exec_fair@basic-deadline.html
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-rkl-4/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg2:          [TIMEOUT][173] ([i915#5493]) -> [PASS][174]
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-5/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-10/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@gem_softpin@noreloc-s3:
    - shard-dg2:          [FAIL][175] ([fdo#103375]) -> [PASS][176]
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-5/igt@gem_softpin@noreloc-s3.html
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@gem_softpin@noreloc-s3.html

  * igt@gem_sync@basic-each:
    - shard-mtlp:         [ABORT][177] ([i915#9262]) -> [PASS][178] +1 other test pass
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-mtlp-2/igt@gem_sync@basic-each.html
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-5/igt@gem_sync@basic-each.html

  * igt@i915_hangman@engine-error-state-capture@vecs0:
    - shard-mtlp:         [DMESG-WARN][179] ([i915#9262]) -> [PASS][180]
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-mtlp-1/igt@i915_hangman@engine-error-state-capture@vecs0.html
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-2/igt@i915_hangman@engine-error-state-capture@vecs0.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
    - shard-dg1:          [FAIL][181] ([i915#3591]) -> [PASS][182] +1 other test pass
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg1-12/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html

  * igt@i915_pm_rpm@dpms-lpsp:
    - shard-dg1:          [SKIP][183] ([i915#1397]) -> [PASS][184] +1 other test pass
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg1-17/igt@i915_pm_rpm@dpms-lpsp.html
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-19/igt@i915_pm_rpm@dpms-lpsp.html

  * igt@i915_pm_rpm@i2c:
    - shard-dg2:          [FAIL][185] ([i915#8717]) -> [PASS][186]
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-2/igt@i915_pm_rpm@i2c.html
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-10/igt@i915_pm_rpm@i2c.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-tglu:         [FAIL][187] ([i915#3743]) -> [PASS][188]
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-tglu-7/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-glk:          [FAIL][189] ([i915#2346]) -> [PASS][190]
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - shard-dg2:          [FAIL][191] ([i915#6880]) -> [PASS][192]
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-1:
    - shard-apl:          [INCOMPLETE][193] -> [PASS][194]
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-apl1/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-1.html
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-apl2/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-1.html

  * igt@kms_universal_plane@cursor-fb-leak-pipe-c:
    - shard-tglu:         [FAIL][195] ([i915#9196]) -> [PASS][196]
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-tglu-2/igt@kms_universal_plane@cursor-fb-leak-pipe-c.html
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-9/igt@kms_universal_plane@cursor-fb-leak-pipe-c.html

  * igt@perf_pmu@busy-accuracy-98@rcs0:
    - shard-mtlp:         [FAIL][197] ([i915#4349]) -> [PASS][198] +2 other tests pass
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-mtlp-4/igt@perf_pmu@busy-accuracy-98@rcs0.html
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-4/igt@perf_pmu@busy-accuracy-98@rcs0.html

  * igt@perf_pmu@busy-double-start@vecs1:
    - shard-dg2:          [FAIL][199] ([i915#4349]) -> [PASS][200] +3 other tests pass
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-10/igt@perf_pmu@busy-double-start@vecs1.html
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@perf_pmu@busy-double-start@vecs1.html

  * igt@syncobj_wait@invalid-single-wait-unsubmitted:
    - shard-dg1:          [DMESG-WARN][201] ([i915#1982] / [i915#4423]) -> [PASS][202]
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg1-14/igt@syncobj_wait@invalid-single-wait-unsubmitted.html
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-16/igt@syncobj_wait@invalid-single-wait-unsubmitted.html

  
#### Warnings ####

  * igt@i915_hangman@gt-error-state-capture@vecs0:
    - shard-mtlp:         [ABORT][203] ([i915#9262]) -> [DMESG-WARN][204] ([i915#9262])
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-mtlp-3/igt@i915_hangman@gt-error-state-capture@vecs0.html
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-8/igt@i915_hangman@gt-error-state-capture@vecs0.html

  * igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_mtl_rc_ccs:
    - shard-dg1:          [SKIP][205] ([i915#4423] / [i915#5354] / [i915#6095]) -> [SKIP][206] ([i915#5354] / [i915#6095])
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg1-14/igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_mtl_rc_ccs.html
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-16/igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_mtl_rc_ccs.html

  * igt@kms_ccs@pipe-c-crc-primary-rotation-180-yf_tiled_ccs:
    - shard-dg1:          [SKIP][207] ([i915#3689] / [i915#4423] / [i915#5354] / [i915#6095]) -> [SKIP][208] ([i915#3689] / [i915#5354] / [i915#6095])
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg1-14/igt@kms_ccs@pipe-c-crc-primary-rotation-180-yf_tiled_ccs.html
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-16/igt@kms_ccs@pipe-c-crc-primary-rotation-180-yf_tiled_ccs.html

  * igt@kms_content_protection@mei_interface:
    - shard-dg2:          [SKIP][209] ([i915#7118]) -> [SKIP][210] ([i915#7118] / [i915#7162])
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-7/igt@kms_content_protection@mei_interface.html
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-11/igt@kms_content_protection@mei_interface.html

  * igt@kms_content_protection@type1:
    - shard-dg2:          [SKIP][211] ([i915#7118] / [i915#7162]) -> [SKIP][212] ([i915#7118])
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-11/igt@kms_content_protection@type1.html
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@kms_content_protection@type1.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-rkl:          [SKIP][213] ([i915#3955]) -> [SKIP][214] ([fdo#110189] / [i915#3955]) +1 other test skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-rkl-4/igt@kms_fbcon_fbt@psr-suspend.html
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-rkl-1/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_force_connector_basic@force-load-detect:
    - shard-rkl:          [SKIP][215] ([fdo#109285] / [i915#4098]) -> [SKIP][216] ([fdo#109285])
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-rkl-2/igt@kms_force_connector_basic@force-load-detect.html
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-rkl-6/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
    - shard-dg1:          [SKIP][217] ([i915#3458] / [i915#4423]) -> [SKIP][218] ([i915#3458])
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg1-14/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html

  * igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-4:
    - shard-dg1:          [SKIP][219] ([i915#4423] / [i915#5176]) -> [SKIP][220] ([i915#5176])
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg1-14/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-4.html
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-16/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-4.html

  * igt@kms_psr@sprite_plane_onoff:
    - shard-dg1:          [SKIP][221] ([i915#1072] / [i915#4078]) -> [SKIP][222] ([i915#1072]) +2 other tests skip
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg1-12/igt@kms_psr@sprite_plane_onoff.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-19/igt@kms_psr@sprite_plane_onoff.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
  [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
  [i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
  [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
  [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
  [i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
  [i915#5889]: https://gitlab.freedesktop.org/drm/intel/issues/5889
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
  [i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
  [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
  [i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
  [i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7790]: https://gitlab.freedesktop.org/drm/intel/issues/7790
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
  [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
  [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
  [i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
  [i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
  [i915#8398]: https://gitlab.freedesktop.org/drm/intel/issues/8398
  [i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
  [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
  [i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
  [i915#8440]: https://gitlab.freedesktop.org/drm/intel/issues/8440
  [i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
  [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
  [i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
  [i915#8691]: https://gitlab.freedesktop.org/drm/intel/issues/8691
  [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
  [i915#8717]: https://gitlab.freedesktop.org/drm/intel/issues/8717
  [i915#8797]: https://gitlab.freedesktop.org/drm/intel/issues/8797
  [i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
  [i915#8875]: https://gitlab.freedesktop.org/drm/intel/issues/8875
  [i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
  [i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
  [i915#9226]: https://gitlab.freedesktop.org/drm/intel/issues/9226
  [i915#9227]: https://gitlab.freedesktop.org/drm/intel/issues/9227
  [i915#9261]: https://gitlab.freedesktop.org/drm/intel/issues/9261
  [i915#9262]: https://gitlab.freedesktop.org/drm/intel/issues/9262


Build changes
-------------

  * Linux: CI_DRM_13623 -> Patchwork_111391v7

  CI-20190529: 20190529
  CI_DRM_13623: eb35627e1c4a3781c161cd04944e403ce6df3e1c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7480: a8d38db9ac258d7fd71b2cf7607e259a864f95be @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111391v7: eb35627e1c4a3781c161cd04944e403ce6df3e1c @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/index.html

[-- Attachment #2: Type: text/html, Size: 74579 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for Add DSC fractional bpp support (rev7)

[Patchwork]

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== Series Details ==

Series: Add DSC fractional bpp support (rev7)
URL   : https://patchwork.freedesktop.org/series/111391/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13623_full -> Patchwork_111391v7_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in Patchwork_111391v7_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@object-reloc-keep-cache:
    - shard-dg2:          NOTRUN -> [SKIP][1] ([i915#8411])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@api_intel_bb@object-reloc-keep-cache.html

  * igt@device_reset@cold-reset-bound:
    - shard-dg2:          NOTRUN -> [SKIP][2] ([i915#7701])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@device_reset@cold-reset-bound.html

  * igt@drm_fdinfo@most-busy-idle-check-all@vecs1:
    - shard-dg2:          NOTRUN -> [SKIP][3] ([i915#8414]) +9 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@drm_fdinfo@most-busy-idle-check-all@vecs1.html

  * igt@drm_fdinfo@virtual-busy-idle-all:
    - shard-mtlp:         NOTRUN -> [SKIP][4] ([i915#8414])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@drm_fdinfo@virtual-busy-idle-all.html

  * igt@feature_discovery@psr1:
    - shard-dg2:          NOTRUN -> [SKIP][5] ([i915#658])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@feature_discovery@psr1.html

  * igt@gem_basic@multigpu-create-close:
    - shard-mtlp:         NOTRUN -> [SKIP][6] ([i915#7697])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@gem_basic@multigpu-create-close.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-dg2:          NOTRUN -> [SKIP][7] ([i915#7697])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - shard-tglu:         [PASS][8] -> [FAIL][9] ([i915#6268])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-tglu-9/igt@gem_ctx_exec@basic-nohangcheck.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-2/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_ctx_param@set-priority-not-supported:
    - shard-dg2:          NOTRUN -> [SKIP][10] ([fdo#109314])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@gem_ctx_param@set-priority-not-supported.html

  * igt@gem_ctx_persistence@heartbeat-hang:
    - shard-dg2:          NOTRUN -> [SKIP][11] ([i915#8555])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@gem_ctx_persistence@heartbeat-hang.html

  * igt@gem_ctx_persistence@processes:
    - shard-snb:          NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1099]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-snb1/igt@gem_ctx_persistence@processes.html

  * igt@gem_exec_balancer@bonded-pair:
    - shard-dg2:          NOTRUN -> [SKIP][13] ([i915#4771])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@gem_exec_balancer@bonded-pair.html

  * igt@gem_exec_balancer@invalid-bonds:
    - shard-mtlp:         NOTRUN -> [SKIP][14] ([i915#4036])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@gem_exec_balancer@invalid-bonds.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-rkl:          [PASS][15] -> [FAIL][16] ([i915#2842]) +2 other tests fail
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-rkl-4/igt@gem_exec_fair@basic-pace@vecs0.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-rkl-4/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_fair@basic-throttle:
    - shard-dg2:          NOTRUN -> [SKIP][17] ([i915#3539])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@gem_exec_fair@basic-throttle.html

  * igt@gem_exec_flush@basic-wb-prw-default:
    - shard-dg2:          NOTRUN -> [SKIP][18] ([i915#3539] / [i915#4852]) +2 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@gem_exec_flush@basic-wb-prw-default.html

  * igt@gem_exec_reloc@basic-gtt-read:
    - shard-mtlp:         NOTRUN -> [SKIP][19] ([i915#3281]) +2 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@gem_exec_reloc@basic-gtt-read.html

  * igt@gem_exec_reloc@basic-range-active:
    - shard-dg2:          NOTRUN -> [SKIP][20] ([i915#3281]) +4 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@gem_exec_reloc@basic-range-active.html

  * igt@gem_exec_schedule@preempt-queue-contexts:
    - shard-dg2:          NOTRUN -> [SKIP][21] ([i915#4537] / [i915#4812])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@gem_exec_schedule@preempt-queue-contexts.html

  * igt@gem_exec_suspend@basic-s3@smem:
    - shard-mtlp:         [PASS][22] -> [ABORT][23] ([i915#9262]) +2 other tests abort
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-mtlp-4/igt@gem_exec_suspend@basic-s3@smem.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-6/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@gem_exec_suspend@basic-s4-devices@lmem0:
    - shard-dg2:          [PASS][24] -> [ABORT][25] ([i915#7975] / [i915#8213])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-11/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
    - shard-dg1:          [PASS][26] -> [ABORT][27] ([i915#7975] / [i915#8213])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg1-19/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-14/igt@gem_exec_suspend@basic-s4-devices@lmem0.html

  * igt@gem_fenced_exec_thrash@no-spare-fences-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][28] ([i915#4860])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@gem_fenced_exec_thrash@no-spare-fences-interruptible.html

  * igt@gem_lmem_swapping@heavy-multi:
    - shard-tglu:         NOTRUN -> [SKIP][29] ([i915#4613])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@gem_lmem_swapping@heavy-multi.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg1:          [PASS][30] -> [DMESG-WARN][31] ([i915#4936] / [i915#5493])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg1-16/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-19/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@gem_mmap_gtt@close-race:
    - shard-mtlp:         NOTRUN -> [SKIP][32] ([i915#4077]) +2 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@gem_mmap_gtt@close-race.html

  * igt@gem_mmap_gtt@fault-concurrent-y:
    - shard-dg2:          NOTRUN -> [SKIP][33] ([i915#4077]) +4 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@gem_mmap_gtt@fault-concurrent-y.html

  * igt@gem_mmap_wc@close:
    - shard-dg2:          NOTRUN -> [SKIP][34] ([i915#4083]) +7 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@gem_mmap_wc@close.html

  * igt@gem_partial_pwrite_pread@reads-uncached:
    - shard-dg2:          NOTRUN -> [SKIP][35] ([i915#3282]) +3 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@gem_partial_pwrite_pread@reads-uncached.html

  * igt@gem_partial_pwrite_pread@write:
    - shard-mtlp:         NOTRUN -> [SKIP][36] ([i915#3282])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@gem_partial_pwrite_pread@write.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-snb:          NOTRUN -> [WARN][37] ([i915#2658])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-snb1/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
    - shard-mtlp:         NOTRUN -> [SKIP][38] ([i915#4270])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html

  * igt@gem_pxp@regular-baseline-src-copy-readible:
    - shard-dg2:          NOTRUN -> [SKIP][39] ([i915#4270]) +1 other test skip
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@gem_pxp@regular-baseline-src-copy-readible.html

  * igt@gem_render_copy@yf-tiled-ccs-to-y-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][40] ([i915#8428]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][41] ([i915#4079])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_softpin@evict-snoop-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][42] ([i915#4885])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@gem_softpin@evict-snoop-interruptible.html

  * igt@gem_spin_batch@spin-all-new:
    - shard-dg2:          NOTRUN -> [FAIL][43] ([i915#5889])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@gem_spin_batch@spin-all-new.html

  * igt@gem_userptr_blits@access-control:
    - shard-dg2:          NOTRUN -> [SKIP][44] ([i915#3297])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@gem_userptr_blits@access-control.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy:
    - shard-dg2:          NOTRUN -> [SKIP][45] ([i915#3297] / [i915#4880]) +1 other test skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@gem_userptr_blits@map-fixed-invalidate-busy.html

  * igt@gem_userptr_blits@unsync-unmap:
    - shard-tglu:         NOTRUN -> [SKIP][46] ([i915#3297])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@gem_userptr_blits@unsync-unmap.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-tglu:         NOTRUN -> [FAIL][47] ([i915#3318])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@gem_userptr_blits@vma-merge.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-mtlp:         NOTRUN -> [ABORT][48] ([i915#9262])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-5/igt@gem_workarounds@suspend-resume-fd.html

  * igt@gen3_render_linear_blits:
    - shard-dg2:          NOTRUN -> [SKIP][49] ([fdo#109289]) +4 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@gen3_render_linear_blits.html

  * igt@gen9_exec_parse@bb-start-param:
    - shard-dg2:          NOTRUN -> [SKIP][50] ([i915#2856]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@gen9_exec_parse@bb-start-param.html

  * igt@i915_pipe_stress@stress-xrgb8888-untiled:
    - shard-mtlp:         [PASS][51] -> [FAIL][52] ([i915#8691])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-mtlp-1/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-2/igt@i915_pipe_stress@stress-xrgb8888-untiled.html

  * igt@i915_pm_freq_api@freq-suspend@gt0:
    - shard-dg2:          [PASS][53] -> [INCOMPLETE][54] ([i915#8797])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-11/igt@i915_pm_freq_api@freq-suspend@gt0.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@i915_pm_freq_api@freq-suspend@gt0.html

  * igt@i915_pm_rc6_residency@rc6-idle@rcs0:
    - shard-tglu:         NOTRUN -> [WARN][55] ([i915#2681]) +3 other tests warn
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html

  * igt@i915_pm_rpm@modeset-lpsp:
    - shard-dg2:          [PASS][56] -> [SKIP][57] ([i915#1397]) +1 other test skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-10/igt@i915_pm_rpm@modeset-lpsp.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@i915_pm_rpm@modeset-lpsp.html

  * igt@i915_pm_rpm@modeset-lpsp-stress:
    - shard-dg2:          NOTRUN -> [SKIP][58] ([i915#1397])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@i915_pm_rpm@modeset-lpsp-stress.html

  * igt@i915_pm_rps@reset:
    - shard-snb:          [PASS][59] -> [INCOMPLETE][60] ([i915#7790])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-snb5/igt@i915_pm_rps@reset.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-snb5/igt@i915_pm_rps@reset.html

  * igt@i915_pm_rps@thresholds-park@gt0:
    - shard-dg2:          NOTRUN -> [SKIP][61] ([i915#8925])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@i915_pm_rps@thresholds-park@gt0.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-rkl:          [PASS][62] -> [FAIL][63] ([fdo#103375])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-rkl-2/igt@i915_suspend@basic-s3-without-i915.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-rkl-4/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_addfb_basic@clobberred-modifier:
    - shard-dg2:          NOTRUN -> [SKIP][64] ([i915#4212]) +1 other test skip
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_addfb_basic@clobberred-modifier.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-4-y-rc_ccs:
    - shard-dg1:          NOTRUN -> [SKIP][65] ([i915#8502]) +7 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-18/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-4-y-rc_ccs.html

  * igt@kms_async_flips@crc@pipe-a-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [FAIL][66] ([i915#8247]) +3 other tests fail
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_async_flips@crc@pipe-a-hdmi-a-2.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-dg2:          NOTRUN -> [SKIP][67] ([i915#404])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-apl:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#1769])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-apl2/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@linear-8bpp-rotate-90:
    - shard-mtlp:         NOTRUN -> [SKIP][69] ([fdo#111614])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_big_fb@linear-8bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-270:
    - shard-dg2:          NOTRUN -> [SKIP][70] ([fdo#111614]) +1 other test skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-0:
    - shard-mtlp:         NOTRUN -> [SKIP][71] ([fdo#111615]) +1 other test skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-5/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-270:
    - shard-dg2:          NOTRUN -> [SKIP][72] ([i915#5190]) +8 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-tglu:         [PASS][73] -> [FAIL][74] ([i915#3743]) +1 other test fail
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-tglu-9/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-apl:          NOTRUN -> [SKIP][75] ([fdo#109271]) +22 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-apl2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
    - shard-dg2:          NOTRUN -> [SKIP][76] ([i915#4538] / [i915#5190]) +6 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-tglu:         NOTRUN -> [SKIP][77] ([fdo#111615])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_joiner@2x-modeset:
    - shard-dg2:          NOTRUN -> [SKIP][78] ([i915#2705])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_big_joiner@2x-modeset.html

  * igt@kms_big_joiner@invalid-modeset:
    - shard-mtlp:         NOTRUN -> [SKIP][79] ([i915#2705])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_big_joiner@invalid-modeset.html

  * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs:
    - shard-tglu:         NOTRUN -> [SKIP][80] ([i915#3689] / [i915#3886] / [i915#5354] / [i915#6095])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_dg2_rc_ccs_cc:
    - shard-tglu:         NOTRUN -> [SKIP][81] ([i915#5354] / [i915#6095]) +4 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_dg2_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs:
    - shard-dg2:          NOTRUN -> [SKIP][82] ([i915#3689] / [i915#3886] / [i915#5354]) +7 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-bad-rotation-90-yf_tiled_ccs:
    - shard-dg2:          NOTRUN -> [SKIP][83] ([i915#3689] / [i915#5354]) +11 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_ccs@pipe-b-bad-rotation-90-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][84] ([i915#3886] / [i915#6095]) +1 other test skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#3886])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-apl2/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-d-bad-pixel-format-4_tiled_dg2_mc_ccs:
    - shard-tglu:         NOTRUN -> [SKIP][86] ([i915#3689] / [i915#5354] / [i915#6095]) +1 other test skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_ccs@pipe-d-bad-pixel-format-4_tiled_dg2_mc_ccs.html

  * igt@kms_ccs@pipe-d-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][87] ([i915#6095]) +3 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs.html

  * igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][88] ([i915#4087] / [i915#7213]) +2 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-10/igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-1.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][89] ([i915#7213])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-10/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html

  * igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][90] ([i915#4087]) +3 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-10/igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1.html

  * igt@kms_chamelium_color@ctm-0-25:
    - shard-tglu:         NOTRUN -> [SKIP][91] ([fdo#111827])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_chamelium_color@ctm-0-25.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-dg2:          NOTRUN -> [SKIP][92] ([fdo#111827]) +1 other test skip
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k:
    - shard-dg2:          NOTRUN -> [SKIP][93] ([i915#7828]) +7 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html

  * igt@kms_chamelium_frames@dp-crc-fast:
    - shard-tglu:         NOTRUN -> [SKIP][94] ([i915#7828])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_chamelium_frames@dp-crc-fast.html

  * igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
    - shard-mtlp:         NOTRUN -> [SKIP][95] ([i915#7828])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-5/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html

  * igt@kms_color@deep-color:
    - shard-dg2:          NOTRUN -> [SKIP][96] ([i915#3555]) +5 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@kms_color@deep-color.html

  * igt@kms_content_protection@atomic:
    - shard-tglu:         NOTRUN -> [SKIP][97] ([i915#6944] / [i915#7116] / [i915#7118]) +1 other test skip
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-mtlp:         NOTRUN -> [SKIP][98] ([i915#6944])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@srm:
    - shard-dg2:          NOTRUN -> [SKIP][99] ([i915#7118])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@kms_content_protection@srm.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-mtlp:         NOTRUN -> [SKIP][100] ([i915#3359])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-tglu:         NOTRUN -> [SKIP][101] ([i915#3359])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-dg2:          NOTRUN -> [SKIP][102] ([i915#3359])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-tglu:         NOTRUN -> [SKIP][103] ([fdo#109274])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
    - shard-dg2:          NOTRUN -> [SKIP][104] ([fdo#109274] / [i915#5354]) +4 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
    - shard-mtlp:         NOTRUN -> [SKIP][105] ([i915#3546]) +1 other test skip
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-apl:          [PASS][106] -> [FAIL][107] ([i915#2346]) +1 other test fail
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-mtlp:         NOTRUN -> [SKIP][108] ([i915#4213])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-dg2:          NOTRUN -> [SKIP][109] ([i915#4103] / [i915#4213])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dirtyfb@dirtyfb-ioctl@drrs-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [SKIP][110] ([i915#9226] / [i915#9261]) +1 other test skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_dirtyfb@dirtyfb-ioctl@drrs-hdmi-a-2.html

  * igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-1:
    - shard-dg1:          NOTRUN -> [SKIP][111] ([i915#9227])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-19/igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-1.html

  * igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [SKIP][112] ([i915#9227])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-2.html

  * igt@kms_dirtyfb@dirtyfb-ioctl@psr-hdmi-a-1:
    - shard-dg1:          NOTRUN -> [SKIP][113] ([i915#9226] / [i915#9261]) +1 other test skip
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-19/igt@kms_dirtyfb@dirtyfb-ioctl@psr-hdmi-a-1.html

  * igt@kms_dsc@dsc-basic:
    - shard-dg2:          NOTRUN -> [SKIP][114] ([i915#3555] / [i915#3840])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@kms_dsc@dsc-basic.html

  * igt@kms_fence_pin_leak:
    - shard-mtlp:         NOTRUN -> [SKIP][115] ([i915#4881])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_fence_pin_leak.html

  * igt@kms_flip@2x-dpms-vs-vblank-race:
    - shard-tglu:         NOTRUN -> [SKIP][116] ([fdo#109274] / [i915#3637])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_flip@2x-dpms-vs-vblank-race.html

  * igt@kms_flip@2x-flip-vs-fences-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][117] ([i915#8381])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_flip@2x-flip-vs-fences-interruptible.html

  * igt@kms_flip@2x-nonexisting-fb:
    - shard-snb:          NOTRUN -> [SKIP][118] ([fdo#109271]) +116 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-snb2/igt@kms_flip@2x-nonexisting-fb.html

  * igt@kms_flip@2x-plain-flip:
    - shard-dg2:          NOTRUN -> [SKIP][119] ([fdo#109274])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip@flip-vs-suspend@b-hdmi-a1:
    - shard-tglu:         [PASS][120] -> [INCOMPLETE][121] ([i915#9369])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-tglu-4/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-4/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][122] ([i915#2672]) +1 other test skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][123] ([i915#3555] / [i915#8810])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt:
    - shard-dg2:          [PASS][124] -> [FAIL][125] ([i915#6880]) +2 other tests fail
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt:
    - shard-dg2:          NOTRUN -> [SKIP][126] ([i915#5354]) +27 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-pwrite:
    - shard-tglu:         NOTRUN -> [SKIP][127] ([fdo#109280]) +4 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][128] ([i915#8708]) +18 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][129] ([i915#3458]) +9 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu:
    - shard-tglu:         NOTRUN -> [SKIP][130] ([fdo#110189]) +5 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][131] ([i915#8708]) +1 other test skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-mtlp:         NOTRUN -> [SKIP][132] ([i915#1825]) +3 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-dg2:          NOTRUN -> [SKIP][133] ([i915#3555] / [i915#8228]) +1 other test skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-tglu:         NOTRUN -> [SKIP][134] ([i915#3555]) +1 other test skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-c-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [SKIP][135] ([i915#5176]) +7 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-c-hdmi-a-2.html

  * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-hdmi-a-1:
    - shard-dg1:          NOTRUN -> [SKIP][136] ([i915#5176]) +11 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-19/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][137] ([i915#5176]) +3 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-rkl-4/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][138] ([i915#5235]) +3 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-dp-4:
    - shard-dg2:          NOTRUN -> [SKIP][139] ([i915#5235]) +19 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-11/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-dp-4.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-1:
    - shard-dg1:          NOTRUN -> [SKIP][140] ([i915#5235]) +19 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-19/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-1.html

  * igt@kms_prime@basic-crc-hybrid:
    - shard-dg2:          NOTRUN -> [SKIP][141] ([i915#6524] / [i915#6805])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_prime@basic-crc-hybrid.html

  * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
    - shard-tglu:         NOTRUN -> [SKIP][142] ([i915#658])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-apl:          NOTRUN -> [SKIP][143] ([fdo#109271] / [i915#658])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-apl2/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@primary_page_flip:
    - shard-dg2:          NOTRUN -> [SKIP][144] ([i915#1072]) +5 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@kms_psr@primary_page_flip.html

  * igt@kms_rotation_crc@exhaust-fences:
    - shard-mtlp:         NOTRUN -> [SKIP][145] ([i915#4235])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@kms_rotation_crc@exhaust-fences.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
    - shard-rkl:          [PASS][146] -> [INCOMPLETE][147] ([i915#8875])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-rkl-1/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-rkl-7/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
    - shard-dg2:          NOTRUN -> [SKIP][148] ([i915#4235]) +1 other test skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html

  * igt@kms_selftest@drm_format:
    - shard-apl:          NOTRUN -> [SKIP][149] ([fdo#109271] / [i915#8661])
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-apl2/igt@kms_selftest@drm_format.html

  * igt@kms_universal_plane@cursor-fb-leak-pipe-a:
    - shard-snb:          NOTRUN -> [FAIL][150] ([i915#9196])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-snb1/igt@kms_universal_plane@cursor-fb-leak-pipe-a.html

  * igt@kms_universal_plane@cursor-fb-leak-pipe-b:
    - shard-apl:          [PASS][151] -> [FAIL][152] ([i915#9196])
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-apl2/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-apl1/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html

  * igt@kms_universal_plane@cursor-fb-leak-pipe-d:
    - shard-dg2:          [PASS][153] -> [FAIL][154] ([i915#9196])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-5/igt@kms_universal_plane@cursor-fb-leak-pipe-d.html
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-10/igt@kms_universal_plane@cursor-fb-leak-pipe-d.html

  * igt@perf@global-sseu-config-invalid:
    - shard-mtlp:         NOTRUN -> [SKIP][155] ([i915#7387])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@perf@global-sseu-config-invalid.html

  * igt@perf_pmu@faulting-read@gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][156] ([i915#8440])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@perf_pmu@faulting-read@gtt.html

  * igt@perf_pmu@most-busy-idle-check-all@rcs0:
    - shard-rkl:          [PASS][157] -> [FAIL][158] ([i915#4349])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-rkl-1/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-rkl-6/igt@perf_pmu@most-busy-idle-check-all@rcs0.html

  * igt@prime_vgem@basic-read:
    - shard-dg2:          NOTRUN -> [SKIP][159] ([i915#3291] / [i915#3708])
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@fence-write-hang:
    - shard-dg2:          NOTRUN -> [SKIP][160] ([i915#3708])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@prime_vgem@fence-write-hang.html

  * igt@v3d/v3d_perfmon@create-perfmon-exceed:
    - shard-mtlp:         NOTRUN -> [SKIP][161] ([i915#2575])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@v3d/v3d_perfmon@create-perfmon-exceed.html

  * igt@v3d/v3d_submit_cl@simple-flush-cache:
    - shard-tglu:         NOTRUN -> [SKIP][162] ([fdo#109315] / [i915#2575]) +1 other test skip
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@v3d/v3d_submit_cl@simple-flush-cache.html

  * igt@v3d/v3d_wait_bo@unused-bo-1ns:
    - shard-dg2:          NOTRUN -> [SKIP][163] ([i915#2575]) +8 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@v3d/v3d_wait_bo@unused-bo-1ns.html

  * igt@vc4/vc4_label_bo@set-bad-name:
    - shard-mtlp:         NOTRUN -> [SKIP][164] ([i915#7711]) +1 other test skip
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@vc4/vc4_label_bo@set-bad-name.html

  * igt@vc4/vc4_label_bo@set-kernel-name:
    - shard-dg2:          NOTRUN -> [SKIP][165] ([i915#7711]) +4 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@vc4/vc4_label_bo@set-kernel-name.html

  * igt@vc4/vc4_purgeable_bo@mark-willneed:
    - shard-tglu:         NOTRUN -> [SKIP][166] ([i915#2575]) +1 other test skip
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@vc4/vc4_purgeable_bo@mark-willneed.html

  
#### Possible fixes ####

  * igt@drm_fdinfo@most-busy-check-all@rcs0:
    - shard-rkl:          [FAIL][167] ([i915#7742]) -> [PASS][168]
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-rkl-1/igt@drm_fdinfo@most-busy-check-all@rcs0.html

  * igt@gem_eio@hibernate:
    - shard-tglu:         [ABORT][169] ([i915#7975] / [i915#8213] / [i915#8398]) -> [PASS][170]
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-tglu-10/igt@gem_eio@hibernate.html
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-8/igt@gem_eio@hibernate.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-rkl:          [FAIL][171] ([i915#2846]) -> [PASS][172]
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-rkl-2/igt@gem_exec_fair@basic-deadline.html
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-rkl-4/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg2:          [TIMEOUT][173] ([i915#5493]) -> [PASS][174]
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-5/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-10/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@gem_softpin@noreloc-s3:
    - shard-dg2:          [FAIL][175] ([fdo#103375]) -> [PASS][176]
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-5/igt@gem_softpin@noreloc-s3.html
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@gem_softpin@noreloc-s3.html

  * igt@gem_sync@basic-each:
    - shard-mtlp:         [ABORT][177] ([i915#9262]) -> [PASS][178] +1 other test pass
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-mtlp-2/igt@gem_sync@basic-each.html
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-5/igt@gem_sync@basic-each.html

  * igt@i915_hangman@engine-error-state-capture@vecs0:
    - shard-mtlp:         [DMESG-WARN][179] ([i915#9262]) -> [PASS][180]
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-mtlp-1/igt@i915_hangman@engine-error-state-capture@vecs0.html
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-2/igt@i915_hangman@engine-error-state-capture@vecs0.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
    - shard-dg1:          [FAIL][181] ([i915#3591]) -> [PASS][182] +1 other test pass
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg1-12/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html

  * igt@i915_pm_rpm@dpms-lpsp:
    - shard-dg1:          [SKIP][183] ([i915#1397]) -> [PASS][184] +1 other test pass
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg1-17/igt@i915_pm_rpm@dpms-lpsp.html
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-19/igt@i915_pm_rpm@dpms-lpsp.html

  * igt@i915_pm_rpm@i2c:
    - shard-dg2:          [FAIL][185] ([i915#8717]) -> [PASS][186]
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-2/igt@i915_pm_rpm@i2c.html
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-10/igt@i915_pm_rpm@i2c.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-tglu:         [FAIL][187] ([i915#3743]) -> [PASS][188]
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-tglu-7/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-glk:          [FAIL][189] ([i915#2346]) -> [PASS][190]
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - shard-dg2:          [FAIL][191] ([i915#6880]) -> [PASS][192]
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-1:
    - shard-apl:          [INCOMPLETE][193] -> [PASS][194]
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-apl1/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-1.html
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-apl2/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-1.html

  * igt@kms_universal_plane@cursor-fb-leak-pipe-c:
    - shard-tglu:         [FAIL][195] ([i915#9196]) -> [PASS][196]
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-tglu-2/igt@kms_universal_plane@cursor-fb-leak-pipe-c.html
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-9/igt@kms_universal_plane@cursor-fb-leak-pipe-c.html

  * igt@perf_pmu@busy-accuracy-98@rcs0:
    - shard-mtlp:         [FAIL][197] ([i915#4349]) -> [PASS][198] +2 other tests pass
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-mtlp-4/igt@perf_pmu@busy-accuracy-98@rcs0.html
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-4/igt@perf_pmu@busy-accuracy-98@rcs0.html

  * igt@perf_pmu@busy-double-start@vecs1:
    - shard-dg2:          [FAIL][199] ([i915#4349]) -> [PASS][200] +3 other tests pass
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-10/igt@perf_pmu@busy-double-start@vecs1.html
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@perf_pmu@busy-double-start@vecs1.html

  * igt@syncobj_wait@invalid-single-wait-unsubmitted:
    - shard-dg1:          [DMESG-WARN][201] ([i915#1982] / [i915#4423]) -> [PASS][202]
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg1-14/igt@syncobj_wait@invalid-single-wait-unsubmitted.html
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-16/igt@syncobj_wait@invalid-single-wait-unsubmitted.html

  
#### Warnings ####

  * igt@i915_hangman@gt-error-state-capture@vecs0:
    - shard-mtlp:         [ABORT][203] ([i915#9262]) -> [DMESG-WARN][204] ([i915#9262])
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-mtlp-3/igt@i915_hangman@gt-error-state-capture@vecs0.html
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-8/igt@i915_hangman@gt-error-state-capture@vecs0.html

  * igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_mtl_rc_ccs:
    - shard-dg1:          [SKIP][205] ([i915#4423] / [i915#5354] / [i915#6095]) -> [SKIP][206] ([i915#5354] / [i915#6095])
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg1-14/igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_mtl_rc_ccs.html
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-16/igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_mtl_rc_ccs.html

  * igt@kms_ccs@pipe-c-crc-primary-rotation-180-yf_tiled_ccs:
    - shard-dg1:          [SKIP][207] ([i915#3689] / [i915#4423] / [i915#5354] / [i915#6095]) -> [SKIP][208] ([i915#3689] / [i915#5354] / [i915#6095])
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg1-14/igt@kms_ccs@pipe-c-crc-primary-rotation-180-yf_tiled_ccs.html
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-16/igt@kms_ccs@pipe-c-crc-primary-rotation-180-yf_tiled_ccs.html

  * igt@kms_content_protection@mei_interface:
    - shard-dg2:          [SKIP][209] ([i915#7118]) -> [SKIP][210] ([i915#7118] / [i915#7162])
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-7/igt@kms_content_protection@mei_interface.html
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-11/igt@kms_content_protection@mei_interface.html

  * igt@kms_content_protection@type1:
    - shard-dg2:          [SKIP][211] ([i915#7118] / [i915#7162]) -> [SKIP][212] ([i915#7118])
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-11/igt@kms_content_protection@type1.html
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@kms_content_protection@type1.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-rkl:          [SKIP][213] ([i915#3955]) -> [SKIP][214] ([fdo#110189] / [i915#3955]) +1 other test skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-rkl-4/igt@kms_fbcon_fbt@psr-suspend.html
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-rkl-1/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_force_connector_basic@force-load-detect:
    - shard-rkl:          [SKIP][215] ([fdo#109285] / [i915#4098]) -> [SKIP][216] ([fdo#109285])
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-rkl-2/igt@kms_force_connector_basic@force-load-detect.html
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-rkl-6/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
    - shard-dg1:          [SKIP][217] ([i915#3458] / [i915#4423]) -> [SKIP][218] ([i915#3458])
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg1-14/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html

  * igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-4:
    - shard-dg1:          [SKIP][219] ([i915#4423] / [i915#5176]) -> [SKIP][220] ([i915#5176])
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg1-14/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-4.html
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-16/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-4.html

  * igt@kms_psr@sprite_plane_onoff:
    - shard-dg1:          [SKIP][221] ([i915#1072] / [i915#4078]) -> [SKIP][222] ([i915#1072]) +2 other tests skip
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg1-12/igt@kms_psr@sprite_plane_onoff.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg1-19/igt@kms_psr@sprite_plane_onoff.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
  [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
  [i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
  [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
  [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
  [i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
  [i915#5889]: https://gitlab.freedesktop.org/drm/intel/issues/5889
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
  [i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
  [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
  [i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
  [i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7790]: https://gitlab.freedesktop.org/drm/intel/issues/7790
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
  [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
  [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
  [i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
  [i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
  [i915#8398]: https://gitlab.freedesktop.org/drm/intel/issues/8398
  [i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
  [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
  [i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
  [i915#8440]: https://gitlab.freedesktop.org/drm/intel/issues/8440
  [i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
  [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
  [i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
  [i915#8691]: https://gitlab.freedesktop.org/drm/intel/issues/8691
  [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
  [i915#8717]: https://gitlab.freedesktop.org/drm/intel/issues/8717
  [i915#8797]: https://gitlab.freedesktop.org/drm/intel/issues/8797
  [i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
  [i915#8875]: https://gitlab.freedesktop.org/drm/intel/issues/8875
  [i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
  [i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
  [i915#9226]: https://gitlab.freedesktop.org/drm/intel/issues/9226
  [i915#9227]: https://gitlab.freedesktop.org/drm/intel/issues/9227
  [i915#9261]: https://gitlab.freedesktop.org/drm/intel/issues/9261
  [i915#9262]: https://gitlab.freedesktop.org/drm/intel/issues/9262
  [i915#9369]: https://gitlab.freedesktop.org/drm/intel/issues/9369


Build changes
-------------

  * Linux: CI_DRM_13623 -> Patchwork_111391v7

  CI-20190529: 20190529
  CI_DRM_13623: eb35627e1c4a3781c161cd04944e403ce6df3e1c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7480: a8d38db9ac258d7fd71b2cf7607e259a864f95be @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111391v7: eb35627e1c4a3781c161cd04944e403ce6df3e1c @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/index.html

[-- Attachment #2: Type: text/html, Size: 73409 bytes --]

Re: [Intel-gfx] [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp prescision

[Jani Nikula]

On Wed, 13 Sep 2023, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>
> Add helper to get the DSC bits_per_pixel precision for the DP sink.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Maarten, Maxime, Thomas, ack for merging this via drm-intel please?

BR,
Jani.

> ---
>  drivers/gpu/drm/display/drm_dp_helper.c | 27 +++++++++++++++++++++++++
>  include/drm/display/drm_dp_helper.h     |  1 +
>  2 files changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> index 8a1b64c57dfd..5c23d5b8fc50 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -2323,6 +2323,33 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
>  }
>  EXPORT_SYMBOL(drm_dp_read_desc);
>  
> +/**
> + * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
> + * @dsc_dpcd: DSC capabilities from DPCD
> + *
> + * Returns the bpp precision supported by the DP sink.
> + */
> +u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
> +{
> +	u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT];
> +
> +	switch (bpp_increment_dpcd) {
> +	case DP_DSC_BITS_PER_PIXEL_1_16:
> +		return 16;
> +	case DP_DSC_BITS_PER_PIXEL_1_8:
> +		return 8;
> +	case DP_DSC_BITS_PER_PIXEL_1_4:
> +		return 4;
> +	case DP_DSC_BITS_PER_PIXEL_1_2:
> +		return 2;
> +	case DP_DSC_BITS_PER_PIXEL_1_1:
> +		return 1;
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
> +
>  /**
>   * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
>   * supported by the DSC sink.
> diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> index 3369104e2d25..6968d4d87931 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -164,6 +164,7 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
>  }
>  
>  /* DP/eDP DSC support */
> +u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
>  u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
>  				   bool is_edp);
>  u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);

-- 
Jani Nikula, Intel

Re: [Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

[Jani Nikula]

On Wed, 13 Sep 2023, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> From: Swati Sharma <swati2.sharma@intel.com>
>
> DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
> to depict sink's precision.
> Also, new debugfs entry is created to enforce fractional bpp.
> If Force_DSC_Fractional_BPP_en is set then while iterating over
> output bpp with fractional step size we will continue if output_bpp is
> computed as integer. With this approach, we will be able to validate
> DSC with fractional bpp.
>
> v2:
> Add drm_modeset_unlock to new line(Suraj)
>
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  .../drm/i915/display/intel_display_debugfs.c  | 83 +++++++++++++++++++
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  2 files changed, 84 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index f05b52381a83..776ab96def1f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -1244,6 +1244,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>  								      DP_DSC_YCbCr420_Native)),
>  			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
>  								      DP_DSC_YCbCr444)));
> +		seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
> +			   drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
>  		seq_printf(m, "Force_DSC_Enable: %s\n",
>  			   str_yes_no(intel_dp->force_dsc_en));
>  		if (!intel_dp_is_edp(intel_dp))
> @@ -1436,6 +1438,84 @@ static const struct file_operations i915_dsc_output_format_fops = {
>  	.write = i915_dsc_output_format_write
>  };
>  
> +static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
> +{
> +	struct drm_connector *connector = m->private;
> +	struct drm_device *dev = connector->dev;
> +	struct drm_crtc *crtc;
> +	struct intel_dp *intel_dp;
> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
> +	int ret;
> +
> +	if (!encoder)
> +		return -ENODEV;
> +
> +	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
> +	if (ret)
> +		return ret;
> +
> +	crtc = connector->state->crtc;
> +	if (connector->status != connector_status_connected || !crtc) {
> +		ret = -ENODEV;
> +		goto out;
> +	}
> +
> +	intel_dp = intel_attached_dp(to_intel_connector(connector));
> +	seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
> +		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));

Why "Force_DSC_Fractional_BPP_Enable" in the output?

Usually debugfs files, like sysfs files, for stuff like this should be
attributes, one thing per file. Why print a long name for it, if the
name of the debugfs file is the name of the attribute?

And even if you print it for humans, why the underscores?

> +
> +out:
> +	drm_modeset_unlock(&dev->mode_config.connection_mutex);
> +
> +	return ret;
> +}
> +
> +static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
> +					     const char __user *ubuf,
> +					     size_t len, loff_t *offp)
> +{
> +	struct drm_connector *connector =
> +		((struct seq_file *)file->private_data)->private;

I know this is copy-pasted from elsewhere, but really it's nicer to
avoid the cast, and copy-paste from the places that get this right:

	struct seq_file *m = file->private_data;
        struct drm_connector *connector = m->private;

> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +	bool dsc_fractional_bpp_enable = false;
> +	int ret;
> +
> +	if (len == 0)
> +		return 0;

kstrtobool_from_user() has this covered.

> +
> +	drm_dbg(&i915->drm,
> +		"Copied %zu bytes from user to force fractional bpp for DSC\n", len);

That's useless.

> +
> +	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
> +	if (ret < 0)
> +		return ret;
> +
> +	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
> +		(dsc_fractional_bpp_enable) ? "true" : "false");

Is this useful?

> +	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
> +
> +	*offp += len;
> +
> +	return len;
> +}
> +
> +static int i915_dsc_fractional_bpp_open(struct inode *inode,
> +					struct file *file)
> +{
> +	return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private);
> +}
> +
> +static const struct file_operations i915_dsc_fractional_bpp_fops = {
> +	.owner = THIS_MODULE,
> +	.open = i915_dsc_fractional_bpp_open,
> +	.read = seq_read,
> +	.llseek = seq_lseek,
> +	.release = single_release,
> +	.write = i915_dsc_fractional_bpp_write
> +};
> +
>  /*
>   * Returns the Current CRTC's bpc.
>   * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
> @@ -1513,6 +1593,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
>  
>  		debugfs_create_file("i915_dsc_output_format", 0644, root,
>  				    connector, &i915_dsc_output_format_fops);
> +
> +		debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
> +				    connector, &i915_dsc_fractional_bpp_fops);
>  	}
>  
>  	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 69bcabec4a29..27b31cb4c7b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1797,6 +1797,7 @@ struct intel_dp {
>  	/* Display stream compression testing */
>  	bool force_dsc_en;
>  	int force_dsc_output_format;
> +	bool force_dsc_fractional_bpp_en;
>  	int force_dsc_bpc;
>  
>  	bool hobl_failed;

-- 
Jani Nikula, Intel

Re: [Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

[Sharma, Swati2]

On 21-Sep-23 1:30 PM, Jani Nikula wrote:
> On Wed, 13 Sep 2023, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
>> From: Swati Sharma <swati2.sharma@intel.com>
>>
>> DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
>> to depict sink's precision.
>> Also, new debugfs entry is created to enforce fractional bpp.
>> If Force_DSC_Fractional_BPP_en is set then while iterating over
>> output bpp with fractional step size we will continue if output_bpp is
>> computed as integer. With this approach, we will be able to validate
>> DSC with fractional bpp.
>>
>> v2:
>> Add drm_modeset_unlock to new line(Suraj)
>>
>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>> ---
>>   .../drm/i915/display/intel_display_debugfs.c  | 83 +++++++++++++++++++
>>   .../drm/i915/display/intel_display_types.h    |  1 +
>>   2 files changed, 84 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> index f05b52381a83..776ab96def1f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> @@ -1244,6 +1244,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>>   								      DP_DSC_YCbCr420_Native)),
>>   			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
>>   								      DP_DSC_YCbCr444)));
>> +		seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
>> +			   drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
>>   		seq_printf(m, "Force_DSC_Enable: %s\n",
>>   			   str_yes_no(intel_dp->force_dsc_en));
>>   		if (!intel_dp_is_edp(intel_dp))
>> @@ -1436,6 +1438,84 @@ static const struct file_operations i915_dsc_output_format_fops = {
>>   	.write = i915_dsc_output_format_write
>>   };
>>   
>> +static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
>> +{
>> +	struct drm_connector *connector = m->private;
>> +	struct drm_device *dev = connector->dev;
>> +	struct drm_crtc *crtc;
>> +	struct intel_dp *intel_dp;
>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>> +	int ret;
>> +
>> +	if (!encoder)
>> +		return -ENODEV;
>> +
>> +	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
>> +	if (ret)
>> +		return ret;
>> +
>> +	crtc = connector->state->crtc;
>> +	if (connector->status != connector_status_connected || !crtc) {
>> +		ret = -ENODEV;
>> +		goto out;
>> +	}
>> +
>> +	intel_dp = intel_attached_dp(to_intel_connector(connector));
>> +	seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
>> +		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
> 
> Why "Force_DSC_Fractional_BPP_Enable" in the output?
> 
> Usually debugfs files, like sysfs files, for stuff like this should be
> attributes, one thing per file. Why print a long name for it, if the
> name of the debugfs file is the name of the attribute?
> 
> And even if you print it for humans, why the underscores?

Hi Jani,
Followed same strategy as we are doing for other dsc scenarios like
force_dsc.
Even naming convention followed same as other dsc stuff like 
Force_DSC_Enable, etc.
All DSC related enteries have underscores in its naming convention.

May be i can consolidate other dsc debugfs enteries into
one as a cleanup task later. But it will impact IGT aswell. And i'm not 
sure if we can break compatibility but since IGT (intel as only vendor) 
is the only consumer, may be we change at both places and clean it up.

> 
>> +
>> +out:
>> +	drm_modeset_unlock(&dev->mode_config.connection_mutex);
>> +
>> +	return ret;
>> +}
>> +
>> +static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
>> +					     const char __user *ubuf,
>> +					     size_t len, loff_t *offp)
>> +{
>> +	struct drm_connector *connector =
>> +		((struct seq_file *)file->private_data)->private;
> 
> I know this is copy-pasted from elsewhere, but really it's nicer to
> avoid the cast, and copy-paste from the places that get this right:
> 
> 	struct seq_file *m = file->private_data;
>          struct drm_connector *connector = m->private;

Done.

> 
>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> +	bool dsc_fractional_bpp_enable = false;
>> +	int ret;
>> +
>> +	if (len == 0)
>> +		return 0;
> 
> kstrtobool_from_user() has this covered.

Done.

> 
>> +
>> +	drm_dbg(&i915->drm,
>> +		"Copied %zu bytes from user to force fractional bpp for DSC\n", len);
> 
> That's useless.

Done.

> 
>> +
>> +	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
>> +	if (ret < 0)
>> +		return ret;
>> +
>> +	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
>> +		(dsc_fractional_bpp_enable) ? "true" : "false");
> 
> Is this useful?

Yes, to know when fractional bpp is enabled.

> 
>> +	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
>> +
>> +	*offp += len;
>> +
>> +	return len;
>> +}
>> +
>> +static int i915_dsc_fractional_bpp_open(struct inode *inode,
>> +					struct file *file)
>> +{
>> +	return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private);
>> +}
>> +
>> +static const struct file_operations i915_dsc_fractional_bpp_fops = {
>> +	.owner = THIS_MODULE,
>> +	.open = i915_dsc_fractional_bpp_open,
>> +	.read = seq_read,
>> +	.llseek = seq_lseek,
>> +	.release = single_release,
>> +	.write = i915_dsc_fractional_bpp_write
>> +};
>> +
>>   /*
>>    * Returns the Current CRTC's bpc.
>>    * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
>> @@ -1513,6 +1593,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
>>   
>>   		debugfs_create_file("i915_dsc_output_format", 0644, root,
>>   				    connector, &i915_dsc_output_format_fops);
>> +
>> +		debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
>> +				    connector, &i915_dsc_fractional_bpp_fops);
>>   	}
>>   
>>   	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 69bcabec4a29..27b31cb4c7b4 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1797,6 +1797,7 @@ struct intel_dp {
>>   	/* Display stream compression testing */
>>   	bool force_dsc_en;
>>   	int force_dsc_output_format;
>> +	bool force_dsc_fractional_bpp_en;
>>   	int force_dsc_bpc;
>>   
>>   	bool hobl_failed;
> 

Re: [Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

[Jani Nikula]

On Thu, 21 Sep 2023, "Sharma, Swati2" <swati2.sharma@intel.com> wrote:
> On 21-Sep-23 1:30 PM, Jani Nikula wrote:
>> On Wed, 13 Sep 2023, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
>>> From: Swati Sharma <swati2.sharma@intel.com>
>>>
>>> DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
>>> to depict sink's precision.
>>> Also, new debugfs entry is created to enforce fractional bpp.
>>> If Force_DSC_Fractional_BPP_en is set then while iterating over
>>> output bpp with fractional step size we will continue if output_bpp is
>>> computed as integer. With this approach, we will be able to validate
>>> DSC with fractional bpp.
>>>
>>> v2:
>>> Add drm_modeset_unlock to new line(Suraj)
>>>
>>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>>> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>>> ---
>>>   .../drm/i915/display/intel_display_debugfs.c  | 83 +++++++++++++++++++
>>>   .../drm/i915/display/intel_display_types.h    |  1 +
>>>   2 files changed, 84 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>> index f05b52381a83..776ab96def1f 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>> @@ -1244,6 +1244,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>>>   								      DP_DSC_YCbCr420_Native)),
>>>   			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
>>>   								      DP_DSC_YCbCr444)));
>>> +		seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
>>> +			   drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
>>>   		seq_printf(m, "Force_DSC_Enable: %s\n",
>>>   			   str_yes_no(intel_dp->force_dsc_en));
>>>   		if (!intel_dp_is_edp(intel_dp))
>>> @@ -1436,6 +1438,84 @@ static const struct file_operations i915_dsc_output_format_fops = {
>>>   	.write = i915_dsc_output_format_write
>>>   };
>>>   
>>> +static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
>>> +{
>>> +	struct drm_connector *connector = m->private;
>>> +	struct drm_device *dev = connector->dev;
>>> +	struct drm_crtc *crtc;
>>> +	struct intel_dp *intel_dp;
>>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>>> +	int ret;
>>> +
>>> +	if (!encoder)
>>> +		return -ENODEV;
>>> +
>>> +	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
>>> +	if (ret)
>>> +		return ret;
>>> +
>>> +	crtc = connector->state->crtc;
>>> +	if (connector->status != connector_status_connected || !crtc) {
>>> +		ret = -ENODEV;
>>> +		goto out;
>>> +	}
>>> +
>>> +	intel_dp = intel_attached_dp(to_intel_connector(connector));
>>> +	seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
>>> +		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
>> 
>> Why "Force_DSC_Fractional_BPP_Enable" in the output?
>> 
>> Usually debugfs files, like sysfs files, for stuff like this should be
>> attributes, one thing per file. Why print a long name for it, if the
>> name of the debugfs file is the name of the attribute?
>> 
>> And even if you print it for humans, why the underscores?
>
> Hi Jani,
> Followed same strategy as we are doing for other dsc scenarios like
> force_dsc.
> Even naming convention followed same as other dsc stuff like 
> Force_DSC_Enable, etc.
> All DSC related enteries have underscores in its naming convention.

There's value in that, though maybe my comment highlights I'm not fond
of the existing stuff. ;)

> May be i can consolidate other dsc debugfs enteries into
> one as a cleanup task later. But it will impact IGT aswell. And i'm not 
> sure if we can break compatibility but since IGT (intel as only vendor) 
> is the only consumer, may be we change at both places and clean it up.

We can do what we want with debugfs, as long as we change both the
driver and igt.

>
>> 
>>> +
>>> +out:
>>> +	drm_modeset_unlock(&dev->mode_config.connection_mutex);
>>> +
>>> +	return ret;
>>> +}
>>> +
>>> +static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
>>> +					     const char __user *ubuf,
>>> +					     size_t len, loff_t *offp)
>>> +{
>>> +	struct drm_connector *connector =
>>> +		((struct seq_file *)file->private_data)->private;
>> 
>> I know this is copy-pasted from elsewhere, but really it's nicer to
>> avoid the cast, and copy-paste from the places that get this right:
>> 
>> 	struct seq_file *m = file->private_data;
>>          struct drm_connector *connector = m->private;
>
> Done.
>
>> 
>>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>>> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>>> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>> +	bool dsc_fractional_bpp_enable = false;
>>> +	int ret;
>>> +
>>> +	if (len == 0)
>>> +		return 0;
>> 
>> kstrtobool_from_user() has this covered.
>
> Done.
>
>> 
>>> +
>>> +	drm_dbg(&i915->drm,
>>> +		"Copied %zu bytes from user to force fractional bpp for DSC\n", len);
>> 
>> That's useless.
>
> Done.
>
>> 
>>> +
>>> +	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
>>> +	if (ret < 0)
>>> +		return ret;
>>> +
>>> +	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
>>> +		(dsc_fractional_bpp_enable) ? "true" : "false");
>> 
>> Is this useful?
>
> Yes, to know when fractional bpp is enabled.

I think it would be more useful to debug log this at the use site, not
when you're setting the debugfs knob.

BR,
Jani.




>
>> 
>>> +	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
>>> +
>>> +	*offp += len;
>>> +
>>> +	return len;
>>> +}
>>> +
>>> +static int i915_dsc_fractional_bpp_open(struct inode *inode,
>>> +					struct file *file)
>>> +{
>>> +	return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private);
>>> +}
>>> +
>>> +static const struct file_operations i915_dsc_fractional_bpp_fops = {
>>> +	.owner = THIS_MODULE,
>>> +	.open = i915_dsc_fractional_bpp_open,
>>> +	.read = seq_read,
>>> +	.llseek = seq_lseek,
>>> +	.release = single_release,
>>> +	.write = i915_dsc_fractional_bpp_write
>>> +};
>>> +
>>>   /*
>>>    * Returns the Current CRTC's bpc.
>>>    * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
>>> @@ -1513,6 +1593,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
>>>   
>>>   		debugfs_create_file("i915_dsc_output_format", 0644, root,
>>>   				    connector, &i915_dsc_output_format_fops);
>>> +
>>> +		debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
>>> +				    connector, &i915_dsc_fractional_bpp_fops);
>>>   	}
>>>   
>>>   	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> index 69bcabec4a29..27b31cb4c7b4 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> @@ -1797,6 +1797,7 @@ struct intel_dp {
>>>   	/* Display stream compression testing */
>>>   	bool force_dsc_en;
>>>   	int force_dsc_output_format;
>>> +	bool force_dsc_fractional_bpp_en;
>>>   	int force_dsc_bpc;
>>>   
>>>   	bool hobl_failed;
>> 

-- 
Jani Nikula, Intel

Re: [Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

[Sharma, Swati2]

On 21-Sep-23 5:44 PM, Jani Nikula wrote:
> On Thu, 21 Sep 2023, "Sharma, Swati2" <swati2.sharma@intel.com> wrote:
>> On 21-Sep-23 1:30 PM, Jani Nikula wrote:
>>> On Wed, 13 Sep 2023, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
>>>> From: Swati Sharma <swati2.sharma@intel.com>
>>>>
>>>> DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
>>>> to depict sink's precision.
>>>> Also, new debugfs entry is created to enforce fractional bpp.
>>>> If Force_DSC_Fractional_BPP_en is set then while iterating over
>>>> output bpp with fractional step size we will continue if output_bpp is
>>>> computed as integer. With this approach, we will be able to validate
>>>> DSC with fractional bpp.
>>>>
>>>> v2:
>>>> Add drm_modeset_unlock to new line(Suraj)
>>>>
>>>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>>>> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>>>> ---
>>>>    .../drm/i915/display/intel_display_debugfs.c  | 83 +++++++++++++++++++
>>>>    .../drm/i915/display/intel_display_types.h    |  1 +
>>>>    2 files changed, 84 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>>> index f05b52381a83..776ab96def1f 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>>> @@ -1244,6 +1244,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>>>>    								      DP_DSC_YCbCr420_Native)),
>>>>    			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
>>>>    								      DP_DSC_YCbCr444)));
>>>> +		seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
>>>> +			   drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
>>>>    		seq_printf(m, "Force_DSC_Enable: %s\n",
>>>>    			   str_yes_no(intel_dp->force_dsc_en));
>>>>    		if (!intel_dp_is_edp(intel_dp))
>>>> @@ -1436,6 +1438,84 @@ static const struct file_operations i915_dsc_output_format_fops = {
>>>>    	.write = i915_dsc_output_format_write
>>>>    };
>>>>    
>>>> +static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
>>>> +{
>>>> +	struct drm_connector *connector = m->private;
>>>> +	struct drm_device *dev = connector->dev;
>>>> +	struct drm_crtc *crtc;
>>>> +	struct intel_dp *intel_dp;
>>>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>>>> +	int ret;
>>>> +
>>>> +	if (!encoder)
>>>> +		return -ENODEV;
>>>> +
>>>> +	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
>>>> +	if (ret)
>>>> +		return ret;
>>>> +
>>>> +	crtc = connector->state->crtc;
>>>> +	if (connector->status != connector_status_connected || !crtc) {
>>>> +		ret = -ENODEV;
>>>> +		goto out;
>>>> +	}
>>>> +
>>>> +	intel_dp = intel_attached_dp(to_intel_connector(connector));
>>>> +	seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
>>>> +		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
>>>
>>> Why "Force_DSC_Fractional_BPP_Enable" in the output?
>>>
>>> Usually debugfs files, like sysfs files, for stuff like this should be
>>> attributes, one thing per file. Why print a long name for it, if the
>>> name of the debugfs file is the name of the attribute?
>>>
>>> And even if you print it for humans, why the underscores?
>>
>> Hi Jani,
>> Followed same strategy as we are doing for other dsc scenarios like
>> force_dsc.
>> Even naming convention followed same as other dsc stuff like
>> Force_DSC_Enable, etc.
>> All DSC related enteries have underscores in its naming convention.
> 
> There's value in that, though maybe my comment highlights I'm not fond
> of the existing stuff. ;)

Sure, I can work on cleanup part later.

> 
>> May be i can consolidate other dsc debugfs enteries into
>> one as a cleanup task later. But it will impact IGT aswell. And i'm not
>> sure if we can break compatibility but since IGT (intel as only vendor)
>> is the only consumer, may be we change at both places and clean it up.
> 
> We can do what we want with debugfs, as long as we change both the
> driver and igt.

Sure, will make corresponding changes in both IGT and KMD.

> 
>>
>>>
>>>> +
>>>> +out:
>>>> +	drm_modeset_unlock(&dev->mode_config.connection_mutex);
>>>> +
>>>> +	return ret;
>>>> +}
>>>> +
>>>> +static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
>>>> +					     const char __user *ubuf,
>>>> +					     size_t len, loff_t *offp)
>>>> +{
>>>> +	struct drm_connector *connector =
>>>> +		((struct seq_file *)file->private_data)->private;
>>>
>>> I know this is copy-pasted from elsewhere, but really it's nicer to
>>> avoid the cast, and copy-paste from the places that get this right:
>>>
>>> 	struct seq_file *m = file->private_data;
>>>           struct drm_connector *connector = m->private;
>>
>> Done.
>>
>>>
>>>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>>>> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>>>> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>>> +	bool dsc_fractional_bpp_enable = false;
>>>> +	int ret;
>>>> +
>>>> +	if (len == 0)
>>>> +		return 0;
>>>
>>> kstrtobool_from_user() has this covered.
>>
>> Done.
>>
>>>
>>>> +
>>>> +	drm_dbg(&i915->drm,
>>>> +		"Copied %zu bytes from user to force fractional bpp for DSC\n", len);
>>>
>>> That's useless.
>>
>> Done.
>>
>>>
>>>> +
>>>> +	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
>>>> +	if (ret < 0)
>>>> +		return ret;
>>>> +
>>>> +	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
>>>> +		(dsc_fractional_bpp_enable) ? "true" : "false");
>>>
>>> Is this useful?
>>
>> Yes, to know when fractional bpp is enabled.
> 
> I think it would be more useful to debug log this at the use site, not
> when you're setting the debugfs knob.

We already have those in IGT. Like said, to maintain consitency with 
other dsc func() like fec_support_write(), this debug print is added 
here. I can drop and will drop from fec_support_write() too during cleanup.

> 
> BR,
> Jani.
> 
> 
> 
> 
>>
>>>
>>>> +	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
>>>> +
>>>> +	*offp += len;
>>>> +
>>>> +	return len;
>>>> +}
>>>> +
>>>> +static int i915_dsc_fractional_bpp_open(struct inode *inode,
>>>> +					struct file *file)
>>>> +{
>>>> +	return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private);
>>>> +}
>>>> +
>>>> +static const struct file_operations i915_dsc_fractional_bpp_fops = {
>>>> +	.owner = THIS_MODULE,
>>>> +	.open = i915_dsc_fractional_bpp_open,
>>>> +	.read = seq_read,
>>>> +	.llseek = seq_lseek,
>>>> +	.release = single_release,
>>>> +	.write = i915_dsc_fractional_bpp_write
>>>> +};
>>>> +
>>>>    /*
>>>>     * Returns the Current CRTC's bpc.
>>>>     * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
>>>> @@ -1513,6 +1593,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
>>>>    
>>>>    		debugfs_create_file("i915_dsc_output_format", 0644, root,
>>>>    				    connector, &i915_dsc_output_format_fops);
>>>> +
>>>> +		debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
>>>> +				    connector, &i915_dsc_fractional_bpp_fops);
>>>>    	}
>>>>    
>>>>    	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> index 69bcabec4a29..27b31cb4c7b4 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> @@ -1797,6 +1797,7 @@ struct intel_dp {
>>>>    	/* Display stream compression testing */
>>>>    	bool force_dsc_en;
>>>>    	int force_dsc_output_format;
>>>> +	bool force_dsc_fractional_bpp_en;
>>>>    	int force_dsc_bpc;
>>>>    
>>>>    	bool hobl_failed;
>>>
> 

With above KMD changes IGT is already rb'ed and validated
https://patchwork.freedesktop.org/series/117493/#rev12
I request if we can get ack on this. As cleanup task,
will make changes as requested.

Re: [Intel-gfx] [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp prescision

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 457 bytes --]

On Thu, Sep 21, 2023 at 10:41:43AM +0300, Jani Nikula wrote:
> On Wed, 13 Sep 2023, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> > From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >
> > Add helper to get the DSC bits_per_pixel precision for the DP sink.
> >
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> Maarten, Maxime, Thomas, ack for merging this via drm-intel please?

That's fine by me :)

Maxime

[-- Attachment #2: signature.asc --]
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Re: [Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

[Jani Nikula]

On Thu, 21 Sep 2023, "Sharma, Swati2" <swati2.sharma@intel.com> wrote:
> On 21-Sep-23 5:44 PM, Jani Nikula wrote:
>> On Thu, 21 Sep 2023, "Sharma, Swati2" <swati2.sharma@intel.com> wrote:
>>> On 21-Sep-23 1:30 PM, Jani Nikula wrote:
>>>> On Wed, 13 Sep 2023, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
>>>>> From: Swati Sharma <swati2.sharma@intel.com>
>>>>>
>>>>> DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
>>>>> to depict sink's precision.
>>>>> Also, new debugfs entry is created to enforce fractional bpp.
>>>>> If Force_DSC_Fractional_BPP_en is set then while iterating over
>>>>> output bpp with fractional step size we will continue if output_bpp is
>>>>> computed as integer. With this approach, we will be able to validate
>>>>> DSC with fractional bpp.
>>>>>
>>>>> v2:
>>>>> Add drm_modeset_unlock to new line(Suraj)
>>>>>
>>>>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>>>>> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>>>>> ---
>>>>>    .../drm/i915/display/intel_display_debugfs.c  | 83 +++++++++++++++++++
>>>>>    .../drm/i915/display/intel_display_types.h    |  1 +
>>>>>    2 files changed, 84 insertions(+)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>>>> index f05b52381a83..776ab96def1f 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>>>> @@ -1244,6 +1244,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>>>>>    								      DP_DSC_YCbCr420_Native)),
>>>>>    			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
>>>>>    								      DP_DSC_YCbCr444)));
>>>>> +		seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
>>>>> +			   drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
>>>>>    		seq_printf(m, "Force_DSC_Enable: %s\n",
>>>>>    			   str_yes_no(intel_dp->force_dsc_en));
>>>>>    		if (!intel_dp_is_edp(intel_dp))
>>>>> @@ -1436,6 +1438,84 @@ static const struct file_operations i915_dsc_output_format_fops = {
>>>>>    	.write = i915_dsc_output_format_write
>>>>>    };
>>>>>    
>>>>> +static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
>>>>> +{
>>>>> +	struct drm_connector *connector = m->private;
>>>>> +	struct drm_device *dev = connector->dev;
>>>>> +	struct drm_crtc *crtc;
>>>>> +	struct intel_dp *intel_dp;
>>>>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>>>>> +	int ret;
>>>>> +
>>>>> +	if (!encoder)
>>>>> +		return -ENODEV;
>>>>> +
>>>>> +	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
>>>>> +	if (ret)
>>>>> +		return ret;
>>>>> +
>>>>> +	crtc = connector->state->crtc;
>>>>> +	if (connector->status != connector_status_connected || !crtc) {
>>>>> +		ret = -ENODEV;
>>>>> +		goto out;
>>>>> +	}
>>>>> +
>>>>> +	intel_dp = intel_attached_dp(to_intel_connector(connector));
>>>>> +	seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
>>>>> +		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
>>>>
>>>> Why "Force_DSC_Fractional_BPP_Enable" in the output?
>>>>
>>>> Usually debugfs files, like sysfs files, for stuff like this should be
>>>> attributes, one thing per file. Why print a long name for it, if the
>>>> name of the debugfs file is the name of the attribute?
>>>>
>>>> And even if you print it for humans, why the underscores?
>>>
>>> Hi Jani,
>>> Followed same strategy as we are doing for other dsc scenarios like
>>> force_dsc.
>>> Even naming convention followed same as other dsc stuff like
>>> Force_DSC_Enable, etc.
>>> All DSC related enteries have underscores in its naming convention.
>> 
>> There's value in that, though maybe my comment highlights I'm not fond
>> of the existing stuff. ;)
>
> Sure, I can work on cleanup part later.
>
>> 
>>> May be i can consolidate other dsc debugfs enteries into
>>> one as a cleanup task later. But it will impact IGT aswell. And i'm not
>>> sure if we can break compatibility but since IGT (intel as only vendor)
>>> is the only consumer, may be we change at both places and clean it up.
>> 
>> We can do what we want with debugfs, as long as we change both the
>> driver and igt.
>
> Sure, will make corresponding changes in both IGT and KMD.
>
>> 
>>>
>>>>
>>>>> +
>>>>> +out:
>>>>> +	drm_modeset_unlock(&dev->mode_config.connection_mutex);
>>>>> +
>>>>> +	return ret;
>>>>> +}
>>>>> +
>>>>> +static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
>>>>> +					     const char __user *ubuf,
>>>>> +					     size_t len, loff_t *offp)
>>>>> +{
>>>>> +	struct drm_connector *connector =
>>>>> +		((struct seq_file *)file->private_data)->private;
>>>>
>>>> I know this is copy-pasted from elsewhere, but really it's nicer to
>>>> avoid the cast, and copy-paste from the places that get this right:
>>>>
>>>> 	struct seq_file *m = file->private_data;
>>>>           struct drm_connector *connector = m->private;
>>>
>>> Done.
>>>
>>>>
>>>>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>>>>> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>>>>> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>>>> +	bool dsc_fractional_bpp_enable = false;
>>>>> +	int ret;
>>>>> +
>>>>> +	if (len == 0)
>>>>> +		return 0;
>>>>
>>>> kstrtobool_from_user() has this covered.
>>>
>>> Done.
>>>
>>>>
>>>>> +
>>>>> +	drm_dbg(&i915->drm,
>>>>> +		"Copied %zu bytes from user to force fractional bpp for DSC\n", len);
>>>>
>>>> That's useless.
>>>
>>> Done.
>>>
>>>>
>>>>> +
>>>>> +	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
>>>>> +	if (ret < 0)
>>>>> +		return ret;
>>>>> +
>>>>> +	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
>>>>> +		(dsc_fractional_bpp_enable) ? "true" : "false");
>>>>
>>>> Is this useful?
>>>
>>> Yes, to know when fractional bpp is enabled.
>> 
>> I think it would be more useful to debug log this at the use site, not
>> when you're setting the debugfs knob.
>
> We already have those in IGT. Like said, to maintain consitency with 
> other dsc func() like fec_support_write(), this debug print is added 
> here. I can drop and will drop from fec_support_write() too during cleanup.
>
>> 
>> BR,
>> Jani.
>> 
>> 
>> 
>> 
>>>
>>>>
>>>>> +	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
>>>>> +
>>>>> +	*offp += len;
>>>>> +
>>>>> +	return len;
>>>>> +}
>>>>> +
>>>>> +static int i915_dsc_fractional_bpp_open(struct inode *inode,
>>>>> +					struct file *file)
>>>>> +{
>>>>> +	return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private);
>>>>> +}
>>>>> +
>>>>> +static const struct file_operations i915_dsc_fractional_bpp_fops = {
>>>>> +	.owner = THIS_MODULE,
>>>>> +	.open = i915_dsc_fractional_bpp_open,
>>>>> +	.read = seq_read,
>>>>> +	.llseek = seq_lseek,
>>>>> +	.release = single_release,
>>>>> +	.write = i915_dsc_fractional_bpp_write
>>>>> +};
>>>>> +
>>>>>    /*
>>>>>     * Returns the Current CRTC's bpc.
>>>>>     * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
>>>>> @@ -1513,6 +1593,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
>>>>>    
>>>>>    		debugfs_create_file("i915_dsc_output_format", 0644, root,
>>>>>    				    connector, &i915_dsc_output_format_fops);
>>>>> +
>>>>> +		debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
>>>>> +				    connector, &i915_dsc_fractional_bpp_fops);
>>>>>    	}
>>>>>    
>>>>>    	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>>>>> index 69bcabec4a29..27b31cb4c7b4 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>>>> @@ -1797,6 +1797,7 @@ struct intel_dp {
>>>>>    	/* Display stream compression testing */
>>>>>    	bool force_dsc_en;
>>>>>    	int force_dsc_output_format;
>>>>> +	bool force_dsc_fractional_bpp_en;
>>>>>    	int force_dsc_bpc;
>>>>>    
>>>>>    	bool hobl_failed;
>>>>
>> 
>
> With above KMD changes IGT is already rb'ed and validated
> https://patchwork.freedesktop.org/series/117493/#rev12
> I request if we can get ack on this. As cleanup task,
> will make changes as requested.

Okay then.

BR,
Jani.


-- 
Jani Nikula, Intel

Re: [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support

[Imre Deak]

On Wed, Sep 13, 2023 at 11:35:58AM +0530, Mitul Golani wrote:
> his patch series adds support for DSC fractional compressed bpp
> for MTL+. The series starts with some fixes, followed by patches that
> lay groundwork to iterate over valid compressed bpps to select the
> 'best' compressed bpp with optimal link configuration (taken from
> upstream series: https://patchwork.freedesktop.org/series/105200/).
> 
> The later patches, add changes to accommodate compressed bpp with
> fractional part, including changes to QP calculations.
> To get the 'best' compressed bpp, we iterate over the valid compressed
> bpp values, but with fractional step size 1/16, 1/8, 1/4 or 1/2 as per
> sink support.
> 
> The last 2 patches add support to depict DSC sink's fractional support,
> and debugfs to enforce use of fractional bpp, while choosing an
> appropriate compressed bpp.

MST/DSC is at the moment broken, so I'd prefer merging this patchset
only after it's fixed. This would mean merging 

https://lore.kernel.org/all/20230921195159.2646027-1-imre.deak@intel.com

first, followed by the DSC parts from

https://lore.kernel.org/all/20230914192659.757475-1-imre.deak@intel.com

which would also need a rebase for this patchset.

> Ankit Nautiyal (5):
>   drm/display/dp: Add helper function to get DSC bpp prescision
>   drm/i915/display: Store compressed bpp in U6.4 format
>   drm/i915/display: Consider fractional vdsc bpp while computing m_n
>     values
>   drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
>   drm/i915/dp: Iterate over output bpp with fractional step size
> 
> Swati Sharma (2):
>   drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
>   drm/i915/dsc: Allow DSC only with fractional bpp when forced from
>     debugfs
> 
> Vandita Kulkarni (1):
>   drm/i915/dsc/mtl: Add support for fractional bpp
> 
>  drivers/gpu/drm/display/drm_dp_helper.c       | 27 ++++++
>  drivers/gpu/drm/i915/display/icl_dsi.c        | 11 +--
>  drivers/gpu/drm/i915/display/intel_audio.c    | 17 ++--
>  drivers/gpu/drm/i915/display/intel_bios.c     |  6 +-
>  drivers/gpu/drm/i915/display/intel_cdclk.c    |  6 +-
>  drivers/gpu/drm/i915/display/intel_display.c  |  8 +-
>  drivers/gpu/drm/i915/display/intel_display.h  |  2 +-
>  .../drm/i915/display/intel_display_debugfs.c  | 83 +++++++++++++++++++
>  .../drm/i915/display/intel_display_types.h    |  4 +-
>  drivers/gpu/drm/i915/display/intel_dp.c       | 81 +++++++++++-------
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   | 32 ++++---
>  drivers/gpu/drm/i915/display/intel_fdi.c      |  2 +-
>  .../i915/display/intel_fractional_helper.h    | 36 ++++++++
>  .../gpu/drm/i915/display/intel_qp_tables.c    |  3 -
>  drivers/gpu/drm/i915/display/intel_vdsc.c     | 30 +++++--
>  include/drm/display/drm_dp_helper.h           |  1 +
>  16 files changed, 275 insertions(+), 74 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/display/intel_fractional_helper.h
> 
> -- 
> 2.25.1
> 

Re: [Intel-gfx] [1/8] drm/display/dp: Add helper function to get DSC bpp prescision

[Sui Jingfeng]

Hi,


The word 'prescision' in the commit title is a typo,
perhaps it's more better correct it as 'precision' when merge.


On 2023/9/13 14:05, Mitul Golani wrote:
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>
> Add helper to get the DSC bits_per_pixel precision for the DP sink.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>   drivers/gpu/drm/display/drm_dp_helper.c | 27 +++++++++++++++++++++++++
>   include/drm/display/drm_dp_helper.h     |  1 +
>   2 files changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> index 8a1b64c57dfd..5c23d5b8fc50 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -2323,6 +2323,33 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
>   }
>   EXPORT_SYMBOL(drm_dp_read_desc);
>   
> +/**
> + * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
> + * @dsc_dpcd: DSC capabilities from DPCD
> + *
> + * Returns the bpp precision supported by the DP sink.
> + */
> +u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
> +{
> +	u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT];
> +
> +	switch (bpp_increment_dpcd) {
> +	case DP_DSC_BITS_PER_PIXEL_1_16:
> +		return 16;
> +	case DP_DSC_BITS_PER_PIXEL_1_8:
> +		return 8;
> +	case DP_DSC_BITS_PER_PIXEL_1_4:
> +		return 4;
> +	case DP_DSC_BITS_PER_PIXEL_1_2:
> +		return 2;
> +	case DP_DSC_BITS_PER_PIXEL_1_1:
> +		return 1;
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
> +
>   /**
>    * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
>    * supported by the DSC sink.
> diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> index 3369104e2d25..6968d4d87931 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -164,6 +164,7 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
>   }
>   
>   /* DP/eDP DSC support */
> +u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
>   u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
>   				   bool is_edp);
>   u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);

Re: [Intel-gfx] [3/8] drm/i915/display: Consider fractional vdsc bpp while computing m_n values

[Sui Jingfeng]

Hi,


On 2023/9/13 14:06, Mitul Golani wrote:
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>
> MTL+ supports fractional compressed bits_per_pixel, with precision of
> 1/16. This compressed bpp is stored in U6.4 format.
> Accommodate this precision while computing m_n values.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_display.c | 6 +++++-
>   drivers/gpu/drm/i915/display/intel_display.h | 2 +-
>   drivers/gpu/drm/i915/display/intel_dp.c      | 5 +++--
>   drivers/gpu/drm/i915/display/intel_dp_mst.c  | 6 ++++--
>   drivers/gpu/drm/i915/display/intel_fdi.c     | 2 +-
>   5 files changed, 14 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index afcbdd4f105a..b37aeac961f4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2380,10 +2380,14 @@ void
>   intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
>   		       int pixel_clock, int link_clock,
>   		       struct intel_link_m_n *m_n,
> -		       bool fec_enable)
> +		       bool fec_enable,
> +		       bool is_dsc_fractional_bpp)
>   {
>   	u32 data_clock = bits_per_pixel * pixel_clock;
>   
> +	if (is_dsc_fractional_bpp)
> +		data_clock = DIV_ROUND_UP(bits_per_pixel * pixel_clock, 16);
> +

The 'bits_per_pixel * pixel_clock' has already been computed
and its result is stored in the 'data_clock' local variable.
can we change it as "data_clock = DIV_ROUND_UP(data_clock, 16)" here ?

>   	if (fec_enable)
>   		data_clock = intel_dp_mode_to_fec_clock(data_clock);
>   
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 49ac8473b988..a4c4ca3cad65 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -398,7 +398,7 @@ u8 intel_calc_active_pipes(struct intel_atomic_state *state,
>   void intel_link_compute_m_n(u16 bpp, int nlanes,
>   			    int pixel_clock, int link_clock,
>   			    struct intel_link_m_n *m_n,
> -			    bool fec_enable);
> +			    bool fec_enable, bool is_dsc_fractional_bpp);
>   u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
>   			      u32 pixel_format, u64 modifier);
>   enum drm_mode_status
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index cb647bb38b12..6e09e21909a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2562,7 +2562,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
>   
>   	intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock,
>   			       pipe_config->port_clock, &pipe_config->dp_m2_n2,
> -			       pipe_config->fec_enable);
> +			       pipe_config->fec_enable, false);
>   
>   	/* FIXME: abstract this better */
>   	if (pipe_config->splitter.enable)
> @@ -2741,7 +2741,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>   			       adjusted_mode->crtc_clock,
>   			       pipe_config->port_clock,
>   			       &pipe_config->dp_m_n,
> -			       pipe_config->fec_enable);
> +			       pipe_config->fec_enable,
> +			       pipe_config->dsc.compression_enable);
>   
>   	/* FIXME: abstract this better */
>   	if (pipe_config->splitter.enable)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 7bf0b6e4ac0b..8f6bd54532cb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -172,7 +172,8 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
>   			       adjusted_mode->crtc_clock,
>   			       crtc_state->port_clock,
>   			       &crtc_state->dp_m_n,
> -			       crtc_state->fec_enable);
> +			       crtc_state->fec_enable,
> +			       false);
>   	crtc_state->dp_m_n.tu = slots;
>   
>   	return 0;
> @@ -269,7 +270,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
>   			       adjusted_mode->crtc_clock,
>   			       crtc_state->port_clock,
>   			       &crtc_state->dp_m_n,
> -			       crtc_state->fec_enable);
> +			       crtc_state->fec_enable,
> +			       crtc_state->dsc.compression_enable);
>   	crtc_state->dp_m_n.tu = slots;
>   
>   	return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index e12b46a84fa1..15fddabf7c2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -259,7 +259,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
>   	pipe_config->fdi_lanes = lane;
>   
>   	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> -			       link_bw, &pipe_config->fdi_m_n, false);
> +			       link_bw, &pipe_config->fdi_m_n, false, false);
>   
>   	ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);
>   	if (ret == -EDEADLK)

Re: [Intel-gfx] [2/8] drm/i915/display: Store compressed bpp in U6.4 format

[Sui Jingfeng]

Hi,


On 2023/9/13 14:06, Mitul Golani wrote:
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>
> DSC parameter bits_per_pixel is stored in U6.4 format.
> The 4 bits represent the fractional part of the bpp.
> Currently we use compressed_bpp member of dsc structure to store
> only the integral part of the bits_per_pixel.
> To store the full bits_per_pixel along with the fractional part,
> compressed_bpp is changed to store bpp in U6.4 formats. Intergral
> part is retrieved by simply right shifting the member compressed_bpp by 4.
>
> v2:
> -Use to_bpp_int, to_bpp_frac_dec, to_bpp_x16 helpers while dealing
>   with compressed bpp. (Suraj)
> -Fix comment styling. (Suraj)
>
> v3:
> -Add separate file for 6.4 fixed point helper(Jani, Nikula)
> -Add comment for magic values(Suraj)
>
> v4:
> -Fix checkpatch caused due to renaming(Suraj)

In this statement, is the 'caused' and the 'due to' duplicated here.

Fix checkpatch warnings due to renaming(Suraj)

Or

Fix checkpatch warnings caused by renaming(Suraj)

Or

Fix checkpatch warnings created due to renaming(Suraj)

> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>   drivers/gpu/drm/i915/display/icl_dsi.c        | 11 +++---
>   drivers/gpu/drm/i915/display/intel_audio.c    |  3 +-
>   drivers/gpu/drm/i915/display/intel_bios.c     |  6 ++--
>   drivers/gpu/drm/i915/display/intel_cdclk.c    |  6 ++--
>   drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
>   .../drm/i915/display/intel_display_types.h    |  3 +-
>   drivers/gpu/drm/i915/display/intel_dp.c       | 33 ++++++++++-------
>   drivers/gpu/drm/i915/display/intel_dp_mst.c   | 26 ++++++++------
>   .../i915/display/intel_fractional_helper.h    | 36 +++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_vdsc.c     |  5 +--
>   10 files changed, 93 insertions(+), 38 deletions(-)
>   create mode 100644 drivers/gpu/drm/i915/display/intel_fractional_helper.h
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index ad6488e9c2b2..0f7594b6aa1f 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -43,6 +43,7 @@
>   #include "intel_de.h"
>   #include "intel_dsi.h"
>   #include "intel_dsi_vbt.h"
> +#include "intel_fractional_helper.h"
>   #include "intel_panel.h"
>   #include "intel_vdsc.h"
>   #include "intel_vdsc_regs.h"
> @@ -330,7 +331,7 @@ static int afe_clk(struct intel_encoder *encoder,
>   	int bpp;
>   
>   	if (crtc_state->dsc.compression_enable)
> -		bpp = crtc_state->dsc.compressed_bpp;
> +		bpp = intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16);
>   	else
>   		bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
>   
> @@ -860,7 +861,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>   	 * compressed and non-compressed bpp.
>   	 */
>   	if (crtc_state->dsc.compression_enable) {
> -		mul = crtc_state->dsc.compressed_bpp;
> +		mul = intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16);
>   		div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
>   	}
>   
> @@ -884,7 +885,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>   		int bpp, line_time_us, byte_clk_period_ns;
>   
>   		if (crtc_state->dsc.compression_enable)
> -			bpp = crtc_state->dsc.compressed_bpp;
> +			bpp = intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16);
>   		else
>   			bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
>   
> @@ -1451,8 +1452,8 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
>   	struct drm_display_mode *adjusted_mode =
>   					&pipe_config->hw.adjusted_mode;
>   
> -	if (pipe_config->dsc.compressed_bpp) {
> -		int div = pipe_config->dsc.compressed_bpp;
> +	if (pipe_config->dsc.compressed_bpp_x16) {
> +		int div = intel_fractional_bpp_from_x16(pipe_config->dsc.compressed_bpp_x16);
>   		int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
>   
>   		adjusted_mode->crtc_htotal =
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> index 19605264a35c..4f1db1581316 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -35,6 +35,7 @@
>   #include "intel_crtc.h"
>   #include "intel_de.h"
>   #include "intel_display_types.h"
> +#include "intel_fractional_helper.h"
>   #include "intel_lpe_audio.h"
>   
>   /**
> @@ -528,7 +529,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
>   	h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
>   	h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
>   	pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
> -	vdsc_bpp = crtc_state->dsc.compressed_bpp;
> +	vdsc_bpp = intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16);
>   	cdclk = i915->display.cdclk.hw.cdclk;
>   	/* fec= 0.972261, using rounding multiplier of 1000000 */
>   	fec_coeff = 972261;
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index f735b035436c..3e4a3c62fc8a 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -33,6 +33,7 @@
>   #include "i915_reg.h"
>   #include "intel_display.h"
>   #include "intel_display_types.h"
> +#include "intel_fractional_helper.h"
>   #include "intel_gmbus.h"
>   
>   #define _INTEL_BIOS_PRIVATE
> @@ -3384,8 +3385,9 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
>   
>   	crtc_state->pipe_bpp = bpc * 3;
>   
> -	crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
> -					     VBT_DSC_MAX_BPP(dsc->max_bpp));
> +	crtc_state->dsc.compressed_bpp_x16 =
> +		intel_fractional_bpp_to_x16(min(crtc_state->pipe_bpp,
> +						VBT_DSC_MAX_BPP(dsc->max_bpp)));
>   
>   	/*
>   	 * FIXME: This is ugly, and slice count should take DSC engine
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index ad5251ba6fe1..b9a07be81dfe 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -34,6 +34,7 @@
>   #include "intel_de.h"
>   #include "intel_dp.h"
>   #include "intel_display_types.h"
> +#include "intel_fractional_helper.h"
>   #include "intel_mchbar_regs.h"
>   #include "intel_pci_config.h"
>   #include "intel_pcode.h"
> @@ -2567,8 +2568,9 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
>   		 * => CDCLK >= compressed_bpp * Pixel clock  / 2 * Bigjoiner Interface bits
>   		 */
>   		int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
> -		int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * pixel_clock) /
> -				   (2 * bigjoiner_interface_bits);
> +		int min_cdclk_bj =
> +			(intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16) *
> +			 pixel_clock) / (2 * bigjoiner_interface_bits);
>   
>   		min_cdclk = max(min_cdclk, min_cdclk_bj);
>   	}
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 83e1bc858b9f..afcbdd4f105a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5365,7 +5365,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>   
>   	PIPE_CONF_CHECK_I(dsc.compression_enable);
>   	PIPE_CONF_CHECK_I(dsc.dsc_split);
> -	PIPE_CONF_CHECK_I(dsc.compressed_bpp);
> +	PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
>   
>   	PIPE_CONF_CHECK_BOOL(splitter.enable);
>   	PIPE_CONF_CHECK_I(splitter.link_count);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c21064794f32..69bcabec4a29 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1353,7 +1353,8 @@ struct intel_crtc_state {
>   	struct {
>   		bool compression_enable;
>   		bool dsc_split;
> -		u16 compressed_bpp;
> +		/* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
> +		u16 compressed_bpp_x16;
>   		u8 slice_count;
>   		struct drm_dsc_config config;
>   	} dsc;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index aa5f602b56fb..cb647bb38b12 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -64,6 +64,7 @@
>   #include "intel_dp_mst.h"
>   #include "intel_dpio_phy.h"
>   #include "intel_dpll.h"
> +#include "intel_fractional_helper.h"
>   #include "intel_fifo_underrun.h"
>   #include "intel_hdcp.h"
>   #include "intel_hdmi.h"
> @@ -1863,7 +1864,8 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
>   					      valid_dsc_bpp[i],
>   					      timeslots);
>   		if (ret == 0) {
> -			pipe_config->dsc.compressed_bpp = valid_dsc_bpp[i];
> +			pipe_config->dsc.compressed_bpp_x16 =
> +				intel_fractional_bpp_to_x16(valid_dsc_bpp[i]);
>   			return 0;
>   		}
>   	}
> @@ -1901,7 +1903,8 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
>   					      compressed_bpp,
>   					      timeslots);
>   		if (ret == 0) {
> -			pipe_config->dsc.compressed_bpp = compressed_bpp;
> +			pipe_config->dsc.compressed_bpp_x16 =
> +				intel_fractional_bpp_to_x16(compressed_bpp);
>   			return 0;
>   		}
>   	}
> @@ -2085,7 +2088,8 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>   	/* Compressed BPP should be less than the Input DSC bpp */
>   	dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
>   
> -	pipe_config->dsc.compressed_bpp = max(dsc_min_bpp, dsc_max_bpp);
> +	pipe_config->dsc.compressed_bpp_x16 =
> +		intel_fractional_bpp_to_x16(max(dsc_min_bpp, dsc_max_bpp));
>   
>   	pipe_config->pipe_bpp = pipe_bpp;
>   
> @@ -2171,18 +2175,19 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>   	ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
>   	if (ret < 0) {
>   		drm_dbg_kms(&dev_priv->drm,
> -			    "Cannot compute valid DSC parameters for Input Bpp = %d "
> -			    "Compressed BPP = %d\n",
> +			    "Cannot compute valid DSC parameters for Input Bpp = %d Compressed BPP = %d.%d\n",
>   			    pipe_config->pipe_bpp,
> -			    pipe_config->dsc.compressed_bpp);
> +			    intel_fractional_bpp_from_x16(pipe_config->dsc.compressed_bpp_x16),
> +			    intel_fractional_bpp_decimal(pipe_config->dsc.compressed_bpp_x16));
>   		return ret;
>   	}
>   
>   	pipe_config->dsc.compression_enable = true;
> -	drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
> -		    "Compressed Bpp = %d Slice Count = %d\n",
> +	drm_dbg_kms(&dev_priv->drm,
> +		    "DP DSC computed with Input Bpp = %d Compressed Bpp = %d.%d Slice Count = %d\n",
>   		    pipe_config->pipe_bpp,
> -		    pipe_config->dsc.compressed_bpp,
> +		    intel_fractional_bpp_from_x16(pipe_config->dsc.compressed_bpp_x16),
> +		    intel_fractional_bpp_decimal(pipe_config->dsc.compressed_bpp_x16),
>   		    pipe_config->dsc.slice_count);
>   
>   	return 0;
> @@ -2261,15 +2266,17 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>   
>   	if (pipe_config->dsc.compression_enable) {
>   		drm_dbg_kms(&i915->drm,
> -			    "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
> +			    "DP lane count %d clock %d Input bpp %d Compressed bpp %d.%d\n",
>   			    pipe_config->lane_count, pipe_config->port_clock,
>   			    pipe_config->pipe_bpp,
> -			    pipe_config->dsc.compressed_bpp);
> +			    intel_fractional_bpp_from_x16(pipe_config->dsc.compressed_bpp_x16),
> +			    intel_fractional_bpp_decimal(pipe_config->dsc.compressed_bpp_x16));
>   
>   		drm_dbg_kms(&i915->drm,
>   			    "DP link rate required %i available %i\n",
>   			    intel_dp_link_required(adjusted_mode->crtc_clock,
> -						   pipe_config->dsc.compressed_bpp),
> +						   intel_fractional_bpp_from_x16
> +						   (pipe_config->dsc.compressed_bpp_x16)),
>   			    intel_dp_max_data_rate(pipe_config->port_clock,
>   						   pipe_config->lane_count));
>   	} else {
> @@ -2702,7 +2709,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>   		intel_dp_limited_color_range(pipe_config, conn_state);
>   
>   	if (pipe_config->dsc.compression_enable)
> -		link_bpp = pipe_config->dsc.compressed_bpp;
> +		link_bpp = pipe_config->dsc.compressed_bpp_x16;
>   	else
>   		link_bpp = intel_dp_output_bpp(pipe_config->output_format,
>   					       pipe_config->pipe_bpp);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 1c7f0b6afe47..7bf0b6e4ac0b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -41,6 +41,7 @@
>   #include "intel_dp_hdcp.h"
>   #include "intel_dp_mst.h"
>   #include "intel_dpio_phy.h"
> +#include "intel_fractional_helper.h"
>   #include "intel_hdcp.h"
>   #include "intel_hotplug.h"
>   #include "skl_scaler.h"
> @@ -140,7 +141,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
>   		if (!dsc)
>   			crtc_state->pipe_bpp = bpp;
>   		else
> -			crtc_state->dsc.compressed_bpp = bpp;
> +			crtc_state->dsc.compressed_bpp_x16 = intel_fractional_bpp_to_x16(bpp);
>   		drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);
>   	}
>   
> @@ -238,13 +239,14 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
>   	if (slots < 0)
>   		return slots;
>   
> -	last_compressed_bpp = crtc_state->dsc.compressed_bpp;
> +	last_compressed_bpp = intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16);
>   
> -	crtc_state->dsc.compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915,
> -									last_compressed_bpp,
> -									crtc_state->pipe_bpp);
> +	crtc_state->dsc.compressed_bpp_x16 =
> +		intel_fractional_bpp_to_x16(intel_dp_dsc_nearest_valid_bpp(i915,
> +									   last_compressed_bpp,
> +									   crtc_state->pipe_bpp));
>   
> -	if (crtc_state->dsc.compressed_bpp != last_compressed_bpp)
> +	if (crtc_state->dsc.compressed_bpp_x16 != intel_fractional_bpp_to_x16(last_compressed_bpp))
>   		need_timeslot_recalc = true;
>   
>   	/*
> @@ -252,15 +254,17 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
>   	 * the actual compressed bpp we use.
>   	 */
>   	if (need_timeslot_recalc) {
> -		slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
> -							     crtc_state->dsc.compressed_bpp,
> -							     crtc_state->dsc.compressed_bpp,
> -							     limits, conn_state, 2 * 3, true);
> +		slots =
> +		intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
> +						     intel_fractional_bpp_from_x16
> +						     (crtc_state->dsc.compressed_bpp_x16),
> +		intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16),
> +		limits, conn_state, 2 * 3, true);
>   		if (slots < 0)
>   			return slots;
>   	}
>   
> -	intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
> +	intel_link_compute_m_n(intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16),
>   			       crtc_state->lane_count,
>   			       adjusted_mode->crtc_clock,
>   			       crtc_state->port_clock,
> diff --git a/drivers/gpu/drm/i915/display/intel_fractional_helper.h b/drivers/gpu/drm/i915/display/intel_fractional_helper.h
> new file mode 100644
> index 000000000000..0212a9041c8f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_fractional_helper.h
> @@ -0,0 +1,36 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +#ifndef __INTEL_FRACTIONAL_HELPERS_H__
> +#define __INTEL_FRACTIONAL_HELPERS_H__
> +
> + /*
> +  * Convert a U6.4 fixed-point bits-per-pixel (bpp) value to an integer bpp value.
> +  */
> +static inline int intel_fractional_bpp_from_x16(int bpp_x16)
> +{
> +	return bpp_x16 >> 4;
> +}
> +
> +/*
> + * Extract the fractional part of a U6.4 fixed-point bpp value based on the
> + * last 4 bits representing fractional bits, obtained by multiplying by 10000
> + * and then dividing by 16, as the bpp value is initially left-shifted by 4
> + * to allocate 4 bits for the fractional part.
> + */
> +static inline int intel_fractional_bpp_decimal(int bpp_x16)
> +{
> +	return (bpp_x16 & 0xf) * 625;
> +}
> +
> +/*
> + * Convert bits-per-pixel (bpp) to a U6.4 fixed-point representation.
> + */
> +static inline int intel_fractional_bpp_to_x16(int bpp)
> +{
> +	return bpp << 4;
> +}
> +
> +#endif /*  __INTEL_FRACTIONAL_HELPERS_H__ */
> +
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 5c00f7ccad7f..1bd9391a6f5a 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -15,6 +15,7 @@
>   #include "intel_de.h"
>   #include "intel_display_types.h"
>   #include "intel_dsi.h"
> +#include "intel_fractional_helper.h"
>   #include "intel_qp_tables.h"
>   #include "intel_vdsc.h"
>   #include "intel_vdsc_regs.h"
> @@ -248,7 +249,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
>   	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
> -	u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
> +	u16 compressed_bpp = intel_fractional_bpp_from_x16(pipe_config->dsc.compressed_bpp_x16);
>   	int err;
>   	int ret;
>   
> @@ -874,7 +875,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
>   	if (vdsc_cfg->native_420)
>   		vdsc_cfg->bits_per_pixel >>= 1;
>   
> -	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> +	crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;
>   
>   	/* PPS 2 */
>   	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);

Re: [Intel-gfx] [7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

[Sui Jingfeng]

Hi,


On 2023/9/13 14:06, Mitul Golani wrote:
> From: Swati Sharma <swati2.sharma@intel.com>
>
> DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
> to depict sink's precision.
> Also, new debugfs entry is created to enforce fractional bpp.
> If Force_DSC_Fractional_BPP_en is set then while iterating over
> output bpp with fractional step size we will continue if output_bpp is
> computed as integer. With this approach, we will be able to validate
> DSC with fractional bpp.
>
> v2:
> Add drm_modeset_unlock to new line(Suraj)
>
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>   .../drm/i915/display/intel_display_debugfs.c  | 83 +++++++++++++++++++
>   .../drm/i915/display/intel_display_types.h    |  1 +
>   2 files changed, 84 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index f05b52381a83..776ab96def1f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -1244,6 +1244,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>   								      DP_DSC_YCbCr420_Native)),
>   			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
>   								      DP_DSC_YCbCr444)));
> +		seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
> +			   drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
>   		seq_printf(m, "Force_DSC_Enable: %s\n",
>   			   str_yes_no(intel_dp->force_dsc_en));
>   		if (!intel_dp_is_edp(intel_dp))
> @@ -1436,6 +1438,84 @@ static const struct file_operations i915_dsc_output_format_fops = {
>   	.write = i915_dsc_output_format_write
>   };
>   
> +static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
> +{
> +	struct drm_connector *connector = m->private;
> +	struct drm_device *dev = connector->dev;
> +	struct drm_crtc *crtc;
> +	struct intel_dp *intel_dp;
> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));

The 'to_intel_connector()' inline function get used twice in this function,
if it were me, I will cache it with a local variable to prevent over long in horizontal.


         struct intel_connector *intel_connector = to_intel_connector(connector);
         struct intel_encoder *encoder = intel_attached_encoder(intel_connector);

> +	int ret;
> +
> +	if (!encoder)
> +		return -ENODEV;
> +
> +	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
> +	if (ret)
> +		return ret;
> +
> +	crtc = connector->state->crtc;
> +	if (connector->status != connector_status_connected || !crtc) {
> +		ret = -ENODEV;
> +		goto out;
> +	}
> +
> +	intel_dp = intel_attached_dp(to_intel_connector(connector));


          intel_dp = intel_attached_dp(intel_connector);

But this patch is OK, I just give a suggestion.

Re: [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support

[Imre Deak]

On Fri, Sep 22, 2023 at 03:45:45PM +0300, Imre Deak wrote:
Hi Mitul, Ankit, Swati, Vandita,

> On Wed, Sep 13, 2023 at 11:35:58AM +0530, Mitul Golani wrote:
> > his patch series adds support for DSC fractional compressed bpp
> > for MTL+. The series starts with some fixes, followed by patches that
> > lay groundwork to iterate over valid compressed bpps to select the
> > 'best' compressed bpp with optimal link configuration (taken from
> > upstream series: https://patchwork.freedesktop.org/series/105200/).
> > 
> > The later patches, add changes to accommodate compressed bpp with
> > fractional part, including changes to QP calculations.
> > To get the 'best' compressed bpp, we iterate over the valid compressed
> > bpp values, but with fractional step size 1/16, 1/8, 1/4 or 1/2 as per
> > sink support.
> > 
> > The last 2 patches add support to depict DSC sink's fractional support,
> > and debugfs to enforce use of fractional bpp, while choosing an
> > appropriate compressed bpp.
> 
> MST/DSC is at the moment broken, so I'd prefer merging this patchset
> only after it's fixed. This would mean merging 
> 
> https://lore.kernel.org/all/20230921195159.2646027-1-imre.deak@intel.com
> 
> first, followed by the DSC parts from
> 
> https://lore.kernel.org/all/20230914192659.757475-1-imre.deak@intel.com
> 
> which would also need a rebase for this patchset.

Are you ok with the above?

Thanks,
Imre

> 
> > Ankit Nautiyal (5):
> >   drm/display/dp: Add helper function to get DSC bpp prescision
> >   drm/i915/display: Store compressed bpp in U6.4 format
> >   drm/i915/display: Consider fractional vdsc bpp while computing m_n
> >     values
> >   drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
> >   drm/i915/dp: Iterate over output bpp with fractional step size
> > 
> > Swati Sharma (2):
> >   drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
> >   drm/i915/dsc: Allow DSC only with fractional bpp when forced from
> >     debugfs
> > 
> > Vandita Kulkarni (1):
> >   drm/i915/dsc/mtl: Add support for fractional bpp
> > 
> >  drivers/gpu/drm/display/drm_dp_helper.c       | 27 ++++++
> >  drivers/gpu/drm/i915/display/icl_dsi.c        | 11 +--
> >  drivers/gpu/drm/i915/display/intel_audio.c    | 17 ++--
> >  drivers/gpu/drm/i915/display/intel_bios.c     |  6 +-
> >  drivers/gpu/drm/i915/display/intel_cdclk.c    |  6 +-
> >  drivers/gpu/drm/i915/display/intel_display.c  |  8 +-
> >  drivers/gpu/drm/i915/display/intel_display.h  |  2 +-
> >  .../drm/i915/display/intel_display_debugfs.c  | 83 +++++++++++++++++++
> >  .../drm/i915/display/intel_display_types.h    |  4 +-
> >  drivers/gpu/drm/i915/display/intel_dp.c       | 81 +++++++++++-------
> >  drivers/gpu/drm/i915/display/intel_dp_mst.c   | 32 ++++---
> >  drivers/gpu/drm/i915/display/intel_fdi.c      |  2 +-
> >  .../i915/display/intel_fractional_helper.h    | 36 ++++++++
> >  .../gpu/drm/i915/display/intel_qp_tables.c    |  3 -
> >  drivers/gpu/drm/i915/display/intel_vdsc.c     | 30 +++++--
> >  include/drm/display/drm_dp_helper.h           |  1 +
> >  16 files changed, 275 insertions(+), 74 deletions(-)
> >  create mode 100644 drivers/gpu/drm/i915/display/intel_fractional_helper.h
> > 
> > -- 
> > 2.25.1
> > 

Re: [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support

[Sharma, Swati2]

On 27-Sep-23 8:52 PM, Imre Deak wrote:
> On Fri, Sep 22, 2023 at 03:45:45PM +0300, Imre Deak wrote:
> Hi Mitul, Ankit, Swati, Vandita,
> 
>> On Wed, Sep 13, 2023 at 11:35:58AM +0530, Mitul Golani wrote:
>>> his patch series adds support for DSC fractional compressed bpp
>>> for MTL+. The series starts with some fixes, followed by patches that
>>> lay groundwork to iterate over valid compressed bpps to select the
>>> 'best' compressed bpp with optimal link configuration (taken from
>>> upstream series: https://patchwork.freedesktop.org/series/105200/).
>>>
>>> The later patches, add changes to accommodate compressed bpp with
>>> fractional part, including changes to QP calculations.
>>> To get the 'best' compressed bpp, we iterate over the valid compressed
>>> bpp values, but with fractional step size 1/16, 1/8, 1/4 or 1/2 as per
>>> sink support.
>>>
>>> The last 2 patches add support to depict DSC sink's fractional support,
>>> and debugfs to enforce use of fractional bpp, while choosing an
>>> appropriate compressed bpp.
>>
>> MST/DSC is at the moment broken, so I'd prefer merging this patchset
>> only after it's fixed. This would mean merging
>>
>> https://lore.kernel.org/all/20230921195159.2646027-1-imre.deak@intel.com
>>
>> first, followed by the DSC parts from
>>
>> https://lore.kernel.org/all/20230914192659.757475-1-imre.deak@intel.com
>>
>> which would also need a rebase for this patchset.
> 
> Are you ok with the above?

Yes, Imre..we are all okay.
You can proceed.

> 
> Thanks,
> Imre
> 
>>
>>> Ankit Nautiyal (5):
>>>    drm/display/dp: Add helper function to get DSC bpp prescision
>>>    drm/i915/display: Store compressed bpp in U6.4 format
>>>    drm/i915/display: Consider fractional vdsc bpp while computing m_n
>>>      values
>>>    drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
>>>    drm/i915/dp: Iterate over output bpp with fractional step size
>>>
>>> Swati Sharma (2):
>>>    drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
>>>    drm/i915/dsc: Allow DSC only with fractional bpp when forced from
>>>      debugfs
>>>
>>> Vandita Kulkarni (1):
>>>    drm/i915/dsc/mtl: Add support for fractional bpp
>>>
>>>   drivers/gpu/drm/display/drm_dp_helper.c       | 27 ++++++
>>>   drivers/gpu/drm/i915/display/icl_dsi.c        | 11 +--
>>>   drivers/gpu/drm/i915/display/intel_audio.c    | 17 ++--
>>>   drivers/gpu/drm/i915/display/intel_bios.c     |  6 +-
>>>   drivers/gpu/drm/i915/display/intel_cdclk.c    |  6 +-
>>>   drivers/gpu/drm/i915/display/intel_display.c  |  8 +-
>>>   drivers/gpu/drm/i915/display/intel_display.h  |  2 +-
>>>   .../drm/i915/display/intel_display_debugfs.c  | 83 +++++++++++++++++++
>>>   .../drm/i915/display/intel_display_types.h    |  4 +-
>>>   drivers/gpu/drm/i915/display/intel_dp.c       | 81 +++++++++++-------
>>>   drivers/gpu/drm/i915/display/intel_dp_mst.c   | 32 ++++---
>>>   drivers/gpu/drm/i915/display/intel_fdi.c      |  2 +-
>>>   .../i915/display/intel_fractional_helper.h    | 36 ++++++++
>>>   .../gpu/drm/i915/display/intel_qp_tables.c    |  3 -
>>>   drivers/gpu/drm/i915/display/intel_vdsc.c     | 30 +++++--
>>>   include/drm/display/drm_dp_helper.h           |  1 +
>>>   16 files changed, 275 insertions(+), 74 deletions(-)
>>>   create mode 100644 drivers/gpu/drm/i915/display/intel_fractional_helper.h
>>>
>>> -- 
>>> 2.25.1
>>>

[Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support

[Mitul Golani]

This patch series adds support for DSC fractional compressed bpp
for MTL+. The series starts with some fixes, followed by patches that
lay groundwork to iterate over valid compressed bpps to select the
'best' compressed bpp with optimal link configuration (taken from
upstream series: https://patchwork.freedesktop.org/series/105200/).

The later patches, add changes to accommodate compressed bpp with
fractional part, including changes to QP calculations.
To get the 'best' compressed bpp, we iterate over the valid compressed
bpp values, but with fractional step size 1/16, 1/8, 1/4 or 1/2 as per
sink support.

The last 2 patches add support to depict DSC sink's fractional support,
and debugfs to enforce use of fractional bpp, while choosing an
appropriate compressed bpp.

Ankit Nautiyal (5):
  drm/display/dp: Add helper function to get DSC bpp precision
  drm/i915/display: Store compressed bpp in U6.4 format
  drm/i915/display: Consider fractional vdsc bpp while computing m_n
    values
  drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
  drm/i915/dp: Iterate over output bpp with fractional step size

Swati Sharma (2):
  drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
  drm/i915/dsc: Allow DSC only with fractional bpp when forced from
    debugfs

Vandita Kulkarni (1):
  drm/i915/dsc/mtl: Add support for fractional bpp

 drivers/gpu/drm/display/drm_dp_helper.c       | 27 ++++++
 drivers/gpu/drm/i915/display/icl_dsi.c        | 11 +--
 drivers/gpu/drm/i915/display/intel_audio.c    | 17 ++--
 drivers/gpu/drm/i915/display/intel_bios.c     |  6 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  6 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  8 +-
 drivers/gpu/drm/i915/display/intel_display.h  |  2 +-
 .../drm/i915/display/intel_display_debugfs.c  | 84 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  4 +-
 drivers/gpu/drm/i915/display/intel_dp.c       | 81 +++++++++++-------
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 32 ++++---
 drivers/gpu/drm/i915/display/intel_fdi.c      |  2 +-
 .../i915/display/intel_fractional_helper.h    | 36 ++++++++
 .../gpu/drm/i915/display/intel_qp_tables.c    |  3 -
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 30 +++++--
 include/drm/display/drm_dp_helper.h           |  1 +
 16 files changed, 276 insertions(+), 74 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_fractional_helper.h

-- 
2.25.1

Re: [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support

[Sui Jingfeng]

Hi,


For coding style and wording part, this version looks fine for me after a brief skim.
Thanks for the patch. :-)


On 2023/9/26 16:23, Mitul Golani wrote:
> This patch series adds support for DSC fractional compressed bpp
> for MTL+. The series starts with some fixes, followed by patches that
> lay groundwork to iterate over valid compressed bpps to select the
> 'best' compressed bpp with optimal link configuration (taken from
> upstream series: https://patchwork.freedesktop.org/series/105200/).
>
> The later patches, add changes to accommodate compressed bpp with
> fractional part, including changes to QP calculations.
> To get the 'best' compressed bpp, we iterate over the valid compressed
> bpp values, but with fractional step size 1/16, 1/8, 1/4 or 1/2 as per
> sink support.
>
> The last 2 patches add support to depict DSC sink's fractional support,
> and debugfs to enforce use of fractional bpp, while choosing an
> appropriate compressed bpp.
>
> Ankit Nautiyal (5):
>    drm/display/dp: Add helper function to get DSC bpp precision
>    drm/i915/display: Store compressed bpp in U6.4 format
>    drm/i915/display: Consider fractional vdsc bpp while computing m_n
>      values
>    drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
>    drm/i915/dp: Iterate over output bpp with fractional step size
>
> Swati Sharma (2):
>    drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
>    drm/i915/dsc: Allow DSC only with fractional bpp when forced from
>      debugfs
>
> Vandita Kulkarni (1):
>    drm/i915/dsc/mtl: Add support for fractional bpp
>
>   drivers/gpu/drm/display/drm_dp_helper.c       | 27 ++++++
>   drivers/gpu/drm/i915/display/icl_dsi.c        | 11 +--
>   drivers/gpu/drm/i915/display/intel_audio.c    | 17 ++--
>   drivers/gpu/drm/i915/display/intel_bios.c     |  6 +-
>   drivers/gpu/drm/i915/display/intel_cdclk.c    |  6 +-
>   drivers/gpu/drm/i915/display/intel_display.c  |  8 +-
>   drivers/gpu/drm/i915/display/intel_display.h  |  2 +-
>   .../drm/i915/display/intel_display_debugfs.c  | 84 +++++++++++++++++++
>   .../drm/i915/display/intel_display_types.h    |  4 +-
>   drivers/gpu/drm/i915/display/intel_dp.c       | 81 +++++++++++-------
>   drivers/gpu/drm/i915/display/intel_dp_mst.c   | 32 ++++---
>   drivers/gpu/drm/i915/display/intel_fdi.c      |  2 +-
>   .../i915/display/intel_fractional_helper.h    | 36 ++++++++
>   .../gpu/drm/i915/display/intel_qp_tables.c    |  3 -
>   drivers/gpu/drm/i915/display/intel_vdsc.c     | 30 +++++--
>   include/drm/display/drm_dp_helper.h           |  1 +
>   16 files changed, 276 insertions(+), 74 deletions(-)
>   create mode 100644 drivers/gpu/drm/i915/display/intel_fractional_helper.h
>

[Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support

[Mitul Golani]

This patch series adds support for DSC fractional compressed bpp
for MTL+. The series starts with some fixes, followed by patches that
lay groundwork to iterate over valid compressed bpps to select the
'best' compressed bpp with optimal link configuration (taken from
upstream series: https://patchwork.freedesktop.org/series/105200/).

The later patches, add changes to accommodate compressed bpp with
fractional part, including changes to QP calculations.
To get the 'best' compressed bpp, we iterate over the valid compressed
bpp values, but with fractional step size 1/16, 1/8, 1/4 or 1/2 as per
sink support.

The last 2 patches add support to depict DSC sink's fractional support,
and debugfs to enforce use of fractional bpp, while choosing an
appropriate compressed bpp.

Ankit Nautiyal (5):
  drm/display/dp: Add helper function to get DSC bpp precision
  drm/i915/display: Store compressed bpp in U6.4 format
  drm/i915/display: Consider fractional vdsc bpp while computing m_n
    values
  drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
  drm/i915/dp: Iterate over output bpp with fractional step size

Swati Sharma (2):
  drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
  drm/i915/dsc: Allow DSC only with fractional bpp when forced from
    debugfs

Vandita Kulkarni (1):
  drm/i915/dsc/mtl: Add support for fractional bpp

 drivers/gpu/drm/display/drm_dp_helper.c       | 27 ++++++
 drivers/gpu/drm/i915/display/icl_dsi.c        | 11 +--
 drivers/gpu/drm/i915/display/intel_audio.c    | 17 ++--
 drivers/gpu/drm/i915/display/intel_bios.c     |  6 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  6 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  8 +-
 drivers/gpu/drm/i915/display/intel_display.h  |  2 +-
 .../drm/i915/display/intel_display_debugfs.c  | 84 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  4 +-
 drivers/gpu/drm/i915/display/intel_dp.c       | 81 +++++++++++-------
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 32 ++++---
 drivers/gpu/drm/i915/display/intel_fdi.c      |  2 +-
 .../i915/display/intel_fractional_helper.h    | 36 ++++++++
 .../gpu/drm/i915/display/intel_qp_tables.c    |  3 -
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 30 +++++--
 include/drm/display/drm_dp_helper.h           |  1 +
 16 files changed, 276 insertions(+), 74 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_fractional_helper.h

-- 
2.25.1

[Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support

[Mitul Golani]

This patch series adds support for DSC fractional compressed bpp
for MTL+. The series starts with some fixes, followed by patches that
lay groundwork to iterate over valid compressed bpps to select the
'best' compressed bpp with optimal link configuration (taken from
upstream series: https://patchwork.freedesktop.org/series/105200/).

The later patches, add changes to accommodate compressed bpp with
fractional part, including changes to QP calculations.
To get the 'best' compressed bpp, we iterate over the valid compressed
bpp values, but with fractional step size 1/16, 1/8, 1/4 or 1/2 as per
sink support.

The last 2 patches add support to depict DSC sink's fractional support,
and debugfs to enforce use of fractional bpp, while choosing an
appropriate compressed bpp.

Ankit Nautiyal (5):
  drm/display/dp: Add helper function to get DSC bpp prescision
  drm/i915/display: Store compressed bpp in U6.4 format
  drm/i915/display: Consider fractional vdsc bpp while computing m_n
    values
  drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
  drm/i915/dp: Iterate over output bpp with fractional step size

Swati Sharma (2):
  drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
  drm/i915/dsc: Allow DSC only with fractional bpp when forced from
    debugfs

Vandita Kulkarni (1):
  drm/i915/dsc/mtl: Add support for fractional bpp

Ankit Nautiyal (5):
  drm/display/dp: Add helper function to get DSC bpp prescision
  drm/i915/display: Store compressed bpp in U6.4 format
  drm/i915/display: Consider fractional vdsc bpp while computing m_n
    values
  drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
  drm/i915/dp: Iterate over output bpp with fractional step size

Swati Sharma (2):
  drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
  drm/i915/dsc: Allow DSC only with fractional bpp when forced from
    debugfs

Vandita Kulkarni (1):
  drm/i915/dsc/mtl: Add support for fractional bpp

Ankit Nautiyal (5):
  drm/display/dp: Add helper function to get DSC bpp prescision
  drm/i915/display: Store compressed bpp in U6.4 format
  drm/i915/display: Consider fractional vdsc bpp while computing m_n
    values
  drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
  drm/i915/dp: Iterate over output bpp with fractional step size

Swati Sharma (2):
  drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
  drm/i915/dsc: Allow DSC only with fractional bpp when forced from
    debugfs

Vandita Kulkarni (1):
  drm/i915/dsc/mtl: Add support for fractional bpp

 drivers/gpu/drm/display/drm_dp_helper.c       | 27 ++++++
 drivers/gpu/drm/i915/display/icl_dsi.c        | 11 +--
 drivers/gpu/drm/i915/display/intel_audio.c    | 17 ++--
 drivers/gpu/drm/i915/display/intel_bios.c     |  6 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  5 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  8 +-
 drivers/gpu/drm/i915/display/intel_display.h  |  2 +-
 .../drm/i915/display/intel_display_debugfs.c  | 83 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  4 +-
 drivers/gpu/drm/i915/display/intel_dp.c       | 78 ++++++++++-------
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 28 ++++---
 drivers/gpu/drm/i915/display/intel_fdi.c      |  2 +-
 .../i915/display/intel_fractional_helper.h    | 36 ++++++++
 .../gpu/drm/i915/display/intel_qp_tables.c    |  3 -
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 30 +++++--
 include/drm/display/drm_dp_helper.h           |  1 +
 16 files changed, 268 insertions(+), 73 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_fractional_helper.h

-- 
2.25.1

[Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support

[Mitul Golani]

This patch series adds support for DSC fractional compressed bpp
for MTL+. The series starts with some fixes, followed by patches that
lay groundwork to iterate over valid compressed bpps to select the
'best' compressed bpp with optimal link configuration (taken from
upstream series: https://patchwork.freedesktop.org/series/105200/).

The later patches, add changes to accommodate compressed bpp with
fractional part, including changes to QP calculations.
To get the 'best' compressed bpp, we iterate over the valid compressed
bpp values, but with fractional step size 1/16, 1/8, 1/4 or 1/2 as per
sink support.

The last 2 patches add support to depict DSC sink's fractional support,
and debugfs to enforce use of fractional bpp, while choosing an
appropriate compressed bpp.

Ankit Nautiyal (5):
  drm/display/dp: Add helper function to get DSC bpp prescision
  drm/i915/display: Store compressed bpp in U6.4 format
  drm/i915/display: Consider fractional vdsc bpp while computing m_n
    values
  drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
  drm/i915/dp: Iterate over output bpp with fractional step size

Swati Sharma (2):
  drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
  drm/i915/dsc: Allow DSC only with fractional bpp when forced from
    debugfs

Vandita Kulkarni (1):
  drm/i915/dsc/mtl: Add support for fractional bpp

 drivers/gpu/drm/display/drm_dp_helper.c       | 27 ++++++
 drivers/gpu/drm/i915/display/icl_dsi.c        | 10 +--
 drivers/gpu/drm/i915/display/intel_audio.c    | 14 ++--
 drivers/gpu/drm/i915/display/intel_bios.c     |  4 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  2 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  8 +-
 drivers/gpu/drm/i915/display/intel_display.h  |  2 +-
 .../drm/i915/display/intel_display_debugfs.c  | 82 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    | 19 ++++-
 drivers/gpu/drm/i915/display/intel_dp.c       | 74 +++++++++++------
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 24 +++---
 drivers/gpu/drm/i915/display/intel_fdi.c      |  2 +-
 .../gpu/drm/i915/display/intel_qp_tables.c    |  3 -
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 29 +++++--
 include/drm/display/drm_dp_helper.h           |  1 +
 15 files changed, 233 insertions(+), 68 deletions(-)

-- 
2.25.1