* Re: [Intel-gfx] [PATCH v5 13/19] drm/i915: Introduce new Tile 4 format
@ 2022-03-24 0:07 Chery, Nanley G
0 siblings, 0 replies; 2+ messages in thread
From: Chery, Nanley G @ 2022-03-24 0:07 UTC (permalink / raw)
To: dri-devel, intel-gfx, C, Ramalingam; +Cc: Auld, Matthew
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Hi all,
Found an error in this description..
> From: Stanislav Lisovskiy stanislav.lisovskiy@intel.com<mailto:stanislav.lisovskiy@intel.com>
>
> This tiling layout uses 4KB tiles in a row-major layout. It has the same
> shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
> only differs from Tile Y at the 256B granularity in between. At this
> granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
> of 64B x 8 rows.
>
256B should be 512B (same feedback for the modifier description).
Regards,
Nanley
> Reviewed-by: Imre Deak imre.deak@intel.com<mailto:imre.deak@intel.com>
> Acked-by: Nanley Chery nanley.g.chery@intel.com<mailto:nanley.g.chery@intel.com>
> Signed-off-by: Stanislav Lisovskiy stanislav.lisovskiy@intel.com<mailto:stanislav.lisovskiy@intel.com>
> ---
> include/uapi/drm/drm_fourcc.h | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index fc0c1454d275..b73fe6797fc3 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -572,6 +572,17 @@ extern "C" {
> */
> #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
>
> +/*
> + * Intel Tile 4 layout
> + *
> + * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
> + * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
> + * only differs from Tile Y at the 256B granularity in between. At this
> + * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
> + * of 64B x 8 rows.
> + */
> +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
> +
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> *
>
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^ permalink raw reply [flat|nested] 2+ messages in thread
* [Intel-gfx] [PATCH v5 13/19] drm/i915: Introduce new Tile 4 format
2022-02-01 10:41 [Intel-gfx] [PATCH v5 00/19] drm/i915/dg2: Enabling 64k page size and flat ccs Ramalingam C
@ 2022-02-01 10:41 ` Ramalingam C
0 siblings, 0 replies; 2+ messages in thread
From: Ramalingam C @ 2022-02-01 10:41 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: Nanley Chery, Matthew Auld
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
This tiling layout uses 4KB tiles in a row-major layout. It has the same
shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
only differs from Tile Y at the 256B granularity in between. At this
granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
of 64B x 8 rows.
Reviewed-by: Imre Deak <imre.deak@intel.com>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
include/uapi/drm/drm_fourcc.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index fc0c1454d275..b73fe6797fc3 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -572,6 +572,17 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+/*
+ * Intel Tile 4 layout
+ *
+ * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
+ * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
+ * only differs from Tile Y at the 256B granularity in between. At this
+ * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
+ * of 64B x 8 rows.
+ */
+#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.20.1
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