* [RFC] Ivy Bridge supprt v2
@ 2011-04-28 22:12 Jesse Barnes
2011-04-28 22:12 ` [PATCH 01/19] drm/i915: make FDI training a display function Jesse Barnes
` (18 more replies)
0 siblings, 19 replies; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 22:12 UTC (permalink / raw)
To: intel-gfx
Updated with review comments, just need to check and make sure all the
rebasing didn't mess anything up, and of course testing is always
needed.
Thanks,
Jesse
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 01/19] drm/i915: make FDI training a display function
2011-04-28 22:12 [RFC] Ivy Bridge supprt v2 Jesse Barnes
@ 2011-04-28 22:12 ` Jesse Barnes
2011-04-28 22:33 ` Keith Packard
2011-04-28 22:12 ` [PATCH 02/19] drm/i915: split irq handling into per-chipset functions Jesse Barnes
` (17 subsequent siblings)
18 siblings, 1 reply; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 22:12 UTC (permalink / raw)
To: intel-gfx
Rather than branching in ironlake_pch_enable, add a new train_fdi
function to the display function pointer struct and use it instead.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 7 +++----
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0296967..05a6929 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -209,7 +209,7 @@ struct drm_i915_display_funcs {
struct drm_display_mode *adjusted_mode,
int x, int y,
struct drm_framebuffer *old_fb);
-
+ void (*fdi_link_train)(struct drm_crtc *crtc);
/* clock updates for mode set */
/* cursor updates */
/* render clock increase/decrease */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 62f9e52..0dadc8e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2465,10 +2465,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
u32 reg, temp;
/* For PCH output, training FDI link */
- if (IS_GEN6(dev))
- gen6_fdi_link_train(crtc);
- else
- ironlake_fdi_link_train(crtc);
+ dev_priv->display.fdi_link_train(crtc);
intel_enable_pch_pll(dev_priv, pipe);
@@ -7290,6 +7287,7 @@ static void intel_init_display(struct drm_device *dev)
"Disable CxSR\n");
dev_priv->display.update_wm = NULL;
}
+ dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
} else if (IS_GEN6(dev)) {
if (SNB_READ_WM0_LATENCY()) {
dev_priv->display.update_wm = sandybridge_update_wm;
@@ -7298,6 +7296,7 @@ static void intel_init_display(struct drm_device *dev)
"Disable CxSR\n");
dev_priv->display.update_wm = NULL;
}
+ dev_priv->display.fdi_link_train = gen6_fdi_link_train;
} else
dev_priv->display.update_wm = NULL;
} else if (IS_PINEVIEW(dev)) {
--
1.7.4.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 02/19] drm/i915: split irq handling into per-chipset functions
2011-04-28 22:12 [RFC] Ivy Bridge supprt v2 Jesse Barnes
2011-04-28 22:12 ` [PATCH 01/19] drm/i915: make FDI training a display function Jesse Barnes
@ 2011-04-28 22:12 ` Jesse Barnes
2011-04-28 22:37 ` Keith Packard
2011-05-18 11:51 ` [SNB: Regression] " Ted Phelps
2011-04-28 22:12 ` [PATCH 03/19] drm/i915: split enable/disable vblank code into chipset specific functions Jesse Barnes
` (16 subsequent siblings)
18 siblings, 2 replies; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 22:12 UTC (permalink / raw)
To: intel-gfx
Set the IRQ handling functions in driver load so they'll just be used
directly, rather than branching over most of the code in the chipset
functions.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_dma.c | 12 ++++++++++
drivers/gpu/drm/i915/i915_drv.h | 6 +++++
drivers/gpu/drm/i915/i915_irq.c | 45 +++++++++++++++++++++-----------------
3 files changed, 43 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 3b69f38..2f653c2 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1253,6 +1253,18 @@ static int i915_load_modeset_init(struct drm_device *dev)
intel_modeset_init(dev);
+ if (HAS_PCH_SPLIT(dev)) {
+ dev->driver->irq_handler = ironlake_irq_handler;
+ dev->driver->irq_preinstall = ironlake_irq_preinstall;
+ dev->driver->irq_postinstall = ironlake_irq_postinstall;
+ dev->driver->irq_uninstall = ironlake_irq_uninstall;
+ } else {
+ dev->driver->irq_preinstall = i915_driver_irq_preinstall;
+ dev->driver->irq_postinstall = i915_driver_irq_postinstall;
+ dev->driver->irq_uninstall = i915_driver_irq_uninstall;
+ dev->driver->irq_handler = i915_driver_irq_handler;
+ }
+
ret = drm_irq_install(dev);
if (ret)
goto cleanup_vga_switcheroo;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 05a6929..4841901 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1024,6 +1024,12 @@ extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
extern void i915_driver_irq_preinstall(struct drm_device * dev);
extern int i915_driver_irq_postinstall(struct drm_device *dev);
extern void i915_driver_irq_uninstall(struct drm_device * dev);
+
+extern irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS);
+extern void ironlake_irq_preinstall(struct drm_device *dev);
+extern int ironlake_irq_postinstall(struct drm_device *dev);
+extern void ironlake_irq_uninstall(struct drm_device *dev);
+
extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
struct drm_file *file_priv);
extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5c0466e..a58d477 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -448,8 +448,9 @@ static void pch_irq_handler(struct drm_device *dev)
DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
}
-static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
+irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
{
+ struct drm_device *dev = (struct drm_device *) arg;
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
int ret = IRQ_NONE;
u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
@@ -457,6 +458,8 @@ static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
struct drm_i915_master_private *master_priv;
u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
+ atomic_inc(&dev_priv->irq_received);
+
if (IS_GEN6(dev))
bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
@@ -1103,9 +1106,6 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
atomic_inc(&dev_priv->irq_received);
- if (HAS_PCH_SPLIT(dev))
- return ironlake_irq_handler(dev);
-
iir = I915_READ(IIR);
if (INTEL_INFO(dev)->gen >= 4)
@@ -1562,10 +1562,15 @@ repeat:
/* drm_dma.h hooks
*/
-static void ironlake_irq_preinstall(struct drm_device *dev)
+void ironlake_irq_preinstall(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ atomic_set(&dev_priv->irq_received, 0);
+
+ INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
+ INIT_WORK(&dev_priv->error_work, i915_error_work_func);
+
I915_WRITE(HWSTAM, 0xeffe);
/* XXX hotplug from PCH */
@@ -1585,7 +1590,7 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
POSTING_READ(SDEIER);
}
-static int ironlake_irq_postinstall(struct drm_device *dev)
+int ironlake_irq_postinstall(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
/* enable kind of interrupts always enabled */
@@ -1594,6 +1599,13 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
u32 render_irqs;
u32 hotplug_mask;
+ DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
+ if (HAS_BSD(dev))
+ DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
+ if (HAS_BLT(dev))
+ DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
+
+ dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
dev_priv->irq_mask = ~display_mask;
/* should always can generate irq */
@@ -1660,11 +1672,6 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
INIT_WORK(&dev_priv->error_work, i915_error_work_func);
- if (HAS_PCH_SPLIT(dev)) {
- ironlake_irq_preinstall(dev);
- return;
- }
-
if (I915_HAS_HOTPLUG(dev)) {
I915_WRITE(PORT_HOTPLUG_EN, 0);
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
@@ -1696,9 +1703,6 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
- if (HAS_PCH_SPLIT(dev))
- return ironlake_irq_postinstall(dev);
-
/* Unmask the interrupts that we always want on. */
dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
@@ -1767,9 +1771,15 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
return 0;
}
-static void ironlake_irq_uninstall(struct drm_device *dev)
+void ironlake_irq_uninstall(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+
+ if (!dev_priv)
+ return;
+
+ dev_priv->vblank_pipe = 0;
+
I915_WRITE(HWSTAM, 0xffffffff);
I915_WRITE(DEIMR, 0xffffffff);
@@ -1791,11 +1801,6 @@ void i915_driver_irq_uninstall(struct drm_device * dev)
dev_priv->vblank_pipe = 0;
- if (HAS_PCH_SPLIT(dev)) {
- ironlake_irq_uninstall(dev);
- return;
- }
-
if (I915_HAS_HOTPLUG(dev)) {
I915_WRITE(PORT_HOTPLUG_EN, 0);
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
--
1.7.4.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 03/19] drm/i915: split enable/disable vblank code into chipset specific functions
2011-04-28 22:12 [RFC] Ivy Bridge supprt v2 Jesse Barnes
2011-04-28 22:12 ` [PATCH 01/19] drm/i915: make FDI training a display function Jesse Barnes
2011-04-28 22:12 ` [PATCH 02/19] drm/i915: split irq handling into per-chipset functions Jesse Barnes
@ 2011-04-28 22:12 ` Jesse Barnes
2011-04-28 22:39 ` Keith Packard
2011-04-28 22:12 ` [PATCH 04/19] drm/i915: add IS_GEN7 macro to cover Ivy Bridge and later Jesse Barnes
` (15 subsequent siblings)
18 siblings, 1 reply; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 22:12 UTC (permalink / raw)
To: intel-gfx
This makes the Ironlake+ code trivial and generally simplifies things.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_dma.c | 4 +++
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_irq.c | 42 ++++++++++++++++++++++++++++----------
3 files changed, 37 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 2f653c2..d124f0e 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1258,11 +1258,15 @@ static int i915_load_modeset_init(struct drm_device *dev)
dev->driver->irq_preinstall = ironlake_irq_preinstall;
dev->driver->irq_postinstall = ironlake_irq_postinstall;
dev->driver->irq_uninstall = ironlake_irq_uninstall;
+ dev->driver->enable_vblank = ironlake_enable_vblank;
+ dev->driver->disable_vblank = ironlake_disable_vblank;
} else {
dev->driver->irq_preinstall = i915_driver_irq_preinstall;
dev->driver->irq_postinstall = i915_driver_irq_postinstall;
dev->driver->irq_uninstall = i915_driver_irq_uninstall;
dev->driver->irq_handler = i915_driver_irq_handler;
+ dev->driver->enable_vblank = i915_enable_vblank;
+ dev->driver->disable_vblank = i915_disable_vblank;
}
ret = drm_irq_install(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4841901..4dfe3fa 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1036,6 +1036,8 @@ extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
struct drm_file *file_priv);
extern int i915_enable_vblank(struct drm_device *dev, int crtc);
extern void i915_disable_vblank(struct drm_device *dev, int crtc);
+extern int ironlake_enable_vblank(struct drm_device *dev, int crtc);
+extern void ironlake_disable_vblank(struct drm_device *dev, int crtc);
extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
extern int i915_vblank_swap(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a58d477..d5dcb8f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1344,10 +1344,7 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
return -EINVAL;
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- if (HAS_PCH_SPLIT(dev))
- ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
- DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
- else if (INTEL_INFO(dev)->gen >= 4)
+ if (INTEL_INFO(dev)->gen >= 4)
i915_enable_pipestat(dev_priv, pipe,
PIPE_START_VBLANK_INTERRUPT_ENABLE);
else
@@ -1362,6 +1359,22 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
return 0;
}
+int ironlake_enable_vblank(struct drm_device *dev, int pipe)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ unsigned long irqflags;
+
+ if (!i915_pipe_enabled(dev, pipe))
+ return -EINVAL;
+
+ spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+ ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
+ DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
+ spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+
+ return 0;
+}
+
/* Called from drm generic code, passed 'crtc' which
* we use as a pipe index
*/
@@ -1375,13 +1388,20 @@ void i915_disable_vblank(struct drm_device *dev, int pipe)
I915_WRITE(INSTPM,
INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);
- if (HAS_PCH_SPLIT(dev))
- ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
- DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
- else
- i915_disable_pipestat(dev_priv, pipe,
- PIPE_VBLANK_INTERRUPT_ENABLE |
- PIPE_START_VBLANK_INTERRUPT_ENABLE);
+ i915_disable_pipestat(dev_priv, pipe,
+ PIPE_VBLANK_INTERRUPT_ENABLE |
+ PIPE_START_VBLANK_INTERRUPT_ENABLE);
+ spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+
+void ironlake_disable_vblank(struct drm_device *dev, int pipe)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+ ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
+ DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
--
1.7.4.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 04/19] drm/i915: add IS_GEN7 macro to cover Ivy Bridge and later
2011-04-28 22:12 [RFC] Ivy Bridge supprt v2 Jesse Barnes
` (2 preceding siblings ...)
2011-04-28 22:12 ` [PATCH 03/19] drm/i915: split enable/disable vblank code into chipset specific functions Jesse Barnes
@ 2011-04-28 22:12 ` Jesse Barnes
2011-04-28 22:40 ` Keith Packard
2011-04-28 22:12 ` [PATCH 05/19] drm/i915: add IS_IVYBRIDGE macro for checks Jesse Barnes
` (14 subsequent siblings)
18 siblings, 1 reply; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 22:12 UTC (permalink / raw)
To: intel-gfx
Note: IS_GEN* are for render related checks. Display and other checks
should use IS_MOBILE, IS_$CHIPSET or test for specific features.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4dfe3fa..93ac632 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -931,11 +931,18 @@ enum intel_chip_family {
#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
+/*
+ * The genX designation typically refers to the render engine, so render
+ * capability related checks should use IS_GEN, while display and other checks
+ * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
+ * chips, etc.).
+ */
#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
+#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
--
1.7.4.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 05/19] drm/i915: add IS_IVYBRIDGE macro for checks
2011-04-28 22:12 [RFC] Ivy Bridge supprt v2 Jesse Barnes
` (3 preceding siblings ...)
2011-04-28 22:12 ` [PATCH 04/19] drm/i915: add IS_GEN7 macro to cover Ivy Bridge and later Jesse Barnes
@ 2011-04-28 22:12 ` Jesse Barnes
2011-04-28 22:41 ` Keith Packard
2011-04-28 22:12 ` [PATCH 06/19] drm/i915: Ivy Bridge has split display and pipe control Jesse Barnes
` (13 subsequent siblings)
18 siblings, 1 reply; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 22:12 UTC (permalink / raw)
To: intel-gfx
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 93ac632..3a23de6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -230,6 +230,7 @@ struct intel_device_info {
u8 is_pineview : 1;
u8 is_broadwater : 1;
u8 is_crestline : 1;
+ u8 is_ivybridge : 1;
u8 has_fbc : 1;
u8 has_pipe_cxsr : 1;
u8 has_hotplug : 1;
@@ -929,6 +930,7 @@ enum intel_chip_family {
#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
+#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
/*
--
1.7.4.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 06/19] drm/i915: Ivy Bridge has split display and pipe control
2011-04-28 22:12 [RFC] Ivy Bridge supprt v2 Jesse Barnes
` (4 preceding siblings ...)
2011-04-28 22:12 ` [PATCH 05/19] drm/i915: add IS_IVYBRIDGE macro for checks Jesse Barnes
@ 2011-04-28 22:12 ` Jesse Barnes
2011-04-28 22:41 ` Keith Packard
2011-04-28 22:12 ` [PATCH 07/19] drm/i915: add swizzle/tiling support for Ivy Bridge Jesse Barnes
` (12 subsequent siblings)
18 siblings, 1 reply; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 22:12 UTC (permalink / raw)
To: intel-gfx
Ivy Bridge has a similar split display controller to Sandy Bridge, so
use HAS_PCH_SPLIT. And gen7 also has the pipe control instruction, so
use HAS_PIPE_CONTROL as well.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3a23de6..4c06eb1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -971,8 +971,8 @@ enum intel_chip_family {
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
-#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
-#define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
+#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
+#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
--
1.7.4.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 07/19] drm/i915: add swizzle/tiling support for Ivy Bridge
2011-04-28 22:12 [RFC] Ivy Bridge supprt v2 Jesse Barnes
` (5 preceding siblings ...)
2011-04-28 22:12 ` [PATCH 06/19] drm/i915: Ivy Bridge has split display and pipe control Jesse Barnes
@ 2011-04-28 22:12 ` Jesse Barnes
2011-04-28 22:42 ` Keith Packard
2011-04-28 22:12 ` [PATCH 08/19] drm/i915: manual FDI training " Jesse Barnes
` (11 subsequent siblings)
18 siblings, 1 reply; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 22:12 UTC (permalink / raw)
To: intel-gfx
Treat it like Ironlake and Sandy Bridge.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_gem_tiling.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index dfb682b..418015f 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -92,7 +92,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
- if (IS_GEN5(dev) || IS_GEN6(dev)) {
+ if (IS_GEN5(dev) || IS_GEN6(dev) || IS_GEN7(dev)) {
/* On Ironlake whatever DRAM config, GPU always do
* same swizzling setup.
*/
--
1.7.4.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 08/19] drm/i915: manual FDI training for Ivy Bridge
2011-04-28 22:12 [RFC] Ivy Bridge supprt v2 Jesse Barnes
` (6 preceding siblings ...)
2011-04-28 22:12 ` [PATCH 07/19] drm/i915: add swizzle/tiling support for Ivy Bridge Jesse Barnes
@ 2011-04-28 22:12 ` Jesse Barnes
2011-04-28 22:43 ` Keith Packard
2011-04-28 22:12 ` [PATCH 09/19] drm/i915: automatic FDI training support " Jesse Barnes
` (10 subsequent siblings)
18 siblings, 1 reply; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 22:12 UTC (permalink / raw)
To: intel-gfx
A0 stepping chips need to use manual training, but the bits have all
moved. So fix things up so we can at least train FDI for VGA links.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_reg.h | 10 +++
drivers/gpu/drm/i915/intel_display.c | 128 +++++++++++++++++++++++++++++++++-
2 files changed, 135 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8848411..aba3fe5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3105,7 +3105,15 @@
#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
/* Ironlake: hardwired to 1 */
#define FDI_TX_PLL_ENABLE (1<<14)
+
+/* Ivybridge has different bits for lolz */
+#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
+#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
+#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
+#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
+
/* both Tx and Rx */
+#define FDI_LINK_TRAIN_AUTO (1<<10)
#define FDI_SCRAMBLING_ENABLE (0<<7)
#define FDI_SCRAMBLING_DISABLE (1<<7)
@@ -3115,6 +3123,8 @@
#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
#define FDI_RX_ENABLE (1<<31)
/* train, dp width same as FDI_TX */
+#define FDI_FS_ERRC_ENABLE (1<<27)
+#define FDI_FE_ERRC_ENABLE (1<<26)
#define FDI_DP_PORT_WIDTH_X8 (7<<19)
#define FDI_8BPC (0<<16)
#define FDI_10BPC (1<<16)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0dadc8e..ab840a6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2047,8 +2047,13 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
/* enable normal train */
reg = FDI_TX_CTL(pipe);
temp = I915_READ(reg);
- temp &= ~FDI_LINK_TRAIN_NONE;
- temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
+ if (IS_GEN6(dev)) {
+ temp &= ~FDI_LINK_TRAIN_NONE;
+ temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
+ } else if (IS_IVYBRIDGE(dev)) {
+ temp &= ~FDI_LINK_TRAIN_NONE_IVB;
+ temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
+ }
I915_WRITE(reg, temp);
reg = FDI_RX_CTL(pipe);
@@ -2065,6 +2070,11 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
/* wait one idle pattern time */
POSTING_READ(reg);
udelay(1000);
+
+ /* IVB wants error correction enabled */
+ if (IS_IVYBRIDGE(dev))
+ I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
+ FDI_FE_ERRC_ENABLE);
}
/* The FDI link training functions for ILK/Ibexpeak. */
@@ -2292,7 +2302,116 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
DRM_DEBUG_KMS("FDI train done.\n");
}
-static void ironlake_fdi_enable(struct drm_crtc *crtc)
+/* Manual link training for Ivy Bridge A0 parts */
+static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc->pipe;
+ u32 reg, temp, i;
+
+ /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
+ for train result */
+ reg = FDI_RX_IMR(pipe);
+ temp = I915_READ(reg);
+ temp &= ~FDI_RX_SYMBOL_LOCK;
+ temp &= ~FDI_RX_BIT_LOCK;
+ I915_WRITE(reg, temp);
+
+ POSTING_READ(reg);
+ udelay(150);
+
+ /* enable CPU FDI TX and PCH FDI RX */
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp &= ~(7 << 19);
+ temp |= (intel_crtc->fdi_lanes - 1) << 19;
+ temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
+ temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
+ temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+ temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
+ I915_WRITE(reg, temp | FDI_TX_ENABLE);
+
+ reg = FDI_RX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp &= ~FDI_LINK_TRAIN_AUTO;
+ temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
+ temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
+ I915_WRITE(reg, temp | FDI_RX_ENABLE);
+
+ POSTING_READ(reg);
+ udelay(150);
+
+ for (i = 0; i < 4; i++ ) {
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+ temp |= snb_b_fdi_train_param[i];
+ I915_WRITE(reg, temp);
+
+ POSTING_READ(reg);
+ udelay(500);
+
+ reg = FDI_RX_IIR(pipe);
+ temp = I915_READ(reg);
+ DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
+
+ if (temp & FDI_RX_BIT_LOCK ||
+ (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
+ I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
+ DRM_DEBUG_KMS("FDI train 1 done.\n");
+ break;
+ }
+ }
+ if (i == 4)
+ DRM_ERROR("FDI train 1 fail!\n");
+
+ /* Train 2 */
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp &= ~FDI_LINK_TRAIN_NONE_IVB;
+ temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
+ temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+ temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
+ I915_WRITE(reg, temp);
+
+ reg = FDI_RX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
+ temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
+ I915_WRITE(reg, temp);
+
+ POSTING_READ(reg);
+ udelay(150);
+
+ for (i = 0; i < 4; i++ ) {
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+ temp |= snb_b_fdi_train_param[i];
+ I915_WRITE(reg, temp);
+
+ POSTING_READ(reg);
+ udelay(500);
+
+ reg = FDI_RX_IIR(pipe);
+ temp = I915_READ(reg);
+ DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
+
+ if (temp & FDI_RX_SYMBOL_LOCK) {
+ I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
+ DRM_DEBUG_KMS("FDI train 2 done.\n");
+ break;
+ }
+ }
+ if (i == 4)
+ DRM_ERROR("FDI train 2 fail!\n");
+
+ DRM_DEBUG_KMS("FDI train done.\n");
+}
+
+static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7297,6 +7416,9 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.update_wm = NULL;
}
dev_priv->display.fdi_link_train = gen6_fdi_link_train;
+ } else if (IS_IVYBRIDGE(dev)) {
+ /* FIXME: detect B0+ stepping and use auto training */
+ dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
} else
dev_priv->display.update_wm = NULL;
} else if (IS_PINEVIEW(dev)) {
--
1.7.4.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 09/19] drm/i915: automatic FDI training support for Ivy Bridge
2011-04-28 22:12 [RFC] Ivy Bridge supprt v2 Jesse Barnes
` (7 preceding siblings ...)
2011-04-28 22:12 ` [PATCH 08/19] drm/i915: manual FDI training " Jesse Barnes
@ 2011-04-28 22:12 ` Jesse Barnes
2011-04-28 22:20 ` Jesse Barnes
2011-04-28 22:43 ` Keith Packard
2011-04-28 22:12 ` [PATCH 10/19] drm/i915: treat Ivy Bridge watermarks like Sandy Bridge Jesse Barnes
` (9 subsequent siblings)
18 siblings, 2 replies; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 22:12 UTC (permalink / raw)
To: intel-gfx
Ivy Bridge supports auto-training on the CPU side, so add a separate
training function to handle it.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_display.c | 82 +++++++++++++++++++++++++++++++--
2 files changed, 79 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index aba3fe5..03c99ed 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3116,6 +3116,8 @@
#define FDI_LINK_TRAIN_AUTO (1<<10)
#define FDI_SCRAMBLING_ENABLE (0<<7)
#define FDI_SCRAMBLING_DISABLE (1<<7)
+/* Ivybridge */
+#define FDI_AUTO_TRAIN_DONE (1<<1)
/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
#define _FDI_RXA_CTL 0xf000c
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ab840a6..3396043 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2411,6 +2411,75 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
DRM_DEBUG_KMS("FDI train done.\n");
}
+/* On Ivybridge we can use auto training */
+static void ivb_fdi_link_train(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ unsigned long start = jiffies_to_msecs(jiffies);
+ int pipe = intel_crtc->pipe;
+ u32 reg, temp, i, j;
+
+ /* Can't pair IVB & Ibex Peak */
+ BUG_ON(HAS_PCH_IBX(dev));
+
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp &= ~(7 << 19);
+ temp |= (intel_crtc->fdi_lanes - 1) << 19;
+ temp &= ~FDI_LINK_TRAIN_NONE;
+ I915_WRITE(reg, temp);
+
+ /* Enable auto training on TX and RX */
+ for (i = 0; i < ARRAY_SIZE(snb_b_fdi_train_param); i++) {
+ /* Try each vswing/pre-emphasis pair twice */
+ for (j = 0; j < 2; j++) {
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp |= FDI_AUTO_TRAINING;
+ temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+ temp |= snb_b_fdi_train_param[i];
+ I915_WRITE(reg, temp | FDI_TX_ENABLE);
+
+ reg = FDI_RX_CTL(pipe);
+ temp = I915_READ(reg);
+ I915_WRITE(reg, temp | FDI_RX_ENABLE);
+ POSTING_READ(reg);
+
+ udelay(5);
+
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ if ((temp & FDI_AUTO_TRAIN_DONE) ||
+ (I915_READ(reg) & FDI_AUTO_TRAIN_DONE)) {
+ DRM_DEBUG_KMS("FDI auto train complete in %d ms\n",
+ jiffies_to_msecs(jiffies) - start);
+ goto done;
+ }
+
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
+
+ reg = FDI_RX_CTL(pipe);
+ temp = I915_READ(reg);
+ I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
+ POSTING_READ(reg);
+ udelay(31); /* wait idle time before retrying */
+ }
+ }
+ DRM_ERROR("FDI auto train failed\n");
+ return;
+
+done:
+ reg = FDI_RX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp |= FDI_FS_ERR_CORRECT_ENABLE | FDI_FE_ERR_CORRECT_ENABLE;
+ I915_WRITE(reg, temp);
+ POSTING_READ(reg);
+}
+
static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
@@ -2452,7 +2521,7 @@ static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
}
}
-static void ironlake_fdi_disable(struct drm_crtc *crtc)
+static void ironlake_fdi_pll_disable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2674,9 +2743,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
is_pch_port = intel_crtc_driving_pch(crtc);
if (is_pch_port)
- ironlake_fdi_enable(crtc);
+ ironlake_fdi_pll_enable(crtc);
else
- ironlake_fdi_disable(crtc);
+ ironlake_fdi_pll_disable(crtc);
/* Enable panel fitting for LVDS */
if (dev_priv->pch_pf_size &&
@@ -2729,7 +2798,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
I915_WRITE(PF_CTL(pipe), 0);
I915_WRITE(PF_WIN_SZ(pipe), 0);
- ironlake_fdi_disable(crtc);
+ ironlake_fdi_pll_disable(crtc);
/* This is a horrible layering violation; we should be doing this in
* the connector/encoder ->prepare instead, but we don't always have
@@ -7418,7 +7487,10 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.fdi_link_train = gen6_fdi_link_train;
} else if (IS_IVYBRIDGE(dev)) {
/* FIXME: detect B0+ stepping and use auto training */
- dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
+ if (0)
+ dev_priv->display.fdi_link_train = ivb_fdi_link_train;
+ else
+ dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
} else
dev_priv->display.update_wm = NULL;
} else if (IS_PINEVIEW(dev)) {
--
1.7.4.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 10/19] drm/i915: treat Ivy Bridge watermarks like Sandy Bridge
2011-04-28 22:12 [RFC] Ivy Bridge supprt v2 Jesse Barnes
` (8 preceding siblings ...)
2011-04-28 22:12 ` [PATCH 09/19] drm/i915: automatic FDI training support " Jesse Barnes
@ 2011-04-28 22:12 ` Jesse Barnes
2011-04-28 22:46 ` Keith Packard
2011-04-28 22:12 ` [PATCH 11/19] drm/i915: interrupt & vblank support for Ivy Bridge Jesse Barnes
` (8 subsequent siblings)
18 siblings, 1 reply; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 22:12 UTC (permalink / raw)
To: intel-gfx
Not fully tested.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/intel_display.c | 9 ++++++++-
1 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3396043..fbb7a6b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7229,7 +7229,7 @@ void intel_enable_clock_gating(struct drm_device *dev)
_3D_CHICKEN2_WM_READ_PIPELINED);
}
- if (IS_GEN6(dev)) {
+ if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
I915_WRITE(WM3_LP_ILK, 0);
I915_WRITE(WM2_LP_ILK, 0);
I915_WRITE(WM1_LP_ILK, 0);
@@ -7491,6 +7491,13 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.fdi_link_train = ivb_fdi_link_train;
else
dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
+ if (SNB_READ_WM0_LATENCY()) {
+ dev_priv->display.update_wm = sandybridge_update_wm;
+ } else {
+ DRM_DEBUG_KMS("Failed to read display plane latency. "
+ "Disable CxSR\n");
+ dev_priv->display.update_wm = NULL;
+ }
} else
dev_priv->display.update_wm = NULL;
} else if (IS_PINEVIEW(dev)) {
--
1.7.4.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 11/19] drm/i915: interrupt & vblank support for Ivy Bridge
2011-04-28 22:12 [RFC] Ivy Bridge supprt v2 Jesse Barnes
` (9 preceding siblings ...)
2011-04-28 22:12 ` [PATCH 10/19] drm/i915: treat Ivy Bridge watermarks like Sandy Bridge Jesse Barnes
@ 2011-04-28 22:12 ` Jesse Barnes
2011-04-28 22:47 ` Keith Packard
2011-06-28 10:55 ` Chris Wilson
2011-04-28 22:12 ` [PATCH 12/19] drm/i915: page flip " Jesse Barnes
` (7 subsequent siblings)
18 siblings, 2 replies; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 22:12 UTC (permalink / raw)
To: intel-gfx
Add new interrupt handling functions for Ivy Bridge.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_dma.c | 12 +++-
drivers/gpu/drm/i915/i915_drv.h | 7 ++
drivers/gpu/drm/i915/i915_irq.c | 156 +++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 13 +++
4 files changed, 186 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index d124f0e..8e27bc4 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1253,7 +1253,15 @@ static int i915_load_modeset_init(struct drm_device *dev)
intel_modeset_init(dev);
- if (HAS_PCH_SPLIT(dev)) {
+ if (IS_IVYBRIDGE(dev)) {
+ /* Share pre & uninstall handlers with ILK/SNB */
+ dev->driver->irq_handler = ivybridge_irq_handler;
+ dev->driver->irq_preinstall = ironlake_irq_preinstall;
+ dev->driver->irq_postinstall = ivybridge_irq_postinstall;
+ dev->driver->irq_uninstall = ironlake_irq_uninstall;
+ dev->driver->enable_vblank = ivybridge_enable_vblank;
+ dev->driver->disable_vblank = ivybridge_disable_vblank;
+ } else if (HAS_PCH_SPLIT(dev)) {
dev->driver->irq_handler = ironlake_irq_handler;
dev->driver->irq_preinstall = ironlake_irq_preinstall;
dev->driver->irq_postinstall = ironlake_irq_postinstall;
@@ -1998,7 +2006,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
dev->driver->get_vblank_counter = i915_get_vblank_counter;
dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
- if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
+ if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
dev->driver->get_vblank_counter = gm45_get_vblank_counter;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4c06eb1..5f906f1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1039,6 +1039,11 @@ extern void ironlake_irq_preinstall(struct drm_device *dev);
extern int ironlake_irq_postinstall(struct drm_device *dev);
extern void ironlake_irq_uninstall(struct drm_device *dev);
+extern irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS);
+extern void ivybridge_irq_preinstall(struct drm_device *dev);
+extern int ivybridge_irq_postinstall(struct drm_device *dev);
+extern void ivybridge_irq_uninstall(struct drm_device *dev);
+
extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
struct drm_file *file_priv);
extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
@@ -1047,6 +1052,8 @@ extern int i915_enable_vblank(struct drm_device *dev, int crtc);
extern void i915_disable_vblank(struct drm_device *dev, int crtc);
extern int ironlake_enable_vblank(struct drm_device *dev, int crtc);
extern void ironlake_disable_vblank(struct drm_device *dev, int crtc);
+extern int ivybridge_enable_vblank(struct drm_device *dev, int crtc);
+extern void ivybridge_disable_vblank(struct drm_device *dev, int crtc);
extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
extern int i915_vblank_swap(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d5dcb8f..a025002 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -448,6 +448,85 @@ static void pch_irq_handler(struct drm_device *dev)
DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
}
+irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
+{
+ struct drm_device *dev = (struct drm_device *) arg;
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ int ret = IRQ_NONE;
+ u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
+ struct drm_i915_master_private *master_priv;
+
+ atomic_inc(&dev_priv->irq_received);
+
+ /* disable master interrupt before clearing iir */
+ de_ier = I915_READ(DEIER);
+ I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
+ POSTING_READ(DEIER);
+
+ de_iir = I915_READ(DEIIR);
+ gt_iir = I915_READ(GTIIR);
+ pch_iir = I915_READ(SDEIIR);
+ pm_iir = I915_READ(GEN6_PMIIR);
+
+ if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
+ goto done;
+
+ ret = IRQ_HANDLED;
+
+ if (dev->primary->master) {
+ master_priv = dev->primary->master->driver_priv;
+ if (master_priv->sarea_priv)
+ master_priv->sarea_priv->last_dispatch =
+ READ_BREADCRUMB(dev_priv);
+ }
+
+ if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
+ notify_ring(dev, &dev_priv->ring[RCS]);
+ if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT)
+ notify_ring(dev, &dev_priv->ring[VCS]);
+ if (gt_iir & GT_BLT_USER_INTERRUPT)
+ notify_ring(dev, &dev_priv->ring[BCS]);
+
+ if (de_iir & DE_GSE_IVB)
+ intel_opregion_gse_intr(dev);
+
+ if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
+ intel_prepare_page_flip(dev, 0);
+ intel_finish_page_flip_plane(dev, 0);
+ }
+
+ if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
+ intel_prepare_page_flip(dev, 1);
+ intel_finish_page_flip_plane(dev, 1);
+ }
+
+ if (de_iir & DE_PIPEA_VBLANK_IVB)
+ drm_handle_vblank(dev, 0);
+
+ if (de_iir & DE_PIPEB_VBLANK_IVB);
+ drm_handle_vblank(dev, 1);
+
+ /* check event from PCH */
+ if (de_iir & DE_PCH_EVENT_IVB) {
+ if (pch_iir & SDE_HOTPLUG_MASK_CPT)
+ queue_work(dev_priv->wq, &dev_priv->hotplug_work);
+ pch_irq_handler(dev);
+ }
+
+ gen6_pm_irq_handler(dev);
+
+ /* should clear PCH hotplug event before clear CPU irq */
+ I915_WRITE(SDEIIR, pch_iir);
+ I915_WRITE(GTIIR, gt_iir);
+ I915_WRITE(DEIIR, de_iir);
+
+done:
+ I915_WRITE(DEIER, de_ier);
+ POSTING_READ(DEIER);
+
+ return ret;
+}
+
irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
{
struct drm_device *dev = (struct drm_device *) arg;
@@ -1375,6 +1454,22 @@ int ironlake_enable_vblank(struct drm_device *dev, int pipe)
return 0;
}
+int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ unsigned long irqflags;
+
+ if (!i915_pipe_enabled(dev, pipe))
+ return -EINVAL;
+
+ spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+ ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
+ DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
+ spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+
+ return 0;
+}
+
/* Called from drm generic code, passed 'crtc' which
* we use as a pipe index
*/
@@ -1405,6 +1500,17 @@ void ironlake_disable_vblank(struct drm_device *dev, int pipe)
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
+void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+ ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
+ DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
+ spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+
/* Set the vblank monitor pipe
*/
int i915_vblank_pipe_set(struct drm_device *dev, void *data,
@@ -1682,6 +1788,56 @@ int ironlake_irq_postinstall(struct drm_device *dev)
return 0;
}
+int ivybridge_irq_postinstall(struct drm_device *dev)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ /* enable kind of interrupts always enabled */
+ u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
+ DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
+ DE_PLANEB_FLIP_DONE_IVB;
+ u32 render_irqs;
+ u32 hotplug_mask;
+
+ DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
+ if (HAS_BSD(dev))
+ DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
+ if (HAS_BLT(dev))
+ DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
+
+ dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
+ dev_priv->irq_mask = ~display_mask;
+
+ /* should always can generate irq */
+ I915_WRITE(DEIIR, I915_READ(DEIIR));
+ I915_WRITE(DEIMR, dev_priv->irq_mask);
+ I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
+ DE_PIPEB_VBLANK_IVB);
+ POSTING_READ(DEIER);
+
+ dev_priv->gt_irq_mask = ~0;
+
+ I915_WRITE(GTIIR, I915_READ(GTIIR));
+ I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
+
+ render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT |
+ GT_BLT_USER_INTERRUPT;
+ I915_WRITE(GTIER, render_irqs);
+ POSTING_READ(GTIER);
+
+ hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
+ SDE_PORTB_HOTPLUG_CPT |
+ SDE_PORTC_HOTPLUG_CPT |
+ SDE_PORTD_HOTPLUG_CPT);
+ dev_priv->pch_irq_mask = ~hotplug_mask;
+
+ I915_WRITE(SDEIIR, I915_READ(SDEIIR));
+ I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
+ I915_WRITE(SDEIER, hotplug_mask);
+ POSTING_READ(SDEIER);
+
+ return 0;
+}
+
void i915_driver_irq_preinstall(struct drm_device * dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 03c99ed..6d4e671 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2779,6 +2779,19 @@
#define DE_PIPEA_VSYNC (1 << 3)
#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
+/* More Ivybridge lolz */
+#define DE_ERR_DEBUG_IVB (1<<30)
+#define DE_GSE_IVB (1<<29)
+#define DE_PCH_EVENT_IVB (1<<28)
+#define DE_DP_A_HOTPLUG_IVB (1<<27)
+#define DE_AUX_CHANNEL_A_IVB (1<<26)
+#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
+#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
+#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
+#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
+#define DE_PIPEB_VBLANK_IVB (1<<5)
+#define DE_PIPEA_VBLANK_IVB (1<<0)
+
#define DEISR 0x44000
#define DEIMR 0x44004
#define DEIIR 0x44008
--
1.7.4.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 12/19] drm/i915: page flip support for Ivy Bridge
2011-04-28 22:12 [RFC] Ivy Bridge supprt v2 Jesse Barnes
` (10 preceding siblings ...)
2011-04-28 22:12 ` [PATCH 11/19] drm/i915: interrupt & vblank support for Ivy Bridge Jesse Barnes
@ 2011-04-28 22:12 ` Jesse Barnes
2011-04-28 22:12 ` [PATCH 13/19] drm/i915: untested DP " Jesse Barnes
` (6 subsequent siblings)
18 siblings, 0 replies; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 22:12 UTC (permalink / raw)
To: intel-gfx
Treat Ivy Bridge like previous chips as far as flip submission is
concerned.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/intel_display.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fbb7a6b..5ce54fe 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6362,6 +6362,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
break;
case 6:
+ case 7:
OUT_RING(MI_DISPLAY_FLIP |
MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
OUT_RING(fb->pitch | obj->tiling_mode);
--
1.7.4.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 13/19] drm/i915: untested DP support for Ivy Bridge
2011-04-28 22:12 [RFC] Ivy Bridge supprt v2 Jesse Barnes
` (11 preceding siblings ...)
2011-04-28 22:12 ` [PATCH 12/19] drm/i915: page flip " Jesse Barnes
@ 2011-04-28 22:12 ` Jesse Barnes
2011-04-28 22:47 ` Keith Packard
2011-05-01 16:26 ` Chris Wilson
2011-04-28 22:13 ` [PATCH 14/19] drm/i915: ring " Jesse Barnes
` (5 subsequent siblings)
18 siblings, 2 replies; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 22:12 UTC (permalink / raw)
To: intel-gfx
Treat it like Sandy Bridge in a few places.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/intel_dp.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0daefca..1d0eccd 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -312,7 +312,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
else
aux_clock_divider = intel_hrawclk(dev) / 2;
- if (IS_GEN6(dev))
+ if (IS_GEN6(dev) || IS_GEN7(dev))
precharge = 3;
else
precharge = 5;
@@ -1302,7 +1302,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
for (;;) {
/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
uint32_t signal_levels;
- if (IS_GEN6(dev) && is_edp(intel_dp)) {
+ if ((IS_GEN6(dev) || IS_GEN7(dev)) && is_edp(intel_dp)) {
signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
} else {
@@ -1376,7 +1376,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
break;
}
- if (IS_GEN6(dev) && is_edp(intel_dp)) {
+ if ((IS_GEN6(dev) || IS_GEN7(dev)) && is_edp(intel_dp)) {
signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
} else {
--
1.7.4.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 14/19] drm/i915: ring support for Ivy Bridge
2011-04-28 22:12 [RFC] Ivy Bridge supprt v2 Jesse Barnes
` (12 preceding siblings ...)
2011-04-28 22:12 ` [PATCH 13/19] drm/i915: untested DP " Jesse Barnes
@ 2011-04-28 22:13 ` Jesse Barnes
2011-04-28 22:48 ` Keith Packard
2011-04-28 22:13 ` [PATCH 15/19] agp/intel: add Ivy Bridge support Jesse Barnes
` (4 subsequent siblings)
18 siblings, 1 reply; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 22:13 UTC (permalink / raw)
To: intel-gfx
Use Sandy Bridge paths in a few places.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index f15d80f..9bcfb9b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -287,7 +287,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
if (INTEL_INFO(dev)->gen > 3) {
int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
- if (IS_GEN6(dev))
+ if (IS_GEN6(dev) || IS_GEN7(dev))
mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
I915_WRITE(MI_MODE, mode);
}
@@ -553,7 +553,7 @@ render_ring_put_irq(struct intel_ring_buffer *ring)
void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
{
drm_i915_private_t *dev_priv = ring->dev->dev_private;
- u32 mmio = IS_GEN6(ring->dev) ?
+ u32 mmio = (IS_GEN6(ring->dev) || IS_GEN7(ring->dev)) ?
RING_HWS_PGA_GEN6(ring->mmio_base) :
RING_HWS_PGA(ring->mmio_base);
I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
@@ -1335,7 +1335,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
drm_i915_private_t *dev_priv = dev->dev_private;
struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
- if (IS_GEN6(dev))
+ if (IS_GEN6(dev) || IS_GEN7(dev))
*ring = gen6_bsd_ring;
else
*ring = bsd_ring;
--
1.7.4.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 15/19] agp/intel: add Ivy Bridge support
2011-04-28 22:12 [RFC] Ivy Bridge supprt v2 Jesse Barnes
` (13 preceding siblings ...)
2011-04-28 22:13 ` [PATCH 14/19] drm/i915: ring " Jesse Barnes
@ 2011-04-28 22:13 ` Jesse Barnes
2011-04-28 22:13 ` [PATCH 16/19] drm/i915: add PantherPoint PCH ID Jesse Barnes
` (3 subsequent siblings)
18 siblings, 0 replies; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 22:13 UTC (permalink / raw)
To: intel-gfx
Just use the Sandy Bridge routines.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/char/agp/intel-agp.c | 3 +++
drivers/char/agp/intel-agp.h | 8 ++++++++
drivers/char/agp/intel-gtt.c | 10 ++++++++++
3 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index b0a0dcc..b427711 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -903,6 +903,9 @@ static struct pci_device_id agp_intel_pci_table[] = {
ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB),
ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB),
ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB),
+ ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB),
+ ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB),
+ ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB),
{ }
};
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 5feebe2..999803c 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -225,6 +225,14 @@
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG 0x0126
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB 0x0108 /* Server */
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG 0x010A
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB 0x0150 /* Desktop */
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG 0x0152
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG 0x0162
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB 0x0154 /* Mobile */
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG 0x0156
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG 0x0166
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB 0x0158 /* Server */
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG 0x015A
int intel_gmch_probe(struct pci_dev *pdev,
struct agp_bridge_data *bridge);
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 0d09b53..8515101 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1420,6 +1420,16 @@ static const struct intel_gtt_driver_description {
"Sandybridge", &sandybridge_gtt_driver },
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
"Sandybridge", &sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG,
+ "Ivybridge", &sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG,
+ "Ivybridge", &sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG,
+ "Ivybridge", &sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG,
+ "Ivybridge", &sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,
+ "Ivybridge", &sandybridge_gtt_driver },
{ 0, NULL, NULL }
};
--
1.7.4.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 16/19] drm/i915: add PantherPoint PCH ID
2011-04-28 22:12 [RFC] Ivy Bridge supprt v2 Jesse Barnes
` (14 preceding siblings ...)
2011-04-28 22:13 ` [PATCH 15/19] agp/intel: add Ivy Bridge support Jesse Barnes
@ 2011-04-28 22:13 ` Jesse Barnes
2011-04-28 22:13 ` [PATCH 17/19] drm/i915: add Ivy Bridge PCI IDs and driver feature structs Jesse Barnes
` (2 subsequent siblings)
18 siblings, 0 replies; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 22:13 UTC (permalink / raw)
To: intel-gfx
We can treat PantherPoint as CougarPoint as far as display goes.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_drv.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5d0d28c..09d2b78 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -236,6 +236,7 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
#define INTEL_PCH_DEVICE_ID_MASK 0xff00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
+#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
void intel_detect_pch (struct drm_device *dev)
{
@@ -257,6 +258,10 @@ void intel_detect_pch (struct drm_device *dev)
if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
+ } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
+ /* PantherPoint is CPT compatible */
+ dev_priv->pch_type = PCH_CPT;
+ DRM_DEBUG_KMS("Found PatherPoint PCH\n");
}
}
pci_dev_put(pch);
--
1.7.4.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 17/19] drm/i915: add Ivy Bridge PCI IDs and driver feature structs
2011-04-28 22:12 [RFC] Ivy Bridge supprt v2 Jesse Barnes
` (15 preceding siblings ...)
2011-04-28 22:13 ` [PATCH 16/19] drm/i915: add PantherPoint PCH ID Jesse Barnes
@ 2011-04-28 22:13 ` Jesse Barnes
2011-04-28 22:49 ` Keith Packard
2011-04-28 22:13 ` [PATCH 18/19] drm/i915: set IBX pch type explicitly Jesse Barnes
2011-04-28 22:13 ` [PATCH 19/19] drm/i915: split clock gating init into per-chipset functions Jesse Barnes
18 siblings, 1 reply; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 22:13 UTC (permalink / raw)
To: intel-gfx
There are several variants, set feature bits appropriately for both
mobile and desktop parts.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_drv.c | 19 +++++++++++++++++++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 09d2b78..14b9c6f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -188,6 +188,20 @@ static const struct intel_device_info intel_sandybridge_m_info = {
.has_blt_ring = 1,
};
+static const struct intel_device_info intel_ivybridge_d_info = {
+ .is_ivybridge = 1, .gen = 7,
+ .need_gfx_hws = 1, .has_hotplug = 1,
+ .has_bsd_ring = 1,
+ .has_blt_ring = 1,
+};
+
+static const struct intel_device_info intel_ivybridge_m_info = {
+ .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
+ .need_gfx_hws = 1, .has_hotplug = 1,
+ .has_bsd_ring = 1,
+ .has_blt_ring = 1,
+};
+
static const struct pci_device_id pciidlist[] = { /* aka */
INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
@@ -227,6 +241,11 @@ static const struct pci_device_id pciidlist[] = { /* aka */
INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
+ INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
+ INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
+ INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
+ INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
+ INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
{0, 0, 0}
};
--
1.7.4.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 18/19] drm/i915: set IBX pch type explicitly
2011-04-28 22:12 [RFC] Ivy Bridge supprt v2 Jesse Barnes
` (16 preceding siblings ...)
2011-04-28 22:13 ` [PATCH 17/19] drm/i915: add Ivy Bridge PCI IDs and driver feature structs Jesse Barnes
@ 2011-04-28 22:13 ` Jesse Barnes
2011-04-28 22:49 ` Keith Packard
2011-04-28 22:13 ` [PATCH 19/19] drm/i915: split clock gating init into per-chipset functions Jesse Barnes
18 siblings, 1 reply; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 22:13 UTC (permalink / raw)
To: intel-gfx
This is a little less confusing than relying on the implicit zeroing of
the dev_priv.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_drv.c | 6 +++++-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 14b9c6f..9290abd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -254,6 +254,7 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
#endif
#define INTEL_PCH_DEVICE_ID_MASK 0xff00
+#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
@@ -274,7 +275,10 @@ void intel_detect_pch (struct drm_device *dev)
int id;
id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
- if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
+ if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
+ dev_priv->pch_type = PCH_IBX;
+ DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
+ } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
--
1.7.4.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 19/19] drm/i915: split clock gating init into per-chipset functions
2011-04-28 22:12 [RFC] Ivy Bridge supprt v2 Jesse Barnes
` (17 preceding siblings ...)
2011-04-28 22:13 ` [PATCH 18/19] drm/i915: set IBX pch type explicitly Jesse Barnes
@ 2011-04-28 22:13 ` Jesse Barnes
18 siblings, 0 replies; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 22:13 UTC (permalink / raw)
To: intel-gfx
This helps contain the mess to init_display() instead.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_suspend.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 337 +++++++++++++++++++---------------
3 files changed, 195 insertions(+), 146 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5f906f1..c4628d4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -210,12 +210,12 @@ struct drm_i915_display_funcs {
int x, int y,
struct drm_framebuffer *old_fb);
void (*fdi_link_train)(struct drm_crtc *crtc);
+ void (*init_clock_gating)(struct drm_device *dev);
/* clock updates for mode set */
/* cursor updates */
/* render clock increase/decrease */
/* display clock increase/decrease */
/* pll clock increase/decrease */
- /* clock gating init */
};
struct intel_device_info {
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index da47415..6cb27ff 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -864,7 +864,7 @@ int i915_restore_state(struct drm_device *dev)
}
/* Clock gating state */
- intel_enable_clock_gating(dev);
+ dev_priv->display.init_clock_gating(dev);
if (IS_IRONLAKE_M(dev)) {
ironlake_enable_drps(dev);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5ce54fe..77a32fe 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7142,161 +7142,194 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
__gen6_gt_force_wake_put(dev_priv);
}
-void intel_enable_clock_gating(struct drm_device *dev)
+static void ironlake_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
+
+ /* Required for FBC */
+ dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
+ DPFCRUNIT_CLOCK_GATE_DISABLE |
+ DPFDUNIT_CLOCK_GATE_DISABLE;
+ /* Required for CxSR */
+ dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
+
+ I915_WRITE(PCH_3DCGDIS0,
+ MARIUNIT_CLOCK_GATE_DISABLE |
+ SVSMUNIT_CLOCK_GATE_DISABLE);
+ I915_WRITE(PCH_3DCGDIS1,
+ VFMUNIT_CLOCK_GATE_DISABLE);
+
+ I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
+
+ /*
+ * On Ibex Peak and Cougar Point, we need to disable clock
+ * gating for the panel power sequencer or it will fail to
+ * start up when no ports are active.
+ */
+ I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
+
+ /*
+ * According to the spec the following bits should be set in
+ * order to enable memory self-refresh
+ * The bit 22/21 of 0x42004
+ * The bit 5 of 0x42020
+ * The bit 15 of 0x45000
+ */
+ I915_WRITE(ILK_DISPLAY_CHICKEN2,
+ (I915_READ(ILK_DISPLAY_CHICKEN2) |
+ ILK_DPARB_GATE | ILK_VSDPFD_FULL));
+ I915_WRITE(ILK_DSPCLK_GATE,
+ (I915_READ(ILK_DSPCLK_GATE) |
+ ILK_DPARB_CLK_GATE));
+ I915_WRITE(DISP_ARB_CTL,
+ (I915_READ(DISP_ARB_CTL) |
+ DISP_FBC_WM_DIS));
+ I915_WRITE(WM3_LP_ILK, 0);
+ I915_WRITE(WM2_LP_ILK, 0);
+ I915_WRITE(WM1_LP_ILK, 0);
+
+ /*
+ * Based on the document from hardware guys the following bits
+ * should be set unconditionally in order to enable FBC.
+ * The bit 22 of 0x42000
+ * The bit 22 of 0x42004
+ * The bit 7,8,9 of 0x42020.
+ */
+ if (IS_IRONLAKE_M(dev)) {
+ I915_WRITE(ILK_DISPLAY_CHICKEN1,
+ I915_READ(ILK_DISPLAY_CHICKEN1) |
+ ILK_FBCQ_DIS);
+ I915_WRITE(ILK_DISPLAY_CHICKEN2,
+ I915_READ(ILK_DISPLAY_CHICKEN2) |
+ ILK_DPARB_GATE);
+ I915_WRITE(ILK_DSPCLK_GATE,
+ I915_READ(ILK_DSPCLK_GATE) |
+ ILK_DPFC_DIS1 |
+ ILK_DPFC_DIS2 |
+ ILK_CLK_FBC);
+ }
+
+ I915_WRITE(ILK_DISPLAY_CHICKEN2,
+ I915_READ(ILK_DISPLAY_CHICKEN2) |
+ ILK_ELPIN_409_SELECT);
+ I915_WRITE(_3D_CHICKEN2,
+ _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
+ _3D_CHICKEN2_WM_READ_PIPELINED);
+}
+
+static void gen6_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
int pipe;
+ uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
+
+ I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
/*
- * Disable clock gating reported to work incorrectly according to the
- * specs, but enable as much else as we can.
+ * On Ibex Peak and Cougar Point, we need to disable clock
+ * gating for the panel power sequencer or it will fail to
+ * start up when no ports are active.
*/
- if (HAS_PCH_SPLIT(dev)) {
- uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
+ I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
- if (IS_GEN5(dev)) {
- /* Required for FBC */
- dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
- DPFCRUNIT_CLOCK_GATE_DISABLE |
- DPFDUNIT_CLOCK_GATE_DISABLE;
- /* Required for CxSR */
- dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
-
- I915_WRITE(PCH_3DCGDIS0,
- MARIUNIT_CLOCK_GATE_DISABLE |
- SVSMUNIT_CLOCK_GATE_DISABLE);
- I915_WRITE(PCH_3DCGDIS1,
- VFMUNIT_CLOCK_GATE_DISABLE);
- }
+ I915_WRITE(ILK_DISPLAY_CHICKEN2,
+ I915_READ(ILK_DISPLAY_CHICKEN2) |
+ ILK_ELPIN_409_SELECT);
- I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
+ I915_WRITE(WM3_LP_ILK, 0);
+ I915_WRITE(WM2_LP_ILK, 0);
+ I915_WRITE(WM1_LP_ILK, 0);
- /*
- * On Ibex Peak and Cougar Point, we need to disable clock
- * gating for the panel power sequencer or it will fail to
- * start up when no ports are active.
- */
- I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
+ /*
+ * According to the spec the following bits should be
+ * set in order to enable memory self-refresh and fbc:
+ * The bit21 and bit22 of 0x42000
+ * The bit21 and bit22 of 0x42004
+ * The bit5 and bit7 of 0x42020
+ * The bit14 of 0x70180
+ * The bit14 of 0x71180
+ */
+ I915_WRITE(ILK_DISPLAY_CHICKEN1,
+ I915_READ(ILK_DISPLAY_CHICKEN1) |
+ ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
+ I915_WRITE(ILK_DISPLAY_CHICKEN2,
+ I915_READ(ILK_DISPLAY_CHICKEN2) |
+ ILK_DPARB_GATE | ILK_VSDPFD_FULL);
+ I915_WRITE(ILK_DSPCLK_GATE,
+ I915_READ(ILK_DSPCLK_GATE) |
+ ILK_DPARB_CLK_GATE |
+ ILK_DPFD_CLK_GATE);
- /*
- * According to the spec the following bits should be set in
- * order to enable memory self-refresh
- * The bit 22/21 of 0x42004
- * The bit 5 of 0x42020
- * The bit 15 of 0x45000
- */
- if (IS_GEN5(dev)) {
- I915_WRITE(ILK_DISPLAY_CHICKEN2,
- (I915_READ(ILK_DISPLAY_CHICKEN2) |
- ILK_DPARB_GATE | ILK_VSDPFD_FULL));
- I915_WRITE(ILK_DSPCLK_GATE,
- (I915_READ(ILK_DSPCLK_GATE) |
- ILK_DPARB_CLK_GATE));
- I915_WRITE(DISP_ARB_CTL,
- (I915_READ(DISP_ARB_CTL) |
- DISP_FBC_WM_DIS));
- I915_WRITE(WM3_LP_ILK, 0);
- I915_WRITE(WM2_LP_ILK, 0);
- I915_WRITE(WM1_LP_ILK, 0);
- }
- /*
- * Based on the document from hardware guys the following bits
- * should be set unconditionally in order to enable FBC.
- * The bit 22 of 0x42000
- * The bit 22 of 0x42004
- * The bit 7,8,9 of 0x42020.
- */
- if (IS_IRONLAKE_M(dev)) {
- I915_WRITE(ILK_DISPLAY_CHICKEN1,
- I915_READ(ILK_DISPLAY_CHICKEN1) |
- ILK_FBCQ_DIS);
- I915_WRITE(ILK_DISPLAY_CHICKEN2,
- I915_READ(ILK_DISPLAY_CHICKEN2) |
- ILK_DPARB_GATE);
- I915_WRITE(ILK_DSPCLK_GATE,
- I915_READ(ILK_DSPCLK_GATE) |
- ILK_DPFC_DIS1 |
- ILK_DPFC_DIS2 |
- ILK_CLK_FBC);
- }
+ for_each_pipe(pipe)
+ I915_WRITE(DSPCNTR(pipe),
+ I915_READ(DSPCNTR(pipe)) |
+ DISPPLANE_TRICKLE_FEED_DISABLE);
+}
- I915_WRITE(ILK_DISPLAY_CHICKEN2,
- I915_READ(ILK_DISPLAY_CHICKEN2) |
- ILK_ELPIN_409_SELECT);
+static void g4x_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ uint32_t dspclk_gate;
- if (IS_GEN5(dev)) {
- I915_WRITE(_3D_CHICKEN2,
- _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
- _3D_CHICKEN2_WM_READ_PIPELINED);
- }
+ I915_WRITE(RENCLK_GATE_D1, 0);
+ I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
+ GS_UNIT_CLOCK_GATE_DISABLE |
+ CL_UNIT_CLOCK_GATE_DISABLE);
+ I915_WRITE(RAMCLK_GATE_D, 0);
+ dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
+ OVRUNIT_CLOCK_GATE_DISABLE |
+ OVCUNIT_CLOCK_GATE_DISABLE;
+ if (IS_GM45(dev))
+ dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
+ I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
+}
- if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
- I915_WRITE(WM3_LP_ILK, 0);
- I915_WRITE(WM2_LP_ILK, 0);
- I915_WRITE(WM1_LP_ILK, 0);
+static void crestline_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
- /*
- * According to the spec the following bits should be
- * set in order to enable memory self-refresh and fbc:
- * The bit21 and bit22 of 0x42000
- * The bit21 and bit22 of 0x42004
- * The bit5 and bit7 of 0x42020
- * The bit14 of 0x70180
- * The bit14 of 0x71180
- */
- I915_WRITE(ILK_DISPLAY_CHICKEN1,
- I915_READ(ILK_DISPLAY_CHICKEN1) |
- ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
- I915_WRITE(ILK_DISPLAY_CHICKEN2,
- I915_READ(ILK_DISPLAY_CHICKEN2) |
- ILK_DPARB_GATE | ILK_VSDPFD_FULL);
- I915_WRITE(ILK_DSPCLK_GATE,
- I915_READ(ILK_DSPCLK_GATE) |
- ILK_DPARB_CLK_GATE |
- ILK_DPFD_CLK_GATE);
-
- for_each_pipe(pipe)
- I915_WRITE(DSPCNTR(pipe),
- I915_READ(DSPCNTR(pipe)) |
- DISPPLANE_TRICKLE_FEED_DISABLE);
- }
- } else if (IS_G4X(dev)) {
- uint32_t dspclk_gate;
- I915_WRITE(RENCLK_GATE_D1, 0);
- I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
- GS_UNIT_CLOCK_GATE_DISABLE |
- CL_UNIT_CLOCK_GATE_DISABLE);
- I915_WRITE(RAMCLK_GATE_D, 0);
- dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
- OVRUNIT_CLOCK_GATE_DISABLE |
- OVCUNIT_CLOCK_GATE_DISABLE;
- if (IS_GM45(dev))
- dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
- I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
- } else if (IS_CRESTLINE(dev)) {
- I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
- I915_WRITE(RENCLK_GATE_D2, 0);
- I915_WRITE(DSPCLK_GATE_D, 0);
- I915_WRITE(RAMCLK_GATE_D, 0);
- I915_WRITE16(DEUC, 0);
- } else if (IS_BROADWATER(dev)) {
- I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
- I965_RCC_CLOCK_GATE_DISABLE |
- I965_RCPB_CLOCK_GATE_DISABLE |
- I965_ISC_CLOCK_GATE_DISABLE |
- I965_FBC_CLOCK_GATE_DISABLE);
- I915_WRITE(RENCLK_GATE_D2, 0);
- } else if (IS_GEN3(dev)) {
- u32 dstate = I915_READ(D_STATE);
+ I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
+ I915_WRITE(RENCLK_GATE_D2, 0);
+ I915_WRITE(DSPCLK_GATE_D, 0);
+ I915_WRITE(RAMCLK_GATE_D, 0);
+ I915_WRITE16(DEUC, 0);
+}
- dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
- DSTATE_DOT_CLOCK_GATING;
- I915_WRITE(D_STATE, dstate);
- } else if (IS_I85X(dev) || IS_I865G(dev)) {
- I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
- } else if (IS_I830(dev)) {
- I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
- }
+static void broadwater_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
+ I965_RCC_CLOCK_GATE_DISABLE |
+ I965_RCPB_CLOCK_GATE_DISABLE |
+ I965_ISC_CLOCK_GATE_DISABLE |
+ I965_FBC_CLOCK_GATE_DISABLE);
+ I915_WRITE(RENCLK_GATE_D2, 0);
+}
+
+static void gen3_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 dstate = I915_READ(D_STATE);
+
+ dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
+ DSTATE_DOT_CLOCK_GATING;
+ I915_WRITE(D_STATE, dstate);
+}
+
+static void i85x_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
+}
+
+static void i830_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
}
static void ironlake_teardown_rc6(struct drm_device *dev)
@@ -7477,6 +7510,7 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.update_wm = NULL;
}
dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
+ dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
} else if (IS_GEN6(dev)) {
if (SNB_READ_WM0_LATENCY()) {
dev_priv->display.update_wm = sandybridge_update_wm;
@@ -7486,6 +7520,7 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.update_wm = NULL;
}
dev_priv->display.fdi_link_train = gen6_fdi_link_train;
+ dev_priv->display.init_clock_gating = gen6_init_clock_gating;
} else if (IS_IVYBRIDGE(dev)) {
/* FIXME: detect B0+ stepping and use auto training */
if (0)
@@ -7499,6 +7534,8 @@ static void intel_init_display(struct drm_device *dev)
"Disable CxSR\n");
dev_priv->display.update_wm = NULL;
}
+ dev_priv->display.init_clock_gating = gen6_init_clock_gating;
+
} else
dev_priv->display.update_wm = NULL;
} else if (IS_PINEVIEW(dev)) {
@@ -7516,18 +7553,30 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.update_wm = NULL;
} else
dev_priv->display.update_wm = pineview_update_wm;
- } else if (IS_G4X(dev))
+ } else if (IS_G4X(dev)) {
dev_priv->display.update_wm = g4x_update_wm;
- else if (IS_GEN4(dev))
+ dev_priv->display.init_clock_gating = g4x_init_clock_gating;
+ } else if (IS_GEN4(dev)) {
dev_priv->display.update_wm = i965_update_wm;
- else if (IS_GEN3(dev)) {
+ if (IS_CRESTLINE(dev))
+ dev_priv->display.init_clock_gating = crestline_init_clock_gating;
+ else if (IS_BROADWATER(dev))
+ dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
+ } else if (IS_GEN3(dev)) {
dev_priv->display.update_wm = i9xx_update_wm;
dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
+ dev_priv->display.init_clock_gating = gen3_init_clock_gating;
+ } else if (IS_I865G(dev)) {
+ dev_priv->display.update_wm = i830_update_wm;
+ dev_priv->display.init_clock_gating = i85x_init_clock_gating;
+ dev_priv->display.get_fifo_size = i830_get_fifo_size;
} else if (IS_I85X(dev)) {
dev_priv->display.update_wm = i9xx_update_wm;
dev_priv->display.get_fifo_size = i85x_get_fifo_size;
+ dev_priv->display.init_clock_gating = i85x_init_clock_gating;
} else {
dev_priv->display.update_wm = i830_update_wm;
+ dev_priv->display.init_clock_gating = i830_init_clock_gating;
if (IS_845G(dev))
dev_priv->display.get_fifo_size = i845_get_fifo_size;
else
@@ -7655,7 +7704,7 @@ void intel_modeset_init(struct drm_device *dev)
intel_setup_outputs(dev);
- intel_enable_clock_gating(dev);
+ dev_priv->display.init_clock_gating(dev);
/* Just disable it once at startup */
i915_disable_vga(dev);
--
1.7.4.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* Re: [PATCH 09/19] drm/i915: automatic FDI training support for Ivy Bridge
2011-04-28 22:12 ` [PATCH 09/19] drm/i915: automatic FDI training support " Jesse Barnes
@ 2011-04-28 22:20 ` Jesse Barnes
2011-04-28 22:43 ` Keith Packard
1 sibling, 0 replies; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 22:20 UTC (permalink / raw)
Cc: intel-gfx
On Thu, 28 Apr 2011 15:12:55 -0700
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Ivy Bridge supports auto-training on the CPU side, so add a separate
> training function to handle it.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> drivers/gpu/drm/i915/intel_display.c | 82 +++++++++++++++++++++++++++++++--
> 2 files changed, 79 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index aba3fe5..03c99ed 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3116,6 +3116,8 @@
> #define FDI_LINK_TRAIN_AUTO (1<<10)
> #define FDI_SCRAMBLING_ENABLE (0<<7)
> #define FDI_SCRAMBLING_DISABLE (1<<7)
> +/* Ivybridge */
> +#define FDI_AUTO_TRAIN_DONE (1<<1)
>
> /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
> #define _FDI_RXA_CTL 0xf000c
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ab840a6..3396043 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2411,6 +2411,75 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
> DRM_DEBUG_KMS("FDI train done.\n");
> }
>
> +/* On Ivybridge we can use auto training */
> +static void ivb_fdi_link_train(struct drm_crtc *crtc)
> +{
> + struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + unsigned long start = jiffies_to_msecs(jiffies);
> + int pipe = intel_crtc->pipe;
> + u32 reg, temp, i, j;
> +
> + /* Can't pair IVB & Ibex Peak */
> + BUG_ON(HAS_PCH_IBX(dev));
> +
> + reg = FDI_TX_CTL(pipe);
> + temp = I915_READ(reg);
> + temp &= ~(7 << 19);
> + temp |= (intel_crtc->fdi_lanes - 1) << 19;
> + temp &= ~FDI_LINK_TRAIN_NONE;
> + I915_WRITE(reg, temp);
> +
> + /* Enable auto training on TX and RX */
> + for (i = 0; i < ARRAY_SIZE(snb_b_fdi_train_param); i++) {
> + /* Try each vswing/pre-emphasis pair twice */
> + for (j = 0; j < 2; j++) {
> + reg = FDI_TX_CTL(pipe);
> + temp = I915_READ(reg);
> + temp |= FDI_AUTO_TRAINING;
> + temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
> + temp |= snb_b_fdi_train_param[i];
> + I915_WRITE(reg, temp | FDI_TX_ENABLE);
> +
> + reg = FDI_RX_CTL(pipe);
> + temp = I915_READ(reg);
> + I915_WRITE(reg, temp | FDI_RX_ENABLE);
> + POSTING_READ(reg);
> +
> + udelay(5);
> +
> + reg = FDI_TX_CTL(pipe);
> + temp = I915_READ(reg);
> + if ((temp & FDI_AUTO_TRAIN_DONE) ||
> + (I915_READ(reg) & FDI_AUTO_TRAIN_DONE)) {
> + DRM_DEBUG_KMS("FDI auto train complete in %d ms\n",
> + jiffies_to_msecs(jiffies) - start);
> + goto done;
> + }
> +
> + reg = FDI_TX_CTL(pipe);
> + temp = I915_READ(reg);
> + I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
> +
> + reg = FDI_RX_CTL(pipe);
> + temp = I915_READ(reg);
> + I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
> + POSTING_READ(reg);
> + udelay(31); /* wait idle time before retrying */
> + }
> + }
> + DRM_ERROR("FDI auto train failed\n");
> + return;
> +
> +done:
> + reg = FDI_RX_CTL(pipe);
> + temp = I915_READ(reg);
> + temp |= FDI_FS_ERR_CORRECT_ENABLE | FDI_FE_ERR_CORRECT_ENABLE;
> + I915_WRITE(reg, temp);
> + POSTING_READ(reg);
> +}
> +
> static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
> {
> struct drm_device *dev = crtc->dev;
> @@ -2452,7 +2521,7 @@ static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
> }
> }
>
> -static void ironlake_fdi_disable(struct drm_crtc *crtc)
> +static void ironlake_fdi_pll_disable(struct drm_crtc *crtc)
> {
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -2674,9 +2743,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> is_pch_port = intel_crtc_driving_pch(crtc);
>
> if (is_pch_port)
> - ironlake_fdi_enable(crtc);
> + ironlake_fdi_pll_enable(crtc);
> else
> - ironlake_fdi_disable(crtc);
> + ironlake_fdi_pll_disable(crtc);
>
> /* Enable panel fitting for LVDS */
> if (dev_priv->pch_pf_size &&
> @@ -2729,7 +2798,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
> I915_WRITE(PF_CTL(pipe), 0);
> I915_WRITE(PF_WIN_SZ(pipe), 0);
>
> - ironlake_fdi_disable(crtc);
> + ironlake_fdi_pll_disable(crtc);
arg, screwed up the rebase here; the fdi_pll name change needs to stay
together.
--
Jesse Barnes, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 01/19] drm/i915: make FDI training a display function
2011-04-28 22:12 ` [PATCH 01/19] drm/i915: make FDI training a display function Jesse Barnes
@ 2011-04-28 22:33 ` Keith Packard
0 siblings, 0 replies; 46+ messages in thread
From: Keith Packard @ 2011-04-28 22:33 UTC (permalink / raw)
To: Jesse Barnes, intel-gfx
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On Thu, 28 Apr 2011 15:12:47 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Rather than branching in ironlake_pch_enable, add a new train_fdi
> function to the display function pointer struct and use it instead.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
--
keith.packard@intel.com
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^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 02/19] drm/i915: split irq handling into per-chipset functions
2011-04-28 22:12 ` [PATCH 02/19] drm/i915: split irq handling into per-chipset functions Jesse Barnes
@ 2011-04-28 22:37 ` Keith Packard
2011-05-18 11:51 ` [SNB: Regression] " Ted Phelps
1 sibling, 0 replies; 46+ messages in thread
From: Keith Packard @ 2011-04-28 22:37 UTC (permalink / raw)
To: Jesse Barnes, intel-gfx
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On Thu, 28 Apr 2011 15:12:48 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Set the IRQ handling functions in driver load so they'll just be used
> directly, rather than branching over most of the code in the chipset
> functions.
Reviewed-by: Keith Packard <keithp@keithp.com>
--
keith.packard@intel.com
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^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 03/19] drm/i915: split enable/disable vblank code into chipset specific functions
2011-04-28 22:12 ` [PATCH 03/19] drm/i915: split enable/disable vblank code into chipset specific functions Jesse Barnes
@ 2011-04-28 22:39 ` Keith Packard
0 siblings, 0 replies; 46+ messages in thread
From: Keith Packard @ 2011-04-28 22:39 UTC (permalink / raw)
To: Jesse Barnes, intel-gfx
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On Thu, 28 Apr 2011 15:12:49 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> This makes the Ironlake+ code trivial and generally simplifies things.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
--
keith.packard@intel.com
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^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 04/19] drm/i915: add IS_GEN7 macro to cover Ivy Bridge and later
2011-04-28 22:12 ` [PATCH 04/19] drm/i915: add IS_GEN7 macro to cover Ivy Bridge and later Jesse Barnes
@ 2011-04-28 22:40 ` Keith Packard
0 siblings, 0 replies; 46+ messages in thread
From: Keith Packard @ 2011-04-28 22:40 UTC (permalink / raw)
To: Jesse Barnes, intel-gfx
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On Thu, 28 Apr 2011 15:12:50 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Note: IS_GEN* are for render related checks. Display and other checks
> should use IS_MOBILE, IS_$CHIPSET or test for specific features.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
--
keith.packard@intel.com
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^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 05/19] drm/i915: add IS_IVYBRIDGE macro for checks
2011-04-28 22:12 ` [PATCH 05/19] drm/i915: add IS_IVYBRIDGE macro for checks Jesse Barnes
@ 2011-04-28 22:41 ` Keith Packard
0 siblings, 0 replies; 46+ messages in thread
From: Keith Packard @ 2011-04-28 22:41 UTC (permalink / raw)
To: Jesse Barnes, intel-gfx
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On Thu, 28 Apr 2011 15:12:51 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
I don't see a patch in this series that sets this value from the PCI
ids. Is that still pending?
--
keith.packard@intel.com
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^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 06/19] drm/i915: Ivy Bridge has split display and pipe control
2011-04-28 22:12 ` [PATCH 06/19] drm/i915: Ivy Bridge has split display and pipe control Jesse Barnes
@ 2011-04-28 22:41 ` Keith Packard
0 siblings, 0 replies; 46+ messages in thread
From: Keith Packard @ 2011-04-28 22:41 UTC (permalink / raw)
To: Jesse Barnes, intel-gfx
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On Thu, 28 Apr 2011 15:12:52 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Ivy Bridge has a similar split display controller to Sandy Bridge, so
> use HAS_PCH_SPLIT. And gen7 also has the pipe control instruction, so
> use HAS_PIPE_CONTROL as well.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
--
keith.packard@intel.com
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^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 07/19] drm/i915: add swizzle/tiling support for Ivy Bridge
2011-04-28 22:12 ` [PATCH 07/19] drm/i915: add swizzle/tiling support for Ivy Bridge Jesse Barnes
@ 2011-04-28 22:42 ` Keith Packard
2011-04-28 23:06 ` Jesse Barnes
0 siblings, 1 reply; 46+ messages in thread
From: Keith Packard @ 2011-04-28 22:42 UTC (permalink / raw)
To: Jesse Barnes, intel-gfx
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On Thu, 28 Apr 2011 15:12:53 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Treat it like Ironlake and Sandy Bridge.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Should use gen >= 5?
--
keith.packard@intel.com
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^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 08/19] drm/i915: manual FDI training for Ivy Bridge
2011-04-28 22:12 ` [PATCH 08/19] drm/i915: manual FDI training " Jesse Barnes
@ 2011-04-28 22:43 ` Keith Packard
2011-04-28 23:06 ` Jesse Barnes
0 siblings, 1 reply; 46+ messages in thread
From: Keith Packard @ 2011-04-28 22:43 UTC (permalink / raw)
To: Jesse Barnes, intel-gfx
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On Thu, 28 Apr 2011 15:12:54 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> + if (IS_GEN6(dev)) {
> + temp &= ~FDI_LINK_TRAIN_NONE;
> + temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
> + } else if (IS_IVYBRIDGE(dev)) {
> + temp &= ~FDI_LINK_TRAIN_NONE_IVB;
> + temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
> + }
This seems inconsistent using IS_GEN6 for SNB and IS_IVYBRIDGE for IVB?
--
keith.packard@intel.com
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^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 09/19] drm/i915: automatic FDI training support for Ivy Bridge
2011-04-28 22:12 ` [PATCH 09/19] drm/i915: automatic FDI training support " Jesse Barnes
2011-04-28 22:20 ` Jesse Barnes
@ 2011-04-28 22:43 ` Keith Packard
1 sibling, 0 replies; 46+ messages in thread
From: Keith Packard @ 2011-04-28 22:43 UTC (permalink / raw)
To: Jesse Barnes, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 308 bytes --]
On Thu, 28 Apr 2011 15:12:55 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Ivy Bridge supports auto-training on the CPU side, so add a separate
> training function to handle it.
Let's leave this out of the kernel until we have hardware that actually
uses it.
--
keith.packard@intel.com
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^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 10/19] drm/i915: treat Ivy Bridge watermarks like Sandy Bridge
2011-04-28 22:12 ` [PATCH 10/19] drm/i915: treat Ivy Bridge watermarks like Sandy Bridge Jesse Barnes
@ 2011-04-28 22:46 ` Keith Packard
2011-04-28 23:06 ` Jesse Barnes
0 siblings, 1 reply; 46+ messages in thread
From: Keith Packard @ 2011-04-28 22:46 UTC (permalink / raw)
To: Jesse Barnes, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 262 bytes --]
On Thu, 28 Apr 2011 15:12:56 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> - if (IS_GEN6(dev)) {
> + if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
IS_GEN6 for SNB and IS_IVYBRIDGE for IVB? More consistency, please.
--
keith.packard@intel.com
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^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 11/19] drm/i915: interrupt & vblank support for Ivy Bridge
2011-04-28 22:12 ` [PATCH 11/19] drm/i915: interrupt & vblank support for Ivy Bridge Jesse Barnes
@ 2011-04-28 22:47 ` Keith Packard
2011-06-28 10:55 ` Chris Wilson
1 sibling, 0 replies; 46+ messages in thread
From: Keith Packard @ 2011-04-28 22:47 UTC (permalink / raw)
To: Jesse Barnes, intel-gfx
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On Thu, 28 Apr 2011 15:12:57 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> - if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
> + if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
IS_G4X || gen >= 5 ?
Otherwise, this looks good (seems like it's just bit shuffling from SNB, right?)
--
keith.packard@intel.com
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^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 13/19] drm/i915: untested DP support for Ivy Bridge
2011-04-28 22:12 ` [PATCH 13/19] drm/i915: untested DP " Jesse Barnes
@ 2011-04-28 22:47 ` Keith Packard
2011-05-01 16:26 ` Chris Wilson
1 sibling, 0 replies; 46+ messages in thread
From: Keith Packard @ 2011-04-28 22:47 UTC (permalink / raw)
To: Jesse Barnes, intel-gfx
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On Thu, 28 Apr 2011 15:12:59 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Treat it like Sandy Bridge in a few places.
gen >= 6?
--
keith.packard@intel.com
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^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 14/19] drm/i915: ring support for Ivy Bridge
2011-04-28 22:13 ` [PATCH 14/19] drm/i915: ring " Jesse Barnes
@ 2011-04-28 22:48 ` Keith Packard
0 siblings, 0 replies; 46+ messages in thread
From: Keith Packard @ 2011-04-28 22:48 UTC (permalink / raw)
To: Jesse Barnes, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 175 bytes --]
On Thu, 28 Apr 2011 15:13:00 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Use Sandy Bridge paths in a few places.
gen >= 6 ?
--
keith.packard@intel.com
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^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 17/19] drm/i915: add Ivy Bridge PCI IDs and driver feature structs
2011-04-28 22:13 ` [PATCH 17/19] drm/i915: add Ivy Bridge PCI IDs and driver feature structs Jesse Barnes
@ 2011-04-28 22:49 ` Keith Packard
0 siblings, 0 replies; 46+ messages in thread
From: Keith Packard @ 2011-04-28 22:49 UTC (permalink / raw)
To: Jesse Barnes, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 328 bytes --]
On Thu, 28 Apr 2011 15:13:03 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> There are several variants, set feature bits appropriately for both
> mobile and desktop parts.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
--
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^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 18/19] drm/i915: set IBX pch type explicitly
2011-04-28 22:13 ` [PATCH 18/19] drm/i915: set IBX pch type explicitly Jesse Barnes
@ 2011-04-28 22:49 ` Keith Packard
0 siblings, 0 replies; 46+ messages in thread
From: Keith Packard @ 2011-04-28 22:49 UTC (permalink / raw)
To: Jesse Barnes, intel-gfx
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On Thu, 28 Apr 2011 15:13:04 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> This is a little less confusing than relying on the implicit zeroing of
> the dev_priv.
Thanks.
Reviewed-by: Keith Packard <keithp@keithp.com>
--
keith.packard@intel.com
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^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 08/19] drm/i915: manual FDI training for Ivy Bridge
2011-04-28 22:43 ` Keith Packard
@ 2011-04-28 23:06 ` Jesse Barnes
0 siblings, 0 replies; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 23:06 UTC (permalink / raw)
To: Keith Packard; +Cc: intel-gfx
On Thu, 28 Apr 2011 15:43:10 -0700
Keith Packard <keithp@keithp.com> wrote:
> On Thu, 28 Apr 2011 15:12:54 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
>
> > + if (IS_GEN6(dev)) {
> > + temp &= ~FDI_LINK_TRAIN_NONE;
> > + temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
> > + } else if (IS_IVYBRIDGE(dev)) {
> > + temp &= ~FDI_LINK_TRAIN_NONE_IVB;
> > + temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
> > + }
>
> This seems inconsistent using IS_GEN6 for SNB and IS_IVYBRIDGE for IVB?
Yes, there are several IS_GEN checks that I'd argue are wrong, I can
clean them up in a subsequent.
--
Jesse Barnes, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 07/19] drm/i915: add swizzle/tiling support for Ivy Bridge
2011-04-28 22:42 ` Keith Packard
@ 2011-04-28 23:06 ` Jesse Barnes
0 siblings, 0 replies; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 23:06 UTC (permalink / raw)
To: Keith Packard; +Cc: intel-gfx
On Thu, 28 Apr 2011 15:42:13 -0700
Keith Packard <keithp@keithp.com> wrote:
> On Thu, 28 Apr 2011 15:12:53 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> > Treat it like Ironlake and Sandy Bridge.
> >
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>
> Should use gen >= 5?
Yeah, probably better.
--
Jesse Barnes, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 10/19] drm/i915: treat Ivy Bridge watermarks like Sandy Bridge
2011-04-28 22:46 ` Keith Packard
@ 2011-04-28 23:06 ` Jesse Barnes
0 siblings, 0 replies; 46+ messages in thread
From: Jesse Barnes @ 2011-04-28 23:06 UTC (permalink / raw)
To: Keith Packard; +Cc: intel-gfx
On Thu, 28 Apr 2011 15:46:06 -0700
Keith Packard <keithp@keithp.com> wrote:
> On Thu, 28 Apr 2011 15:12:56 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
>
> > - if (IS_GEN6(dev)) {
> > + if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
>
> IS_GEN6 for SNB and IS_IVYBRIDGE for IVB? More consistency, please.
>
See earlier mail; GEN6 is the wrong one to use here imo.
--
Jesse Barnes, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 13/19] drm/i915: untested DP support for Ivy Bridge
2011-04-28 22:12 ` [PATCH 13/19] drm/i915: untested DP " Jesse Barnes
2011-04-28 22:47 ` Keith Packard
@ 2011-05-01 16:26 ` Chris Wilson
2011-05-02 0:43 ` Keith Packard
2011-05-02 20:07 ` Jesse Barnes
1 sibling, 2 replies; 46+ messages in thread
From: Chris Wilson @ 2011-05-01 16:26 UTC (permalink / raw)
To: Jesse Barnes, intel-gfx
On Thu, 28 Apr 2011 15:12:59 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Treat it like Sandy Bridge in a few places.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 6 +++---
> 1 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 0daefca..1d0eccd 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -312,7 +312,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
> else
> aux_clock_divider = intel_hrawclk(dev) / 2;
>
> - if (IS_GEN6(dev))
> + if (IS_GEN6(dev) || IS_GEN7(dev))
Shouldn't these be IS_SANDYBRIDGE(dev) || IS_IVYBRIDGE(dev) following the
convention that info->gen is reserved for the render engine.
Perhaps if you do the s/IS_GEN6/IS_SNADYBRIDGE/ fixes first it will become
much clearer? :)
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 13/19] drm/i915: untested DP support for Ivy Bridge
2011-05-01 16:26 ` Chris Wilson
@ 2011-05-02 0:43 ` Keith Packard
2011-05-02 20:07 ` Jesse Barnes
1 sibling, 0 replies; 46+ messages in thread
From: Keith Packard @ 2011-05-02 0:43 UTC (permalink / raw)
To: Chris Wilson, Jesse Barnes, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 373 bytes --]
On Sun, 01 May 2011 17:26:11 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> Perhaps if you do the s/IS_GEN6/IS_SNADYBRIDGE/ fixes first it will become
> much clearer? :)
The only question is one of regressions; getting the cleanups tested in
isolation from the IVB patches. That seems do-able for the 2.6.40 merge
window.
--
keith.packard@intel.com
[-- Attachment #1.2: Type: application/pgp-signature, Size: 189 bytes --]
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 13/19] drm/i915: untested DP support for Ivy Bridge
2011-05-01 16:26 ` Chris Wilson
2011-05-02 0:43 ` Keith Packard
@ 2011-05-02 20:07 ` Jesse Barnes
1 sibling, 0 replies; 46+ messages in thread
From: Jesse Barnes @ 2011-05-02 20:07 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Sun, 01 May 2011 17:26:11 +0100
Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Thu, 28 Apr 2011 15:12:59 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> > Treat it like Sandy Bridge in a few places.
> >
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 6 +++---
> > 1 files changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 0daefca..1d0eccd 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -312,7 +312,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
> > else
> > aux_clock_divider = intel_hrawclk(dev) / 2;
> >
> > - if (IS_GEN6(dev))
> > + if (IS_GEN6(dev) || IS_GEN7(dev))
>
> Shouldn't these be IS_SANDYBRIDGE(dev) || IS_IVYBRIDGE(dev) following the
> convention that info->gen is reserved for the render engine.
>
> Perhaps if you do the s/IS_GEN6/IS_SNADYBRIDGE/ fixes first it will become
> much clearer? :)
Yeah, sorry I violated my own rule, will fix (this one can be delayed
until I can test it anyway).
--
Jesse Barnes, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 46+ messages in thread
* [SNB: Regression] Re: [PATCH 02/19] drm/i915: split irq handling into per-chipset functions
2011-04-28 22:12 ` [PATCH 02/19] drm/i915: split irq handling into per-chipset functions Jesse Barnes
2011-04-28 22:37 ` Keith Packard
@ 2011-05-18 11:51 ` Ted Phelps
2011-05-18 15:58 ` Jesse Barnes
1 sibling, 1 reply; 46+ messages in thread
From: Ted Phelps @ 2011-05-18 11:51 UTC (permalink / raw)
To: Jesse Barnes, intel-gfx
Jesse Barnes writes:
> Set the IRQ handling functions in driver load so they'll just be used
> directly, rather than branching over most of the code in the chipset
> functions.
I'm seeing a kernel panic on my SNB i7-2600K with keithp/drm-intel-next
(61e499b). I've bisected to 4697995 -- the commit mentioned in the
subject.
My photo of the stack trace is a bit blurry, but below is my attempted
transcription of the the stack. I can't read the addresses at all;
please let me know if you'd like me to obtain a better dump.
Call Trace:
<IRQ>
queue_work_op+0x1d/0x30
queue_work+0x35/0x50
ironlake_irq_handler+0xec9/0xfa0 [i915]
handle_irq_event_percpu+0x75/0x260
handle_edge_irq+0x6f/0x110
handle_irq+0x1d/0x30
do_IRQ+0x58/0xe9
common_interrupt+0x13/0x13
... more stuff that I assume is irrelevent ...
Please let me know if I can provide additional useful information.
Thanks,
-Ted
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [SNB: Regression] Re: [PATCH 02/19] drm/i915: split irq handling into per-chipset functions
2011-05-18 11:51 ` [SNB: Regression] " Ted Phelps
@ 2011-05-18 15:58 ` Jesse Barnes
2011-05-19 12:59 ` Ted Phelps
0 siblings, 1 reply; 46+ messages in thread
From: Jesse Barnes @ 2011-05-18 15:58 UTC (permalink / raw)
To: Ted Phelps; +Cc: intel-gfx
On Wed, 18 May 2011 21:51:23 +1000
Ted Phelps <phelps@gnusto.com> wrote:
>
> Jesse Barnes writes:
> > Set the IRQ handling functions in driver load so they'll just be used
> > directly, rather than branching over most of the code in the chipset
> > functions.
>
> I'm seeing a kernel panic on my SNB i7-2600K with keithp/drm-intel-next
> (61e499b). I've bisected to 4697995 -- the commit mentioned in the
> subject.
>
> My photo of the stack trace is a bit blurry, but below is my attempted
> transcription of the the stack. I can't read the addresses at all;
> please let me know if you'd like me to obtain a better dump.
>
> Call Trace:
> <IRQ>
> queue_work_op+0x1d/0x30
> queue_work+0x35/0x50
> ironlake_irq_handler+0xec9/0xfa0 [i915]
> handle_irq_event_percpu+0x75/0x260
> handle_edge_irq+0x6f/0x110
> handle_irq+0x1d/0x30
> do_IRQ+0x58/0xe9
> common_interrupt+0x13/0x13
> ... more stuff that I assume is irrelevent ...
>
> Please let me know if I can provide additional useful information.
Please try this patch.
--
Jesse Barnes, Intel Open Source Technology Center
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 349a03e..e0aed1e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1736,6 +1736,7 @@ void ironlake_irq_preinstall(struct drm_device *dev)
INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
INIT_WORK(&dev_priv->error_work, i915_error_work_func);
+ INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
I915_WRITE(HWSTAM, 0xeffe);
^ permalink raw reply related [flat|nested] 46+ messages in thread
* Re: [SNB: Regression] Re: [PATCH 02/19] drm/i915: split irq handling into per-chipset functions
2011-05-18 15:58 ` Jesse Barnes
@ 2011-05-19 12:59 ` Ted Phelps
0 siblings, 0 replies; 46+ messages in thread
From: Ted Phelps @ 2011-05-19 12:59 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
Jesse Barnes writes:
> Please try this patch.
Works a treat, as does the one that Keith merged into drm-intel-next.
Thanks for the speedy patch!
-Ted
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 11/19] drm/i915: interrupt & vblank support for Ivy Bridge
2011-04-28 22:12 ` [PATCH 11/19] drm/i915: interrupt & vblank support for Ivy Bridge Jesse Barnes
2011-04-28 22:47 ` Keith Packard
@ 2011-06-28 10:55 ` Chris Wilson
1 sibling, 0 replies; 46+ messages in thread
From: Chris Wilson @ 2011-06-28 10:55 UTC (permalink / raw)
To: Jesse Barnes, intel-gfx
On Thu, 28 Apr 2011 15:12:57 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Add new interrupt handling functions for Ivy Bridge.
There's a slight discrepancy here:
> + if (IS_IVYBRIDGE(dev)) {
> + /* Share pre & uninstall handlers with ILK/SNB */
> + dev->driver->irq_handler = ivybridge_irq_handler;
> + dev->driver->irq_preinstall = ironlake_irq_preinstall;
> + dev->driver->irq_postinstall = ivybridge_irq_postinstall;
> + dev->driver->irq_uninstall = ironlake_irq_uninstall;
> + dev->driver->enable_vblank = ivybridge_enable_vblank;
> + dev->driver->disable_vblank = ivybridge_disable_vblank;
and later you say:
> +extern irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS);
> +extern void ivybridge_irq_preinstall(struct drm_device *dev);
> +extern int ivybridge_irq_postinstall(struct drm_device *dev);
> +extern void ivybridge_irq_uninstall(struct drm_device *dev);
Can you please tidy up this latter bit of copy'n'paste, it scared me
whilst running git grep ;-)
I'd like to move those declarations out of the header, make the functions
static and just export a single function from i915_irq.c to i915_dma.c that
set the irq_handlers on the driver vfunc table and so prevent the
possibility of any further confusion like Konstantin pointed out.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 46+ messages in thread
end of thread, other threads:[~2011-06-28 10:55 UTC | newest]
Thread overview: 46+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-04-28 22:12 [RFC] Ivy Bridge supprt v2 Jesse Barnes
2011-04-28 22:12 ` [PATCH 01/19] drm/i915: make FDI training a display function Jesse Barnes
2011-04-28 22:33 ` Keith Packard
2011-04-28 22:12 ` [PATCH 02/19] drm/i915: split irq handling into per-chipset functions Jesse Barnes
2011-04-28 22:37 ` Keith Packard
2011-05-18 11:51 ` [SNB: Regression] " Ted Phelps
2011-05-18 15:58 ` Jesse Barnes
2011-05-19 12:59 ` Ted Phelps
2011-04-28 22:12 ` [PATCH 03/19] drm/i915: split enable/disable vblank code into chipset specific functions Jesse Barnes
2011-04-28 22:39 ` Keith Packard
2011-04-28 22:12 ` [PATCH 04/19] drm/i915: add IS_GEN7 macro to cover Ivy Bridge and later Jesse Barnes
2011-04-28 22:40 ` Keith Packard
2011-04-28 22:12 ` [PATCH 05/19] drm/i915: add IS_IVYBRIDGE macro for checks Jesse Barnes
2011-04-28 22:41 ` Keith Packard
2011-04-28 22:12 ` [PATCH 06/19] drm/i915: Ivy Bridge has split display and pipe control Jesse Barnes
2011-04-28 22:41 ` Keith Packard
2011-04-28 22:12 ` [PATCH 07/19] drm/i915: add swizzle/tiling support for Ivy Bridge Jesse Barnes
2011-04-28 22:42 ` Keith Packard
2011-04-28 23:06 ` Jesse Barnes
2011-04-28 22:12 ` [PATCH 08/19] drm/i915: manual FDI training " Jesse Barnes
2011-04-28 22:43 ` Keith Packard
2011-04-28 23:06 ` Jesse Barnes
2011-04-28 22:12 ` [PATCH 09/19] drm/i915: automatic FDI training support " Jesse Barnes
2011-04-28 22:20 ` Jesse Barnes
2011-04-28 22:43 ` Keith Packard
2011-04-28 22:12 ` [PATCH 10/19] drm/i915: treat Ivy Bridge watermarks like Sandy Bridge Jesse Barnes
2011-04-28 22:46 ` Keith Packard
2011-04-28 23:06 ` Jesse Barnes
2011-04-28 22:12 ` [PATCH 11/19] drm/i915: interrupt & vblank support for Ivy Bridge Jesse Barnes
2011-04-28 22:47 ` Keith Packard
2011-06-28 10:55 ` Chris Wilson
2011-04-28 22:12 ` [PATCH 12/19] drm/i915: page flip " Jesse Barnes
2011-04-28 22:12 ` [PATCH 13/19] drm/i915: untested DP " Jesse Barnes
2011-04-28 22:47 ` Keith Packard
2011-05-01 16:26 ` Chris Wilson
2011-05-02 0:43 ` Keith Packard
2011-05-02 20:07 ` Jesse Barnes
2011-04-28 22:13 ` [PATCH 14/19] drm/i915: ring " Jesse Barnes
2011-04-28 22:48 ` Keith Packard
2011-04-28 22:13 ` [PATCH 15/19] agp/intel: add Ivy Bridge support Jesse Barnes
2011-04-28 22:13 ` [PATCH 16/19] drm/i915: add PantherPoint PCH ID Jesse Barnes
2011-04-28 22:13 ` [PATCH 17/19] drm/i915: add Ivy Bridge PCI IDs and driver feature structs Jesse Barnes
2011-04-28 22:49 ` Keith Packard
2011-04-28 22:13 ` [PATCH 18/19] drm/i915: set IBX pch type explicitly Jesse Barnes
2011-04-28 22:49 ` Keith Packard
2011-04-28 22:13 ` [PATCH 19/19] drm/i915: split clock gating init into per-chipset functions Jesse Barnes
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