intel-xe.lists.freedesktop.org archive mirror
 help / color / mirror / Atom feed
* [CI 1/5] drm/xe: Introduce has_atomic_enable_pte_bit device info
@ 2024-04-26  9:20 Nirmoy Das
  2024-04-26  9:20 ` [CI 2/5] drm/xe: Move vm bind bo validation to a helper function Nirmoy Das
                   ` (10 more replies)
  0 siblings, 11 replies; 12+ messages in thread
From: Nirmoy Das @ 2024-04-26  9:20 UTC (permalink / raw)
  To: intel-xe

Add has_atomic_enable_pte_bit to specify that a device
has PTE_AE bit in its PTE feild. Currently XE2 and PVC
supports this so set this for those two.

This will help consolidate setting atomic access bit in PTE
logic which is spread between multiple files.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Oak Zeng <oak.zeng@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/xe/xe_device_types.h | 2 ++
 drivers/gpu/drm/xe/xe_pci.c          | 3 +++
 drivers/gpu/drm/xe/xe_pci_types.h    | 1 +
 3 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 0f68c55ea405..7cddb00f9c35 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -281,6 +281,8 @@ struct xe_device {
 		u8 has_heci_gscfi:1;
 		/** @info.skip_guc_pc: Skip GuC based PM feature init */
 		u8 skip_guc_pc:1;
+		/** @info.has_atomic_enable_pte_bit: Device has atomic enable PTE bit */
+		u8 has_atomic_enable_pte_bit:1;
 
 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
 		struct {
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index a0cf5dd803c2..5618318e6f3a 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -146,6 +146,7 @@ static const struct xe_graphics_desc graphics_xehpc = {
 	.vram_flags = XE_VRAM_FLAGS_NEED64K,
 
 	.has_asid = 1,
+	.has_atomic_enable_pte_bit = 1,
 	.has_flat_ccs = 0,
 	.has_usm = 1,
 };
@@ -163,6 +164,7 @@ static const struct xe_graphics_desc graphics_xelpg = {
 #define XE2_GFX_FEATURES \
 	.dma_mask_size = 46, \
 	.has_asid = 1, \
+	.has_atomic_enable_pte_bit = 1, \
 	.has_flat_ccs = 1, \
 	.has_range_tlb_invalidation = 1, \
 	.has_usm = 1, \
@@ -629,6 +631,7 @@ static int xe_info_init(struct xe_device *xe,
 	xe->info.va_bits = graphics_desc->va_bits;
 	xe->info.vm_max_level = graphics_desc->vm_max_level;
 	xe->info.has_asid = graphics_desc->has_asid;
+	xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit;
 	xe->info.has_flat_ccs = graphics_desc->has_flat_ccs;
 	xe->info.has_range_tlb_invalidation = graphics_desc->has_range_tlb_invalidation;
 	xe->info.has_usm = graphics_desc->has_usm;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index b1ad12fa22d6..e1f2b4879fc2 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -25,6 +25,7 @@ struct xe_graphics_desc {
 	u8 max_remote_tiles:2;
 
 	u8 has_asid:1;
+	u8 has_atomic_enable_pte_bit:1;
 	u8 has_flat_ccs:1;
 	u8 has_range_tlb_invalidation:1;
 	u8 has_usm:1;
-- 
2.42.0


^ permalink raw reply related	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2024-04-26 10:56 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-04-26  9:20 [CI 1/5] drm/xe: Introduce has_atomic_enable_pte_bit device info Nirmoy Das
2024-04-26  9:20 ` [CI 2/5] drm/xe: Move vm bind bo validation to a helper function Nirmoy Das
2024-04-26  9:20 ` [CI 3/5] drm/xe: Introduce has_device_atomics_on_smem device info Nirmoy Das
2024-04-26  9:20 ` [CI 4/5] drm/xe: Add function to check if BO has single placement Nirmoy Das
2024-04-26  9:20 ` [CI 5/5] drm/xe: Refactor default device atomic settings Nirmoy Das
2024-04-26 10:03 ` ✓ CI.Patch_applied: success for series starting with [CI,1/5] drm/xe: Introduce has_atomic_enable_pte_bit device info Patchwork
2024-04-26 10:03 ` ✓ CI.checkpatch: " Patchwork
2024-04-26 10:05 ` ✓ CI.KUnit: " Patchwork
2024-04-26 10:17 ` ✓ CI.Build: " Patchwork
2024-04-26 10:19 ` ✓ CI.Hooks: " Patchwork
2024-04-26 10:21 ` ✓ CI.checksparse: " Patchwork
2024-04-26 10:56 ` ✓ CI.BAT: " Patchwork

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).