Re: [MAINTAINER SUMMIT] User-space requirements for accelerator drivers

[Arnd Bergmann <arnd@arndb.de>]

On Tue, Sep 14, 2021 at 1:33 AM Dave Airlie <airlied@gmail.com> wrote:
> On Tue, 14 Sept 2021 at 08:05, Arnd Bergmann <arnd@arndb.de> wrote:
> > >On Mon, Sep 13, 2021 at 3:54 PM Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> > > I think BLAS are too high-level for these. Sure fore perfect speed the
> > > vendor probably wants to have their own BLAS thing, their own NN
> > > optmizer and a heap of other things, but for the low-level userspace
> > > we're talking about here that pretty much doesn't matter.
> >
> > I suppose high-level vs low-level is not the correct distinction here,
> > it's more like fixed-function vs programmable.
> >
> > As a fixed-function interface, something like GEMM is probably as
> > low-level as you would want to get, as it's big enough to make sense
> > as a single atomic command, but small enough to be able to build on
> > top of it.
>
> The distinctions is more programming model than fixed vs programmable
> in rough order of complexity
>
> a) device is MMIO programmed and can process one thing, kernel needs
> to mediate between exclusive users (big lock, initial drm subsystem)
> b) device has a queue that can process untrusted userspace command
> with no memory safety (old drm drivers, in-kernel command stream
> parsing)
> c) device has queues, contexts, memory safety, virtual address space
> (newer drm drivers)
> d) device has full preempt on all hw blocks, is fully coherent, can
> trigger paging sanely, userspace can submit directly (pipe dream).
>
> What the device processes is of little consequence to the kernel
> driver model. the uAPI of course needs to reflect the above along with
> what the device can program. Since there could be a queue for a DMA
> device that isn't specificed but can be programmed to DMA random
> system memory.

Thank you for the useful overview!

> Devices in category (a) are the sort of things that can need kernel
> interfaces like a GEMM or BLAS level, however there is no point having
> an interface at that level for any of the b/c/d device. That interface
> needs to be in userspace somewhere, level0 or something like is
> probably where things will end up, and the type (a) devices will die
> out.

I can see two reasons why one would want to support a type (a)
interface even with the more versatile devices:

- It can be done in a generic way so that simply adding a kernel
  driver and loading some firmware into it makes existing user space
  software work out of the box.

- It gives the manufacturer a way to get an upstream kernel driver
  without open sourcing their firmware (a.k.a. compiler and user
  space driver). Whether you consider this a good or bad thing is
  of course a matter of perspective.

> > I realize that fixed-function is not fashionable on GPUs, but they
> > are widely used in other areas (video codecs, crypto, ...) even when
> > you are running precompiled code on the accelerator hardware.
> > This would of course replace the question of open source user space
> > with the question of open-source firmware, as the user side would
> > become mostly while the accelerator goes from dynamically created
> > to a firmware blob.
>
> We have lots of fixed function on GPUs, video codecs are on most x86
> GPUs. It's how you program them that matters, most of them are behind
> queues similar to the 3D engine, so you program them the same way.

So these would go through /dev/dri instead of /dev/media0? I can definitely
see a lot of codec drivers in the kernel that use a /dev/media interfaces,
and the tradeoffs between those two seem very similar to the tradeoffs
you get for machine learning accelerators.

> What isn't fashionable on GPUs is programmable blocks that are single
> user that only the kernel can program one user on at a time, since hw
> has long since left that model as desirable. There are some AI
> accelerators going doing the same path, but eventually they'll have to
> be shareable and catch up with GPU programming models to remain
> competitive.

I'm not convinced by this at all. While I totally understand this argument
for GPUs and general-purpose users (phone, PC, server, ...), I also see
a lot of cheap SoC hardware with much simpler requirements. If the chip
is built for an embedded application (face detection, smart speaker, ...)
you would never need to have two processes access the same
accelerator hardware, or even just load a new model into it after
boot. Adding any complexity to the hardware increases the cost, so
you would only do it if absolutely necessary, or if the cheapest
off-the-shelf solution already includes it.

           Arnd