[PATCH 1/3] KVM: x86/pmu: Ignore pmu->global_ctrl check if vPMU doesn't support global_ctrl

[PATCH 1/3] KVM: x86/pmu: Ignore pmu->global_ctrl check if vPMU doesn't support global_ctrl

[Like Xu]

From: Like Xu <likexu@tencent.com>

MSR_CORE_PERF_GLOBAL_CTRL is introduced as part of Architecture PMU V2,
as indicated by Intel SDM 19.2.2 and the intel_is_valid_msr() function.

So in the absence of global_ctrl support, all PMCs are enabled as AMD does.

Signed-off-by: Like Xu <likexu@tencent.com>
---
 arch/x86/kvm/vmx/pmu_intel.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index b82b6709d7a8..cff03baf8921 100644
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
@@ -98,6 +98,9 @@ static bool intel_pmc_is_enabled(struct kvm_pmc *pmc)
 {
 	struct kvm_pmu *pmu = pmc_to_pmu(pmc);
 
+	if (pmu->version < 2)
+		return true;
+
 	return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl);
 }
 
-- 
2.36.1

[PATCH 2/3] KVM: x86/pmu: Don't pre-set the pmu->global_ctrl when refreshing

[Like Xu]

From: Like Xu <likexu@tencent.com>

Assigning a value to pmu->global_ctrl just to set the value of
pmu->global_ctrl_mask in a more readable way leaves a side effect of
not conforming to the specification. The global_ctrl is reset to zero on
Power up and Reset but keeps unchanged on INIT, like an ordinary MSR.

Signed-off-by: Like Xu <likexu@tencent.com>
---
 arch/x86/kvm/vmx/pmu_intel.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index cff03baf8921..4d6cc95bc770 100644
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
@@ -525,9 +525,8 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
 		setup_fixed_pmc_eventsel(pmu);
 	}
 
-	pmu->global_ctrl = ((1ull << pmu->nr_arch_gp_counters) - 1) |
+	pmu->global_ctrl_mask = ~((1ull << pmu->nr_arch_gp_counters) - 1) |
 		(((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED);
-	pmu->global_ctrl_mask = ~pmu->global_ctrl;
 	pmu->global_ovf_ctrl_mask = pmu->global_ctrl_mask
 			& ~(MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF |
 			    MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD);
-- 
2.36.1

[PATCH 3/3] KVM: x86/pmu: Drop redundant-clumsy-asymmetric PERFCTR_CORE MSRs handling

[Like Xu]

From: Like Xu <likexu@tencent.com>

In commit c51eb52b8f98 ("KVM: x86: Add support for AMD Core Perf Extension
in guest"), the entry "case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5 " is
introduced asymmetrically into kvm_get_msr_common(), ignoring the set part.

The missing guest PERFCTR_CORE cpuid check from the above commit leads to
the commit c28fa560c5bb ("KVM: x86/vPMU: Forbid reading from MSR_F15H_PERF
MSRs when guest doesn't have X86_FEATURE_PERFCTR_CORE"), but it simply
duplicates the default entry at the end of the switch statement explicitly.

Removing the PERFCTR_CORE MSRs entry in kvm_get_msr_common() thoroughly
would be more maintainable, as we did for the same group of MSRs in the
kvm_set_msr_common() at the very beginning when the feature was enabled.

Signed-off-by: Like Xu <likexu@tencent.com>
---
 arch/x86/kvm/x86.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 4790f0d7d40b..2b9089701ef5 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -3841,13 +3841,6 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 	case MSR_DRAM_ENERGY_STATUS:	/* DRAM controller */
 		msr_info->data = 0;
 		break;
-	case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
-		if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
-			return kvm_pmu_get_msr(vcpu, msr_info);
-		if (!msr_info->host_initiated)
-			return 1;
-		msr_info->data = 0;
-		break;
 	case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
 	case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
 	case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
-- 
2.36.1

Re: [PATCH V2 2/3] KVM: x86/pmu: Don't pre-set the pmu->global_ctrl when refreshing

[Like Xu]

From: Like Xu <likexu@tencent.com>

Assigning a value to pmu->global_ctrl just to set the value of
pmu->global_ctrl_mask in a more readable way leaves a side effect of
not conforming to the specification. The value is reset to zero on
Power up and Reset but keeps unchanged on INIT, like an ordinary MSR.

Signed-off-by: Like Xu <likexu@tencent.com>
---
v1 -> v2 Changelog:
- Explicitly add parentheses around;

  arch/x86/kvm/vmx/pmu_intel.c | 5 ++---
  1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index cff03baf8921..7945e97db0af 100644
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
@@ -525,9 +525,8 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
          setup_fixed_pmc_eventsel(pmu);
      }

-    pmu->global_ctrl = ((1ull << pmu->nr_arch_gp_counters) - 1) |
-        (((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED);
-    pmu->global_ctrl_mask = ~pmu->global_ctrl;
+    pmu->global_ctrl_mask = ~(((1ull << pmu->nr_arch_gp_counters) - 1) |
+        (((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED));
      pmu->global_ovf_ctrl_mask = pmu->global_ctrl_mask
              & ~(MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF |
                  MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD);
-- 
2.36.1

[PATCH v2] KVM: x86/pmu: Don't pre-set the pmu->global_ctrl when refreshing

[Like Xu]

From: Like Xu <likexu@tencent.com>

Assigning a value to pmu->global_ctrl just to set the value of
pmu->global_ctrl_mask in a more readable way leaves a side effect of
not conforming to the specification. The value is reset to zero on
Power up and Reset but keeps unchanged on INIT, like an ordinary MSR.

Signed-off-by: Like Xu <likexu@tencent.com>
---
v1 -> v2 Changelog:
- Explicitly add parentheses around;

 arch/x86/kvm/vmx/pmu_intel.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index b82b6709d7a8..7829ec457b28 100644
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
@@ -522,9 +522,8 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
 		setup_fixed_pmc_eventsel(pmu);
 	}
 
-	pmu->global_ctrl = ((1ull << pmu->nr_arch_gp_counters) - 1) |
-		(((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED);
-	pmu->global_ctrl_mask = ~pmu->global_ctrl;
+	pmu->global_ctrl_mask = ~(((1ull << pmu->nr_arch_gp_counters) - 1) |
+		(((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED));
 	pmu->global_ovf_ctrl_mask = pmu->global_ctrl_mask
 			& ~(MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF |
 			    MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD);
-- 
2.36.1

Re: [PATCH v2] KVM: x86/pmu: Don't pre-set the pmu->global_ctrl when refreshing

[Paolo Bonzini]

Queued, thanks.

Paolo

Re: [PATCH 3/3] KVM: x86/pmu: Drop redundant-clumsy-asymmetric PERFCTR_CORE MSRs handling

[Paolo Bonzini]

On 5/9/22 12:22, Like Xu wrote:
> In commit c51eb52b8f98 ("KVM: x86: Add support for AMD Core Perf Extension
> in guest"), the entry "case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5 " is
> introduced asymmetrically into kvm_get_msr_common(), ignoring the set part.
> 
> The missing guest PERFCTR_CORE cpuid check from the above commit leads to
> the commit c28fa560c5bb ("KVM: x86/vPMU: Forbid reading from MSR_F15H_PERF
> MSRs when guest doesn't have X86_FEATURE_PERFCTR_CORE"), but it simply
> duplicates the default entry at the end of the switch statement explicitly.
> 
> Removing the PERFCTR_CORE MSRs entry in kvm_get_msr_common() thoroughly
> would be more maintainable, as we did for the same group of MSRs in the
> kvm_set_msr_common() at the very beginning when the feature was enabled.

The code and the commit message suggest that some guests are expecting a 
#GP, and complain if they don't get it.

Paolo