From: Paolo Bonzini <pbonzini@redhat.com>
To: Kai Huang <kai.huang@intel.com>,
kvm@vger.kernel.org, linux-sgx@vger.kernel.org
Cc: seanjc@google.com, bp@alien8.de, jarkko@kernel.org,
dave.hansen@intel.com, luto@kernel.org,
rick.p.edgecombe@intel.com, haitao.huang@intel.com
Subject: Re: [PATCH v5 08/11] KVM: VMX: Add emulation of SGX Launch Control LE hash MSRs
Date: Sat, 17 Apr 2021 15:55:42 +0200 [thread overview]
Message-ID: <0f4eaeb2-df66-af8e-d716-7060edf03e90@redhat.com> (raw)
In-Reply-To: <c58ef601ddf88f3a113add837969533099b1364a.1618196135.git.kai.huang@intel.com>
On 12/04/21 06:21, Kai Huang wrote:
> Note, KVM allows writes to the LE hash MSRs if IA32_FEATURE_CONTROL is
> unlocked. This is technically not architectural behavior, but it's
> roughly equivalent to the arch behavior of the MSRs being writable prior
> to activating SGX[1]. Emulating SGX activation is feasible, but adds no
> tangible benefits and would just create extra work for KVM and guest
> firmware.
>
> [1] SGX related bits in IA32_FEATURE_CONTROL cannot be set until SGX
> is activated, e.g. by firmware. SGX activation is triggered by
> setting bit 0 in MSR 0x7a. Until SGX is activated, the LE hash
> MSRs are writable, e.g. to allow firmware to lock down the LE
> root key with a non-Intel value.
I turned these into a comment in vmx_set_msr:
/*
* On real hardware, the LE hash MSRs are writable before
* the firmware sets bit 0 in MSR 0x7a ("activating" SGX),
* at which point SGX related bits in IA32_FEATURE_CONTROL
* become writable.
*
* KVM does not emulate SGX activation for simplicity, so
* allow writes to the LE hash MSRs if IA32_FEATURE_CONTROL
* is unlocked. This is technically not architectural
* behavior, but close enough.
*/
Paolo
next prev parent reply other threads:[~2021-04-17 13:55 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-12 4:21 [PATCH v5 00/11] KVM SGX virtualization support (KVM part) Kai Huang
2021-04-12 4:21 ` [PATCH v5 01/11] KVM: x86: Export kvm_mmu_gva_to_gpa_{read,write}() for SGX (VMX) Kai Huang
2021-04-12 4:21 ` [PATCH v5 02/11] KVM: x86: Define new #PF SGX error code bit Kai Huang
2021-04-12 4:21 ` [PATCH v5 03/11] KVM: x86: Add support for reverse CPUID lookup of scattered features Kai Huang
2021-04-17 13:39 ` Paolo Bonzini
2021-04-12 4:21 ` [PATCH v5 04/11] KVM: x86: Add reverse-CPUID lookup support for scattered SGX features Kai Huang
2021-04-17 13:39 ` Paolo Bonzini
2021-04-12 4:21 ` [PATCH v5 05/11] KVM: VMX: Add basic handling of VM-Exit from SGX enclave Kai Huang
2021-04-12 4:21 ` [PATCH v5 06/11] KVM: VMX: Frame in ENCLS handler for SGX virtualization Kai Huang
2021-04-12 4:21 ` [PATCH v5 07/11] KVM: VMX: Add SGX ENCLS[ECREATE] handler to enforce CPUID restrictions Kai Huang
2021-04-12 4:21 ` [PATCH v5 08/11] KVM: VMX: Add emulation of SGX Launch Control LE hash MSRs Kai Huang
2021-04-17 13:55 ` Paolo Bonzini [this message]
2021-04-12 4:21 ` [PATCH v5 09/11] KVM: VMX: Add ENCLS[EINIT] handler to support SGX Launch Control (LC) Kai Huang
2021-04-12 4:21 ` [PATCH v5 10/11] KVM: VMX: Enable SGX virtualization for SGX1, SGX2 and LC Kai Huang
2021-04-12 9:51 ` kernel test robot
2021-04-12 10:47 ` Kai Huang
2021-04-17 14:11 ` Paolo Bonzini
2021-04-19 11:44 ` Kai Huang
2021-04-19 15:16 ` Sean Christopherson
2021-04-19 17:14 ` Paolo Bonzini
2021-04-12 4:21 ` [PATCH v5 11/11] KVM: x86: Add capability to grant VM access to privileged SGX attribute Kai Huang
2021-04-12 11:28 ` kernel test robot
2021-04-13 14:51 ` [PATCH v5 00/11] KVM SGX virtualization support (KVM part) Paolo Bonzini
2021-04-13 15:01 ` Borislav Petkov
2021-04-13 21:47 ` Kai Huang
2021-04-17 14:15 ` Paolo Bonzini
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