[PATCH 00/15] ARM: add and use convenience macros for PC relative references

[PATCH 00/15] ARM: add and use convenience macros for PC relative references

[Ard Biesheuvel]

Every year or so, I make an attempt at contributing assembler macros
that encapsulate PC-relative references, including loads and stores,
and updating existing assembler code to make it more readable and
concise.

Patch #1 implements adr_l, ldr_l and str_l macros that emit PC-relative
references with unlimited range. For v7 and later, relative movw/movt
pairs are used (avoiding the need for loading literals via the D-cache).
For older CPUs, a literal containing a relative offset wrt the instruction
that adds the value of PC is emitted into a subsection, which works around
the objections given last time around, regarding the limited range of
PC-relative group relocations, and the fact that they are EABI only. In
this case, the range is unlimited, although the subsection needs to be
emitted within 4 K of the ldr instruction. (This limit can be extended
but that is currently unnecessary: .text sizes of objects built from .S
files never exceed 4 K in size. Please refer to the list below, after
the diffstat, for the sizes of the .text sections of all such objects
that are built as part of a multi_v7_defconfig kernel)

All patches beyond #1 are independent, but obviously all depend on the
first one. I understand there may be concerns about churn, but some of
these cleanups are really quite nice so please don't dismiss the series
wholesale for that reason.

Ard Biesheuvel (15):
  ARM: assembler: introduce adr_l, ldr_l and str_l macros
  ARM: head-common.S: use PC-relative insn sequence for __proc_info
  ARM: head-common.S: use PC-relative insn sequence for __turn_mmu_on
  ARM: head.S: use PC-relative insn sequence for secondary_data
  ARM: head: use PC-relative insn sequence for __smp_alt
  ARM: sleep.S: use PC-relative insn sequence for
    sleep_save_sp/mpidr_hash
  ARM: head.S: use PC-relative insn sequences for __fixup_pv_table
  ARM: head.S: use PC relative insn sequence to calculate PHYS_OFFSET
  ARM: kvm: replace open coded VA->PA calculations with adr_l call
  arm-soc: exynos: replace open coded VA->PA conversions
  arm-soc: mvebu: replace open coded VA->PA conversion
  arm-soc: omap: replace open coded VA->PA calculations
  arm-soc: various: replace open coded VA->PA calculation of pen_release
  arm-soc: shmobile: replace open coded VA->PA calculation
  ARM: l2c: replace open coded VA->PA calculation

 arch/arm/boot/compressed/head.S    | 15 +---
 arch/arm/include/asm/assembler.h   | 70 +++++++++++++++++
 arch/arm/kernel/head-common.S      | 22 ++----
 arch/arm/kernel/head.S             | 80 +++++---------------
 arch/arm/kernel/hyp-stub.S         | 33 +++-----
 arch/arm/kernel/sleep.S            | 16 +---
 arch/arm/kvm/init.S                |  8 +-
 arch/arm/mach-exynos/headsmp.S     |  9 +--
 arch/arm/mach-exynos/sleep.S       | 26 ++-----
 arch/arm/mach-mvebu/coherency_ll.S |  8 +-
 arch/arm/mach-omap2/sleep34xx.S    | 21 +----
 arch/arm/mach-omap2/sleep44xx.S    | 12 +--
 arch/arm/mach-prima2/headsmp.S     | 11 +--
 arch/arm/mach-shmobile/headsmp.S   | 14 +---
 arch/arm/mach-spear/headsmp.S      | 11 +--
 arch/arm/mach-sti/headsmp.S        | 10 +--
 arch/arm/mm/l2c-l2x0-resume.S      |  7 +-
 arch/arm/plat-versatile/headsmp.S  |  9 +--
 18 files changed, 140 insertions(+)

-- 
2.11.0

   text	   data	    bss	    dec	    hex  filename
    240	      0	      0	    240	     f0  linux-arm-build/arch/arm/lib/div64.o
   1608	      0	      0	   1608	    648  linux-arm-build/arch/arm/lib/copy_to_user.o
    892	      0	      0	    892	    37c  linux-arm-build/arch/arm/lib/csumpartialcopy.o
    288	      0	      0	    288	    120  linux-arm-build/arch/arm/lib/io-writesb.o
     28	      0	      0	     28	     1c  linux-arm-build/arch/arm/lib/ashldi3.o
    104	      0	      0	    104	     68  linux-arm-build/arch/arm/lib/testclearbit.o
     44	      0	      0	     44	     2c  linux-arm-build/arch/arm/lib/ucmpdi2.o
    204	      0	      0	    204	     cc  linux-arm-build/arch/arm/lib/io-writesw-armv4.o
     52	      0	      0	     52	     34  linux-arm-build/arch/arm/lib/csumipv6.o
    900	      0	      0	    900	    384  linux-arm-build/arch/arm/lib/memmove.o
    764	      0	      0	    764	    2fc  linux-arm-build/arch/arm/lib/lib1funcs.o
     68	      0	      0	     68	     44  linux-arm-build/arch/arm/lib/changebit.o
    104	      0	      0	    104	     68  linux-arm-build/arch/arm/lib/testsetbit.o
    188	      0	      0	    188	     bc  linux-arm-build/arch/arm/lib/io-readsl.o
   1476	      0	      0	   1476	    5c4  linux-arm-build/arch/arm/lib/csumpartialcopyuser.o
     12	      0	      0	     12	      c  linux-arm-build/arch/arm/lib/bswapsdi2.o
     48	      0	      0	     48	     30  linux-arm-build/arch/arm/lib/delay-loop.o
    144	      0	      0	    144	     90  linux-arm-build/arch/arm/lib/putuser.o
     28	      0	      0	     28	     1c  linux-arm-build/arch/arm/lib/ashrdi3.o
    172	      0	      0	    172	     ac  linux-arm-build/arch/arm/lib/findbit.o
   1616	      0	      0	   1616	    650  linux-arm-build/arch/arm/lib/copy_from_user.o
    148	      0	      0	    148	     94  linux-arm-build/arch/arm/lib/getuser.o
    212	      0	      0	    212	     d4  linux-arm-build/arch/arm/lib/clear_user.o
    228	      0	      0	    228	     e4  linux-arm-build/arch/arm/lib/io-readsw-armv4.o
    176	      0	      0	    176	     b0  linux-arm-build/arch/arm/lib/memzero.o
      4	      0	      0	      4	      4  linux-arm-build/arch/arm/lib/backtrace.o
    104	      0	      0	    104	     68  linux-arm-build/arch/arm/lib/testchangebit.o
    232	      0	      0	    232	     e8  linux-arm-build/arch/arm/lib/csumpartial.o
     28	      0	      0	     28	     1c  linux-arm-build/arch/arm/lib/strrchr.o
    184	      0	      0	    184	     b8  linux-arm-build/arch/arm/lib/memset.o
     68	      0	      0	     68	     44  linux-arm-build/arch/arm/lib/setbit.o
     32	      0	      0	     32	     20  linux-arm-build/arch/arm/lib/strchr.o
     60	      0	      0	     60	     3c  linux-arm-build/arch/arm/lib/muldi3.o
     24	      0	      0	     24	     18  linux-arm-build/arch/arm/lib/memchr.o
    320	      0	      0	    320	    140  linux-arm-build/arch/arm/lib/io-readsb.o
     28	      0	      0	     28	     1c  linux-arm-build/arch/arm/lib/lshrdi3.o
     32	      0	      0	     32	     20  linux-arm-build/arch/arm/lib/call_with_stack.o
    112	      0	      0	    112	     70  linux-arm-build/arch/arm/lib/copy_page.o
    156	      0	      0	    156	     9c  linux-arm-build/arch/arm/lib/io-writesl.o
     68	      0	      0	     68	     44  linux-arm-build/arch/arm/lib/clearbit.o
    884	      0	      0	    884	    374  linux-arm-build/arch/arm/lib/memcpy.o
    104	      0	      0	    104	     68  linux-arm-build/arch/arm/common/vlock.o
    280	      0	    260	    540	    21c  linux-arm-build/arch/arm/common/mcpm_head.o
   2760	      0	   4096	   6856	   1ac8  linux-arm-build/arch/arm/boot/compressed/head.o
7324164	      0	      0	7324164	 6fc204  linux-arm-build/arch/arm/boot/compressed/piggy.o
      4	      0	      0	      4	      4  linux-arm-build/arch/arm/mach-berlin/headsmp.o
    116	      0	    192	    308	    134  linux-arm-build/arch/arm/mach-shmobile/headsmp.o
     32	      0	      0	     32	     20  linux-arm-build/arch/arm/mach-shmobile/headsmp-scu.o
     16	      0	      0	     16	     10  linux-arm-build/arch/arm/mach-exynos/exynos-smc.o
    168	      8	      0	    176	     b0  linux-arm-build/arch/arm/mach-exynos/sleep.o
     28	      0	      0	     28	     1c  linux-arm-build/arch/arm/mach-exynos/headsmp.o
     12	      0	      0	     12	      c  linux-arm-build/arch/arm/mach-keystone/smc.o
    676	      0	      0	    676	    2a4  linux-arm-build/arch/arm/mach-at91/pm_suspend.o
      8	      0	      0	      8	      8  linux-arm-build/arch/arm/mach-zynq/headsmp.o
     20	      0	      0	     20	     14  linux-arm-build/arch/arm/mach-highbank/smc.o
      0	     64	      0	     64	     40  linux-arm-build/arch/arm/mach-rockchip/sleep.o
      8	      0	      0	      8	      8  linux-arm-build/arch/arm/mach-rockchip/headsmp.o
     24	      0	      0	     24	     18  linux-arm-build/arch/arm/mm/abort-ev7.o
    792	     44	      0	    836	    344  linux-arm-build/arch/arm/mm/cache-v7.o
   1672	    192	     28	   1892	    764  linux-arm-build/arch/arm/mm/proc-v7.o
    140	      0	      0	    140	     8c  linux-arm-build/arch/arm/mm/tlb-v7.o
     12	      0	      0	     12	      c  linux-arm-build/arch/arm/mm/pabort-v7.o
     88	      0	      0	     88	     58  linux-arm-build/arch/arm/mm/l2c-l2x0-resume.o
     28	      0	      0	     28	     1c  linux-arm-build/arch/arm/mach-sti/headsmp.o
    164	      0	      0	    164	     a4  linux-arm-build/arch/arm/mach-imx/suspend-imx53.o
    648	      0	      0	    648	    288  linux-arm-build/arch/arm/mach-imx/suspend-imx6.o
     24	      0	      0	     24	     18  linux-arm-build/arch/arm/mach-imx/headsmp.o
    148	      0	      0	    148	     94  linux-arm-build/arch/arm/mach-omap2/omap-smc.o
    148	      0	      0	    148	     94  linux-arm-build/arch/arm/mach-omap2/omap-headsmp.o
    864	    124	      0	    988	    3dc  linux-arm-build/arch/arm/mach-omap2/sleep34xx.o
    748	     12	      0	    760	    2f8  linux-arm-build/arch/arm/mach-omap2/sleep44xx.o
     28	      0	      0	     28	     1c  linux-arm-build/arch/arm/plat-versatile/headsmp.o
   1156	      0	      0	   1156	    484  linux-arm-build/arch/arm/mach-tegra/sleep-tegra20.o
    640	      0	      0	    640	    280  linux-arm-build/arch/arm/mach-tegra/reset-handler.o
   2308	      0	      0	   2308	    904  linux-arm-build/arch/arm/mach-tegra/sleep-tegra30.o
    284	      0	      0	    284	    11c  linux-arm-build/arch/arm/mach-tegra/sleep.o
     76	      0	      0	     76	     4c  linux-arm-build/arch/arm/mach-mvebu/pmsu_ll.o
    192	      0	      0	    192	     c0  linux-arm-build/arch/arm/mach-mvebu/coherency_ll.o
      8	      0	      0	      8	      8  linux-arm-build/arch/arm/mach-mvebu/headsmp-a9.o
     12	      0	      0	     12	      c  linux-arm-build/arch/arm/mach-mvebu/headsmp.o
     32	      0	      0	     32	     20  linux-arm-build/arch/arm/mach-socfpga/headsmp.o
     40	      0	      0	     40	     28  linux-arm-build/arch/arm/mach-spear/headsmp.o
    100	      0	      0	    100	     64  linux-arm-build/arch/arm/mach-prima2/sleep.o
     28	      0	      0	     28	     1c  linux-arm-build/arch/arm/mach-prima2/headsmp.o
     24	      0	      0	     24	     18  linux-arm-build/arch/arm/vdso/datapage.o
      0	   4096	      0	   4096	   1000  linux-arm-build/arch/arm/vdso/vdso.o
     36	      0	      0	     36	     24  linux-arm-build/arch/arm/vfp/entry.o
   1296	      0	      0	   1296	    510  linux-arm-build/arch/arm/vfp/vfphw.o
    356	      4	      0	    360	    168  linux-arm-build/arch/arm/kernel/hyp-stub.o
   1096	     16	      0	   1112	    458  linux-arm-build/arch/arm/kernel/head.o
   3308	     12	      0	   3320	    cf8  linux-arm-build/arch/arm/kernel/entry-armv.o
    644	      4	      0	    648	    288  linux-arm-build/arch/arm/kernel/iwmmxt.o
     28	      0	      0	     28	     1c  linux-arm-build/arch/arm/kernel/sigreturn_codes.o
   2148	      0	      0	   2148	    864  linux-arm-build/arch/arm/kernel/entry-common.o
     64	      0	      0	     64	     40  linux-arm-build/arch/arm/kernel/smccc-call.o
    328	      8	      0	    336	    150  linux-arm-build/arch/arm/kernel/sleep.o
    104	      0	      0	    104	     68  linux-arm-build/arch/arm/kernel/relocate_kernel.o

[PATCH 01/15] ARM: assembler: introduce adr_l, ldr_l and str_l macros

[Ard Biesheuvel]

Like arm64, ARM supports position independent code sequences that
produce symbol references with a greater reach than the ordinary
adr/ldr instructions.

Currently, we use open coded instruction sequences involving literals
and arithmetic operations. Instead, we can use movw/movt pairs on v7
CPUs, circumventing the D-cache entirely. For older CPUs, we can emit
the literal into a subsection, allowing it to be emitted out of line
while retaining the ability to perform arithmetic on label offsets.

E.g., on pre-v7 CPUs, we can emit a PC-relative reference as follows:

       ldr          <reg>, 222f
  111: add          <reg>, <reg>, pc
       .subsection  1
  222: .long        <sym> - (111b + 8)
       .previous

This is allowed by the assembler because, unlike ordinary sections,
subsections are combined into a single section into the object file,
and so the label references are not true cross-section references that
are visible as relocations. Note that we could even do something like

       add          <reg>, pc, #(222f - 111f) & ~0xfff
       ldr          <reg>, [<reg>, #(222f - 111f) & 0xfff]
  111: add          <reg>, <reg>, pc
       .subsection  1
  222: .long        <sym> - (111b + 8)
       .previous

if it turns out that the 4 KB range of the ldr instruction is insufficient
to reach the literal in the subsection, although this is currently not a
problem (of the 98 objects built from .S files in a multi_v7_defconfig
build, only 11 have .text sections that are over 1 KB, and the largest one
[entry-armv.o] is 3308 bytes)

Subsections have been available in binutils since 2004 at least, so
they should not cause any issues with older toolchains.

So use the above to implement the macros mov_l, adr_l, adrm_l (using ldm
to load multiple literals at once), ldr_l and str_l, all of which will
use movw/movt pairs on v7 and later CPUs, and use PC-relative literals
otherwise.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 arch/arm/include/asm/assembler.h | 70 ++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index ad301f107dd2..cedf59a7f853 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -518,4 +518,74 @@ THUMB(	orr	\reg , \reg , #PSR_T_BIT	)
 #endif
 	.endm
 
+#ifdef CONFIG_THUMB2_KERNEL
+#define	ARM_PC_BIAS		4
+#else
+#define	ARM_PC_BIAS		8
+#endif
+
+	.macro		__adldst_l, op, reg, sym, tmp
+	.if		__LINUX_ARM_ARCH__ < 7
+	ldr		\tmp, 111f
+	.subsection	1
+	.align		2
+111:	.long		\sym - (222f + ARM_PC_BIAS)
+	.previous
+	.else
+	movw		\tmp, #:lower16:\sym - (222f + ARM_PC_BIAS)
+	movt		\tmp, #:upper16:\sym - (222f + ARM_PC_BIAS)
+	.endif
+222:;	.ifc		\op, add
+	add		\reg, \tmp, pc
+	.elseif		CONFIG_THUMB2_KERNEL == 1
+	add		\tmp, \tmp, pc
+	\op		\reg, [\tmp]
+	.else
+	\op		\reg, [pc, \tmp]
+	.endif
+	.endm
+
+	/*
+	 * mov_l - move a constant value or [relocated] address into a register
+	 */
+	.macro		mov_l, dst:req, imm:req
+	.if		__LINUX_ARM_ARCH__ < 7
+	ldr		\dst, =\imm
+	.else
+	movw		\dst, #:lower16:\imm
+	movt		\dst, #:upper16:\imm
+	.endif
+	.endm
+
+	/*
+	 * adr_l - adr pseudo-op with unlimited range
+	 *
+	 * @dst: destination register
+	 * @sym: name of the symbol
+	 */
+	.macro		adr_l, dst:req, sym:req
+	__adldst_l	add, \dst, \sym, \dst
+	.endm
+
+	/*
+	 * ldr_l - ldr <literal> pseudo-op with unlimited range
+	 *
+	 * @dst: destination register
+	 * @sym: name of the symbol
+	 */
+	.macro		ldr_l, dst:req, sym:req
+	__adldst_l	ldr, \dst, \sym, \dst
+	.endm
+
+	/*
+	 * str_l - str <literal> pseudo-op with unlimited range
+	 *
+	 * @src: source register
+	 * @sym: name of the symbol
+	 * @tmp: mandatory scratch register
+	 */
+	.macro		str_l, src:req, sym:req, tmp:req
+	__adldst_l	str, \src, \sym, \tmp
+	.endm
+
 #endif /* __ASM_ASSEMBLER_H__ */
-- 
2.11.0

[PATCH 02/15] ARM: head-common.S: use PC-relative insn sequence for __proc_info

[Ard Biesheuvel]

Replace the open coded PC relative offset calculations with a pair
of adr_l invocations.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 arch/arm/kernel/head-common.S | 22 ++++++--------------
 1 file changed, 6 insertions(+), 16 deletions(-)

diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index 8733012d231f..06035488130c 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -150,11 +150,12 @@ ENDPROC(lookup_processor_type)
  *	r9 = cpuid (preserved)
  */
 __lookup_processor_type:
-	adr	r3, __lookup_processor_type_data
-	ldmia	r3, {r4 - r6}
-	sub	r3, r3, r4			@ get offset between virt&phys
-	add	r5, r5, r3			@ convert virt addresses to
-	add	r6, r6, r3			@ physical address space
+	/*
+	 * Look in <asm/procinfo.h> for information about the __proc_info
+	 * structure.
+	 */
+	adr_l	r5, __proc_info_begin
+	adr_l	r6, __proc_info_end
 1:	ldmia	r5, {r3, r4}			@ value, mask
 	and	r4, r4, r9			@ mask wanted bits
 	teq	r3, r4
@@ -166,17 +167,6 @@ __lookup_processor_type:
 2:	ret	lr
 ENDPROC(__lookup_processor_type)
 
-/*
- * Look in <asm/procinfo.h> for information about the __proc_info structure.
- */
-	.align	2
-	.type	__lookup_processor_type_data, %object
-__lookup_processor_type_data:
-	.long	.
-	.long	__proc_info_begin
-	.long	__proc_info_end
-	.size	__lookup_processor_type_data, . - __lookup_processor_type_data
-
 __error_lpae:
 #ifdef CONFIG_DEBUG_LL
 	adr	r0, str_lpae
-- 
2.11.0

[PATCH 03/15] ARM: head-common.S: use PC-relative insn sequence for __turn_mmu_on

[Ard Biesheuvel]

Replace the open coded PC relative offset calculations with a pair
of adr_l invocations.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 arch/arm/kernel/head.S | 12 ++----------
 1 file changed, 2 insertions(+), 10 deletions(-)

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 04286fd9e09c..0a98aec0e39d 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -227,11 +227,8 @@ __create_page_tables:
 	 * Create identity mapping to cater for __enable_mmu.
 	 * This identity mapping will be removed by paging_init().
 	 */
-	adr	r0, __turn_mmu_on_loc
-	ldmia	r0, {r3, r5, r6}
-	sub	r0, r0, r3			@ virt->phys offset
-	add	r5, r5, r0			@ phys __turn_mmu_on
-	add	r6, r6, r0			@ phys __turn_mmu_on_end
+	adr_l	r5, __turn_mmu_on		@ _pa(__turn_mmu_on)
+	adr_l	r6, __turn_mmu_on_end		@ _pa(__turn_mmu_on_end)
 	mov	r5, r5, lsr #SECTION_SHIFT
 	mov	r6, r6, lsr #SECTION_SHIFT
 
@@ -354,11 +351,6 @@ __create_page_tables:
 	ret	lr
 ENDPROC(__create_page_tables)
 	.ltorg
-	.align
-__turn_mmu_on_loc:
-	.long	.
-	.long	__turn_mmu_on
-	.long	__turn_mmu_on_end
 
 #if defined(CONFIG_SMP)
 	.text
-- 
2.11.0

[PATCH 04/15] ARM: head.S: use PC-relative insn sequence for secondary_data

[Ard Biesheuvel]

Replace the open coded PC relative offset calculations with adr_l
and ldr_l invocations.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 arch/arm/kernel/head.S | 19 ++++---------------
 1 file changed, 4 insertions(+), 15 deletions(-)

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 0a98aec0e39d..6e9df3663a57 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -386,10 +386,8 @@ ENTRY(secondary_startup)
 	/*
 	 * Use the page tables supplied from  __cpu_up.
 	 */
-	adr	r4, __secondary_data
-	ldmia	r4, {r5, r7, r12}		@ address to jump to after
-	sub	lr, r4, r5			@ mmu has been enabled
-	add	r3, r7, lr
+	adr_l	r3, secondary_data
+	mov_l	r12, __secondary_switched
 	ldrd	r4, [r3, #0]			@ get secondary_data.pgdir
 ARM_BE8(eor	r4, r4, r5)			@ Swap r5 and r4 in BE:
 ARM_BE8(eor	r5, r4, r5)			@ it can be done in 3 steps
@@ -404,22 +402,13 @@ ARM_BE8(eor	r4, r4, r5)			@ without using a temp reg.
 ENDPROC(secondary_startup)
 ENDPROC(secondary_startup_arm)
 
-	/*
-	 * r6  = &secondary_data
-	 */
 ENTRY(__secondary_switched)
-	ldr	sp, [r7, #12]			@ get secondary_data.stack
+	ldr_l	r7, secondary_data + 12		@ get secondary_data.stack
+	mov	sp, r7
 	mov	fp, #0
 	b	secondary_start_kernel
 ENDPROC(__secondary_switched)
 
-	.align
-
-	.type	__secondary_data, %object
-__secondary_data:
-	.long	.
-	.long	secondary_data
-	.long	__secondary_switched
 #endif /* defined(CONFIG_SMP) */
 
 
-- 
2.11.0

[PATCH 05/15] ARM: head: use PC-relative insn sequence for __smp_alt

[Ard Biesheuvel]

Replace the open coded PC relative offset calculations with a pair
of adr_l invocations.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 arch/arm/kernel/head.S | 12 ++----------
 1 file changed, 2 insertions(+), 10 deletions(-)

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 6e9df3663a57..aed341e0f530 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -523,19 +523,11 @@ ARM_BE8(rev	r0, r0)			@ byteswap if big endian
 	retne	lr
 
 __fixup_smp_on_up:
-	adr	r0, 1f
-	ldmia	r0, {r3 - r5}
-	sub	r3, r0, r3
-	add	r4, r4, r3
-	add	r5, r5, r3
+	adr_l	r4, __smpalt_begin
+	adr_l	r5, __smpalt_end
 	b	__do_fixup_smp_on_up
 ENDPROC(__fixup_smp)
 
-	.align
-1:	.word	.
-	.word	__smpalt_begin
-	.word	__smpalt_end
-
 	.pushsection .data
 	.globl	smp_on_up
 smp_on_up:
-- 
2.11.0

[PATCH 06/15] ARM: sleep.S: use PC-relative insn sequence for sleep_save_sp/mpidr_hash

[Ard Biesheuvel]

Replace the open coded PC relative offset calculations with adr_l and
ldr_l invocations.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 arch/arm/kernel/sleep.S | 16 +++-------------
 1 file changed, 3 insertions(+), 13 deletions(-)

diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 0f6c1000582c..3026b119d3ff 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -137,9 +137,8 @@ ARM_BE8(setend be)			@ ensure we are in BE mode
 	mov	r1, #0
 	ALT_SMP(mrc p15, 0, r0, c0, c0, 5)
 	ALT_UP_B(1f)
-	adr	r2, mpidr_hash_ptr
-	ldr	r3, [r2]
-	add	r2, r2, r3		@ r2 = struct mpidr_hash phys address
+	adr_l	r2, mpidr_hash		@ r2 = struct mpidr_hash phys address
+
 	/*
 	 * This ldmia relies on the memory layout of the mpidr_hash
 	 * struct mpidr_hash.
@@ -147,10 +146,7 @@ ARM_BE8(setend be)			@ ensure we are in BE mode
 	ldmia	r2, { r3-r6 }	@ r3 = mpidr mask (r4,r5,r6) = l[0,1,2] shifts
 	compute_mpidr_hash	r1, r4, r5, r6, r0, r3
 1:
-	adr	r0, _sleep_save_sp
-	ldr	r2, [r0]
-	add	r0, r0, r2
-	ldr	r0, [r0, #SLEEP_SAVE_SP_PHYS]
+	ldr_l	r0, sleep_save_sp + SLEEP_SAVE_SP_PHYS
 	ldr	r0, [r0, r1, lsl #2]
 
 	@ load phys pgd, stack, resume fn
@@ -164,12 +160,6 @@ ENDPROC(cpu_resume)
 ENDPROC(cpu_resume_arm)
 #endif
 
-	.align 2
-_sleep_save_sp:
-	.long	sleep_save_sp - .
-mpidr_hash_ptr:
-	.long	mpidr_hash - .			@ mpidr_hash struct offset
-
 	.data
 	.type	sleep_save_sp, #object
 ENTRY(sleep_save_sp)
-- 
2.11.0

[PATCH 07/15] ARM: head.S: use PC-relative insn sequences for __fixup_pv_table

[Ard Biesheuvel]

Replace the open coded PC relative offset calculations with adr_l
and mov_l invocations.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 arch/arm/kernel/head.S | 27 ++++++--------------
 1 file changed, 8 insertions(+), 19 deletions(-)

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index aed341e0f530..939543e73874 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -578,14 +578,11 @@ ENDPROC(fixup_smp)
  */
 	__HEAD
 __fixup_pv_table:
-	adr	r0, 1f
-	ldmia	r0, {r3-r7}
+	adr_l	r6, __pv_phys_pfn_offset
+	adr_l	r7, __pv_offset			@ __pa(__pv_offset)
+	mov_l	r3, __pv_offset			@ __va(__pv_offset)
 	mvn	ip, #0
-	subs	r3, r0, r3	@ PHYS_OFFSET - PAGE_OFFSET
-	add	r4, r4, r3	@ adjust table start address
-	add	r5, r5, r3	@ adjust table end address
-	add	r6, r6, r3	@ adjust __pv_phys_pfn_offset address
-	add	r7, r7, r3	@ adjust __pv_offset address
+	subs	r3, r7, r3	@ PHYS_OFFSET - PAGE_OFFSET
 	mov	r0, r8, lsr #PAGE_SHIFT	@ convert to PFN
 	str	r0, [r6]	@ save computed PHYS_OFFSET to __pv_phys_pfn_offset
 	strcc	ip, [r7, #HIGH_OFFSET]	@ save to __pv_offset high bits
@@ -594,20 +591,15 @@ __fixup_pv_table:
 THUMB(	it	ne		@ cross section branch )
 	bne	__error
 	str	r3, [r7, #LOW_OFFSET]	@ save to __pv_offset low bits
+	adr_l	r4, __pv_table_begin
+	adr_l	r5, __pv_table_end
 	b	__fixup_a_pv_table
 ENDPROC(__fixup_pv_table)
-
-	.align
-1:	.long	.
-	.long	__pv_table_begin
-	.long	__pv_table_end
-2:	.long	__pv_phys_pfn_offset
-	.long	__pv_offset
+	.ltorg
 
 	.text
 __fixup_a_pv_table:
-	adr	r0, 3f
-	ldr	r6, [r0]
+	mov_l	r6, __pv_offset
 	add	r6, r6, r3
 	ldr	r0, [r6, #HIGH_OFFSET]	@ pv_offset high word
 	ldr	r6, [r6, #LOW_OFFSET]	@ pv_offset low word
@@ -676,9 +668,6 @@ ARM_BE8(rev16	ip, ip)
 #endif
 ENDPROC(__fixup_a_pv_table)
 
-	.align
-3:	.long __pv_offset
-
 ENTRY(fixup_pv_table)
 	stmfd	sp!, {r4 - r7, lr}
 	mov	r3, #0			@ no offset
-- 
2.11.0

[PATCH 08/15] ARM: head.S: use PC relative insn sequence to calculate PHYS_OFFSET

[Ard Biesheuvel]

Replace the open coded arithmetic with a simple adr_l/sub pair.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 arch/arm/kernel/head.S | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 939543e73874..e08a4623a980 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -106,10 +106,8 @@ ENTRY(stext)
 #endif
 
 #ifndef CONFIG_XIP_KERNEL
-	adr	r3, 2f
-	ldmia	r3, {r4, r8}
-	sub	r4, r3, r4			@ (PHYS_OFFSET - PAGE_OFFSET)
-	add	r8, r8, r4			@ PHYS_OFFSET
+	adr_l	r8, _text			@ __pa(_text)
+	sub	r8, r8, #TEXT_OFFSET		@ PHYS_OFFSET
 #else
 	ldr	r8, =PLAT_PHYS_OFFSET		@ always constant in this case
 #endif
@@ -161,10 +159,6 @@ ENTRY(stext)
 1:	b	__enable_mmu
 ENDPROC(stext)
 	.ltorg
-#ifndef CONFIG_XIP_KERNEL
-2:	.long	.
-	.long	PAGE_OFFSET
-#endif
 
 /*
  * Setup the initial page tables.  We only setup the barest
-- 
2.11.0

[PATCH 09/15] ARM: kvm: replace open coded VA->PA calculations with adr_l call

[Ard Biesheuvel]

Replace the open coded calculations of the actual physical address
of the KVM stub vector table with a single adr_l invocation.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 arch/arm/boot/compressed/head.S | 15 ++-------
 arch/arm/kernel/hyp-stub.S      | 33 +++++++-------------
 arch/arm/kvm/init.S             |  8 +----
 3 files changed, 15 insertions(+), 41 deletions(-)

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 8a756870c238..5884e8151376 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -427,15 +427,10 @@ dtb_check_done:
 
 		/*
 		 * Compute the address of the hyp vectors after relocation.
-		 * This requires some arithmetic since we cannot directly
-		 * reference __hyp_stub_vectors in a PC-relative way.
 		 * Call __hyp_set_vectors with the new address so that we
 		 * can HVC again after the copy.
 		 */
-0:		adr	r0, 0b
-		movw	r1, #:lower16:__hyp_stub_vectors - 0b
-		movt	r1, #:upper16:__hyp_stub_vectors - 0b
-		add	r0, r0, r1
+		adr_l	r0, __hyp_stub_vectors
 		sub	r0, r0, r5
 		add	r0, r0, r10
 		bl	__hyp_set_vectors
@@ -568,17 +563,11 @@ not_relocated:	mov	r0, #0
 		cmp	r0, #HYP_MODE		@ if not booted in HYP mode...
 		bne	__enter_kernel		@ boot kernel directly
 
-		adr	r12, .L__hyp_reentry_vectors_offset
-		ldr	r0, [r12]
-		add	r0, r0, r12
-
+		adr_l	r0, __hyp_reentry_vectors
 		bl	__hyp_set_vectors
 		__HVC(0)			@ otherwise bounce to hyp mode
 
 		b	.			@ should never be reached
-
-		.align	2
-.L__hyp_reentry_vectors_offset:	.long	__hyp_reentry_vectors - .
 #else
 		b	__enter_kernel
 #endif
diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S
index ec7e7377d423..55b5fab83861 100644
--- a/arch/arm/kernel/hyp-stub.S
+++ b/arch/arm/kernel/hyp-stub.S
@@ -36,41 +36,38 @@ ENTRY(__boot_cpu_mode)
 .text
 
 	/*
-	 * Save the primary CPU boot mode. Requires 3 scratch registers.
+	 * Save the primary CPU boot mode. Requires 2 scratch registers.
 	 */
-	.macro	store_primary_cpu_mode	reg1, reg2, reg3
+	.macro	store_primary_cpu_mode	reg1, reg2
 	mrs	\reg1, cpsr
 	and	\reg1, \reg1, #MODE_MASK
-	adr	\reg2, .L__boot_cpu_mode_offset
-	ldr	\reg3, [\reg2]
-	str	\reg1, [\reg2, \reg3]
+	str_l	\reg1, __boot_cpu_mode, \reg2
 	.endm
 
 	/*
 	 * Compare the current mode with the one saved on the primary CPU.
 	 * If they don't match, record that fact. The Z bit indicates
 	 * if there's a match or not.
-	 * Requires 3 additionnal scratch registers.
+	 * Requires 2 additionnal scratch registers.
 	 */
-	.macro	compare_cpu_mode_with_primary mode, reg1, reg2, reg3
-	adr	\reg2, .L__boot_cpu_mode_offset
-	ldr	\reg3, [\reg2]
-	ldr	\reg1, [\reg2, \reg3]
+	.macro	compare_cpu_mode_with_primary mode, reg1, reg2
+	adr_l	\reg2, __boot_cpu_mode
+	ldr	\reg1, [\reg2]
 	cmp	\mode, \reg1		@ matches primary CPU boot mode?
 	orrne	\reg1, \reg1, #BOOT_CPU_MODE_MISMATCH
-	strne	\reg1, [\reg2, \reg3]	@ record what happened and give up
+	strne	\reg1, [\reg2]		@ record what happened and give up
 	.endm
 
 #else	/* ZIMAGE */
 
-	.macro	store_primary_cpu_mode	reg1:req, reg2:req, reg3:req
+	.macro	store_primary_cpu_mode	reg1:req, reg2:req
 	.endm
 
 /*
  * The zImage loader only runs on one CPU, so we don't bother with mult-CPU
  * consistency checking:
  */
-	.macro	compare_cpu_mode_with_primary mode, reg1, reg2, reg3
+	.macro	compare_cpu_mode_with_primary mode, reg1, reg2
 	cmp	\mode, \mode
 	.endm
 
@@ -85,7 +82,7 @@ ENTRY(__boot_cpu_mode)
  */
 @ Call this from the primary CPU
 ENTRY(__hyp_stub_install)
-	store_primary_cpu_mode	r4, r5, r6
+	store_primary_cpu_mode	r4, r5
 ENDPROC(__hyp_stub_install)
 
 	@ fall through...
@@ -99,7 +96,7 @@ ENTRY(__hyp_stub_install_secondary)
 	 * If the secondary has booted with a different mode, give up
 	 * immediately.
 	 */
-	compare_cpu_mode_with_primary	r4, r5, r6, r7
+	compare_cpu_mode_with_primary	r4, r5, r6
 	retne	lr
 
 	/*
@@ -264,12 +261,6 @@ ENTRY(__hyp_reset_vectors)
 	ret	lr
 ENDPROC(__hyp_reset_vectors)
 
-#ifndef ZIMAGE
-.align 2
-.L__boot_cpu_mode_offset:
-	.long	__boot_cpu_mode - .
-#endif
-
 .align 5
 ENTRY(__hyp_stub_vectors)
 __hyp_stub_reset:	W(b)	.
diff --git a/arch/arm/kvm/init.S b/arch/arm/kvm/init.S
index 5386528665b5..d777c6fbd869 100644
--- a/arch/arm/kvm/init.S
+++ b/arch/arm/kvm/init.S
@@ -143,13 +143,7 @@ reset:
 	bic	r1, r1, r0
 	mcr	p15, 4, r1, c1, c0, 0	@ HSCTLR
 
-	/*
-	 * Install stub vectors, using ardb's VA->PA trick.
-	 */
-0:	adr	r0, 0b					@ PA(0)
-	movw	r1, #:lower16:__hyp_stub_vectors - 0b   @ VA(stub) - VA(0)
-	movt	r1, #:upper16:__hyp_stub_vectors - 0b
-	add	r1, r1, r0				@ PA(stub)
+	adr_l	r1, __hyp_stub_vectors			@ PA(stub)
 	mcr	p15, 4, r1, c12, c0, 0	@ HVBAR
 	b	exit
 
-- 
2.11.0

[PATCH 10/15] arm-soc: exynos: replace open coded VA->PA conversions

[Ard Biesheuvel]

This replaces a couple of open coded calculations to obtain the
physical address of a far symbol with calls to the new adr_l etc
macros.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 arch/arm/mach-exynos/headsmp.S |  9 +------
 arch/arm/mach-exynos/sleep.S   | 26 ++++----------------
 2 files changed, 6 insertions(+), 29 deletions(-)

diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S
index d3d24ab351ae..25de5aff1c41 100644
--- a/arch/arm/mach-exynos/headsmp.S
+++ b/arch/arm/mach-exynos/headsmp.S
@@ -23,10 +23,7 @@ ENTRY(exynos4_secondary_startup)
 ARM_BE8(setend	be)
 	mrc	p15, 0, r0, c0, c0, 5
 	and	r0, r0, #15
-	adr	r4, 1f
-	ldmia	r4, {r5, r6}
-	sub	r4, r4, r5
-	add	r6, r6, r4
+	adr_l	r6, pen_release
 pen:	ldr	r7, [r6]
 	cmp	r7, r0
 	bne	pen
@@ -37,7 +34,3 @@ pen:	ldr	r7, [r6]
 	 */
 	b	secondary_startup
 ENDPROC(exynos4_secondary_startup)
-
-	.align 2
-1:	.long	.
-	.long	pen_release
diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S
index cf950790fbdc..003465699263 100644
--- a/arch/arm/mach-exynos/sleep.S
+++ b/arch/arm/mach-exynos/sleep.S
@@ -17,6 +17,7 @@
 
 #include <linux/linkage.h>
 #include <asm/asm-offsets.h>
+#include <asm/assembler.h>
 #include <asm/hardware/cache-l2x0.h>
 #include "smc.h"
 
@@ -62,19 +63,13 @@ ENTRY(exynos_cpu_resume_ns)
 	cmp	r0, r1
 	bne	skip_cp15
 
-	adr	r0, _cp15_save_power
-	ldr	r1, [r0]
-	ldr	r1, [r0, r1]
-	adr	r0, _cp15_save_diag
-	ldr	r2, [r0]
-	ldr	r2, [r0, r2]
+	ldr_l	r1, cp15_save_power
+	ldr_l	r2, cp15_save_diag
 	mov	r0, #SMC_CMD_C15RESUME
 	dsb
 	smc	#0
 #ifdef CONFIG_CACHE_L2X0
-	adr	r0, 1f
-	ldr	r2, [r0]
-	add	r0, r2, r0
+	adr_l	r0, l2x0_saved_regs
 
 	/* Check that the address has been initialised. */
 	ldr	r1, [r0, #L2X0_R_PHY_BASE]
@@ -93,9 +88,7 @@ ENTRY(exynos_cpu_resume_ns)
 	smc	#0
 
 	/* Reload saved regs pointer because smc corrupts registers. */
-	adr	r0, 1f
-	ldr	r2, [r0]
-	add	r0, r2, r0
+	adr_l	r0, l2x0_saved_regs
 
 	ldr	r1, [r0, #L2X0_R_PWR_CTRL]
 	ldr	r2, [r0, #L2X0_R_AUX_CTRL]
@@ -114,15 +107,6 @@ skip_cp15:
 	b	cpu_resume
 ENDPROC(exynos_cpu_resume_ns)
 
-	.align
-_cp15_save_power:
-	.long	cp15_save_power - .
-_cp15_save_diag:
-	.long	cp15_save_diag - .
-#ifdef CONFIG_CACHE_L2X0
-1:	.long	l2x0_saved_regs - .
-#endif /* CONFIG_CACHE_L2X0 */
-
 	.data
 	.globl cp15_save_diag
 cp15_save_diag:
-- 
2.11.0

[PATCH 11/15] arm-soc: mvebu: replace open coded VA->PA conversion

[Ard Biesheuvel]

This replaces an open coded calculation to obtain the physical
address of a far symbol with a call to the new ldr_l etc macro.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 arch/arm/mach-mvebu/coherency_ll.S | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
index 8b2fbc8b6bc6..df0ccb5cef1d 100644
--- a/arch/arm/mach-mvebu/coherency_ll.S
+++ b/arch/arm/mach-mvebu/coherency_ll.S
@@ -42,9 +42,7 @@ ENTRY(ll_get_coherency_base)
 	ldr	r1, =coherency_base
 	cmp	r1, #0
 	beq	2f
-	adr	r1, 3f
-	ldr	r3, [r1]
-	ldr	r1, [r1, r3]
+	ldr_l	r1, coherency_phys_base
 	b	2f
 1:
 	/*
@@ -160,7 +158,3 @@ ENTRY(ll_disable_coherency)
 	dsb
 	ret	lr
 ENDPROC(ll_disable_coherency)
-
-	.align 2
-3:
-	.long	coherency_phys_base - .
-- 
2.11.0

[PATCH 12/15] arm-soc: omap: replace open coded VA->PA calculations

[Ard Biesheuvel]

This replaces a couple of open coded calculations to obtain the
physical address of a far symbol with calls to the new adr_l etc
macros.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 arch/arm/mach-omap2/sleep34xx.S | 21 ++++----------------
 arch/arm/mach-omap2/sleep44xx.S | 12 ++---------
 2 files changed, 6 insertions(+), 27 deletions(-)

diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 1b9f0520dea9..418a4478622d 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -86,9 +86,7 @@ ENTRY(enable_omap3630_toggle_l2_on_restore)
 	stmfd	sp!, {lr}	@ save registers on stack
 	/* Setup so that we will disable and enable l2 */
 	mov	r1, #0x1
-	adrl	r3, l2dis_3630_offset	@ may be too distant for plain adr
-	ldr	r2, [r3]		@ value for offset
-	str	r1, [r2, r3]		@ write to l2dis_3630
+	str_l	r1, l2dis_3630, r2	@ write to l2dis_3630
 	ldmfd	sp!, {pc}	@ restore regs and return
 ENDPROC(enable_omap3630_toggle_l2_on_restore)
 
@@ -422,9 +420,7 @@ ENTRY(omap3_restore)
 	cmp	r2, #0x0	@ Check if target power state was OFF or RET
 	bne	logic_l1_restore
 
-	adr	r1, l2dis_3630_offset	@ address for offset
-	ldr	r0, [r1]		@ value for offset
-	ldr	r0, [r1, r0]		@ value at l2dis_3630
+	ldr_l	r0, l2dis_3630	@ value at l2dis_3630
 	cmp	r0, #0x1	@ should we disable L2 on 3630?
 	bne	skipl2dis
 	mrc	p15, 0, r0, c1, c0, 1
@@ -436,9 +432,7 @@ skipl2dis:
 	and	r1, #0x700
 	cmp	r1, #0x300
 	beq	l2_inv_gp
-	adr	r0, l2_inv_api_params_offset
-	ldr	r3, [r0]
-	add	r3, r3, r0		@ r3 points to dummy parameters
+	adr_l	r3, l2_inv_api_params	@ r3 points to dummy parameters
 	mov	r0, #40			@ set service ID for PPA
 	mov	r12, r0			@ copy secure Service ID in r12
 	mov	r1, #0			@ set task id for ROM code in r1
@@ -476,9 +470,6 @@ skipl2dis:
 #endif
 	b	logic_l1_restore
 
-	.align
-l2_inv_api_params_offset:
-	.long	l2_inv_api_params - .
 l2_inv_gp:
 	/* Execute smi to invalidate L2 cache */
 	mov r12, #0x1			@ set up to invalidate L2
@@ -495,9 +486,7 @@ l2_inv_gp:
 	mov	r12, #0x2
 	smc	#0			@ Call SMI monitor (smieq)
 logic_l1_restore:
-	adr	r0, l2dis_3630_offset	@ adress for offset
-	ldr	r1, [r0]		@ value for offset
-	ldr	r1, [r0, r1]		@ value at l2dis_3630
+	ldr_l	r1, l2dis_3630		@ value at l2dis_3630
 	cmp	r1, #0x1		@ Test if L2 re-enable needed on 3630
 	bne	skipl2reen
 	mrc	p15, 0, r1, c1, c0, 1
@@ -526,8 +515,6 @@ control_stat:
 	.word	CONTROL_STAT
 control_mem_rta:
 	.word	CONTROL_MEM_RTA_CTRL
-l2dis_3630_offset:
-	.long	l2dis_3630 - .
 
 	.data
 l2dis_3630:
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index c7a3b4aab4b5..274fbb91f08f 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -260,9 +260,7 @@ ENTRY(omap4_cpu_resume)
 	beq	skip_ns_smp_enable
 ppa_actrl_retry:
 	mov     r0, #OMAP4_PPA_CPU_ACTRL_SMP_INDEX
-	adr	r1, ppa_zero_params_offset
-	ldr	r3, [r1]
-	add	r3, r3, r1			@ Pointer to ppa_zero_params
+	adr_l	r3, ppa_zero_params		@ Pointer to ppa_zero_params
 	mov	r1, #0x0			@ Process ID
 	mov	r2, #0x4			@ Flag
 	mov	r6, #0xff
@@ -299,9 +297,7 @@ skip_ns_smp_enable:
 	ldr     r0, =OMAP4_PPA_L2_POR_INDEX
 	ldr     r1, =OMAP44XX_SAR_RAM_BASE
 	ldr     r4, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
-	adr     r1, ppa_por_params_offset
-	ldr	r3, [r1]
-	add	r3, r3, r1			@ Pointer to ppa_por_params
+	adr_l	r3, ppa_por_params		@ Pointer to ppa_por_params
 	str     r4, [r3, #0x04]
 	mov	r1, #0x0			@ Process ID
 	mov	r2, #0x4			@ Flag
@@ -326,8 +322,6 @@ skip_l2en:
 #endif
 
 	b	cpu_resume			@ Jump to generic resume
-ppa_por_params_offset:
-	.long	ppa_por_params - .
 ENDPROC(omap4_cpu_resume)
 #endif	/* CONFIG_ARCH_OMAP4 */
 
@@ -380,8 +374,6 @@ ENTRY(omap_do_wfi)
 	nop
 
 	ldmfd	sp!, {pc}
-ppa_zero_params_offset:
-	.long	ppa_zero_params - .
 ENDPROC(omap_do_wfi)
 
 	.data
-- 
2.11.0

[PATCH 13/15] arm-soc: various: replace open coded VA->PA calculation of pen_release

[Ard Biesheuvel]

This replaces a few copies of the open coded calculations of the
physical address of 'pen_release' in the secondary startup code
of a couple of platforms.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 arch/arm/mach-prima2/headsmp.S    | 11 +++--------
 arch/arm/mach-spear/headsmp.S     | 11 +++--------
 arch/arm/mach-sti/headsmp.S       | 10 +++-------
 arch/arm/plat-versatile/headsmp.S |  9 +--------
 4 files changed, 10 insertions(+), 31 deletions(-)

diff --git a/arch/arm/mach-prima2/headsmp.S b/arch/arm/mach-prima2/headsmp.S
index 209d9fc5c16c..070df700bb38 100644
--- a/arch/arm/mach-prima2/headsmp.S
+++ b/arch/arm/mach-prima2/headsmp.S
@@ -9,6 +9,8 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 
+#include <asm/assembler.h>
+
 /*
  * SIRFSOC specific entry point for secondary CPUs.  This provides
  * a "holding pen" into which all secondary cores are held until we're
@@ -17,10 +19,7 @@
 ENTRY(sirfsoc_secondary_startup)
         mrc     p15, 0, r0, c0, c0, 5
         and     r0, r0, #15
-        adr     r4, 1f
-        ldmia   r4, {r5, r6}
-        sub     r4, r4, r5
-        add     r6, r6, r4
+        adr_l   r6, pen_release
 pen:    ldr     r7, [r6]
         cmp     r7, r0
         bne     pen
@@ -31,7 +30,3 @@ pen:    ldr     r7, [r6]
          */
         b       secondary_startup
 ENDPROC(sirfsoc_secondary_startup)
-
-        .align
-1:      .long   .
-        .long   pen_release
diff --git a/arch/arm/mach-spear/headsmp.S b/arch/arm/mach-spear/headsmp.S
index c52192dc3d9f..4da01b103f33 100644
--- a/arch/arm/mach-spear/headsmp.S
+++ b/arch/arm/mach-spear/headsmp.S
@@ -13,6 +13,8 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 
+#include <asm/assembler.h>
+
 	__INIT
 
 /*
@@ -23,10 +25,7 @@
 ENTRY(spear13xx_secondary_startup)
 	mrc	p15, 0, r0, c0, c0, 5
 	and	r0, r0, #15
-	adr	r4, 1f
-	ldmia	r4, {r5, r6}
-	sub	r4, r4, r5
-	add	r6, r6, r4
+	adr_l	r6, pen_release
 pen:	ldr	r7, [r6]
 	cmp	r7, r0
 	bne	pen
@@ -40,8 +39,4 @@ pen:	ldr	r7, [r6]
 	 * should now contain the SVC stack for this core
 	 */
 	b	secondary_startup
-
-	.align
-1:	.long	.
-	.long	pen_release
 ENDPROC(spear13xx_secondary_startup)
diff --git a/arch/arm/mach-sti/headsmp.S b/arch/arm/mach-sti/headsmp.S
index e0ad451700d5..cdf3442f397b 100644
--- a/arch/arm/mach-sti/headsmp.S
+++ b/arch/arm/mach-sti/headsmp.S
@@ -16,6 +16,8 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 
+#include <asm/assembler.h>
+
 /*
  * ST specific entry point for secondary CPUs.  This provides
  * a "holding pen" into which all secondary cores are held until we're
@@ -24,10 +26,7 @@
 ENTRY(sti_secondary_startup)
 	mrc	p15, 0, r0, c0, c0, 5
 	and	r0, r0, #15
-	adr	r4, 1f
-	ldmia	r4, {r5, r6}
-	sub	r4, r4, r5
-	add	r6, r6, r4
+	adr_l	r6, pen_release
 pen:	ldr	r7, [r6]
 	cmp	r7, r0
 	bne	pen
@@ -38,6 +37,3 @@ pen:	ldr	r7, [r6]
 	 */
 	b	secondary_startup
 ENDPROC(sti_secondary_startup)
-
-1:	.long	.
-	.long	pen_release
diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S
index 40f27e52de75..0f2a5eddac5a 100644
--- a/arch/arm/plat-versatile/headsmp.S
+++ b/arch/arm/plat-versatile/headsmp.S
@@ -21,10 +21,7 @@ ENTRY(versatile_secondary_startup)
  ARM_BE8(setend	be)
 	mrc	p15, 0, r0, c0, c0, 5
 	bic	r0, #0xff000000
-	adr	r4, 1f
-	ldmia	r4, {r5, r6}
-	sub	r4, r4, r5
-	add	r6, r6, r4
+	adr_l	r6, pen_release
 pen:	ldr	r7, [r6]
 	cmp	r7, r0
 	bne	pen
@@ -34,8 +31,4 @@ pen:	ldr	r7, [r6]
 	 * should now contain the SVC stack for this core
 	 */
 	b	secondary_startup
-
-	.align
-1:	.long	.
-	.long	pen_release
 ENDPROC(versatile_secondary_startup)
-- 
2.11.0

[PATCH 14/15] arm-soc: shmobile: replace open coded VA->PA calculation

[Ard Biesheuvel]

This replaces a couple of open coded calculations to obtain the
physical address of a far symbol with calls to the new adr_l etc
macros.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 arch/arm/mach-shmobile/headsmp.S | 14 ++++----------
 1 file changed, 4 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index 32e0bf6e3ccb..f5e0d7c93cda 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -46,11 +46,10 @@ ENTRY(shmobile_smp_boot)
 	and	r0, r1, #0xffffff		@ MPIDR_HWID_BITMASK
 						@ r0 = cpu_logical_map() value
 	mov	r1, #0				@ r1 = CPU index
-	adr	r2, 1f
-	ldmia	r2, {r5, r6, r7}
-	add	r5, r5, r2			@ array of per-cpu mpidr values
-	add	r6, r6, r2			@ array of per-cpu functions
-	add	r7, r7, r2			@ array of per-cpu arguments
+
+	adr_l	r5, shmobile_smp_mpidr		@ array of per-cpu mpidr values
+	adr_l	r6, shmobile_smp_fn		@ array of per-cpu functions
+	adr_l	r7, shmobile_smp_arg		@ array of per-cpu arguments
 
 shmobile_smp_boot_find_mpidr:
 	ldr	r8, [r5, r1, lsl #2]
@@ -78,11 +77,6 @@ ENTRY(shmobile_smp_sleep)
 	b	shmobile_smp_boot
 ENDPROC(shmobile_smp_sleep)
 
-	.align	2
-1:	.long	shmobile_smp_mpidr - .
-	.long	shmobile_smp_fn - 1b
-	.long	shmobile_smp_arg - 1b
-
 	.bss
 	.globl	shmobile_smp_mpidr
 shmobile_smp_mpidr:
-- 
2.11.0

[PATCH 15/15] ARM: l2c: replace open coded VA->PA calculation

[Ard Biesheuvel]

This replaces an open coded calculation to obtain the physical
address of a far symbol with a call to the new adr_l macro.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 arch/arm/mm/l2c-l2x0-resume.S | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/arch/arm/mm/l2c-l2x0-resume.S b/arch/arm/mm/l2c-l2x0-resume.S
index fda415e4ca8f..3e75aa8c1aff 100644
--- a/arch/arm/mm/l2c-l2x0-resume.S
+++ b/arch/arm/mm/l2c-l2x0-resume.S
@@ -12,9 +12,7 @@
 	.text
 
 ENTRY(l2c310_early_resume)
-	adr	r0, 1f
-	ldr	r2, [r0]
-	add	r0, r2, r0
+	adr_l	r0, l2x0_saved_regs
 
 	ldmia	r0, {r1, r2, r3, r4, r5, r6, r7, r8}
 	@ r1 = phys address of L2C-310 controller
@@ -54,6 +52,3 @@ ENTRY(l2c310_early_resume)
 	str	r9, [r1, #L2X0_CTRL]
 	ret	lr
 ENDPROC(l2c310_early_resume)
-
-	.align
-1:	.long	l2x0_saved_regs - .
-- 
2.11.0

Re: [PATCH 01/15] ARM: assembler: introduce adr_l, ldr_l and str_l macros

[Nicolas Pitre]

On Sat, 5 Aug 2017, Ard Biesheuvel wrote:

> Like arm64, ARM supports position independent code sequences that
> produce symbol references with a greater reach than the ordinary
> adr/ldr instructions.
> 
> Currently, we use open coded instruction sequences involving literals
> and arithmetic operations. Instead, we can use movw/movt pairs on v7
> CPUs, circumventing the D-cache entirely. For older CPUs, we can emit
> the literal into a subsection, allowing it to be emitted out of line
> while retaining the ability to perform arithmetic on label offsets.
> 
> E.g., on pre-v7 CPUs, we can emit a PC-relative reference as follows:
> 
>        ldr          <reg>, 222f
>   111: add          <reg>, <reg>, pc
>        .subsection  1
>   222: .long        <sym> - (111b + 8)
>        .previous
> 
> This is allowed by the assembler because, unlike ordinary sections,
> subsections are combined into a single section into the object file,
> and so the label references are not true cross-section references that
> are visible as relocations. Note that we could even do something like
> 
>        add          <reg>, pc, #(222f - 111f) & ~0xfff
>        ldr          <reg>, [<reg>, #(222f - 111f) & 0xfff]
>   111: add          <reg>, <reg>, pc
>        .subsection  1
>   222: .long        <sym> - (111b + 8)
>        .previous
> 
> if it turns out that the 4 KB range of the ldr instruction is insufficient
> to reach the literal in the subsection, although this is currently not a
> problem (of the 98 objects built from .S files in a multi_v7_defconfig
> build, only 11 have .text sections that are over 1 KB, and the largest one
> [entry-armv.o] is 3308 bytes)
> 
> Subsections have been available in binutils since 2004 at least, so
> they should not cause any issues with older toolchains.
> 
> So use the above to implement the macros mov_l, adr_l, adrm_l (using ldm
> to load multiple literals at once), ldr_l and str_l, all of which will
> use movw/movt pairs on v7 and later CPUs, and use PC-relative literals
> otherwise.

There is no adrm_l definition in this patch.

Also, might it be better to change mov_l to movl? Tthis looks similar to 
the ARM64 movl pseudo-instruction, and unlike all the other _l variants, 
this is not producing a pc relative result.

Talking about the _l suffix: I wonder if this could be more meaningful, 
like _rel maybe? At least in the adr_l case, this could easily be 
confused with adrl.

Otherwise I like it pretty much.


> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
>  arch/arm/include/asm/assembler.h | 70 ++++++++++++++++++++
>  1 file changed, 70 insertions(+)
> 
> diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
> index ad301f107dd2..cedf59a7f853 100644
> --- a/arch/arm/include/asm/assembler.h
> +++ b/arch/arm/include/asm/assembler.h
> @@ -518,4 +518,74 @@ THUMB(	orr	\reg , \reg , #PSR_T_BIT	)
>  #endif
>  	.endm
>  
> +#ifdef CONFIG_THUMB2_KERNEL
> +#define	ARM_PC_BIAS		4
> +#else
> +#define	ARM_PC_BIAS		8
> +#endif
> +
> +	.macro		__adldst_l, op, reg, sym, tmp
> +	.if		__LINUX_ARM_ARCH__ < 7
> +	ldr		\tmp, 111f
> +	.subsection	1
> +	.align		2
> +111:	.long		\sym - (222f + ARM_PC_BIAS)
> +	.previous
> +	.else
> +	movw		\tmp, #:lower16:\sym - (222f + ARM_PC_BIAS)
> +	movt		\tmp, #:upper16:\sym - (222f + ARM_PC_BIAS)
> +	.endif
> +222:;	.ifc		\op, add
> +	add		\reg, \tmp, pc
> +	.elseif		CONFIG_THUMB2_KERNEL == 1
> +	add		\tmp, \tmp, pc
> +	\op		\reg, [\tmp]
> +	.else
> +	\op		\reg, [pc, \tmp]
> +	.endif
> +	.endm
> +
> +	/*
> +	 * mov_l - move a constant value or [relocated] address into a register
> +	 */
> +	.macro		mov_l, dst:req, imm:req
> +	.if		__LINUX_ARM_ARCH__ < 7
> +	ldr		\dst, =\imm
> +	.else
> +	movw		\dst, #:lower16:\imm
> +	movt		\dst, #:upper16:\imm
> +	.endif
> +	.endm
> +
> +	/*
> +	 * adr_l - adr pseudo-op with unlimited range
> +	 *
> +	 * @dst: destination register
> +	 * @sym: name of the symbol
> +	 */
> +	.macro		adr_l, dst:req, sym:req
> +	__adldst_l	add, \dst, \sym, \dst
> +	.endm
> +
> +	/*
> +	 * ldr_l - ldr <literal> pseudo-op with unlimited range
> +	 *
> +	 * @dst: destination register
> +	 * @sym: name of the symbol
> +	 */
> +	.macro		ldr_l, dst:req, sym:req
> +	__adldst_l	ldr, \dst, \sym, \dst
> +	.endm
> +
> +	/*
> +	 * str_l - str <literal> pseudo-op with unlimited range
> +	 *
> +	 * @src: source register
> +	 * @sym: name of the symbol
> +	 * @tmp: mandatory scratch register
> +	 */
> +	.macro		str_l, src:req, sym:req, tmp:req
> +	__adldst_l	str, \src, \sym, \tmp
> +	.endm
> +
>  #endif /* __ASM_ASSEMBLER_H__ */
> -- 
> 2.11.0
> 
> 

Re: [PATCH 01/15] ARM: assembler: introduce adr_l, ldr_l and str_l macros

[Ard Biesheuvel]

On 8 August 2017 at 16:10, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
> On Sat, 5 Aug 2017, Ard Biesheuvel wrote:
>
>> Like arm64, ARM supports position independent code sequences that
>> produce symbol references with a greater reach than the ordinary
>> adr/ldr instructions.
>>
>> Currently, we use open coded instruction sequences involving literals
>> and arithmetic operations. Instead, we can use movw/movt pairs on v7
>> CPUs, circumventing the D-cache entirely. For older CPUs, we can emit
>> the literal into a subsection, allowing it to be emitted out of line
>> while retaining the ability to perform arithmetic on label offsets.
>>
>> E.g., on pre-v7 CPUs, we can emit a PC-relative reference as follows:
>>
>>        ldr          <reg>, 222f
>>   111: add          <reg>, <reg>, pc
>>        .subsection  1
>>   222: .long        <sym> - (111b + 8)
>>        .previous
>>
>> This is allowed by the assembler because, unlike ordinary sections,
>> subsections are combined into a single section into the object file,
>> and so the label references are not true cross-section references that
>> are visible as relocations. Note that we could even do something like
>>
>>        add          <reg>, pc, #(222f - 111f) & ~0xfff
>>        ldr          <reg>, [<reg>, #(222f - 111f) & 0xfff]
>>   111: add          <reg>, <reg>, pc
>>        .subsection  1
>>   222: .long        <sym> - (111b + 8)
>>        .previous
>>
>> if it turns out that the 4 KB range of the ldr instruction is insufficient
>> to reach the literal in the subsection, although this is currently not a
>> problem (of the 98 objects built from .S files in a multi_v7_defconfig
>> build, only 11 have .text sections that are over 1 KB, and the largest one
>> [entry-armv.o] is 3308 bytes)
>>
>> Subsections have been available in binutils since 2004 at least, so
>> they should not cause any issues with older toolchains.
>>
>> So use the above to implement the macros mov_l, adr_l, adrm_l (using ldm
>> to load multiple literals at once), ldr_l and str_l, all of which will
>> use movw/movt pairs on v7 and later CPUs, and use PC-relative literals
>> otherwise.
>
> There is no adrm_l definition in this patch.
>

Ah yes, I played around with it but it becomes a bit clunky so I removed it:

        adrl         <reg1>, 222f
        ldm          <reg1>, {<reg1>, <reg2>}
   111: add          <reg1>, <reg1>, pc
        add          <reg2>, <reg2>, pc
        .subsection  1
   222: .long        <sym1> - (111b + 8)
        .long        <sym2> - (111b + 12)
        .previous

The adrl pseudo op always assembles to two instructions, so you need 5
instructions while using adr_l twice uses only 4. I am not sure if
eliminating one of the loads would make a huge difference, given that
there are no use cases for adrm_l on hot paths, at least not in this
series.

> Also, might it be better to change mov_l to movl? Tthis looks similar to
> the ARM64 movl pseudo-instruction, and unlike all the other _l variants,
> this is not producing a pc relative result.
>

On arm64, we have mov_q for a 64-bit absolute load, and I thought
mov_l was less confusing than mov_w. In general, I like the underscore
in the middle because on the one hand, it looks like a ordinary
mnemonic but on the other hand, it is obvious that it is not a true
instruction. mov_abs perhaps?

> Talking about the _l suffix: I wonder if this could be more meaningful,
> like _rel maybe? At least in the adr_l case, this could easily be
> confused with adrl.
>

On arm64, we have ldr_l, str_l and adr_l as well, and I usually try to
align between ARM and arm64 if I can.

> Otherwise I like it pretty much.
>

Thanks!

Re: [PATCH 01/15] ARM: assembler: introduce adr_l, ldr_l and str_l macros

[Nicolas Pitre]

On Tue, 8 Aug 2017, Ard Biesheuvel wrote:

> On 8 August 2017 at 16:10, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
> > On Sat, 5 Aug 2017, Ard Biesheuvel wrote:
> >
> >> Like arm64, ARM supports position independent code sequences that
> >> produce symbol references with a greater reach than the ordinary
> >> adr/ldr instructions.
> >>
> >> Currently, we use open coded instruction sequences involving literals
> >> and arithmetic operations. Instead, we can use movw/movt pairs on v7
> >> CPUs, circumventing the D-cache entirely. For older CPUs, we can emit
> >> the literal into a subsection, allowing it to be emitted out of line
> >> while retaining the ability to perform arithmetic on label offsets.
> >>
> >> E.g., on pre-v7 CPUs, we can emit a PC-relative reference as follows:
> >>
> >>        ldr          <reg>, 222f
> >>   111: add          <reg>, <reg>, pc
> >>        .subsection  1
> >>   222: .long        <sym> - (111b + 8)
> >>        .previous
> >>
> >> This is allowed by the assembler because, unlike ordinary sections,
> >> subsections are combined into a single section into the object file,
> >> and so the label references are not true cross-section references that
> >> are visible as relocations. Note that we could even do something like
> >>
> >>        add          <reg>, pc, #(222f - 111f) & ~0xfff
> >>        ldr          <reg>, [<reg>, #(222f - 111f) & 0xfff]
> >>   111: add          <reg>, <reg>, pc
> >>        .subsection  1
> >>   222: .long        <sym> - (111b + 8)
> >>        .previous
> >>
> >> if it turns out that the 4 KB range of the ldr instruction is insufficient
> >> to reach the literal in the subsection, although this is currently not a
> >> problem (of the 98 objects built from .S files in a multi_v7_defconfig
> >> build, only 11 have .text sections that are over 1 KB, and the largest one
> >> [entry-armv.o] is 3308 bytes)
> >>
> >> Subsections have been available in binutils since 2004 at least, so
> >> they should not cause any issues with older toolchains.
> >>
> >> So use the above to implement the macros mov_l, adr_l, adrm_l (using ldm
> >> to load multiple literals at once), ldr_l and str_l, all of which will
> >> use movw/movt pairs on v7 and later CPUs, and use PC-relative literals
> >> otherwise.
> >
> > There is no adrm_l definition in this patch.
> >
> 
> Ah yes, I played around with it but it becomes a bit clunky so I removed it:
> 
>         adrl         <reg1>, 222f
>         ldm          <reg1>, {<reg1>, <reg2>}
>    111: add          <reg1>, <reg1>, pc
>         add          <reg2>, <reg2>, pc
>         .subsection  1
>    222: .long        <sym1> - (111b + 8)
>         .long        <sym2> - (111b + 12)
>         .previous
> 
> The adrl pseudo op always assembles to two instructions, so you need 5
> instructions while using adr_l twice uses only 4. I am not sure if
> eliminating one of the loads would make a huge difference, given that
> there are no use cases for adrm_l on hot paths, at least not in this
> series.

I'd suggest you keep it to a minimum.  Using adr_l twice is clear and 
obvious.

> > Also, might it be better to change mov_l to movl? Tthis looks similar to
> > the ARM64 movl pseudo-instruction, and unlike all the other _l variants,
> > this is not producing a pc relative result.
> >
> 
> On arm64, we have mov_q for a 64-bit absolute load, and I thought
> mov_l was less confusing than mov_w. In general, I like the underscore
> in the middle because on the one hand, it looks like a ordinary
> mnemonic but on the other hand, it is obvious that it is not a true
> instruction. mov_abs perhaps?
> 
> > Talking about the _l suffix: I wonder if this could be more meaningful,
> > like _rel maybe? At least in the adr_l case, this could easily be
> > confused with adrl.
> >
> 
> On arm64, we have ldr_l, str_l and adr_l as well, and I usually try to
> align between ARM and arm64 if I can.

OK. I'm much less versed into ARM64 assembly so I'll defer to your 
judgment.  It's good if this mnemonic scheme already exists there with 
a similar meaning.


Nicolas

Re: [PATCH 12/15] arm-soc: omap: replace open coded VA->PA calculations

[Tony Lindgren]

* Ard Biesheuvel <ard.biesheuvel@linaro.org> [170805 13:54]:
> This replaces a couple of open coded calculations to obtain the
> physical address of a far symbol with calls to the new adr_l etc
> macros.

I gave this series a quick test and omap3 no longer boots it seems.

Regards,

Tony

Re: [PATCH 12/15] arm-soc: omap: replace open coded VA->PA calculations

[Ard Biesheuvel]

On 9 August 2017 at 20:05, Tony Lindgren <tony@atomide.com> wrote:
> * Ard Biesheuvel <ard.biesheuvel@linaro.org> [170805 13:54]:
>> This replaces a couple of open coded calculations to obtain the
>> physical address of a far symbol with calls to the new adr_l etc
>> macros.
>
> I gave this series a quick test and omap3 no longer boots it seems.
>

Thanks Tony. I will investigate

Re: [PATCH 12/15] arm-soc: omap: replace open coded VA->PA calculations

[Tony Lindgren]

* Ard Biesheuvel <ard.biesheuvel@linaro.org> [170809 12:24]:
> On 9 August 2017 at 20:05, Tony Lindgren <tony@atomide.com> wrote:
> > * Ard Biesheuvel <ard.biesheuvel@linaro.org> [170805 13:54]:
> >> This replaces a couple of open coded calculations to obtain the
> >> physical address of a far symbol with calls to the new adr_l etc
> >> macros.
> >
> > I gave this series a quick test and omap3 no longer boots it seems.
> >
> 
> Thanks Tony. I will investigate

Thanks. Looks like omap4 still boots with all your patches, but
omap3 won't boot even with patch 12 left out.

Regards,

Tony

Re: [PATCH 12/15] arm-soc: omap: replace open coded VA->PA calculations

[Ard Biesheuvel]

On 9 August 2017 at 22:05, Tony Lindgren <tony@atomide.com> wrote:
> * Ard Biesheuvel <ard.biesheuvel@linaro.org> [170809 12:24]:
>> On 9 August 2017 at 20:05, Tony Lindgren <tony@atomide.com> wrote:
>> > * Ard Biesheuvel <ard.biesheuvel@linaro.org> [170805 13:54]:
>> >> This replaces a couple of open coded calculations to obtain the
>> >> physical address of a far symbol with calls to the new adr_l etc
>> >> macros.
>> >
>> > I gave this series a quick test and omap3 no longer boots it seems.
>> >
>>
>> Thanks Tony. I will investigate
>
> Thanks. Looks like omap4 still boots with all your patches, but
> omap3 won't boot even with patch 12 left out.
>

Are you using the same image on both? Which .config?

Re: [PATCH 12/15] arm-soc: omap: replace open coded VA->PA calculations

[Tony Lindgren]

* Ard Biesheuvel <ard.biesheuvel@linaro.org> [170810 02:23]:
> On 9 August 2017 at 22:05, Tony Lindgren <tony@atomide.com> wrote:
> > * Ard Biesheuvel <ard.biesheuvel@linaro.org> [170809 12:24]:
> >> On 9 August 2017 at 20:05, Tony Lindgren <tony@atomide.com> wrote:
> >> > * Ard Biesheuvel <ard.biesheuvel@linaro.org> [170805 13:54]:
> >> >> This replaces a couple of open coded calculations to obtain the
> >> >> physical address of a far symbol with calls to the new adr_l etc
> >> >> macros.
> >> >
> >> > I gave this series a quick test and omap3 no longer boots it seems.
> >> >
> >>
> >> Thanks Tony. I will investigate
> >
> > Thanks. Looks like omap4 still boots with all your patches, but
> > omap3 won't boot even with patch 12 left out.
> >
> 
> Are you using the same image on both? Which .config?

Yes it's the same image compiled with omap2plus_defconfig.

Regards,

Tony

Re: [PATCH 12/15] arm-soc: omap: replace open coded VA->PA calculations

[Ard Biesheuvel]

On 10 August 2017 at 15:03, Tony Lindgren <tony@atomide.com> wrote:
> * Ard Biesheuvel <ard.biesheuvel@linaro.org> [170810 02:23]:
>> On 9 August 2017 at 22:05, Tony Lindgren <tony@atomide.com> wrote:
>> > * Ard Biesheuvel <ard.biesheuvel@linaro.org> [170809 12:24]:
>> >> On 9 August 2017 at 20:05, Tony Lindgren <tony@atomide.com> wrote:
>> >> > * Ard Biesheuvel <ard.biesheuvel@linaro.org> [170805 13:54]:
>> >> >> This replaces a couple of open coded calculations to obtain the
>> >> >> physical address of a far symbol with calls to the new adr_l etc
>> >> >> macros.
>> >> >
>> >> > I gave this series a quick test and omap3 no longer boots it seems.
>> >> >
>> >>
>> >> Thanks Tony. I will investigate
>> >
>> > Thanks. Looks like omap4 still boots with all your patches, but
>> > omap3 won't boot even with patch 12 left out.
>> >
>>
>> Are you using the same image on both? Which .config?
>
> Yes it's the same image compiled with omap2plus_defconfig.
>

Unfortunately, I am failing to reproduce this on beaglebone white or
QEMU's beagle-xm emulation.

Anything you can share regarding the failure mode? Do you get any output at all?

Re: [PATCH 12/15] arm-soc: omap: replace open coded VA->PA calculations

[Tony Lindgren]

* Ard Biesheuvel <ard.biesheuvel@linaro.org> [170811 06:48]:
> On 10 August 2017 at 15:03, Tony Lindgren <tony@atomide.com> wrote:
> > * Ard Biesheuvel <ard.biesheuvel@linaro.org> [170810 02:23]:
> >> On 9 August 2017 at 22:05, Tony Lindgren <tony@atomide.com> wrote:
> >> > * Ard Biesheuvel <ard.biesheuvel@linaro.org> [170809 12:24]:
> >> >> On 9 August 2017 at 20:05, Tony Lindgren <tony@atomide.com> wrote:
> >> >> > * Ard Biesheuvel <ard.biesheuvel@linaro.org> [170805 13:54]:
> >> >> >> This replaces a couple of open coded calculations to obtain the
> >> >> >> physical address of a far symbol with calls to the new adr_l etc
> >> >> >> macros.
> >> >> >
> >> >> > I gave this series a quick test and omap3 no longer boots it seems.
> >> >> >
> >> >>
> >> >> Thanks Tony. I will investigate
> >> >
> >> > Thanks. Looks like omap4 still boots with all your patches, but
> >> > omap3 won't boot even with patch 12 left out.
> >> >
> >>
> >> Are you using the same image on both? Which .config?
> >
> > Yes it's the same image compiled with omap2plus_defconfig.
> >
> 
> Unfortunately, I am failing to reproduce this on beaglebone white or
> QEMU's beagle-xm emulation.
> 
> Anything you can share regarding the failure mode? Do you get any output at all?

No output at all, I've tried omap3-evm, logicpd torpedo
and n900. We do copy some of the PM code to SRAM on
omap3 though that's not done on am335x.

But as it's not caused by this patch, I'll try to
narrow it down to the patch causing it.

Regards,

Tony

Re: [PATCH 05/15] ARM: head: use PC-relative insn sequence for __smp_alt

[Tony Lindgren]

* Ard Biesheuvel <ard.biesheuvel@linaro.org> [170805 13:54]:
> Replace the open coded PC relative offset calculations with a pair
> of adr_l invocations.
> 
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
>  arch/arm/kernel/head.S | 12 ++----------
>  1 file changed, 2 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> index 6e9df3663a57..aed341e0f530 100644
> --- a/arch/arm/kernel/head.S
> +++ b/arch/arm/kernel/head.S
> @@ -523,19 +523,11 @@ ARM_BE8(rev	r0, r0)			@ byteswap if big endian
>  	retne	lr
>  
>  __fixup_smp_on_up:
> -	adr	r0, 1f
> -	ldmia	r0, {r3 - r5}
> -	sub	r3, r0, r3
> -	add	r4, r4, r3
> -	add	r5, r5, r3
> +	adr_l	r4, __smpalt_begin
> +	adr_l	r5, __smpalt_end
>  	b	__do_fixup_smp_on_up
>  ENDPROC(__fixup_smp)
>  
> -	.align
> -1:	.word	.
> -	.word	__smpalt_begin
> -	.word	__smpalt_end
> -
>  	.pushsection .data
>  	.globl	smp_on_up
>  smp_on_up:

Ard, it's this one that cause boot to fail on omap3.
The rest of your set works for me with just this one
left out.

Regards,

Tony

Re: [PATCH 05/15] ARM: head: use PC-relative insn sequence for __smp_alt

[Ard Biesheuvel]

On 11 August 2017 at 16:13, Tony Lindgren <tony@atomide.com> wrote:
> * Ard Biesheuvel <ard.biesheuvel@linaro.org> [170805 13:54]:
>> Replace the open coded PC relative offset calculations with a pair
>> of adr_l invocations.
>>
>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> ---
>>  arch/arm/kernel/head.S | 12 ++----------
>>  1 file changed, 2 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
>> index 6e9df3663a57..aed341e0f530 100644
>> --- a/arch/arm/kernel/head.S
>> +++ b/arch/arm/kernel/head.S
>> @@ -523,19 +523,11 @@ ARM_BE8(rev     r0, r0)                 @ byteswap if big endian
>>       retne   lr
>>
>>  __fixup_smp_on_up:
>> -     adr     r0, 1f
>> -     ldmia   r0, {r3 - r5}
>> -     sub     r3, r0, r3
>> -     add     r4, r4, r3
>> -     add     r5, r5, r3
>> +     adr_l   r4, __smpalt_begin
>> +     adr_l   r5, __smpalt_end
>>       b       __do_fixup_smp_on_up
>>  ENDPROC(__fixup_smp)
>>
>> -     .align
>> -1:   .word   .
>> -     .word   __smpalt_begin
>> -     .word   __smpalt_end
>> -
>>       .pushsection .data
>>       .globl  smp_on_up
>>  smp_on_up:
>
> Ard, it's this one that cause boot to fail on omap3.
> The rest of your set works for me with just this one
> left out.
>

I'm completely puzzled. The change is so simple that it is difficult
to reduce it in parts, but if you still have the time to spare, mind
trying the diff below?


diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 6e9df3663a57..c0361e608210 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -524,17 +524,15 @@ ARM_BE8(rev       r0, r0)                 @
byteswap if big endian

 __fixup_smp_on_up:
        adr     r0, 1f
-       ldmia   r0, {r3 - r5}
-       sub     r3, r0, r3
-       add     r4, r4, r3
-       add     r5, r5, r3
+       ldmia   r0, {r4 - r5}
+       add     r4, r4, r0
+       add     r5, r5, r0
        b       __do_fixup_smp_on_up
 ENDPROC(__fixup_smp)

        .align
-1:     .word   .
-       .word   __smpalt_begin
-       .word   __smpalt_end
+1:     .word   __smpalt_begin - 1b
+       .word   __smpalt_end - 1b

        .pushsection .data
        .globl  smp_on_up

The main point of these changes is to eliminate absolute references,
not to use the new macros, so if this does work, I will go with this
instead.

Re: [PATCH 05/15] ARM: head: use PC-relative insn sequence for __smp_alt

[Nicolas Pitre]

On Fri, 11 Aug 2017, Ard Biesheuvel wrote:

> On 11 August 2017 at 16:13, Tony Lindgren <tony@atomide.com> wrote:
> > * Ard Biesheuvel <ard.biesheuvel@linaro.org> [170805 13:54]:
> >> Replace the open coded PC relative offset calculations with a pair
> >> of adr_l invocations.
> >>
> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> >> ---
> >>  arch/arm/kernel/head.S | 12 ++----------
> >>  1 file changed, 2 insertions(+), 10 deletions(-)
> >>
> >> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> >> index 6e9df3663a57..aed341e0f530 100644
> >> --- a/arch/arm/kernel/head.S
> >> +++ b/arch/arm/kernel/head.S
> >> @@ -523,19 +523,11 @@ ARM_BE8(rev     r0, r0)                 @ byteswap if big endian
> >>       retne   lr
> >>
> >>  __fixup_smp_on_up:
> >> -     adr     r0, 1f
> >> -     ldmia   r0, {r3 - r5}
> >> -     sub     r3, r0, r3
> >> -     add     r4, r4, r3
> >> -     add     r5, r5, r3
> >> +     adr_l   r4, __smpalt_begin
> >> +     adr_l   r5, __smpalt_end
> >>       b       __do_fixup_smp_on_up
> >>  ENDPROC(__fixup_smp)
> >>
> >> -     .align
> >> -1:   .word   .
> >> -     .word   __smpalt_begin
> >> -     .word   __smpalt_end
> >> -
> >>       .pushsection .data
> >>       .globl  smp_on_up
> >>  smp_on_up:
> >
> > Ard, it's this one that cause boot to fail on omap3.
> > The rest of your set works for me with just this one
> > left out.
> >
> 
> I'm completely puzzled.

Found it.

You replaced:

-       adr     r0, 1f
-       ldmia   r0, {r3 - r5}
-       sub     r3, r0, r3
-       add     r4, r4, r3
-       add     r5, r5, r3
+       adr_l   r4, __smpalt_begin
+       adr_l   r5, __smpalt_end
        b       __do_fixup_smp_on_up

Notice that r3 is now uninitialized.

Now have a look at the code for __do_fixup_smp_on_up.


Nicolas

Re: [PATCH 05/15] ARM: head: use PC-relative insn sequence for __smp_alt

[Ard Biesheuvel]

On 11 August 2017 at 20:58, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
> On Fri, 11 Aug 2017, Ard Biesheuvel wrote:
>
>> On 11 August 2017 at 16:13, Tony Lindgren <tony@atomide.com> wrote:
>> > * Ard Biesheuvel <ard.biesheuvel@linaro.org> [170805 13:54]:
>> >> Replace the open coded PC relative offset calculations with a pair
>> >> of adr_l invocations.
>> >>
>> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> >> ---
>> >>  arch/arm/kernel/head.S | 12 ++----------
>> >>  1 file changed, 2 insertions(+), 10 deletions(-)
>> >>
>> >> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
>> >> index 6e9df3663a57..aed341e0f530 100644
>> >> --- a/arch/arm/kernel/head.S
>> >> +++ b/arch/arm/kernel/head.S
>> >> @@ -523,19 +523,11 @@ ARM_BE8(rev     r0, r0)                 @ byteswap if big endian
>> >>       retne   lr
>> >>
>> >>  __fixup_smp_on_up:
>> >> -     adr     r0, 1f
>> >> -     ldmia   r0, {r3 - r5}
>> >> -     sub     r3, r0, r3
>> >> -     add     r4, r4, r3
>> >> -     add     r5, r5, r3
>> >> +     adr_l   r4, __smpalt_begin
>> >> +     adr_l   r5, __smpalt_end
>> >>       b       __do_fixup_smp_on_up
>> >>  ENDPROC(__fixup_smp)
>> >>
>> >> -     .align
>> >> -1:   .word   .
>> >> -     .word   __smpalt_begin
>> >> -     .word   __smpalt_end
>> >> -
>> >>       .pushsection .data
>> >>       .globl  smp_on_up
>> >>  smp_on_up:
>> >
>> > Ard, it's this one that cause boot to fail on omap3.
>> > The rest of your set works for me with just this one
>> > left out.
>> >
>>
>> I'm completely puzzled.
>
> Found it.
>
> You replaced:
>
> -       adr     r0, 1f
> -       ldmia   r0, {r3 - r5}
> -       sub     r3, r0, r3
> -       add     r4, r4, r3
> -       add     r5, r5, r3
> +       adr_l   r4, __smpalt_begin
> +       adr_l   r5, __smpalt_end
>         b       __do_fixup_smp_on_up
>
> Notice that r3 is now uninitialized.
>
> Now have a look at the code for __do_fixup_smp_on_up.
>

I still don't see it :-)

__do_fixup_smp_on_up() mentions r3 in the comment block, but it does
not actually refer to it in the code, does it?

Re: [PATCH 05/15] ARM: head: use PC-relative insn sequence for __smp_alt

[Nicolas Pitre]

On Fri, 11 Aug 2017, Ard Biesheuvel wrote:

> On 11 August 2017 at 20:58, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
> > On Fri, 11 Aug 2017, Ard Biesheuvel wrote:
> >
> >> On 11 August 2017 at 16:13, Tony Lindgren <tony@atomide.com> wrote:
> >> > * Ard Biesheuvel <ard.biesheuvel@linaro.org> [170805 13:54]:
> >> >> Replace the open coded PC relative offset calculations with a pair
> >> >> of adr_l invocations.
> >> >>
> >> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> >> >> ---
> >> >>  arch/arm/kernel/head.S | 12 ++----------
> >> >>  1 file changed, 2 insertions(+), 10 deletions(-)
> >> >>
> >> >> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> >> >> index 6e9df3663a57..aed341e0f530 100644
> >> >> --- a/arch/arm/kernel/head.S
> >> >> +++ b/arch/arm/kernel/head.S
> >> >> @@ -523,19 +523,11 @@ ARM_BE8(rev     r0, r0)                 @ byteswap if big endian
> >> >>       retne   lr
> >> >>
> >> >>  __fixup_smp_on_up:
> >> >> -     adr     r0, 1f
> >> >> -     ldmia   r0, {r3 - r5}
> >> >> -     sub     r3, r0, r3
> >> >> -     add     r4, r4, r3
> >> >> -     add     r5, r5, r3
> >> >> +     adr_l   r4, __smpalt_begin
> >> >> +     adr_l   r5, __smpalt_end
> >> >>       b       __do_fixup_smp_on_up
> >> >>  ENDPROC(__fixup_smp)
> >> >>
> >> >> -     .align
> >> >> -1:   .word   .
> >> >> -     .word   __smpalt_begin
> >> >> -     .word   __smpalt_end
> >> >> -
> >> >>       .pushsection .data
> >> >>       .globl  smp_on_up
> >> >>  smp_on_up:
> >> >
> >> > Ard, it's this one that cause boot to fail on omap3.
> >> > The rest of your set works for me with just this one
> >> > left out.
> >> >
> >>
> >> I'm completely puzzled.
> >
> > Found it.
> >
> > You replaced:
> >
> > -       adr     r0, 1f
> > -       ldmia   r0, {r3 - r5}
> > -       sub     r3, r0, r3
> > -       add     r4, r4, r3
> > -       add     r5, r5, r3
> > +       adr_l   r4, __smpalt_begin
> > +       adr_l   r5, __smpalt_end
> >         b       __do_fixup_smp_on_up
> >
> > Notice that r3 is now uninitialized.
> >
> > Now have a look at the code for __do_fixup_smp_on_up.
> >
> 
> I still don't see it :-)
> 
> __do_fixup_smp_on_up() mentions r3 in the comment block, but it does
> not actually refer to it in the code, does it?

__do_fixup_smp_on_up:
        cmp     r4, r5
        reths   lr
        ldmia   r4!, {r0, r6}
 ARM(   str     r6, [r0, r3]    )	<<============
 THUMB( add     r0, r0, r3      )	<<============
[...]


Nicolas

Re: [PATCH 05/15] ARM: head: use PC-relative insn sequence for __smp_alt

[Ard Biesheuvel]

On 11 August 2017 at 21:06, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
> On Fri, 11 Aug 2017, Ard Biesheuvel wrote:
>
>> On 11 August 2017 at 20:58, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
>> > On Fri, 11 Aug 2017, Ard Biesheuvel wrote:
>> >
>> >> On 11 August 2017 at 16:13, Tony Lindgren <tony@atomide.com> wrote:
>> >> > * Ard Biesheuvel <ard.biesheuvel@linaro.org> [170805 13:54]:
>> >> >> Replace the open coded PC relative offset calculations with a pair
>> >> >> of adr_l invocations.
>> >> >>
>> >> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> >> >> ---
>> >> >>  arch/arm/kernel/head.S | 12 ++----------
>> >> >>  1 file changed, 2 insertions(+), 10 deletions(-)
>> >> >>
>> >> >> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
>> >> >> index 6e9df3663a57..aed341e0f530 100644
>> >> >> --- a/arch/arm/kernel/head.S
>> >> >> +++ b/arch/arm/kernel/head.S
>> >> >> @@ -523,19 +523,11 @@ ARM_BE8(rev     r0, r0)                 @ byteswap if big endian
>> >> >>       retne   lr
>> >> >>
>> >> >>  __fixup_smp_on_up:
>> >> >> -     adr     r0, 1f
>> >> >> -     ldmia   r0, {r3 - r5}
>> >> >> -     sub     r3, r0, r3
>> >> >> -     add     r4, r4, r3
>> >> >> -     add     r5, r5, r3
>> >> >> +     adr_l   r4, __smpalt_begin
>> >> >> +     adr_l   r5, __smpalt_end
>> >> >>       b       __do_fixup_smp_on_up
>> >> >>  ENDPROC(__fixup_smp)
>> >> >>
>> >> >> -     .align
>> >> >> -1:   .word   .
>> >> >> -     .word   __smpalt_begin
>> >> >> -     .word   __smpalt_end
>> >> >> -
>> >> >>       .pushsection .data
>> >> >>       .globl  smp_on_up
>> >> >>  smp_on_up:
>> >> >
>> >> > Ard, it's this one that cause boot to fail on omap3.
>> >> > The rest of your set works for me with just this one
>> >> > left out.
>> >> >
>> >>
>> >> I'm completely puzzled.
>> >
>> > Found it.
>> >
>> > You replaced:
>> >
>> > -       adr     r0, 1f
>> > -       ldmia   r0, {r3 - r5}
>> > -       sub     r3, r0, r3
>> > -       add     r4, r4, r3
>> > -       add     r5, r5, r3
>> > +       adr_l   r4, __smpalt_begin
>> > +       adr_l   r5, __smpalt_end
>> >         b       __do_fixup_smp_on_up
>> >
>> > Notice that r3 is now uninitialized.
>> >
>> > Now have a look at the code for __do_fixup_smp_on_up.
>> >
>>
>> I still don't see it :-)
>>
>> __do_fixup_smp_on_up() mentions r3 in the comment block, but it does
>> not actually refer to it in the code, does it?
>
> __do_fixup_smp_on_up:
>         cmp     r4, r5
>         reths   lr
>         ldmia   r4!, {r0, r6}
>  ARM(   str     r6, [r0, r3]    )       <<============
>  THUMB( add     r0, r0, r3      )       <<============
> [...]
>

Aahhh

Looking at the wrong version of the file.

Thanks for spotting that.

Re: [PATCH 05/15] ARM: head: use PC-relative insn sequence for __smp_alt

[Nicolas Pitre]

On Fri, 11 Aug 2017, Ard Biesheuvel wrote:

> On 11 August 2017 at 21:06, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
> > On Fri, 11 Aug 2017, Ard Biesheuvel wrote:
> >
> >> On 11 August 2017 at 20:58, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
> >> > On Fri, 11 Aug 2017, Ard Biesheuvel wrote:
> >> >
> >> >> On 11 August 2017 at 16:13, Tony Lindgren <tony@atomide.com> wrote:
> >> >> > * Ard Biesheuvel <ard.biesheuvel@linaro.org> [170805 13:54]:
> >> >> >> Replace the open coded PC relative offset calculations with a pair
> >> >> >> of adr_l invocations.
> >> >> >>
> >> >> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> >> >> >> ---
> >> >> >>  arch/arm/kernel/head.S | 12 ++----------
> >> >> >>  1 file changed, 2 insertions(+), 10 deletions(-)
> >> >> >>
> >> >> >> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> >> >> >> index 6e9df3663a57..aed341e0f530 100644
> >> >> >> --- a/arch/arm/kernel/head.S
> >> >> >> +++ b/arch/arm/kernel/head.S
> >> >> >> @@ -523,19 +523,11 @@ ARM_BE8(rev     r0, r0)                 @ byteswap if big endian
> >> >> >>       retne   lr
> >> >> >>
> >> >> >>  __fixup_smp_on_up:
> >> >> >> -     adr     r0, 1f
> >> >> >> -     ldmia   r0, {r3 - r5}
> >> >> >> -     sub     r3, r0, r3
> >> >> >> -     add     r4, r4, r3
> >> >> >> -     add     r5, r5, r3
> >> >> >> +     adr_l   r4, __smpalt_begin
> >> >> >> +     adr_l   r5, __smpalt_end
> >> >> >>       b       __do_fixup_smp_on_up
> >> >> >>  ENDPROC(__fixup_smp)
> >> >> >>
> >> >> >> -     .align
> >> >> >> -1:   .word   .
> >> >> >> -     .word   __smpalt_begin
> >> >> >> -     .word   __smpalt_end
> >> >> >> -
> >> >> >>       .pushsection .data
> >> >> >>       .globl  smp_on_up
> >> >> >>  smp_on_up:
> >> >> >
> >> >> > Ard, it's this one that cause boot to fail on omap3.
> >> >> > The rest of your set works for me with just this one
> >> >> > left out.
> >> >> >
> >> >>
> >> >> I'm completely puzzled.
> >> >
> >> > Found it.
> >> >
> >> > You replaced:
> >> >
> >> > -       adr     r0, 1f
> >> > -       ldmia   r0, {r3 - r5}
> >> > -       sub     r3, r0, r3
> >> > -       add     r4, r4, r3
> >> > -       add     r5, r5, r3
> >> > +       adr_l   r4, __smpalt_begin
> >> > +       adr_l   r5, __smpalt_end
> >> >         b       __do_fixup_smp_on_up
> >> >
> >> > Notice that r3 is now uninitialized.
> >> >
> >> > Now have a look at the code for __do_fixup_smp_on_up.
> >> >
> >>
> >> I still don't see it :-)
> >>
> >> __do_fixup_smp_on_up() mentions r3 in the comment block, but it does
> >> not actually refer to it in the code, does it?
> >
> > __do_fixup_smp_on_up:
> >         cmp     r4, r5
> >         reths   lr
> >         ldmia   r4!, {r0, r6}
> >  ARM(   str     r6, [r0, r3]    )       <<============
> >  THUMB( add     r0, r0, r3      )       <<============
> > [...]
> >
> 
> Aahhh
> 
> Looking at the wrong version of the file.
> 
> Thanks for spotting that.

No problem. Can't attribute that to my sharp eyes though.  :-)


Nicolas

Re: [PATCH 05/15] ARM: head: use PC-relative insn sequence for __smp_alt

[Tony Lindgren]

* Ard Biesheuvel <ard.biesheuvel@linaro.org> [170811 12:37]:
> On 11 August 2017 at 16:13, Tony Lindgren <tony@atomide.com> wrote:
> > * Ard Biesheuvel <ard.biesheuvel@linaro.org> [170805 13:54]:
> >> Replace the open coded PC relative offset calculations with a pair
> >> of adr_l invocations.
> >>
> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> >> ---
> >>  arch/arm/kernel/head.S | 12 ++----------
> >>  1 file changed, 2 insertions(+), 10 deletions(-)
> >>
> >> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> >> index 6e9df3663a57..aed341e0f530 100644
> >> --- a/arch/arm/kernel/head.S
> >> +++ b/arch/arm/kernel/head.S
> >> @@ -523,19 +523,11 @@ ARM_BE8(rev     r0, r0)                 @ byteswap if big endian
> >>       retne   lr
> >>
> >>  __fixup_smp_on_up:
> >> -     adr     r0, 1f
> >> -     ldmia   r0, {r3 - r5}
> >> -     sub     r3, r0, r3
> >> -     add     r4, r4, r3
> >> -     add     r5, r5, r3
> >> +     adr_l   r4, __smpalt_begin
> >> +     adr_l   r5, __smpalt_end
> >>       b       __do_fixup_smp_on_up
> >>  ENDPROC(__fixup_smp)
> >>
> >> -     .align
> >> -1:   .word   .
> >> -     .word   __smpalt_begin
> >> -     .word   __smpalt_end
> >> -
> >>       .pushsection .data
> >>       .globl  smp_on_up
> >>  smp_on_up:
> >
> > Ard, it's this one that cause boot to fail on omap3.
> > The rest of your set works for me with just this one
> > left out.
> >
> 
> I'm completely puzzled. The change is so simple that it is difficult
> to reduce it in parts, but if you still have the time to spare, mind
> trying the diff below?
> 
> 
> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> index 6e9df3663a57..c0361e608210 100644
> --- a/arch/arm/kernel/head.S
> +++ b/arch/arm/kernel/head.S
> @@ -524,17 +524,15 @@ ARM_BE8(rev       r0, r0)                 @
> byteswap if big endian
> 
>  __fixup_smp_on_up:
>         adr     r0, 1f
> -       ldmia   r0, {r3 - r5}
> -       sub     r3, r0, r3
> -       add     r4, r4, r3
> -       add     r5, r5, r3
> +       ldmia   r0, {r4 - r5}
> +       add     r4, r4, r0
> +       add     r5, r5, r0
>         b       __do_fixup_smp_on_up
>  ENDPROC(__fixup_smp)
> 
>         .align
> -1:     .word   .
> -       .word   __smpalt_begin
> -       .word   __smpalt_end
> +1:     .word   __smpalt_begin - 1b
> +       .word   __smpalt_end - 1b
> 
>         .pushsection .data
>         .globl  smp_on_up
> 
> The main point of these changes is to eliminate absolute references,
> not to use the new macros, so if this does work, I will go with this
> instead.

For reference, I manually did this changes as it did not apply
after reverting your earlier version of this patch. No luck with
this change, so I'll test again when you you have updated patches
available.

Regards,

Tony

Re: [PATCH 05/15] ARM: head: use PC-relative insn sequence for __smp_alt

[Ard Biesheuvel]

On 14 August 2017 at 17:19, Tony Lindgren <tony@atomide.com> wrote:
> * Ard Biesheuvel <ard.biesheuvel@linaro.org> [170811 12:37]:
>> On 11 August 2017 at 16:13, Tony Lindgren <tony@atomide.com> wrote:
>> > * Ard Biesheuvel <ard.biesheuvel@linaro.org> [170805 13:54]:
>> >> Replace the open coded PC relative offset calculations with a pair
>> >> of adr_l invocations.
>> >>
>> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> >> ---
>> >>  arch/arm/kernel/head.S | 12 ++----------
>> >>  1 file changed, 2 insertions(+), 10 deletions(-)
>> >>
>> >> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
>> >> index 6e9df3663a57..aed341e0f530 100644
>> >> --- a/arch/arm/kernel/head.S
>> >> +++ b/arch/arm/kernel/head.S
>> >> @@ -523,19 +523,11 @@ ARM_BE8(rev     r0, r0)                 @ byteswap if big endian
>> >>       retne   lr
>> >>
>> >>  __fixup_smp_on_up:
>> >> -     adr     r0, 1f
>> >> -     ldmia   r0, {r3 - r5}
>> >> -     sub     r3, r0, r3
>> >> -     add     r4, r4, r3
>> >> -     add     r5, r5, r3
>> >> +     adr_l   r4, __smpalt_begin
>> >> +     adr_l   r5, __smpalt_end
>> >>       b       __do_fixup_smp_on_up
>> >>  ENDPROC(__fixup_smp)
>> >>
>> >> -     .align
>> >> -1:   .word   .
>> >> -     .word   __smpalt_begin
>> >> -     .word   __smpalt_end
>> >> -
>> >>       .pushsection .data
>> >>       .globl  smp_on_up
>> >>  smp_on_up:
>> >
>> > Ard, it's this one that cause boot to fail on omap3.
>> > The rest of your set works for me with just this one
>> > left out.
>> >
>>
>> I'm completely puzzled. The change is so simple that it is difficult
>> to reduce it in parts, but if you still have the time to spare, mind
>> trying the diff below?
>>
>>
>> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
>> index 6e9df3663a57..c0361e608210 100644
>> --- a/arch/arm/kernel/head.S
>> +++ b/arch/arm/kernel/head.S
>> @@ -524,17 +524,15 @@ ARM_BE8(rev       r0, r0)                 @
>> byteswap if big endian
>>
>>  __fixup_smp_on_up:
>>         adr     r0, 1f
>> -       ldmia   r0, {r3 - r5}
>> -       sub     r3, r0, r3
>> -       add     r4, r4, r3
>> -       add     r5, r5, r3
>> +       ldmia   r0, {r4 - r5}
>> +       add     r4, r4, r0
>> +       add     r5, r5, r0
>>         b       __do_fixup_smp_on_up
>>  ENDPROC(__fixup_smp)
>>
>>         .align
>> -1:     .word   .
>> -       .word   __smpalt_begin
>> -       .word   __smpalt_end
>> +1:     .word   __smpalt_begin - 1b
>> +       .word   __smpalt_end - 1b
>>
>>         .pushsection .data
>>         .globl  smp_on_up
>>
>> The main point of these changes is to eliminate absolute references,
>> not to use the new macros, so if this does work, I will go with this
>> instead.
>
> For reference, I manually did this changes as it did not apply
> after reverting your earlier version of this patch. No luck with
> this change, so I'll test again when you you have updated patches
> available.
>

Thanks Tony,

But Nico already found the issue: I was looking at the code with
another patch on top, which removed the reference to r3 in the
followup code.

In the KASLR series I just posted, I reordered that patch with this
one, so everything should be good.