From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Markovic" <amarkovic@wavecomp.com>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Eduardo Habkost" <ehabkost@redhat.com>,
"Thomas Huth" <thuth@redhat.com>,
"Igor Mammedov" <imammedo@redhat.com>,
"Anthony Perard" <anthony.perard@citrix.com>,
"Stefano Stabellini" <sstabellini@kernel.org>,
"Paul Durrant" <paul@xen.org>,
"Hervé Poussineau" <hpoussin@reactos.org>,
"Aleksandar Rikalo" <aleksandar.rikalo@rt-rk.com>,
xen-devel@lists.xenproject.org,
"Laurent Vivier" <lvivier@redhat.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Richard Henderson" <rth@twiddle.net>,
kvm@vger.kernel.org, "Philippe Mathieu-Daudé" <philmd@redhat.com>
Subject: [PATCH 27/32] hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
Date: Tue, 15 Oct 2019 18:27:00 +0200 [thread overview]
Message-ID: <20191015162705.28087-28-philmd@redhat.com> (raw)
In-Reply-To: <20191015162705.28087-1-philmd@redhat.com>
The IRQ Route Control registers definitions belong to the PIIX
chipset. We were only defining the 'A' register. Define the other
B, C and D registers, and use them.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/i386/xen/xen-hvm.c | 5 +++--
hw/mips/gt64xxx_pci.c | 4 ++--
hw/pci-host/piix.c | 9 ++++-----
include/hw/southbridge/piix.h | 6 ++++++
4 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c
index 6b5e5bb7f5..4ce2fb9c89 100644
--- a/hw/i386/xen/xen-hvm.c
+++ b/hw/i386/xen/xen-hvm.c
@@ -14,6 +14,7 @@
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
#include "hw/irq.h"
#include "hw/hw.h"
#include "hw/i386/apic-msidef.h"
@@ -156,8 +157,8 @@ void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len)
v = 0;
}
v &= 0xf;
- if (((address + i) >= 0x60) && ((address + i) <= 0x63)) {
- xen_set_pci_link_route(xen_domid, address + i - 0x60, v);
+ if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) {
+ xen_set_pci_link_route(xen_domid, address + i - PIIX_PIRQCA, v);
}
}
}
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index c277398c0d..5cab9c1ee1 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -1013,12 +1013,12 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
/* now we change the pic irq level according to the piix irq mappings */
/* XXX: optimize */
- pic_irq = piix4_dev->config[0x60 + irq_num];
+ pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
if (pic_irq < 16) {
/* The pic level is the logical OR of all the PCI irqs mapped to it. */
pic_level = 0;
for (i = 0; i < 4; i++) {
- if (pic_irq == piix4_dev->config[0x60 + i]) {
+ if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
pic_level |= pci_irq_levels[i];
}
}
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 3770575c1a..a450fc726e 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -61,7 +61,6 @@ typedef struct I440FXState {
#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
#define XEN_PIIX_NUM_PIRQS 128ULL
-#define PIIX_PIRQC 0x60
typedef struct PIIX3State {
PCIDevice dev;
@@ -468,7 +467,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
int pic_irq;
uint64_t mask;
- pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
+ pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
if (pic_irq >= PIIX_NUM_PIC_IRQS) {
return;
}
@@ -482,7 +481,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
{
int pic_irq;
- pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
+ pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
if (pic_irq >= PIIX_NUM_PIC_IRQS) {
return;
}
@@ -501,7 +500,7 @@ static void piix3_set_irq(void *opaque, int pirq, int level)
static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
{
PIIX3State *piix3 = opaque;
- int irq = piix3->dev.config[PIIX_PIRQC + pin];
+ int irq = piix3->dev.config[PIIX_PIRQCA + pin];
PCIINTxRoute route;
if (irq < PIIX_NUM_PIC_IRQS) {
@@ -530,7 +529,7 @@ static void piix3_write_config(PCIDevice *dev,
uint32_t address, uint32_t val, int len)
{
pci_default_write_config(dev, address, val, len);
- if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
+ if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
int pic_irq;
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 79ebe0089b..9c92c37a4d 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq, qemu_irq smi_irq,
int smm_enabled, DeviceState **piix4_pm);
+/* PIRQRC[A:D]: PIRQx Route Control Registers */
+#define PIIX_PIRQCA 0x60
+#define PIIX_PIRQCB 0x61
+#define PIIX_PIRQCC 0x62
+#define PIIX_PIRQCD 0x63
+
/*
* Reset Control Register: PCI-accessible ISA-Compatible Register at address
* 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
--
2.21.0
next prev parent reply other threads:[~2019-10-15 16:32 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-15 16:26 [PATCH 00/32] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge Philippe Mathieu-Daudé
2019-10-15 16:26 ` [PATCH 01/32] hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers Philippe Mathieu-Daudé
2019-10-15 16:29 ` Philippe Mathieu-Daudé
2019-11-01 10:19 ` Dr. David Alan Gilbert
2019-10-15 16:26 ` [PATCH 02/32] hw/i386/pc: Move kvm_i8259_init() declaration to sysemu/kvm.h Philippe Mathieu-Daudé
2019-10-17 15:04 ` Thomas Huth
2019-10-17 15:31 ` Philippe Mathieu-Daudé
2019-10-17 15:40 ` Thomas Huth
[not found] ` <CAL1e-=iC9hR-jqTSu9c6KtgiNWFwftnTMq9W87NWFPb37hjCoA@mail.gmail.com>
2019-10-17 15:08 ` Philippe Mathieu-Daudé
2019-10-15 16:26 ` [PATCH 03/32] mc146818rtc: move structure to header file Philippe Mathieu-Daudé
2019-10-15 16:26 ` [PATCH 04/32] mc146818rtc: Move RTC_ISA_IRQ definition Philippe Mathieu-Daudé
[not found] ` <CAL1e-=jOiMe2--=ht0Wgwh0a_At=sDhUzX7EkNU86nPt230a-g@mail.gmail.com>
2019-10-17 15:12 ` Philippe Mathieu-Daudé
2019-10-15 16:26 ` [PATCH 05/32] mc146818rtc: Include "mc146818rtc_regs.h" directly in mc146818rtc.c Philippe Mathieu-Daudé
2019-10-15 16:26 ` [PATCH 06/32] mc146818rtc: always register rtc to rtc list Philippe Mathieu-Daudé
2019-10-15 16:26 ` [PATCH 07/32] MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets Philippe Mathieu-Daudé
2019-10-15 16:26 ` [PATCH 08/32] piix4: rename some variables in realize function Philippe Mathieu-Daudé
2019-10-17 15:13 ` Thomas Huth
2019-10-15 16:26 ` [PATCH 09/32] piix4: add Reset Control Register Philippe Mathieu-Daudé
2019-10-15 16:26 ` [PATCH 10/32] piix4: add a i8259 interrupt controller as specified in datasheet Philippe Mathieu-Daudé
2019-10-15 16:26 ` [PATCH 11/32] Revert "irq: introduce qemu_irq_proxy()" Philippe Mathieu-Daudé
2019-10-17 15:16 ` Thomas Huth
2019-10-15 16:26 ` [PATCH 12/32] piix4: rename PIIX4 object to piix4-isa Philippe Mathieu-Daudé
2019-10-15 16:26 ` [PATCH 13/32] piix4: convert reset function to QOM Philippe Mathieu-Daudé
2019-10-15 16:26 ` [PATCH 14/32] piix4: add a i8257 dma controller as specified in datasheet Philippe Mathieu-Daudé
2019-10-17 15:19 ` Thomas Huth
2019-10-15 16:26 ` [PATCH 15/32] piix4: add a i8254 pit " Philippe Mathieu-Daudé
2019-10-15 16:26 ` [PATCH 16/32] piix4: add a mc146818rtc " Philippe Mathieu-Daudé
2019-10-15 16:26 ` [PATCH 17/32] hw/mips/mips_malta: Create IDE hard drive array dynamically Philippe Mathieu-Daudé
2019-10-15 16:26 ` [PATCH 18/32] hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create() Philippe Mathieu-Daudé
2019-10-15 16:26 ` [PATCH 19/32] hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c Philippe Mathieu-Daudé
2019-10-15 16:26 ` [PATCH 20/32] hw/i386/pc: Extract pc_gsi_create() Philippe Mathieu-Daudé
2019-10-17 15:33 ` Thomas Huth
2019-10-15 16:26 ` [PATCH 21/32] hw/i386/pc: Reduce gsi_handler scope Philippe Mathieu-Daudé
[not found] ` <CAL1e-=hLUDDqFiV8W1f2PFGYJMomvmZUXmjA55X7WEEYMykjHQ@mail.gmail.com>
2019-10-17 15:37 ` Philippe Mathieu-Daudé
2019-10-17 15:41 ` Thomas Huth
2019-10-15 16:26 ` [PATCH 22/32] hw/i386/pc: Move gsi_state creation code Philippe Mathieu-Daudé
2019-10-15 16:26 ` [PATCH 23/32] hw/i386/pc: Extract pc_i8259_create() Philippe Mathieu-Daudé
2019-10-15 16:26 ` [PATCH 24/32] hw/i386/pc: Remove kvm_i386.h include Philippe Mathieu-Daudé
2019-10-15 16:26 ` [PATCH 25/32] hw/pci-host/piix: Extract piix3_create() Philippe Mathieu-Daudé
2019-10-15 16:26 ` [PATCH 26/32] hw/pci-host/piix: Move RCR_IOPORT register definition Philippe Mathieu-Daudé
[not found] ` <CAL1e-=jVr+idQKNdOGSrODeq7XU-0JcCFTwapqk9-JvAKxk6Pw@mail.gmail.com>
2019-10-18 10:13 ` Philippe Mathieu-Daudé
2019-10-15 16:27 ` Philippe Mathieu-Daudé [this message]
2019-10-16 11:24 ` [PATCH 27/32] hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers Paul Durrant
2019-10-15 16:27 ` [PATCH 28/32] hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h Philippe Mathieu-Daudé
2019-10-15 16:27 ` [PATCH 29/32] hw/pci-host/piix: Fix code style issues Philippe Mathieu-Daudé
2019-10-15 16:27 ` [PATCH 30/32] hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c Philippe Mathieu-Daudé
2019-10-15 16:27 ` [PATCH 31/32] hw/pci-host: Rename incorrectly named 'piix' as 'i440fx' Philippe Mathieu-Daudé
2019-10-15 16:27 ` [PATCH 32/32] hw/pci-host/i440fx: Remove the last PIIX3 traces Philippe Mathieu-Daudé
2019-10-16 4:13 ` [PATCH 00/32] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge no-reply
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