From: "Andersen, John" <john.s.andersen@intel.com>
To: Dave Hansen <dave.hansen@intel.com>
Cc: corbet@lwn.net, pbonzini@redhat.com, tglx@linutronix.de,
mingo@redhat.com, bp@alien8.de, x86@kernel.org, hpa@zytor.com,
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eric.auger@redhat.com, aaronlewis@google.com, peterx@redhat.com,
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linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
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kernel-hardening@lists.openwall.com
Subject: Re: [PATCH 2/4] KVM: x86: Introduce paravirt feature CR0/CR4 pinning
Date: Thu, 18 Jun 2020 14:43:14 +0000 [thread overview]
Message-ID: <20200618144314.GB23@258ff54ff3c0> (raw)
In-Reply-To: <0fa9682e-59d4-75f7-366f-103d6b8e71b8@intel.com>
On Thu, Jun 18, 2020 at 07:18:09AM -0700, Dave Hansen wrote:
> On 6/17/20 12:07 PM, John Andersen wrote:
> > +#define KVM_CR0_PIN_ALLOWED (X86_CR0_WP)
> > +#define KVM_CR4_PIN_ALLOWED (X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP)
>
> Why *is* there an allowed set? Why don't we just allow everything?
>
> Shouldn't we also pin any unknown bits? The CR4.FSGSBASE bit is an
> example of something that showed up CPUs without Linux knowing about it.
> If set, it causes problems. This set couldn't have helped FSGSBASE
> because it is not in the allowed set.
>
> Let's say Intel loses its marbles and adds a CR4 bit that lets userspace
> write to kernel memory. Linux won't set it, but an attacker would go
> after it, first thing.
The allowed set came about because there were comments from internal review
where it was said that allowing the guest to pin TS and MP adds unnecessary
complexity.
Also because KVM always intercepts these bits via the CR0/4_GUEST_HOST_MASK. If
we allow setting of any bits, then we have to add some infrastructure for
modifying the mask when pinned bits are updated. I have a patch for that if we
want to go that route, but it doesn't account for the added complexity
mentioned above.
next prev parent reply other threads:[~2020-06-18 14:47 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-17 19:07 [PATCH 0/4] Paravirtualized Control Register pinning John Andersen
2020-06-17 19:07 ` [PATCH 1/4] X86: Update mmu_cr4_features during feature identification John Andersen
2020-06-18 14:09 ` Dave Hansen
2020-06-17 19:07 ` [PATCH 2/4] KVM: x86: Introduce paravirt feature CR0/CR4 pinning John Andersen
2020-06-18 14:18 ` Dave Hansen
2020-06-18 14:43 ` Andersen, John [this message]
2020-06-18 14:51 ` Dave Hansen
2020-07-07 21:12 ` Sean Christopherson
2020-07-07 21:48 ` Dave Hansen
2020-07-07 21:51 ` Paolo Bonzini
2020-07-09 15:44 ` Andersen, John
2020-07-09 15:56 ` Dave Hansen
[not found] ` <CALCETrWxt0CHUoonWX1fgbM46ydJPQZhj8Q=G+45EG4wW3wZqQ@mail.gmail.com>
2020-07-09 16:22 ` Dave Hansen
2020-07-09 23:37 ` Kees Cook
[not found] ` <CALCETrUHcpqjDfAM9SbrZUM7xcS2wkVm=r1Nb1JmxV7A-KAeUQ@mail.gmail.com>
2020-07-14 5:36 ` Andersen, John, Arvind Sankar
2020-07-14 5:39 ` Andersen, John
2020-07-15 4:41 ` Sean Christopherson
2020-07-15 19:58 ` Andersen, John
2020-06-17 19:07 ` [PATCH 3/4] selftests: kvm: add test for CR pinning with SMM John Andersen
2020-06-17 19:07 ` [PATCH 4/4] X86: Use KVM CR pin MSRs John Andersen
2020-06-18 14:41 ` Dave Hansen
2020-06-18 15:26 ` Andersen, John
2020-06-18 15:38 ` Dave Hansen
2020-06-18 15:49 ` Andersen, John
2020-06-20 5:13 ` Andy Lutomirski
2020-06-23 20:03 ` Andersen, John
2020-07-03 21:48 ` Andersen, John
2020-07-04 15:11 ` Arvind Sankar
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