From: Like Xu <like.xu@linux.intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>
Cc: Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
kvm@vger.kernel.org, x86@kernel.org, wei.w.wang@intel.com,
linux-kernel@vger.kernel.org, Like Xu <like.xu@linux.intel.com>,
Kan Liang <kan.liang@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Borislav Petkov <bp@alien8.de>, Ingo Molnar <mingo@redhat.com>,
Andi Kleen <ak@linux.intel.com>
Subject: [PATCH v4 02/11] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers
Date: Sun, 14 Mar 2021 23:52:15 +0800 [thread overview]
Message-ID: <20210314155225.206661-3-like.xu@linux.intel.com> (raw)
In-Reply-To: <20210314155225.206661-1-like.xu@linux.intel.com>
If the platform supports LBR_INFO register, the x86_pmu.lbr_info will
be assigned in intel_pmu_?_lbr_init_?() and it's safe to expose LBR_INFO
in the x86_perf_get_lbr() directly, instead of relying on lbr_format check.
Also Architectural LBR has IA32_LBR_x_INFO instead of LBR_FORMAT_INFO_x
to hold metadata for the operation, including mispredict, TSX, and
elapsed cycle time information.
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Ingo Molnar <mingo@redhat.com>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/events/intel/lbr.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index 21890dacfcfe..355ea70f1879 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -1832,12 +1832,10 @@ void __init intel_pmu_arch_lbr_init(void)
*/
int x86_perf_get_lbr(struct x86_pmu_lbr *lbr)
{
- int lbr_fmt = x86_pmu.intel_cap.lbr_format;
-
lbr->nr = x86_pmu.lbr_nr;
lbr->from = x86_pmu.lbr_from;
lbr->to = x86_pmu.lbr_to;
- lbr->info = (lbr_fmt == LBR_FORMAT_INFO) ? x86_pmu.lbr_info : 0;
+ lbr->info = x86_pmu.lbr_info;
return 0;
}
--
2.29.2
next prev parent reply other threads:[~2021-03-14 16:01 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-14 15:52 [PATCH v4 00/11] KVM: x86/pmu: Guest Architectural LBR Enabling Like Xu
2021-03-14 15:52 ` [PATCH v4 01/11] perf/x86/intel: Fix the comment about guest LBR support on KVM Like Xu
2021-03-14 15:52 ` Like Xu [this message]
2021-03-14 15:52 ` [PATCH v4 03/11] perf/x86/lbr: Skip checking for the existence of LBR_TOS for Arch LBR Like Xu
2021-03-14 15:52 ` [PATCH v4 04/11] perf/x86/lbr: Move cpuc->lbr_xsave allocation out of sleeping region Like Xu
2021-03-14 15:52 ` [PATCH v4 05/11] perf/x86: Move ARCH_LBR_CTL_MASK definition to include/asm/msr-index.h Like Xu
2021-03-14 15:52 ` [PATCH v4 06/11] KVM: vmx/pmu: Add MSR_ARCH_LBR_DEPTH emulation for Arch LBR Like Xu
2021-03-14 15:52 ` [PATCH v4 07/11] KVM: vmx/pmu: Add MSR_ARCH_LBR_CTL " Like Xu
2021-03-14 15:52 ` [PATCH v4 08/11] KVM: vmx/pmu: Add Arch LBR emulation and its VMCS field Like Xu
2021-03-14 15:52 ` [PATCH v4 09/11] KVM: x86: Expose Architectural LBR CPUID leaf Like Xu
2021-03-14 15:52 ` [PATCH v4 10/11] KVM: x86: Refine the matching and clearing logic for supported_xss Like Xu
2021-03-14 15:52 ` [PATCH v4 11/11] KVM: x86: Add XSAVE Support for Architectural LBRs Like Xu
2021-03-14 15:52 ` [PATCH v2] x86: Update guest LBR tests for Architectural LBR Like Xu
2021-03-22 6:18 ` [PATCH v4 00/11] KVM: x86/pmu: Guest Architectural LBR Enabling Xu, Like
2021-04-06 3:19 ` Xu, Like
2021-04-21 2:25 ` Like Xu
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