From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,
kvmarm@lists.cs.columbia.edu
Cc: James Morse <james.morse@arm.com>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Eric Auger <eric.auger@redhat.com>,
Hector Martin <marcan@marcan.st>,
Mark Rutland <mark.rutland@arm.com>,
kernel-team@android.com
Subject: [PATCH 10/11] irqchip/apple-aic: Initialise SYS_APL_VM_TMR_FIQ_ENA_EL1 at boot time
Date: Tue, 16 Mar 2021 17:46:15 +0000 [thread overview]
Message-ID: <20210316174617.173033-11-maz@kernel.org> (raw)
In-Reply-To: <20210316174617.173033-1-maz@kernel.org>
Instead of masking the guest timer at the source, take advantage of
the SYS_APL_VM_TMR_FIQ_ENA_EL1 register and properly mask the
timers at init time.
For a good measure, add the missing ISB that synchronises all
the previous sysreg accesses.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
drivers/irqchip/irq-apple-aic.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-aic.c
index 447c9e87f13a..26ee149dbae3 100644
--- a/drivers/irqchip/irq-apple-aic.c
+++ b/drivers/irqchip/irq-apple-aic.c
@@ -622,8 +622,8 @@ static int aic_init_cpu(unsigned int cpu)
/* Timer FIQs */
sysreg_clear_set(cntp_ctl_el0, 0, ARCH_TIMER_CTRL_IT_MASK);
sysreg_clear_set(cntv_ctl_el0, 0, ARCH_TIMER_CTRL_IT_MASK);
- sysreg_clear_set_s(SYS_CNTP_CTL_EL02, 0, ARCH_TIMER_CTRL_IT_MASK);
- sysreg_clear_set_s(SYS_CNTV_CTL_EL02, 0, ARCH_TIMER_CTRL_IT_MASK);
+ sysreg_clear_set_s(SYS_APL_VM_TMR_FIQ_ENA_EL1,
+ VM_TMR_FIQ_ENABLE_V | VM_TMR_FIQ_ENABLE_P, 0);
/* PMC FIQ */
sysreg_clear_set_s(SYS_APL_PMCR0_EL1, PMCR0_IMODE | PMCR0_IACT,
@@ -633,6 +633,9 @@ static int aic_init_cpu(unsigned int cpu)
sysreg_clear_set_s(SYS_APL_UPMCR0_EL1, UPMCR0_IMODE,
FIELD_PREP(UPMCR0_IMODE, UPMCR0_IMODE_OFF));
+ /* Commit all of the above */
+ isb();
+
/*
* Make sure the kernel's idea of logical CPU order is the same as AIC's
* If we ever end up with a mismatch here, we will have to introduce
--
2.29.2
next prev parent reply other threads:[~2021-03-16 17:54 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-16 17:46 [PATCH 00/11] KVM: arm64: Initial host support for the Apple M1 Marc Zyngier
2021-03-16 17:46 ` [PATCH 01/11] irqchip/gic: Split vGIC probing information from the GIC code Marc Zyngier
2021-03-16 17:46 ` [PATCH 02/11] KVM: arm64: Handle physical FIQ as an IRQ while running a guest Marc Zyngier
2021-03-16 17:46 ` [PATCH 03/11] KVM: arm64: vgic: Be tolerant to the lack of maintenance interrupt Marc Zyngier
2021-03-16 17:46 ` [PATCH 04/11] KVM: arm64: vgic: Let an interrupt controller advertise lack of HW deactivation Marc Zyngier
2021-03-16 17:46 ` [PATCH 05/11] KVM: arm64: vgic: move irq->get_input_level into an ops structure Marc Zyngier
2021-03-16 17:46 ` [PATCH 06/11] KVM: arm64: vgic: Implement SW-driven deactivation Marc Zyngier
2021-03-16 17:46 ` [PATCH 07/11] KVM: arm64: timer: Refactor IRQ configuration Marc Zyngier
2021-03-16 17:46 ` [PATCH 08/11] KVM: arm64: timer: Add support for SW-based deactivation Marc Zyngier
2021-03-16 17:46 ` [PATCH 09/11] irqchip/apple-aic: Fix [un]masking of guest timers Marc Zyngier
2021-03-16 17:46 ` Marc Zyngier [this message]
2021-03-16 17:46 ` [PATCH 11/11] irqchip/apple-aic: Advertise some level of vGICv3 compatibility Marc Zyngier
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