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From: Yifei Jiang <jiangyifei@huawei.com>
To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>
Cc: <kvm-riscv@lists.infradead.org>, <kvm@vger.kernel.org>,
	<libvir-list@redhat.com>, <anup.patel@wdc.com>,
	<palmer@dabbelt.com>, <Alistair.Francis@wdc.com>,
	<bin.meng@windriver.com>, <fanliang@huawei.com>,
	<wu.wubin@huawei.com>, <wanghaibin.wang@huawei.com>,
	<wanbo13@huawei.com>, Yifei Jiang <jiangyifei@huawei.com>,
	Mingwang Li <limingwang@huawei.com>
Subject: [PATCH v1 01/12] update-linux-headers: Add asm-riscv/kvm.h
Date: Sat, 20 Nov 2021 15:46:33 +0800	[thread overview]
Message-ID: <20211120074644.729-2-jiangyifei@huawei.com> (raw)
In-Reply-To: <20211120074644.729-1-jiangyifei@huawei.com>

Add asm-riscv/kvm.h for RISC-V KVM, and update linux/kvm.h

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
---
 linux-headers/asm-riscv/kvm.h | 128 ++++++++++++++++++++++++++++++++++
 linux-headers/linux/kvm.h     |   8 +++
 2 files changed, 136 insertions(+)
 create mode 100644 linux-headers/asm-riscv/kvm.h

diff --git a/linux-headers/asm-riscv/kvm.h b/linux-headers/asm-riscv/kvm.h
new file mode 100644
index 0000000000..f808ad1ce5
--- /dev/null
+++ b/linux-headers/asm-riscv/kvm.h
@@ -0,0 +1,128 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Copyright (C) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *     Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __LINUX_KVM_RISCV_H
+#define __LINUX_KVM_RISCV_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+#include <asm/ptrace.h>
+
+#define __KVM_HAVE_READONLY_MEM
+
+#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
+
+#define KVM_INTERRUPT_SET	-1U
+#define KVM_INTERRUPT_UNSET	-2U
+
+/* for KVM_GET_REGS and KVM_SET_REGS */
+struct kvm_regs {
+};
+
+/* for KVM_GET_FPU and KVM_SET_FPU */
+struct kvm_fpu {
+};
+
+/* KVM Debug exit structure */
+struct kvm_debug_exit_arch {
+};
+
+/* for KVM_SET_GUEST_DEBUG */
+struct kvm_guest_debug_arch {
+};
+
+/* definition of registers in kvm_run */
+struct kvm_sync_regs {
+};
+
+/* for KVM_GET_SREGS and KVM_SET_SREGS */
+struct kvm_sregs {
+};
+
+/* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
+struct kvm_riscv_config {
+	unsigned long isa;
+};
+
+/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
+struct kvm_riscv_core {
+	struct user_regs_struct regs;
+	unsigned long mode;
+};
+
+/* Possible privilege modes for kvm_riscv_core */
+#define KVM_RISCV_MODE_S	1
+#define KVM_RISCV_MODE_U	0
+
+/* CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
+struct kvm_riscv_csr {
+	unsigned long sstatus;
+	unsigned long sie;
+	unsigned long stvec;
+	unsigned long sscratch;
+	unsigned long sepc;
+	unsigned long scause;
+	unsigned long stval;
+	unsigned long sip;
+	unsigned long satp;
+	unsigned long scounteren;
+};
+
+/* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
+struct kvm_riscv_timer {
+	__u64 frequency;
+	__u64 time;
+	__u64 compare;
+	__u64 state;
+};
+
+/* Possible states for kvm_riscv_timer */
+#define KVM_RISCV_TIMER_STATE_OFF	0
+#define KVM_RISCV_TIMER_STATE_ON	1
+
+#define KVM_REG_SIZE(id)		\
+	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
+
+/* If you need to interpret the index values, here is the key: */
+#define KVM_REG_RISCV_TYPE_MASK		0x00000000FF000000
+#define KVM_REG_RISCV_TYPE_SHIFT	24
+
+/* Config registers are mapped as type 1 */
+#define KVM_REG_RISCV_CONFIG		(0x01 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_CONFIG_REG(name)	\
+	(offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))
+
+/* Core registers are mapped as type 2 */
+#define KVM_REG_RISCV_CORE		(0x02 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_CORE_REG(name)	\
+		(offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))
+
+/* Control and status registers are mapped as type 3 */
+#define KVM_REG_RISCV_CSR		(0x03 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_CSR_REG(name)	\
+		(offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
+
+/* Timer registers are mapped as type 4 */
+#define KVM_REG_RISCV_TIMER		(0x04 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_TIMER_REG(name)	\
+		(offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
+
+/* F extension registers are mapped as type 5 */
+#define KVM_REG_RISCV_FP_F		(0x05 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_FP_F_REG(name)	\
+		(offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32))
+
+/* D extension registers are mapped as type 6 */
+#define KVM_REG_RISCV_FP_D		(0x06 << KVM_REG_RISCV_TYPE_SHIFT)
+#define KVM_REG_RISCV_FP_D_REG(name)	\
+		(offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
+
+#endif
+
+#endif /* __LINUX_KVM_RISCV_H */
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index bcaf66cc4d..5e290c3c3e 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -269,6 +269,7 @@ struct kvm_xen_exit {
 #define KVM_EXIT_AP_RESET_HOLD    32
 #define KVM_EXIT_X86_BUS_LOCK     33
 #define KVM_EXIT_XEN              34
+#define KVM_EXIT_RISCV_SBI        35
 
 /* For KVM_EXIT_INTERNAL_ERROR */
 /* Emulate instruction failed. */
@@ -469,6 +470,13 @@ struct kvm_run {
 		} msr;
 		/* KVM_EXIT_XEN */
 		struct kvm_xen_exit xen;
+		/* KVM_EXIT_RISCV_SBI */
+		struct {
+			unsigned long extension_id;
+			unsigned long function_id;
+			unsigned long args[6];
+			unsigned long ret[2];
+		} riscv_sbi;
 		/* Fix the size of the union. */
 		char padding[256];
 	};
-- 
2.19.1


  reply	other threads:[~2021-11-20  7:47 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-20  7:46 [PATCH v1 00/12] Add riscv kvm accel support Yifei Jiang
2021-11-20  7:46 ` Yifei Jiang [this message]
2021-11-23  6:13   ` [PATCH v1 01/12] update-linux-headers: Add asm-riscv/kvm.h Alistair Francis
2021-12-03  5:07   ` Anup Patel
2021-11-20  7:46 ` [PATCH v1 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang
2021-12-03  5:08   ` Anup Patel
2021-11-20  7:46 ` [PATCH v1 03/12] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang
2021-11-20 22:19   ` Richard Henderson
2021-12-10  9:55     ` Jiangyifei
2021-11-20  7:46 ` [PATCH v1 04/12] target/riscv: Implement kvm_arch_get_registers Yifei Jiang
2021-12-03  6:20   ` Anup Patel
2021-12-10  9:57     ` Jiangyifei
2021-11-20  7:46 ` [PATCH v1 05/12] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
2021-12-03  6:22   ` Anup Patel
2021-12-10  9:58     ` Jiangyifei
2021-11-20  7:46 ` [PATCH v1 06/12] target/riscv: Support start kernel directly by KVM Yifei Jiang
2021-12-03  6:31   ` Anup Patel
2021-12-10 10:00     ` Jiangyifei
2021-11-20  7:46 ` [PATCH v1 07/12] target/riscv: Support setting external interrupt " Yifei Jiang
2021-12-03  9:15   ` Anup Patel
2021-12-10 10:01     ` Jiangyifei
2021-11-20  7:46 ` [PATCH v1 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang
2021-11-20 12:24   ` Philippe Mathieu-Daudé
2021-12-10 10:02     ` Jiangyifei
2021-11-20  7:46 ` [PATCH v1 09/12] target/riscv: Add host cpu type Yifei Jiang
2021-12-03  9:26   ` Anup Patel
2021-11-20  7:46 ` [PATCH v1 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang
2021-12-03  9:38   ` Anup Patel
2021-12-10 10:03     ` Jiangyifei
2021-11-20  7:46 ` [PATCH v1 11/12] target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang
2021-11-20  7:46 ` [PATCH v1 12/12] target/riscv: Support virtual time context synchronization Yifei Jiang
2021-11-20 22:34   ` Richard Henderson
2021-12-10 10:03     ` Jiangyifei
2021-12-10 10:11     ` Paolo Bonzini
2021-12-03  8:41 ` [PATCH v1 00/12] Add riscv kvm accel support Michal Prívozník

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