From: Jiangyifei <jiangyifei@huawei.com>
To: Anup Patel <anup@brainfault.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"kvm-riscv@lists.infradead.org" <kvm-riscv@lists.infradead.org>,
KVM General <kvm@vger.kernel.org>,
"libvir-list@redhat.com" <libvir-list@redhat.com>,
Anup Patel <anup.patel@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
"Fanliang (EulerOS)" <fanliang@huawei.com>,
"Wubin (H)" <wu.wubin@huawei.com>,
"Wanghaibin (D)" <wanghaibin.wang@huawei.com>,
"wanbo (G)" <wanbo13@huawei.com>,
"limingwang (A)" <limingwang@huawei.com>
Subject: RE: [PATCH v1 05/12] target/riscv: Implement kvm_arch_put_registers
Date: Fri, 10 Dec 2021 09:58:52 +0000 [thread overview]
Message-ID: <240d9fa6bf214abf8169816e6901fd90@huawei.com> (raw)
In-Reply-To: <CAAhSdy0umeb2Qu=6hJZGy4g1FhW-bsYL=80Msao_pULsJ0+2mw@mail.gmail.com>
> -----Original Message-----
> From: Anup Patel [mailto:anup@brainfault.org]
> Sent: Friday, December 3, 2021 2:22 PM
> To: Jiangyifei <jiangyifei@huawei.com>
> Cc: QEMU Developers <qemu-devel@nongnu.org>; open list:RISC-V
> <qemu-riscv@nongnu.org>; kvm-riscv@lists.infradead.org; KVM General
> <kvm@vger.kernel.org>; libvir-list@redhat.com; Anup Patel
> <anup.patel@wdc.com>; Palmer Dabbelt <palmer@dabbelt.com>; Alistair
> Francis <Alistair.Francis@wdc.com>; Bin Meng <bin.meng@windriver.com>;
> Fanliang (EulerOS) <fanliang@huawei.com>; Wubin (H)
> <wu.wubin@huawei.com>; Wanghaibin (D) <wanghaibin.wang@huawei.com>;
> wanbo (G) <wanbo13@huawei.com>; limingwang (A)
> <limingwang@huawei.com>
> Subject: Re: [PATCH v1 05/12] target/riscv: Implement kvm_arch_put_registers
>
> On Sat, Nov 20, 2021 at 1:17 PM Yifei Jiang <jiangyifei@huawei.com> wrote:
> >
> > Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl
> >
> > Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> > Signed-off-by: Mingwang Li <limingwang@huawei.com>
> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > target/riscv/kvm.c | 141
> > ++++++++++++++++++++++++++++++++++++++++++++-
> > 1 file changed, 140 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index
> > b49c24be0a..5fe5ca4434 100644
> > --- a/target/riscv/kvm.c
> > +++ b/target/riscv/kvm.c
> > @@ -90,6 +90,31 @@ static int kvm_riscv_get_regs_core(CPUState *cs)
> > return ret;
> > }
> >
> > +static int kvm_riscv_put_regs_core(CPUState *cs) {
> > + int ret = 0;
> > + int i;
> > + target_ulong reg;
> > + CPURISCVState *env = &RISCV_CPU(cs)->env;
> > +
> > + reg = env->pc;
> > + ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®);
> > + if (ret) {
> > + return ret;
> > + }
> > +
> > + for (i = 1; i < 32; i++) {
> > + uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
> > + reg = env->gpr[i];
> > + ret = kvm_set_one_reg(cs, id, ®);
> > + if (ret) {
> > + return ret;
> > + }
> > + }
> > +
> > + return ret;
> > +}
> > +
> > static int kvm_riscv_get_regs_csr(CPUState *cs) {
> > int ret = 0;
> > @@ -153,6 +178,69 @@ static int kvm_riscv_get_regs_csr(CPUState *cs)
> > return ret;
> > }
> >
> > +static int kvm_riscv_put_regs_csr(CPUState *cs) {
> > + int ret = 0;
> > + target_ulong reg;
> > + CPURISCVState *env = &RISCV_CPU(cs)->env;
> > +
> > + reg = env->mstatus;
> > + ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, sstatus), ®);
> > + if (ret) {
> > + return ret;
> > + }
> > +
> > + reg = env->mie;
> > + ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, sie), ®);
> > + if (ret) {
> > + return ret;
> > + }
> > +
> > + reg = env->stvec;
> > + ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, stvec), ®);
> > + if (ret) {
> > + return ret;
> > + }
> > +
> > + reg = env->sscratch;
> > + ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, sscratch), ®);
> > + if (ret) {
> > + return ret;
> > + }
> > +
> > + reg = env->sepc;
> > + ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, sepc), ®);
> > + if (ret) {
> > + return ret;
> > + }
> > +
> > + reg = env->scause;
> > + ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, scause), ®);
> > + if (ret) {
> > + return ret;
> > + }
> > +
> > + reg = env->stval;
> > + ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, stval), ®);
> > + if (ret) {
> > + return ret;
> > + }
> > +
> > + reg = env->mip;
> > + ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, sip), ®);
> > + if (ret) {
> > + return ret;
> > + }
> > +
> > + reg = env->satp;
> > + ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, satp), ®);
> > + if (ret) {
> > + return ret;
> > + }
>
> Same as the previous patch, there is a common pattern in above
> kvm_set_one_reg() calls. Please use a macro to simplify.
>
> Regards,
> Anup
>
Thanks, it will be modified in the next series.
Yifei
> > +
> > + return ret;
> > +}
> > +
> > static int kvm_riscv_get_regs_fp(CPUState *cs) {
> > int ret = 0;
> > @@ -186,6 +274,40 @@ static int kvm_riscv_get_regs_fp(CPUState *cs)
> > return ret;
> > }
> >
> > +static int kvm_riscv_put_regs_fp(CPUState *cs) {
> > + int ret = 0;
> > + int i;
> > + CPURISCVState *env = &RISCV_CPU(cs)->env;
> > +
> > + if (riscv_has_ext(env, RVD)) {
> > + uint64_t reg;
> > + for (i = 0; i < 32; i++) {
> > + reg = env->fpr[i];
> > + ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), ®);
> > + if (ret) {
> > + return ret;
> > + }
> > + }
> > + return ret;
> > + }
> > +
> > + if (riscv_has_ext(env, RVF)) {
> > + uint32_t reg;
> > + for (i = 0; i < 32; i++) {
> > + reg = env->fpr[i];
> > + ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(env, i), ®);
> > + if (ret) {
> > + return ret;
> > + }
> > + }
> > + return ret;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +
> > const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
> > KVM_CAP_LAST_INFO
> > };
> > @@ -214,7 +336,24 @@ int kvm_arch_get_registers(CPUState *cs)
> >
> > int kvm_arch_put_registers(CPUState *cs, int level) {
> > - return 0;
> > + int ret = 0;
> > +
> > + ret = kvm_riscv_put_regs_core(cs);
> > + if (ret) {
> > + return ret;
> > + }
> > +
> > + ret = kvm_riscv_put_regs_csr(cs);
> > + if (ret) {
> > + return ret;
> > + }
> > +
> > + ret = kvm_riscv_put_regs_fp(cs);
> > + if (ret) {
> > + return ret;
> > + }
> > +
> > + return ret;
> > }
> >
> > int kvm_arch_release_virq_post(int virq)
> > --
> > 2.19.1
> >
> >
> > --
> > kvm-riscv mailing list
> > kvm-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/kvm-riscv
next prev parent reply other threads:[~2021-12-10 9:58 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-20 7:46 [PATCH v1 00/12] Add riscv kvm accel support Yifei Jiang
2021-11-20 7:46 ` [PATCH v1 01/12] update-linux-headers: Add asm-riscv/kvm.h Yifei Jiang
2021-11-23 6:13 ` Alistair Francis
2021-12-03 5:07 ` Anup Patel
2021-11-20 7:46 ` [PATCH v1 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang
2021-12-03 5:08 ` Anup Patel
2021-11-20 7:46 ` [PATCH v1 03/12] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang
2021-11-20 22:19 ` Richard Henderson
2021-12-10 9:55 ` Jiangyifei
2021-11-20 7:46 ` [PATCH v1 04/12] target/riscv: Implement kvm_arch_get_registers Yifei Jiang
2021-12-03 6:20 ` Anup Patel
2021-12-10 9:57 ` Jiangyifei
2021-11-20 7:46 ` [PATCH v1 05/12] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
2021-12-03 6:22 ` Anup Patel
2021-12-10 9:58 ` Jiangyifei [this message]
2021-11-20 7:46 ` [PATCH v1 06/12] target/riscv: Support start kernel directly by KVM Yifei Jiang
2021-12-03 6:31 ` Anup Patel
2021-12-10 10:00 ` Jiangyifei
2021-11-20 7:46 ` [PATCH v1 07/12] target/riscv: Support setting external interrupt " Yifei Jiang
2021-12-03 9:15 ` Anup Patel
2021-12-10 10:01 ` Jiangyifei
2021-11-20 7:46 ` [PATCH v1 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang
2021-11-20 12:24 ` Philippe Mathieu-Daudé
2021-12-10 10:02 ` Jiangyifei
2021-11-20 7:46 ` [PATCH v1 09/12] target/riscv: Add host cpu type Yifei Jiang
2021-12-03 9:26 ` Anup Patel
2021-11-20 7:46 ` [PATCH v1 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang
2021-12-03 9:38 ` Anup Patel
2021-12-10 10:03 ` Jiangyifei
2021-11-20 7:46 ` [PATCH v1 11/12] target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang
2021-11-20 7:46 ` [PATCH v1 12/12] target/riscv: Support virtual time context synchronization Yifei Jiang
2021-11-20 22:34 ` Richard Henderson
2021-12-10 10:03 ` Jiangyifei
2021-12-10 10:11 ` Paolo Bonzini
2021-12-03 8:41 ` [PATCH v1 00/12] Add riscv kvm accel support Michal Prívozník
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